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ASoC: rt5677: Add option to configure gpio as floating/pullup/pulldown
[linux-2.6-block.git] / sound / soc / codecs / rt5677.c
CommitLineData
0e826e86
OC		 1/*
2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/fs.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
f9f6a592 18#include <linux/of_gpio.h>
0e826e86
OC		 19#include <linux/regmap.h>
20#include <linux/i2c.h>
21#include <linux/platform_device.h>
22#include <linux/spi/spi.h>
44caf764 23#include <linux/gpio.h>
0e826e86
OC		 24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
28#include <sound/soc-dapm.h>
29#include <sound/initval.h>
30#include <sound/tlv.h>
31
30f14b43 32#include "rl6231.h"
0e826e86
OC		 33#include "rt5677.h"
34
35#define RT5677_DEVICE_ID 0x6327
36
37#define RT5677_PR_RANGE_BASE (0xff + 1)
38#define RT5677_PR_SPACING 0x100
39
40#define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
41
42static const struct regmap_range_cfg rt5677_ranges[] = {
43 {
44 .name = "PR",
45 .range_min = RT5677_PR_BASE,
46 .range_max = RT5677_PR_BASE + 0xfd,
47 .selector_reg = RT5677_PRIV_INDEX,
48 .selector_mask = 0xff,
49 .selector_shift = 0x0,
50 .window_start = RT5677_PRIV_DATA,
51 .window_len = 0x1,
52 },
53};
54
55static const struct reg_default init_list[] = {
56 {RT5677_PR_BASE + 0x3d, 0x364d},
57 {RT5677_PR_BASE + 0x17, 0x4fc0},
58 {RT5677_PR_BASE + 0x13, 0x0312},
59 {RT5677_PR_BASE + 0x1e, 0x0000},
60 {RT5677_PR_BASE + 0x12, 0x0eaa},
61 {RT5677_PR_BASE + 0x14, 0x018a},
62};
63#define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
64
65static const struct reg_default rt5677_reg[] = {
66 {RT5677_RESET , 0x0000},
67 {RT5677_LOUT1 , 0xa800},
68 {RT5677_IN1 , 0x0000},
69 {RT5677_MICBIAS , 0x0000},
70 {RT5677_SLIMBUS_PARAM , 0x0000},
71 {RT5677_SLIMBUS_RX , 0x0000},
72 {RT5677_SLIMBUS_CTRL , 0x0000},
73 {RT5677_SIDETONE_CTRL , 0x000b},
74 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
75 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
76 {RT5677_DAC4_DIG_VOL , 0xafaf},
77 {RT5677_DAC3_DIG_VOL , 0xafaf},
78 {RT5677_DAC1_DIG_VOL , 0xafaf},
79 {RT5677_DAC2_DIG_VOL , 0xafaf},
80 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
81 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
82 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
83 {RT5677_STO1_2_ADC_BST , 0x0000},
84 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
85 {RT5677_ADC_BST_CTRL2 , 0x0000},
86 {RT5677_STO3_4_ADC_BST , 0x0000},
87 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
88 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
89 {RT5677_STO4_ADC_MIXER , 0xd4c0},
90 {RT5677_STO3_ADC_MIXER , 0xd4c0},
91 {RT5677_STO2_ADC_MIXER , 0xd4c0},
92 {RT5677_STO1_ADC_MIXER , 0xd4c0},
93 {RT5677_MONO_ADC_MIXER , 0xd4d1},
94 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
95 {RT5677_STO1_DAC_MIXER , 0xaaaa},
96 {RT5677_MONO_DAC_MIXER , 0xaaaa},
97 {RT5677_DD1_MIXER , 0xaaaa},
98 {RT5677_DD2_MIXER , 0xaaaa},
99 {RT5677_IF3_DATA , 0x0000},
100 {RT5677_IF4_DATA , 0x0000},
101 {RT5677_PDM_OUT_CTRL , 0x8888},
102 {RT5677_PDM_DATA_CTRL1 , 0x0000},
103 {RT5677_PDM_DATA_CTRL2 , 0x0000},
104 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
105 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
106 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
107 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
108 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
109 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
110 {RT5677_TDM1_CTRL1 , 0x0300},
111 {RT5677_TDM1_CTRL2 , 0x0000},
112 {RT5677_TDM1_CTRL3 , 0x4000},
113 {RT5677_TDM1_CTRL4 , 0x0123},
114 {RT5677_TDM1_CTRL5 , 0x4567},
115 {RT5677_TDM2_CTRL1 , 0x0300},
116 {RT5677_TDM2_CTRL2 , 0x0000},
117 {RT5677_TDM2_CTRL3 , 0x4000},
118 {RT5677_TDM2_CTRL4 , 0x0123},
119 {RT5677_TDM2_CTRL5 , 0x4567},
120 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
121 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
122 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
123 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
124 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
125 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
126 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
127 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
128 {RT5677_DMIC_CTRL1 , 0x1505},
129 {RT5677_DMIC_CTRL2 , 0x0055},
130 {RT5677_HAP_GENE_CTRL1 , 0x0111},
131 {RT5677_HAP_GENE_CTRL2 , 0x0064},
132 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
133 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
134 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
135 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
136 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
137 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
138 {RT5677_HAP_GENE_CTRL9 , 0xf000},
139 {RT5677_HAP_GENE_CTRL10 , 0x0000},
140 {RT5677_PWR_DIG1 , 0x0000},
141 {RT5677_PWR_DIG2 , 0x0000},
142 {RT5677_PWR_ANLG1 , 0x0055},
143 {RT5677_PWR_ANLG2 , 0x0000},
144 {RT5677_PWR_DSP1 , 0x0001},
145 {RT5677_PWR_DSP_ST , 0x0000},
146 {RT5677_PWR_DSP2 , 0x0000},
147 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
148 {RT5677_PRIV_INDEX , 0x0000},
149 {RT5677_PRIV_DATA , 0x0000},
150 {RT5677_I2S4_SDP , 0x8000},
151 {RT5677_I2S1_SDP , 0x8000},
152 {RT5677_I2S2_SDP , 0x8000},
153 {RT5677_I2S3_SDP , 0x8000},
154 {RT5677_CLK_TREE_CTRL1 , 0x1111},
155 {RT5677_CLK_TREE_CTRL2 , 0x1111},
156 {RT5677_CLK_TREE_CTRL3 , 0x0000},
157 {RT5677_PLL1_CTRL1 , 0x0000},
158 {RT5677_PLL1_CTRL2 , 0x0000},
159 {RT5677_PLL2_CTRL1 , 0x0c60},
160 {RT5677_PLL2_CTRL2 , 0x2000},
161 {RT5677_GLB_CLK1 , 0x0000},
162 {RT5677_GLB_CLK2 , 0x0000},
163 {RT5677_ASRC_1 , 0x0000},
164 {RT5677_ASRC_2 , 0x0000},
165 {RT5677_ASRC_3 , 0x0000},
166 {RT5677_ASRC_4 , 0x0000},
167 {RT5677_ASRC_5 , 0x0000},
168 {RT5677_ASRC_6 , 0x0000},
169 {RT5677_ASRC_7 , 0x0000},
170 {RT5677_ASRC_8 , 0x0000},
171 {RT5677_ASRC_9 , 0x0000},
172 {RT5677_ASRC_10 , 0x0000},
173 {RT5677_ASRC_11 , 0x0000},
174 {RT5677_ASRC_12 , 0x0008},
175 {RT5677_ASRC_13 , 0x0000},
176 {RT5677_ASRC_14 , 0x0000},
177 {RT5677_ASRC_15 , 0x0000},
178 {RT5677_ASRC_16 , 0x0000},
179 {RT5677_ASRC_17 , 0x0000},
180 {RT5677_ASRC_18 , 0x0000},
181 {RT5677_ASRC_19 , 0x0000},
182 {RT5677_ASRC_20 , 0x0000},
183 {RT5677_ASRC_21 , 0x000c},
184 {RT5677_ASRC_22 , 0x0000},
185 {RT5677_ASRC_23 , 0x0000},
186 {RT5677_VAD_CTRL1 , 0x2184},
187 {RT5677_VAD_CTRL2 , 0x010a},
188 {RT5677_VAD_CTRL3 , 0x0aea},
189 {RT5677_VAD_CTRL4 , 0x000c},
190 {RT5677_VAD_CTRL5 , 0x0000},
191 {RT5677_DSP_INB_CTRL1 , 0x0000},
192 {RT5677_DSP_INB_CTRL2 , 0x0000},
193 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
194 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
195 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
196 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
197 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
198 {RT5677_ADC_EQ_CTRL1 , 0x6000},
199 {RT5677_ADC_EQ_CTRL2 , 0x0000},
200 {RT5677_EQ_CTRL1 , 0xc000},
201 {RT5677_EQ_CTRL2 , 0x0000},
202 {RT5677_EQ_CTRL3 , 0x0000},
203 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
204 {RT5677_JD_CTRL1 , 0x0000},
205 {RT5677_JD_CTRL2 , 0x0000},
206 {RT5677_JD_CTRL3 , 0x0000},
207 {RT5677_IRQ_CTRL1 , 0x0000},
208 {RT5677_IRQ_CTRL2 , 0x0000},
209 {RT5677_GPIO_ST , 0x0000},
210 {RT5677_GPIO_CTRL1 , 0x0000},
211 {RT5677_GPIO_CTRL2 , 0x0000},
212 {RT5677_GPIO_CTRL3 , 0x0000},
213 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
214 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
215 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
216 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
217 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
218 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
219 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
220 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
221 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
222 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
223 {RT5677_MB_DRC_CTRL1 , 0x0f20},
224 {RT5677_DRC1_CTRL1 , 0x001f},
225 {RT5677_DRC1_CTRL2 , 0x020c},
226 {RT5677_DRC1_CTRL3 , 0x1f00},
227 {RT5677_DRC1_CTRL4 , 0x0000},
228 {RT5677_DRC1_CTRL5 , 0x0000},
229 {RT5677_DRC1_CTRL6 , 0x0029},
230 {RT5677_DRC2_CTRL1 , 0x001f},
231 {RT5677_DRC2_CTRL2 , 0x020c},
232 {RT5677_DRC2_CTRL3 , 0x1f00},
233 {RT5677_DRC2_CTRL4 , 0x0000},
234 {RT5677_DRC2_CTRL5 , 0x0000},
235 {RT5677_DRC2_CTRL6 , 0x0029},
236 {RT5677_DRC1_HL_CTRL1 , 0x8000},
237 {RT5677_DRC1_HL_CTRL2 , 0x0200},
238 {RT5677_DRC2_HL_CTRL1 , 0x8000},
239 {RT5677_DRC2_HL_CTRL2 , 0x0200},
240 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
241 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
242 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
243 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
244 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
245 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
246 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
247 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
248 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
249 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
250 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
251 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
252 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
253 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
254 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
255 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
256 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
257 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
258 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
259 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
260 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
261 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
262 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
263 {RT5677_DIG_MISC , 0x0000},
264 {RT5677_GEN_CTRL1 , 0x0000},
265 {RT5677_GEN_CTRL2 , 0x0000},
266 {RT5677_VENDOR_ID , 0x0000},
267 {RT5677_VENDOR_ID1 , 0x10ec},
268 {RT5677_VENDOR_ID2 , 0x6327},
269};
270
271static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
272{
273 int i;
274
275 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
276 if (reg >= rt5677_ranges[i].range_min &&
277 reg <= rt5677_ranges[i].range_max) {
278 return true;
279 }
280 }
281
282 switch (reg) {
283 case RT5677_RESET:
284 case RT5677_SLIMBUS_PARAM:
285 case RT5677_PDM_DATA_CTRL1:
286 case RT5677_PDM_DATA_CTRL2:
287 case RT5677_PDM1_DATA_CTRL4:
288 case RT5677_PDM2_DATA_CTRL4:
289 case RT5677_I2C_MASTER_CTRL1:
290 case RT5677_I2C_MASTER_CTRL7:
291 case RT5677_I2C_MASTER_CTRL8:
292 case RT5677_HAP_GENE_CTRL2:
293 case RT5677_PWR_DSP_ST:
294 case RT5677_PRIV_DATA:
295 case RT5677_PLL1_CTRL2:
296 case RT5677_PLL2_CTRL2:
297 case RT5677_ASRC_22:
298 case RT5677_ASRC_23:
299 case RT5677_VAD_CTRL5:
300 case RT5677_ADC_EQ_CTRL1:
301 case RT5677_EQ_CTRL1:
302 case RT5677_IRQ_CTRL1:
303 case RT5677_IRQ_CTRL2:
304 case RT5677_GPIO_ST:
305 case RT5677_DSP_INB1_SRC_CTRL4:
306 case RT5677_DSP_INB2_SRC_CTRL4:
307 case RT5677_DSP_INB3_SRC_CTRL4:
308 case RT5677_DSP_OUTB1_SRC_CTRL4:
309 case RT5677_DSP_OUTB2_SRC_CTRL4:
310 case RT5677_VENDOR_ID:
311 case RT5677_VENDOR_ID1:
312 case RT5677_VENDOR_ID2:
313 return true;
314 default:
315 return false;
316 }
317}
318
319static bool rt5677_readable_register(struct device *dev, unsigned int reg)
320{
321 int i;
322
323 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
324 if (reg >= rt5677_ranges[i].range_min &&
325 reg <= rt5677_ranges[i].range_max) {
326 return true;
327 }
328 }
329
330 switch (reg) {
331 case RT5677_RESET:
332 case RT5677_LOUT1:
333 case RT5677_IN1:
334 case RT5677_MICBIAS:
335 case RT5677_SLIMBUS_PARAM:
336 case RT5677_SLIMBUS_RX:
337 case RT5677_SLIMBUS_CTRL:
338 case RT5677_SIDETONE_CTRL:
339 case RT5677_ANA_DAC1_2_3_SRC:
340 case RT5677_IF_DSP_DAC3_4_MIXER:
341 case RT5677_DAC4_DIG_VOL:
342 case RT5677_DAC3_DIG_VOL:
343 case RT5677_DAC1_DIG_VOL:
344 case RT5677_DAC2_DIG_VOL:
345 case RT5677_IF_DSP_DAC2_MIXER:
346 case RT5677_STO1_ADC_DIG_VOL:
347 case RT5677_MONO_ADC_DIG_VOL:
348 case RT5677_STO1_2_ADC_BST:
349 case RT5677_STO2_ADC_DIG_VOL:
350 case RT5677_ADC_BST_CTRL2:
351 case RT5677_STO3_4_ADC_BST:
352 case RT5677_STO3_ADC_DIG_VOL:
353 case RT5677_STO4_ADC_DIG_VOL:
354 case RT5677_STO4_ADC_MIXER:
355 case RT5677_STO3_ADC_MIXER:
356 case RT5677_STO2_ADC_MIXER:
357 case RT5677_STO1_ADC_MIXER:
358 case RT5677_MONO_ADC_MIXER:
359 case RT5677_ADC_IF_DSP_DAC1_MIXER:
360 case RT5677_STO1_DAC_MIXER:
361 case RT5677_MONO_DAC_MIXER:
362 case RT5677_DD1_MIXER:
363 case RT5677_DD2_MIXER:
364 case RT5677_IF3_DATA:
365 case RT5677_IF4_DATA:
366 case RT5677_PDM_OUT_CTRL:
367 case RT5677_PDM_DATA_CTRL1:
368 case RT5677_PDM_DATA_CTRL2:
369 case RT5677_PDM1_DATA_CTRL2:
370 case RT5677_PDM1_DATA_CTRL3:
371 case RT5677_PDM1_DATA_CTRL4:
372 case RT5677_PDM2_DATA_CTRL2:
373 case RT5677_PDM2_DATA_CTRL3:
374 case RT5677_PDM2_DATA_CTRL4:
375 case RT5677_TDM1_CTRL1:
376 case RT5677_TDM1_CTRL2:
377 case RT5677_TDM1_CTRL3:
378 case RT5677_TDM1_CTRL4:
379 case RT5677_TDM1_CTRL5:
380 case RT5677_TDM2_CTRL1:
381 case RT5677_TDM2_CTRL2:
382 case RT5677_TDM2_CTRL3:
383 case RT5677_TDM2_CTRL4:
384 case RT5677_TDM2_CTRL5:
385 case RT5677_I2C_MASTER_CTRL1:
386 case RT5677_I2C_MASTER_CTRL2:
387 case RT5677_I2C_MASTER_CTRL3:
388 case RT5677_I2C_MASTER_CTRL4:
389 case RT5677_I2C_MASTER_CTRL5:
390 case RT5677_I2C_MASTER_CTRL6:
391 case RT5677_I2C_MASTER_CTRL7:
392 case RT5677_I2C_MASTER_CTRL8:
393 case RT5677_DMIC_CTRL1:
394 case RT5677_DMIC_CTRL2:
395 case RT5677_HAP_GENE_CTRL1:
396 case RT5677_HAP_GENE_CTRL2:
397 case RT5677_HAP_GENE_CTRL3:
398 case RT5677_HAP_GENE_CTRL4:
399 case RT5677_HAP_GENE_CTRL5:
400 case RT5677_HAP_GENE_CTRL6:
401 case RT5677_HAP_GENE_CTRL7:
402 case RT5677_HAP_GENE_CTRL8:
403 case RT5677_HAP_GENE_CTRL9:
404 case RT5677_HAP_GENE_CTRL10:
405 case RT5677_PWR_DIG1:
406 case RT5677_PWR_DIG2:
407 case RT5677_PWR_ANLG1:
408 case RT5677_PWR_ANLG2:
409 case RT5677_PWR_DSP1:
410 case RT5677_PWR_DSP_ST:
411 case RT5677_PWR_DSP2:
412 case RT5677_ADC_DAC_HPF_CTRL1:
413 case RT5677_PRIV_INDEX:
414 case RT5677_PRIV_DATA:
415 case RT5677_I2S4_SDP:
416 case RT5677_I2S1_SDP:
417 case RT5677_I2S2_SDP:
418 case RT5677_I2S3_SDP:
419 case RT5677_CLK_TREE_CTRL1:
420 case RT5677_CLK_TREE_CTRL2:
421 case RT5677_CLK_TREE_CTRL3:
422 case RT5677_PLL1_CTRL1:
423 case RT5677_PLL1_CTRL2:
424 case RT5677_PLL2_CTRL1:
425 case RT5677_PLL2_CTRL2:
426 case RT5677_GLB_CLK1:
427 case RT5677_GLB_CLK2:
428 case RT5677_ASRC_1:
429 case RT5677_ASRC_2:
430 case RT5677_ASRC_3:
431 case RT5677_ASRC_4:
432 case RT5677_ASRC_5:
433 case RT5677_ASRC_6:
434 case RT5677_ASRC_7:
435 case RT5677_ASRC_8:
436 case RT5677_ASRC_9:
437 case RT5677_ASRC_10:
438 case RT5677_ASRC_11:
439 case RT5677_ASRC_12:
440 case RT5677_ASRC_13:
441 case RT5677_ASRC_14:
442 case RT5677_ASRC_15:
443 case RT5677_ASRC_16:
444 case RT5677_ASRC_17:
445 case RT5677_ASRC_18:
446 case RT5677_ASRC_19:
447 case RT5677_ASRC_20:
448 case RT5677_ASRC_21:
449 case RT5677_ASRC_22:
450 case RT5677_ASRC_23:
451 case RT5677_VAD_CTRL1:
452 case RT5677_VAD_CTRL2:
453 case RT5677_VAD_CTRL3:
454 case RT5677_VAD_CTRL4:
455 case RT5677_VAD_CTRL5:
456 case RT5677_DSP_INB_CTRL1:
457 case RT5677_DSP_INB_CTRL2:
458 case RT5677_DSP_IN_OUTB_CTRL:
459 case RT5677_DSP_OUTB0_1_DIG_VOL:
460 case RT5677_DSP_OUTB2_3_DIG_VOL:
461 case RT5677_DSP_OUTB4_5_DIG_VOL:
462 case RT5677_DSP_OUTB6_7_DIG_VOL:
463 case RT5677_ADC_EQ_CTRL1:
464 case RT5677_ADC_EQ_CTRL2:
465 case RT5677_EQ_CTRL1:
466 case RT5677_EQ_CTRL2:
467 case RT5677_EQ_CTRL3:
468 case RT5677_SOFT_VOL_ZERO_CROSS1:
469 case RT5677_JD_CTRL1:
470 case RT5677_JD_CTRL2:
471 case RT5677_JD_CTRL3:
472 case RT5677_IRQ_CTRL1:
473 case RT5677_IRQ_CTRL2:
474 case RT5677_GPIO_ST:
475 case RT5677_GPIO_CTRL1:
476 case RT5677_GPIO_CTRL2:
477 case RT5677_GPIO_CTRL3:
478 case RT5677_STO1_ADC_HI_FILTER1:
479 case RT5677_STO1_ADC_HI_FILTER2:
480 case RT5677_MONO_ADC_HI_FILTER1:
481 case RT5677_MONO_ADC_HI_FILTER2:
482 case RT5677_STO2_ADC_HI_FILTER1:
483 case RT5677_STO2_ADC_HI_FILTER2:
484 case RT5677_STO3_ADC_HI_FILTER1:
485 case RT5677_STO3_ADC_HI_FILTER2:
486 case RT5677_STO4_ADC_HI_FILTER1:
487 case RT5677_STO4_ADC_HI_FILTER2:
488 case RT5677_MB_DRC_CTRL1:
489 case RT5677_DRC1_CTRL1:
490 case RT5677_DRC1_CTRL2:
491 case RT5677_DRC1_CTRL3:
492 case RT5677_DRC1_CTRL4:
493 case RT5677_DRC1_CTRL5:
494 case RT5677_DRC1_CTRL6:
495 case RT5677_DRC2_CTRL1:
496 case RT5677_DRC2_CTRL2:
497 case RT5677_DRC2_CTRL3:
498 case RT5677_DRC2_CTRL4:
499 case RT5677_DRC2_CTRL5:
500 case RT5677_DRC2_CTRL6:
501 case RT5677_DRC1_HL_CTRL1:
502 case RT5677_DRC1_HL_CTRL2:
503 case RT5677_DRC2_HL_CTRL1:
504 case RT5677_DRC2_HL_CTRL2:
505 case RT5677_DSP_INB1_SRC_CTRL1:
506 case RT5677_DSP_INB1_SRC_CTRL2:
507 case RT5677_DSP_INB1_SRC_CTRL3:
508 case RT5677_DSP_INB1_SRC_CTRL4:
509 case RT5677_DSP_INB2_SRC_CTRL1:
510 case RT5677_DSP_INB2_SRC_CTRL2:
511 case RT5677_DSP_INB2_SRC_CTRL3:
512 case RT5677_DSP_INB2_SRC_CTRL4:
513 case RT5677_DSP_INB3_SRC_CTRL1:
514 case RT5677_DSP_INB3_SRC_CTRL2:
515 case RT5677_DSP_INB3_SRC_CTRL3:
516 case RT5677_DSP_INB3_SRC_CTRL4:
517 case RT5677_DSP_OUTB1_SRC_CTRL1:
518 case RT5677_DSP_OUTB1_SRC_CTRL2:
519 case RT5677_DSP_OUTB1_SRC_CTRL3:
520 case RT5677_DSP_OUTB1_SRC_CTRL4:
521 case RT5677_DSP_OUTB2_SRC_CTRL1:
522 case RT5677_DSP_OUTB2_SRC_CTRL2:
523 case RT5677_DSP_OUTB2_SRC_CTRL3:
524 case RT5677_DSP_OUTB2_SRC_CTRL4:
525 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
526 case RT5677_DSP_OUTB_45_MIXER_CTRL:
527 case RT5677_DSP_OUTB_67_MIXER_CTRL:
528 case RT5677_DIG_MISC:
529 case RT5677_GEN_CTRL1:
530 case RT5677_GEN_CTRL2:
531 case RT5677_VENDOR_ID:
532 case RT5677_VENDOR_ID1:
533 case RT5677_VENDOR_ID2:
534 return true;
535 default:
536 return false;
537 }
538}
539
540static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
541static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
542static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
543static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
544static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
90bdbb46 545static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
0e826e86
OC		 546
547/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
548static unsigned int bst_tlv[] = {
549 TLV_DB_RANGE_HEAD(7),
550 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
551 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
552 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
553 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
554 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
555 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
556 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
557};
558
559static const struct snd_kcontrol_new rt5677_snd_controls[] = {
560 /* OUTPUT Control */
561 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
562 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
563 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
564 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
565 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
566 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
567
568 /* DAC Digital Volume */
569 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
570 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
571 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
572 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
573 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
574 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
575 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
576 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
577
578 /* IN1/IN2 Control */
579 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
580 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
581
582 /* ADC Digital Volume Control */
583 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
584 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
585 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
586 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
587 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
588 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
589 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
590 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
591 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
592 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
593
594 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
595 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
596 adc_vol_tlv),
597 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
598 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
599 adc_vol_tlv),
600 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
601 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
602 adc_vol_tlv),
603 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
604 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
605 adc_vol_tlv),
606 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
607 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 127, 0,
608 adc_vol_tlv),
609
90bdbb46
OC		 610 /* Sidetone Control */
611 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
612 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
613
0e826e86 614 /* ADC Boost Volume Control */
80220f29 615 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
0e826e86
OC		 616 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
617 adc_bst_tlv),
80220f29 618 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
0e826e86
OC		 619 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
620 adc_bst_tlv),
80220f29 621 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
0e826e86
OC		 622 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
623 adc_bst_tlv),
80220f29 624 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
0e826e86
OC		 625 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
626 adc_bst_tlv),
80220f29 627 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
0e826e86
OC		 628 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
629 adc_bst_tlv),
630};
631
632/**
633 * set_dmic_clk - Set parameter of dmic.
634 *
635 * @w: DAPM widget.
636 * @kcontrol: The kcontrol of this widget.
637 * @event: Event id.
638 *
639 * Choose dmic clock between 1MHz and 3MHz.
640 * It is better for clock to approximate 3MHz.
641 */
642static int set_dmic_clk(struct snd_soc_dapm_widget *w,
643 struct snd_kcontrol *kcontrol, int event)
644{
645 struct snd_soc_codec *codec = w->codec;
646 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
9a53581e 647 int idx = rl6231_calc_dmic_clk(rt5677->sysclk);
0e826e86
OC		 648
649 if (idx < 0)
650 dev_err(codec->dev, "Failed to set DMIC clock\n");
651 else
652 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
653 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
654 return idx;
655}
656
657static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
658 struct snd_soc_dapm_widget *sink)
659{
660 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(source->codec);
661 unsigned int val;
662
663 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
664 val &= RT5677_SCLK_SRC_MASK;
665 if (val == RT5677_SCLK_SRC_PLL1)
666 return 1;
667 else
668 return 0;
669}
670
671/* Digital Mixer */
672static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
673 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
674 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
675 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
676 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
677};
678
679static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
680 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
681 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
682 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
683 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
684};
685
686static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
687 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
688 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
689 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
690 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
691};
692
693static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
694 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
695 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
696 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
697 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
698};
699
700static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
701 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
702 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
703 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
704 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
705};
706
707static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
708 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
709 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
710 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
711 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
712};
713
714static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
715 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
716 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
717 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
718 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
719};
720
721static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
722 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
723 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
724 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
725 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
726};
727
728static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
729 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
730 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
731 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
732 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
733};
734
735static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
736 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
737 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
738 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
739 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
740};
741
742static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
743 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
744 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
745 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
746 RT5677_M_DAC1_L_SFT, 1, 1),
747};
748
749static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
750 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
751 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
752 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
753 RT5677_M_DAC1_R_SFT, 1, 1),
754};
755
756static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
757 SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
758 RT5677_M_ST_DAC1_L_SFT, 1, 1),
759 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
760 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
761 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
762 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
763 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
764 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
765};
766
767static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
768 SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
769 RT5677_M_ST_DAC1_R_SFT, 1, 1),
770 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
771 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
772 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
773 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
774 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
775 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
776};
777
778static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
779 SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
780 RT5677_M_ST_DAC2_L_SFT, 1, 1),
781 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
782 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
783 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
784 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
785 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
786 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
787};
788
789static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
790 SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
791 RT5677_M_ST_DAC2_R_SFT, 1, 1),
792 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
793 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
794 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
795 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
796 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
797 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
798};
799
800static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
801 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
802 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
803 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
804 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
805 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
806 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
807 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
808 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
809};
810
811static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
812 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
813 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
814 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
815 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
816 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
817 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
818 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
819 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
820};
821
822static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
823 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
824 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
825 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
826 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
827 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
828 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
829 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
830 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
831};
832
833static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
834 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
835 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
836 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
837 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
838 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
839 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
840 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
841 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
842};
843
844static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
845 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
846 RT5677_DSP_IB_01_H_SFT, 1, 1),
847 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
848 RT5677_DSP_IB_23_H_SFT, 1, 1),
849 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
850 RT5677_DSP_IB_45_H_SFT, 1, 1),
851 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
852 RT5677_DSP_IB_6_H_SFT, 1, 1),
853 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
854 RT5677_DSP_IB_7_H_SFT, 1, 1),
855 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
856 RT5677_DSP_IB_8_H_SFT, 1, 1),
857 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
858 RT5677_DSP_IB_9_H_SFT, 1, 1),
859};
860
861static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
862 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
863 RT5677_DSP_IB_01_L_SFT, 1, 1),
864 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
865 RT5677_DSP_IB_23_L_SFT, 1, 1),
866 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
867 RT5677_DSP_IB_45_L_SFT, 1, 1),
868 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
869 RT5677_DSP_IB_6_L_SFT, 1, 1),
870 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
871 RT5677_DSP_IB_7_L_SFT, 1, 1),
872 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
873 RT5677_DSP_IB_8_L_SFT, 1, 1),
874 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
875 RT5677_DSP_IB_9_L_SFT, 1, 1),
876};
877
878static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
879 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
880 RT5677_DSP_IB_01_H_SFT, 1, 1),
881 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
882 RT5677_DSP_IB_23_H_SFT, 1, 1),
883 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
884 RT5677_DSP_IB_45_H_SFT, 1, 1),
885 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
886 RT5677_DSP_IB_6_H_SFT, 1, 1),
887 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
888 RT5677_DSP_IB_7_H_SFT, 1, 1),
889 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
890 RT5677_DSP_IB_8_H_SFT, 1, 1),
891 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
892 RT5677_DSP_IB_9_H_SFT, 1, 1),
893};
894
895static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
896 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
897 RT5677_DSP_IB_01_L_SFT, 1, 1),
898 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
899 RT5677_DSP_IB_23_L_SFT, 1, 1),
900 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
901 RT5677_DSP_IB_45_L_SFT, 1, 1),
902 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
903 RT5677_DSP_IB_6_L_SFT, 1, 1),
904 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
905 RT5677_DSP_IB_7_L_SFT, 1, 1),
906 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
907 RT5677_DSP_IB_8_L_SFT, 1, 1),
908 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
909 RT5677_DSP_IB_9_L_SFT, 1, 1),
910};
911
912static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
913 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
914 RT5677_DSP_IB_01_H_SFT, 1, 1),
915 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
916 RT5677_DSP_IB_23_H_SFT, 1, 1),
917 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
918 RT5677_DSP_IB_45_H_SFT, 1, 1),
919 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
920 RT5677_DSP_IB_6_H_SFT, 1, 1),
921 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
922 RT5677_DSP_IB_7_H_SFT, 1, 1),
923 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
924 RT5677_DSP_IB_8_H_SFT, 1, 1),
925 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
926 RT5677_DSP_IB_9_H_SFT, 1, 1),
927};
928
929static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
930 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
931 RT5677_DSP_IB_01_L_SFT, 1, 1),
932 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
933 RT5677_DSP_IB_23_L_SFT, 1, 1),
934 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
935 RT5677_DSP_IB_45_L_SFT, 1, 1),
936 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
937 RT5677_DSP_IB_6_L_SFT, 1, 1),
938 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
939 RT5677_DSP_IB_7_L_SFT, 1, 1),
940 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
941 RT5677_DSP_IB_8_L_SFT, 1, 1),
942 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
943 RT5677_DSP_IB_9_L_SFT, 1, 1),
944};
945
946
947/* Mux */
1b7fd76a 948/* DAC1 L/R Source */ /* MX-29 [10:8] */
0e826e86
OC		 949static const char * const rt5677_dac1_src[] = {
950 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
951 "OB 01"
952};
953
954static SOC_ENUM_SINGLE_DECL(
955 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
956 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
957
958static const struct snd_kcontrol_new rt5677_dac1_mux =
1b7fd76a 959 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
0e826e86 960
1b7fd76a 961/* ADDA1 L/R Source */ /* MX-29 [1:0] */
0e826e86
OC		 962static const char * const rt5677_adda1_src[] = {
963 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
964};
965
966static SOC_ENUM_SINGLE_DECL(
967 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
968 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
969
970static const struct snd_kcontrol_new rt5677_adda1_mux =
1b7fd76a 971 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
0e826e86
OC		 972
973
1b7fd76a 974/*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
0e826e86
OC		 975static const char * const rt5677_dac2l_src[] = {
976 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
977 "OB 2",
978};
979
980static SOC_ENUM_SINGLE_DECL(
981 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
982 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
983
984static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1b7fd76a 985 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
0e826e86
OC		 986
987static const char * const rt5677_dac2r_src[] = {
988 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
989 "OB 3", "Haptic Generator", "VAD ADC"
990};
991
992static SOC_ENUM_SINGLE_DECL(
993 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
994 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
995
996static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1b7fd76a 997 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
0e826e86 998
1b7fd76a 999/*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
0e826e86
OC		 1000static const char * const rt5677_dac3l_src[] = {
1001 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1002 "SLB DAC 4", "OB 4"
1003};
1004
1005static SOC_ENUM_SINGLE_DECL(
1006 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1007 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1008
1009static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1b7fd76a 1010 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
0e826e86
OC		 1011
1012static const char * const rt5677_dac3r_src[] = {
1013 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1014 "SLB DAC 5", "OB 5"
1015};
1016
1017static SOC_ENUM_SINGLE_DECL(
1018 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1019 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1020
1021static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1b7fd76a 1022 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
0e826e86 1023
1b7fd76a 1024/*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
0e826e86
OC		 1025static const char * const rt5677_dac4l_src[] = {
1026 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1027 "SLB DAC 6", "OB 6"
1028};
1029
1030static SOC_ENUM_SINGLE_DECL(
1031 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1032 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1033
1034static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1b7fd76a 1035 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
0e826e86
OC		 1036
1037static const char * const rt5677_dac4r_src[] = {
1038 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1039 "SLB DAC 7", "OB 7"
1040};
1041
1042static SOC_ENUM_SINGLE_DECL(
1043 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1044 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1045
1046static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1b7fd76a 1047 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
0e826e86
OC		 1048
1049/* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1050static const char * const rt5677_iob_bypass_src[] = {
1051 "Bypass", "Pass SRC"
1052};
1053
1054static SOC_ENUM_SINGLE_DECL(
1055 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1056 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1057
1058static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1b7fd76a 1059 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
0e826e86
OC		 1060
1061static SOC_ENUM_SINGLE_DECL(
1062 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1063 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1064
1065static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1b7fd76a 1066 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
0e826e86
OC		 1067
1068static SOC_ENUM_SINGLE_DECL(
1069 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1070 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1071
1072static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1b7fd76a 1073 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
0e826e86
OC		 1074
1075static SOC_ENUM_SINGLE_DECL(
1076 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1077 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1078
1079static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1b7fd76a 1080 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
0e826e86
OC		 1081
1082static SOC_ENUM_SINGLE_DECL(
1083 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1084 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1085
1086static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1b7fd76a 1087 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
0e826e86
OC		 1088
1089/* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1090static const char * const rt5677_stereo_adc2_src[] = {
1091 "DD MIX1", "DMIC", "Stereo DAC MIX"
1092};
1093
1094static SOC_ENUM_SINGLE_DECL(
1095 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1096 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1097
1098static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1b7fd76a 1099 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
0e826e86
OC		 1100
1101static SOC_ENUM_SINGLE_DECL(
1102 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1103 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1104
1105static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1b7fd76a 1106 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
0e826e86
OC		 1107
1108static SOC_ENUM_SINGLE_DECL(
1109 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1110 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1111
1112static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1b7fd76a 1113 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
0e826e86
OC		 1114
1115/* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1116static const char * const rt5677_dmic_src[] = {
1117 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1118};
1119
1120static SOC_ENUM_SINGLE_DECL(
1121 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1122 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1123
1124static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1b7fd76a 1125 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
0e826e86
OC		 1126
1127static SOC_ENUM_SINGLE_DECL(
1128 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1129 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1130
1131static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1b7fd76a 1132 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
0e826e86
OC		 1133
1134static SOC_ENUM_SINGLE_DECL(
1135 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1136 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1137
1138static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1b7fd76a 1139 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
0e826e86
OC		 1140
1141static SOC_ENUM_SINGLE_DECL(
1142 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1143 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1144
1145static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1b7fd76a 1146 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
0e826e86
OC		 1147
1148static SOC_ENUM_SINGLE_DECL(
1149 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1150 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1151
1152static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1b7fd76a 1153 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
0e826e86
OC		 1154
1155static SOC_ENUM_SINGLE_DECL(
1156 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1157 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1158
1159static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1b7fd76a 1160 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
0e826e86 1161
1b7fd76a 1162/* Stereo2 ADC Source */ /* MX-26 [0] */
0e826e86
OC		 1163static const char * const rt5677_stereo2_adc_lr_src[] = {
1164 "L", "LR"
1165};
1166
1167static SOC_ENUM_SINGLE_DECL(
1168 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1169 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1170
1171static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1b7fd76a 1172 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
0e826e86
OC		 1173
1174/* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1175static const char * const rt5677_stereo_adc1_src[] = {
1176 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1177};
1178
1179static SOC_ENUM_SINGLE_DECL(
1180 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1181 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1182
1183static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1b7fd76a 1184 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
0e826e86
OC		 1185
1186static SOC_ENUM_SINGLE_DECL(
1187 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1188 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1189
1190static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1b7fd76a 1191 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
0e826e86
OC		 1192
1193static SOC_ENUM_SINGLE_DECL(
1194 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1195 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1196
1197static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1b7fd76a 1198 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
0e826e86 1199
1b7fd76a 1200/* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
0e826e86
OC		 1201static const char * const rt5677_mono_adc2_l_src[] = {
1202 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1203};
1204
1205static SOC_ENUM_SINGLE_DECL(
1206 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1207 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1208
1209static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1b7fd76a 1210 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
0e826e86 1211
1b7fd76a 1212/* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
0e826e86
OC		 1213static const char * const rt5677_mono_adc1_l_src[] = {
1214 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1215};
1216
1217static SOC_ENUM_SINGLE_DECL(
1218 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1219 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1220
1221static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1b7fd76a 1222 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
0e826e86 1223
1b7fd76a 1224/* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
0e826e86
OC		 1225static const char * const rt5677_mono_adc2_r_src[] = {
1226 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1227};
1228
1229static SOC_ENUM_SINGLE_DECL(
1230 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1231 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1232
1233static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1b7fd76a 1234 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
0e826e86 1235
1b7fd76a 1236/* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
0e826e86
OC		 1237static const char * const rt5677_mono_adc1_r_src[] = {
1238 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1239};
1240
1241static SOC_ENUM_SINGLE_DECL(
1242 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1243 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1244
1245static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1b7fd76a 1246 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
0e826e86
OC		 1247
1248/* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1249static const char * const rt5677_stereo4_adc2_src[] = {
1250 "DD MIX1", "DMIC", "DD MIX2"
1251};
1252
1253static SOC_ENUM_SINGLE_DECL(
1254 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1255 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1256
1257static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1b7fd76a 1258 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
0e826e86
OC		 1259
1260
1261/* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1262static const char * const rt5677_stereo4_adc1_src[] = {
1263 "DD MIX1", "ADC1/2", "DD MIX2"
1264};
1265
1266static SOC_ENUM_SINGLE_DECL(
1267 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1268 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1269
1270static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1b7fd76a 1271 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
0e826e86
OC		 1272
1273/* InBound0/1 Source */ /* MX-A3 [14:12] */
1274static const char * const rt5677_inbound01_src[] = {
1275 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1276 "VAD ADC/DAC1 FS"
1277};
1278
1279static SOC_ENUM_SINGLE_DECL(
1280 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1281 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1282
1283static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1284 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1285
1286/* InBound2/3 Source */ /* MX-A3 [10:8] */
1287static const char * const rt5677_inbound23_src[] = {
1288 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1289 "DAC1 FS", "IF4 DAC"
1290};
1291
1292static SOC_ENUM_SINGLE_DECL(
1293 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1294 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1295
1296static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1297 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1298
1299/* InBound4/5 Source */ /* MX-A3 [6:4] */
1300static const char * const rt5677_inbound45_src[] = {
1301 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1302 "IF3 DAC"
1303};
1304
1305static SOC_ENUM_SINGLE_DECL(
1306 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1307 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1308
1309static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1310 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1311
1312/* InBound6 Source */ /* MX-A3 [2:0] */
1313static const char * const rt5677_inbound6_src[] = {
1314 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1315 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1316};
1317
1318static SOC_ENUM_SINGLE_DECL(
1319 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1320 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1321
1322static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1323 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1324
1325/* InBound7 Source */ /* MX-A4 [14:12] */
1326static const char * const rt5677_inbound7_src[] = {
1327 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1328 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1329};
1330
1331static SOC_ENUM_SINGLE_DECL(
1332 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1333 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1334
1335static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1336 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1337
1338/* InBound8 Source */ /* MX-A4 [10:8] */
1339static const char * const rt5677_inbound8_src[] = {
1340 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1341 "MONO ADC MIX L", "DACL1 FS"
1342};
1343
1344static SOC_ENUM_SINGLE_DECL(
1345 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1346 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1347
1348static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1349 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1350
1351/* InBound9 Source */ /* MX-A4 [6:4] */
1352static const char * const rt5677_inbound9_src[] = {
1353 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1354 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1355};
1356
1357static SOC_ENUM_SINGLE_DECL(
1358 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1359 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1360
1361static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1362 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1363
1364/* VAD Source */ /* MX-9F [6:4] */
1365static const char * const rt5677_vad_src[] = {
1366 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1367 "STO3 ADC MIX L"
1368};
1369
1370static SOC_ENUM_SINGLE_DECL(
1371 rt5677_vad_enum, RT5677_VAD_CTRL4,
1372 RT5677_VAD_SRC_SFT, rt5677_vad_src);
1373
1374static const struct snd_kcontrol_new rt5677_vad_src_mux =
1375 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1376
1377/* Sidetone Source */ /* MX-13 [11:9] */
1378static const char * const rt5677_sidetone_src[] = {
1379 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1380};
1381
1382static SOC_ENUM_SINGLE_DECL(
1383 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
1384 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
1385
1386static const struct snd_kcontrol_new rt5677_sidetone_mux =
1387 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
1388
1389/* DAC1/2 Source */ /* MX-15 [1:0] */
1390static const char * const rt5677_dac12_src[] = {
1391 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1392};
1393
1394static SOC_ENUM_SINGLE_DECL(
1395 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
1396 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
1397
1398static const struct snd_kcontrol_new rt5677_dac12_mux =
1399 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
1400
1401/* DAC3 Source */ /* MX-15 [5:4] */
1402static const char * const rt5677_dac3_src[] = {
1403 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
1404};
1405
1406static SOC_ENUM_SINGLE_DECL(
1407 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
1408 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
1409
1410static const struct snd_kcontrol_new rt5677_dac3_mux =
1411 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
1412
1b7fd76a 1413/* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
0e826e86
OC		 1414static const char * const rt5677_pdm_src[] = {
1415 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1416};
1417
1418static SOC_ENUM_SINGLE_DECL(
1419 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
1420 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
1421
1422static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
1b7fd76a 1423 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
0e826e86
OC		 1424
1425static SOC_ENUM_SINGLE_DECL(
1426 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
1427 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
1428
1429static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
1b7fd76a 1430 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
0e826e86
OC		 1431
1432static SOC_ENUM_SINGLE_DECL(
1433 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
1434 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
1435
1436static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
1b7fd76a 1437 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
0e826e86
OC		 1438
1439static SOC_ENUM_SINGLE_DECL(
1440 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
1441 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
1442
1443static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
1b7fd76a 1444 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
0e826e86
OC		 1445
1446/* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0]*/
1447static const char * const rt5677_if12_adc1_src[] = {
1448 "STO1 ADC MIX", "OB01", "VAD ADC"
1449};
1450
1451static SOC_ENUM_SINGLE_DECL(
1452 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
1453 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
1454
1455static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
1b7fd76a 1456 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
0e826e86
OC		 1457
1458static SOC_ENUM_SINGLE_DECL(
1459 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
1460 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
1461
1462static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
1b7fd76a 1463 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
0e826e86
OC		 1464
1465static SOC_ENUM_SINGLE_DECL(
1466 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
1467 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
1468
1469static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
1b7fd76a 1470 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
0e826e86
OC		 1471
1472/* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
1473static const char * const rt5677_if12_adc2_src[] = {
1474 "STO2 ADC MIX", "OB23"
1475};
1476
1477static SOC_ENUM_SINGLE_DECL(
1478 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
1479 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
1480
1481static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
1b7fd76a 1482 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
0e826e86
OC		 1483
1484static SOC_ENUM_SINGLE_DECL(
1485 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
1486 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
1487
1488static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
1b7fd76a 1489 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
0e826e86
OC		 1490
1491static SOC_ENUM_SINGLE_DECL(
1492 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
1493 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
1494
1495static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
1b7fd76a 1496 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
0e826e86
OC		 1497
1498/* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
1499static const char * const rt5677_if12_adc3_src[] = {
1500 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
1501};
1502
1503static SOC_ENUM_SINGLE_DECL(
1504 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
1505 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
1506
1507static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
1b7fd76a 1508 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
0e826e86
OC		 1509
1510static SOC_ENUM_SINGLE_DECL(
1511 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
1512 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
1513
1514static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
1b7fd76a 1515 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
0e826e86
OC		 1516
1517static SOC_ENUM_SINGLE_DECL(
1518 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
1519 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
1520
1521static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
1b7fd76a 1522 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
0e826e86
OC		 1523
1524/* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
1525static const char * const rt5677_if12_adc4_src[] = {
1526 "STO4 ADC MIX", "OB67", "OB01"
1527};
1528
1529static SOC_ENUM_SINGLE_DECL(
1530 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
1531 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
1532
1533static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
1b7fd76a 1534 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
0e826e86
OC		 1535
1536static SOC_ENUM_SINGLE_DECL(
1537 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
1538 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
1539
1540static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
1b7fd76a 1541 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
0e826e86
OC		 1542
1543static SOC_ENUM_SINGLE_DECL(
1544 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
1545 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
1546
1547static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
1b7fd76a 1548 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
0e826e86
OC		 1549
1550/* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4]*/
1551static const char * const rt5677_if34_adc_src[] = {
1552 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
1553 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
1554};
1555
1556static SOC_ENUM_SINGLE_DECL(
1557 rt5677_if3_adc_enum, RT5677_IF3_DATA,
1558 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
1559
1560static const struct snd_kcontrol_new rt5677_if3_adc_mux =
1b7fd76a 1561 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
0e826e86
OC		 1562
1563static SOC_ENUM_SINGLE_DECL(
1564 rt5677_if4_adc_enum, RT5677_IF4_DATA,
1565 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
1566
1567static const struct snd_kcontrol_new rt5677_if4_adc_mux =
1b7fd76a 1568 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
0e826e86
OC		 1569
1570static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
1571 struct snd_kcontrol *kcontrol, int event)
1572{
1573 struct snd_soc_codec *codec = w->codec;
1574 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1575
1576 switch (event) {
1577 case SND_SOC_DAPM_POST_PMU:
1578 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1579 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
1580 break;
1581
1582 case SND_SOC_DAPM_PRE_PMD:
1583 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1584 RT5677_PWR_BST1_P, 0);
1585 break;
1586
1587 default:
1588 return 0;
1589 }
1590
1591 return 0;
1592}
1593
1594static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
1595 struct snd_kcontrol *kcontrol, int event)
1596{
1597 struct snd_soc_codec *codec = w->codec;
1598 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1599
1600 switch (event) {
1601 case SND_SOC_DAPM_POST_PMU:
1602 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1603 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
1604 break;
1605
1606 case SND_SOC_DAPM_PRE_PMD:
1607 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1608 RT5677_PWR_BST2_P, 0);
1609 break;
1610
1611 default:
1612 return 0;
1613 }
1614
1615 return 0;
1616}
1617
1618static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
1619 struct snd_kcontrol *kcontrol, int event)
1620{
1621 struct snd_soc_codec *codec = w->codec;
1622 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1623
1624 switch (event) {
1625 case SND_SOC_DAPM_POST_PMU:
1626 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
1627 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
1628 break;
1629 default:
1630 return 0;
1631 }
1632
1633 return 0;
1634}
1635
1636static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
1637 struct snd_kcontrol *kcontrol, int event)
1638{
1639 struct snd_soc_codec *codec = w->codec;
1640 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1641
1642 switch (event) {
1643 case SND_SOC_DAPM_POST_PMU:
1644 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
1645 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
1646 break;
1647 default:
1648 return 0;
1649 }
1650
1651 return 0;
1652}
1653
1654static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
1655 struct snd_kcontrol *kcontrol, int event)
1656{
1657 struct snd_soc_codec *codec = w->codec;
1658 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1659
1660 switch (event) {
1661 case SND_SOC_DAPM_POST_PMU:
1662 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1663 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
1664 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
1665 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
1666 break;
f58c3b91
OC		 1667
1668 case SND_SOC_DAPM_PRE_PMD:
1669 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1670 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
1671 RT5677_PWR_CLK_MB, 0);
1672 break;
1673
0e826e86
OC		 1674 default:
1675 return 0;
1676 }
1677
1678 return 0;
1679}
1680
1681static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
1682 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
1683 0, rt5677_set_pll1_event, SND_SOC_DAPM_POST_PMU),
1684 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
1685 0, rt5677_set_pll2_event, SND_SOC_DAPM_POST_PMU),
1686
1687 /* Input Side */
1688 /* micbias */
3d0c03d9 1689 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
f58c3b91
OC		 1690 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
1691 SND_SOC_DAPM_POST_PMU),
0e826e86
OC		 1692
1693 /* Input Lines */
1694 SND_SOC_DAPM_INPUT("DMIC L1"),
1695 SND_SOC_DAPM_INPUT("DMIC R1"),
1696 SND_SOC_DAPM_INPUT("DMIC L2"),
1697 SND_SOC_DAPM_INPUT("DMIC R2"),
1698 SND_SOC_DAPM_INPUT("DMIC L3"),
1699 SND_SOC_DAPM_INPUT("DMIC R3"),
1700 SND_SOC_DAPM_INPUT("DMIC L4"),
1701 SND_SOC_DAPM_INPUT("DMIC R4"),
1702
1703 SND_SOC_DAPM_INPUT("IN1P"),
1704 SND_SOC_DAPM_INPUT("IN1N"),
1705 SND_SOC_DAPM_INPUT("IN2P"),
1706 SND_SOC_DAPM_INPUT("IN2N"),
1707
1708 SND_SOC_DAPM_INPUT("Haptic Generator"),
1709
2d15d974
BL		 1710 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1711 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1712 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1713 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1714
1715 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
1716 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
1717 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
1718 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
1719 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
1720 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
1721 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
1722 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
0e826e86
OC		 1723
1724 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1725 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1726
1727 /* Boost */
1728 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
1729 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
1730 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1731 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
1732 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
1733 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1734
1735 /* ADCs */
1736 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
1737 0, 0),
1738 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
1739 0, 0),
1740 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
1741
1742 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
1743 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
1744 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
1745 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
1746 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
1747 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
1748 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
1749 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
1750
1751 /* ADC Mux */
1752 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1753 &rt5677_sto1_dmic_mux),
1754 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1755 &rt5677_sto1_adc1_mux),
1756 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1757 &rt5677_sto1_adc2_mux),
1758 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
1759 &rt5677_sto2_dmic_mux),
1760 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1761 &rt5677_sto2_adc1_mux),
1762 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1763 &rt5677_sto2_adc2_mux),
1764 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
1765 &rt5677_sto2_adc_lr_mux),
1766 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
1767 &rt5677_sto3_dmic_mux),
1768 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1769 &rt5677_sto3_adc1_mux),
1770 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1771 &rt5677_sto3_adc2_mux),
1772 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
1773 &rt5677_sto4_dmic_mux),
1774 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1775 &rt5677_sto4_adc1_mux),
1776 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1777 &rt5677_sto4_adc2_mux),
1778 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1779 &rt5677_mono_dmic_l_mux),
1780 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1781 &rt5677_mono_dmic_r_mux),
1782 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
1783 &rt5677_mono_adc2_l_mux),
1784 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
1785 &rt5677_mono_adc1_l_mux),
1786 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
1787 &rt5677_mono_adc1_r_mux),
1788 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
1789 &rt5677_mono_adc2_r_mux),
1790
1791 /* ADC Mixer */
1792 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
1793 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
1794 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
1795 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
1796 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
1797 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
1798 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
1799 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
1800 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1801 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
1802 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
1803 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
1804 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
1805 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
1806 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
1807 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
1808 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
1809 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
1810 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
1811 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
1812 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
1813 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
1814 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
1815 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
1816 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
1817 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1818 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1819 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
1820 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
1821 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1822 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1823 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
1824
1825 /* ADC PGA */
1826 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1827 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1828 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1829 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1830 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1831 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1832 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1833 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1834 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1835 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1836 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1837 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1838 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1839 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1840 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1841 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1842 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1843 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1844
1845 /* DSP */
1846 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
1847 &rt5677_ib9_src_mux),
1848 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
1849 &rt5677_ib8_src_mux),
1850 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
1851 &rt5677_ib7_src_mux),
1852 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
1853 &rt5677_ib6_src_mux),
1854 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
1855 &rt5677_ib45_src_mux),
1856 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
1857 &rt5677_ib23_src_mux),
1858 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
1859 &rt5677_ib01_src_mux),
1860 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
1861 &rt5677_ib45_bypass_src_mux),
1862 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
1863 &rt5677_ib23_bypass_src_mux),
1864 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
1865 &rt5677_ib01_bypass_src_mux),
1866 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
1867 &rt5677_ob23_bypass_src_mux),
1868 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
1869 &rt5677_ob01_bypass_src_mux),
1870
1871 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
1872 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
1873
1874 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
1875 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
1876 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
1877 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
1878 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
1879 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
1880
1881 /* Digital Interface */
1882 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
1883 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
1884 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1885 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1886 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1887 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1888 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1889 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
1890 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
1891 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
1892 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
1893 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
1894 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
1895 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
1896 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1897 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1898 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1899 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1900
1901 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
1902 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
1903 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1904 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1905 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1906 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1907 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1908 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
1909 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
1910 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
1911 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
1912 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
1913 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
1914 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
1915 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1916 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1917 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1918 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1919
1920 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
1921 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
1922 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1923 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1924 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1925 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1926 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1927 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1928
1929 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
1930 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
1931 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1932 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1933 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1934 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1935 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1936 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1937
1938 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
1939 RT5677_PWR_SLB_BIT, 0, NULL, 0),
1940 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1941 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1942 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1943 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1944 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1945 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
1946 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
1947 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
1948 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
1949 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
1950 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
1951 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
1952 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1953 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1954 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1955 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1956
1957 /* Digital Interface Select */
1958 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1959 &rt5677_if1_adc1_mux),
1960 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1961 &rt5677_if1_adc2_mux),
1962 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
1963 &rt5677_if1_adc3_mux),
1964 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
1965 &rt5677_if1_adc4_mux),
1966 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1967 &rt5677_if2_adc1_mux),
1968 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1969 &rt5677_if2_adc2_mux),
1970 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
1971 &rt5677_if2_adc3_mux),
1972 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
1973 &rt5677_if2_adc4_mux),
1974 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
1975 &rt5677_if3_adc_mux),
1976 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
1977 &rt5677_if4_adc_mux),
1978 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
1979 &rt5677_slb_adc1_mux),
1980 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
1981 &rt5677_slb_adc2_mux),
1982 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
1983 &rt5677_slb_adc3_mux),
1984 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
1985 &rt5677_slb_adc4_mux),
1986
1987 /* Audio Interface */
1988 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1989 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1990 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1991 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1992 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1993 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1994 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
1995 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
1996 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
1997 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
1998
1999 /* Sidetone Mux */
2000 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
2001 &rt5677_sidetone_mux),
90bdbb46
OC		 2002 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
2003 RT5677_ST_EN_SFT, 0, NULL, 0),
2004
0e826e86
OC		 2005 /* VAD Mux*/
2006 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
2007 &rt5677_vad_src_mux),
2008
2009 /* Tensilica DSP */
2010 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
2011 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
2012 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
2013 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
2014 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
2015 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
2016 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
2017 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
2018 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
2019 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
2020 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
2021 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
2022 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
2023
2024 /* Output Side */
2025 /* DAC mixer before sound effect */
2026 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2027 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
2028 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2029 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
2030 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
2031
2032 /* DAC Mux */
2033 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
2034 &rt5677_dac1_mux),
2035 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
2036 &rt5677_adda1_mux),
2037 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
2038 &rt5677_dac12_mux),
2039 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
2040 &rt5677_dac3_mux),
2041
2042 /* DAC2 channel Mux */
2043 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2044 &rt5677_dac2_l_mux),
2045 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2046 &rt5677_dac2_r_mux),
2047
2048 /* DAC3 channel Mux */
2049 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
2050 &rt5677_dac3_l_mux),
2051 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
2052 &rt5677_dac3_r_mux),
2053
2054 /* DAC4 channel Mux */
2055 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
2056 &rt5677_dac4_l_mux),
2057 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
2058 &rt5677_dac4_r_mux),
2059
2060 /* DAC Mixer */
2061 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
2062 RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
2063 SND_SOC_DAPM_SUPPLY("dac mono left filter", RT5677_PWR_DIG2,
2064 RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
2065 SND_SOC_DAPM_SUPPLY("dac mono right filter", RT5677_PWR_DIG2,
2066 RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
2067
2068 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2069 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
2070 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2071 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
2072 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2073 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
2074 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2075 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
2076 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
2077 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
2078 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
2079 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
2080 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
2081 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
2082 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
2083 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
2084 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2085 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2086 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2087 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2088
2089 /* DACs */
2090 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
2091 RT5677_PWR_DAC1_BIT, 0),
2092 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
2093 RT5677_PWR_DAC2_BIT, 0),
2094 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
2095 RT5677_PWR_DAC3_BIT, 0),
2096
2097 /* PDM */
2098 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
2099 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
2100 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
2101 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
2102
2103 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
2104 1, &rt5677_pdm1_l_mux),
2105 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
2106 1, &rt5677_pdm1_r_mux),
2107 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
2108 1, &rt5677_pdm2_l_mux),
2109 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
2110 1, &rt5677_pdm2_r_mux),
2111
2112 SND_SOC_DAPM_PGA_S("LOUT1 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
2113 0, NULL, 0),
2114 SND_SOC_DAPM_PGA_S("LOUT2 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
2115 0, NULL, 0),
2116 SND_SOC_DAPM_PGA_S("LOUT3 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
2117 0, NULL, 0),
2118
2119 /* Output Lines */
2120 SND_SOC_DAPM_OUTPUT("LOUT1"),
2121 SND_SOC_DAPM_OUTPUT("LOUT2"),
2122 SND_SOC_DAPM_OUTPUT("LOUT3"),
2123 SND_SOC_DAPM_OUTPUT("PDM1L"),
2124 SND_SOC_DAPM_OUTPUT("PDM1R"),
2125 SND_SOC_DAPM_OUTPUT("PDM2L"),
2126 SND_SOC_DAPM_OUTPUT("PDM2R"),
2127};
2128
2129static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
2130 { "DMIC1", NULL, "DMIC L1" },
2131 { "DMIC1", NULL, "DMIC R1" },
2132 { "DMIC2", NULL, "DMIC L2" },
2133 { "DMIC2", NULL, "DMIC R2" },
2134 { "DMIC3", NULL, "DMIC L3" },
2135 { "DMIC3", NULL, "DMIC R3" },
2136 { "DMIC4", NULL, "DMIC L4" },
2137 { "DMIC4", NULL, "DMIC R4" },
2138
2139 { "DMIC L1", NULL, "DMIC CLK" },
2140 { "DMIC R1", NULL, "DMIC CLK" },
2141 { "DMIC L2", NULL, "DMIC CLK" },
2142 { "DMIC R2", NULL, "DMIC CLK" },
2143 { "DMIC L3", NULL, "DMIC CLK" },
2144 { "DMIC R3", NULL, "DMIC CLK" },
2145 { "DMIC L4", NULL, "DMIC CLK" },
2146 { "DMIC R4", NULL, "DMIC CLK" },
2147
2d15d974
BL		 2148 { "DMIC L1", NULL, "DMIC1 power" },
2149 { "DMIC R1", NULL, "DMIC1 power" },
2150 { "DMIC L3", NULL, "DMIC3 power" },
2151 { "DMIC R3", NULL, "DMIC3 power" },
2152 { "DMIC L4", NULL, "DMIC4 power" },
2153 { "DMIC R4", NULL, "DMIC4 power" },
2154
0e826e86
OC		 2155 { "BST1", NULL, "IN1P" },
2156 { "BST1", NULL, "IN1N" },
2157 { "BST2", NULL, "IN2P" },
2158 { "BST2", NULL, "IN2N" },
2159
22e51345
BL		 2160 { "IN1P", NULL, "MICBIAS1" },
2161 { "IN1N", NULL, "MICBIAS1" },
2162 { "IN2P", NULL, "MICBIAS1" },
2163 { "IN2N", NULL, "MICBIAS1" },
0e826e86
OC		 2164
2165 { "ADC 1", NULL, "BST1" },
2166 { "ADC 1", NULL, "ADC 1 power" },
2167 { "ADC 1", NULL, "ADC1 clock" },
2168 { "ADC 2", NULL, "BST2" },
2169 { "ADC 2", NULL, "ADC 2 power" },
2170 { "ADC 2", NULL, "ADC2 clock" },
2171
2172 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2173 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
2174 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
2175 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
2176
2177 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
2178 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
2179 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
2180 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
2181
2182 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
2183 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
2184 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
2185 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
2186
2187 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
2188 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
2189 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
2190 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
2191
2192 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
2193 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
2194 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
2195 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
2196
2197 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
2198 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
2199 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
2200 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
2201
2202 { "ADC 1_2", NULL, "ADC 1" },
2203 { "ADC 1_2", NULL, "ADC 2" },
2204
2205 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2206 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2207 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2208
2209 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2210 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2211 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2212
2213 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2214 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2215 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2216
2217 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2218 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
2219 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2220
2221 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2222 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2223 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2224
2225 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2226 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2227 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2228
2229 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2230 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2231 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
2232
2233 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2234 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2235 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
2236
2237 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
2238 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
2239 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2240
2241 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
2242 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
2243 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2244
2245 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
2246 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
2247 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2248
2249 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
2250 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
2251 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2252
2253 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
2254 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
2255 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
2256 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
2257
2258 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
2259 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
2260 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2261
2262 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
2263 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
2264 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2265
2266 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
2267 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
2268
2269 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
2270 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
2271 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
2272 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
2273
2274 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
2275 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
2276
2277 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
2278 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
2279
2280 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
2281 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
2282 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
2283
2284 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
2285 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
2286 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
2287
2288 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
2289 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
2290
2291 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
2292 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
2293 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
2294 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
2295
2296 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
2297 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
2298 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
2299
2300 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
2301 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
2302 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
2303
2304 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
2305 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
2306
2307 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
2308 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
2309 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
2310 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
2311
2312 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
2313 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
2314 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
2315
2316 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
2317 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
2318 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
2319
2320 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
2321 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
2322
2323 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
2324 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
2325 { "Mono ADC MIXL", NULL, "adc mono left filter" },
2326 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
2327
2328 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
2329 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
2330 { "Mono ADC MIXR", NULL, "adc mono right filter" },
2331 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
2332
2333 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
2334 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
2335
2336 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2337 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
2338 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
2339 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2340 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2341
2342 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2343 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2344 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2345
2346 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2347 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2348
2349 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2350 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2351 { "IF1 ADC3 Mux", "OB45", "OB45" },
2352
2353 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2354 { "IF1 ADC4 Mux", "OB67", "OB67" },
2355 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2356
2357 { "AIF1TX", NULL, "I2S1" },
2358 { "AIF1TX", NULL, "IF1 ADC1 Mux" },
2359 { "AIF1TX", NULL, "IF1 ADC2 Mux" },
2360 { "AIF1TX", NULL, "IF1 ADC3 Mux" },
2361 { "AIF1TX", NULL, "IF1 ADC4 Mux" },
2362
2363 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2364 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2365 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2366
2367 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2368 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2369
2370 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2371 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2372 { "IF2 ADC3 Mux", "OB45", "OB45" },
2373
2374 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2375 { "IF2 ADC4 Mux", "OB67", "OB67" },
2376 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2377
2378 { "AIF2TX", NULL, "I2S2" },
2379 { "AIF2TX", NULL, "IF2 ADC1 Mux" },
2380 { "AIF2TX", NULL, "IF2 ADC2 Mux" },
2381 { "AIF2TX", NULL, "IF2 ADC3 Mux" },
2382 { "AIF2TX", NULL, "IF2 ADC4 Mux" },
2383
2384 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2385 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2386 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2387 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2388 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
2389 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
2390 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
2391 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
2392
2393 { "AIF3TX", NULL, "I2S3" },
2394 { "AIF3TX", NULL, "IF3 ADC Mux" },
2395
2396 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2397 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2398 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2399 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2400 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
2401 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
2402 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
2403 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
2404
2405 { "AIF4TX", NULL, "I2S4" },
2406 { "AIF4TX", NULL, "IF4 ADC Mux" },
2407
2408 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2409 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2410 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2411
2412 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2413 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2414
2415 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2416 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2417 { "SLB ADC3 Mux", "OB45", "OB45" },
2418
2419 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2420 { "SLB ADC4 Mux", "OB67", "OB67" },
2421 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2422
2423 { "SLBTX", NULL, "SLB" },
2424 { "SLBTX", NULL, "SLB ADC1 Mux" },
2425 { "SLBTX", NULL, "SLB ADC2 Mux" },
2426 { "SLBTX", NULL, "SLB ADC3 Mux" },
2427 { "SLBTX", NULL, "SLB ADC4 Mux" },
2428
2429 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
2430 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
2431 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
2432 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2433 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
2434
2435 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
2436 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
2437
2438 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
2439 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
2440 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
2441 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2442 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
2443 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
2444
2445 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
2446 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
2447
2448 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
2449 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
2450 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
2451 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2452 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
2453
2454 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
2455 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
2456
2457 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6" },
2458 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6" },
2459 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
2460 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
2461 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
2462 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2463 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2464 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2465
2466 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7" },
2467 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7" },
2468 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
2469 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
2470 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
2471 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
2472 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
2473 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
2474
2475 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2476 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2477 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2478 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
2479 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
2480 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
2481
2482 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
2483 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
2484 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
2485 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
2486 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
2487 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
2488 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
2489
2490 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2491 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2492 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2493 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
2494 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
2495 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
2496 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
2497
2498 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2499 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2500 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2501 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
2502 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
2503 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
2504 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
2505
2506 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2507 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2508 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2509 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
2510 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
2511 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
2512 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
2513
2514 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2515 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2516 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2517 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
2518 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
2519 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
2520 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
2521
2522 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2523 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2524 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2525 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
2526 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
2527 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
2528 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
2529
2530 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2531 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2532 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2533 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
2534 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
2535 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
2536 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
2537
2538 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
2539 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
2540 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
2541 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
2542
2543 { "OutBound2", NULL, "OB23 Bypass Mux" },
2544 { "OutBound3", NULL, "OB23 Bypass Mux" },
2545 { "OutBound4", NULL, "OB4 MIX" },
2546 { "OutBound5", NULL, "OB5 MIX" },
2547 { "OutBound6", NULL, "OB6 MIX" },
2548 { "OutBound7", NULL, "OB7 MIX" },
2549
2550 { "OB45", NULL, "OutBound4" },
2551 { "OB45", NULL, "OutBound5" },
2552 { "OB67", NULL, "OutBound6" },
2553 { "OB67", NULL, "OutBound7" },
2554
2555 { "IF1 DAC0", NULL, "AIF1RX" },
2556 { "IF1 DAC1", NULL, "AIF1RX" },
2557 { "IF1 DAC2", NULL, "AIF1RX" },
2558 { "IF1 DAC3", NULL, "AIF1RX" },
2559 { "IF1 DAC4", NULL, "AIF1RX" },
2560 { "IF1 DAC5", NULL, "AIF1RX" },
2561 { "IF1 DAC6", NULL, "AIF1RX" },
2562 { "IF1 DAC7", NULL, "AIF1RX" },
2563 { "IF1 DAC0", NULL, "I2S1" },
2564 { "IF1 DAC1", NULL, "I2S1" },
2565 { "IF1 DAC2", NULL, "I2S1" },
2566 { "IF1 DAC3", NULL, "I2S1" },
2567 { "IF1 DAC4", NULL, "I2S1" },
2568 { "IF1 DAC5", NULL, "I2S1" },
2569 { "IF1 DAC6", NULL, "I2S1" },
2570 { "IF1 DAC7", NULL, "I2S1" },
2571
2572 { "IF1 DAC01", NULL, "IF1 DAC0" },
2573 { "IF1 DAC01", NULL, "IF1 DAC1" },
2574 { "IF1 DAC23", NULL, "IF1 DAC2" },
2575 { "IF1 DAC23", NULL, "IF1 DAC3" },
2576 { "IF1 DAC45", NULL, "IF1 DAC4" },
2577 { "IF1 DAC45", NULL, "IF1 DAC5" },
2578 { "IF1 DAC67", NULL, "IF1 DAC6" },
2579 { "IF1 DAC67", NULL, "IF1 DAC7" },
2580
2581 { "IF2 DAC0", NULL, "AIF2RX" },
2582 { "IF2 DAC1", NULL, "AIF2RX" },
2583 { "IF2 DAC2", NULL, "AIF2RX" },
2584 { "IF2 DAC3", NULL, "AIF2RX" },
2585 { "IF2 DAC4", NULL, "AIF2RX" },
2586 { "IF2 DAC5", NULL, "AIF2RX" },
2587 { "IF2 DAC6", NULL, "AIF2RX" },
2588 { "IF2 DAC7", NULL, "AIF2RX" },
2589 { "IF2 DAC0", NULL, "I2S2" },
2590 { "IF2 DAC1", NULL, "I2S2" },
2591 { "IF2 DAC2", NULL, "I2S2" },
2592 { "IF2 DAC3", NULL, "I2S2" },
2593 { "IF2 DAC4", NULL, "I2S2" },
2594 { "IF2 DAC5", NULL, "I2S2" },
2595 { "IF2 DAC6", NULL, "I2S2" },
2596 { "IF2 DAC7", NULL, "I2S2" },
2597
2598 { "IF2 DAC01", NULL, "IF2 DAC0" },
2599 { "IF2 DAC01", NULL, "IF2 DAC1" },
2600 { "IF2 DAC23", NULL, "IF2 DAC2" },
2601 { "IF2 DAC23", NULL, "IF2 DAC3" },
2602 { "IF2 DAC45", NULL, "IF2 DAC4" },
2603 { "IF2 DAC45", NULL, "IF2 DAC5" },
2604 { "IF2 DAC67", NULL, "IF2 DAC6" },
2605 { "IF2 DAC67", NULL, "IF2 DAC7" },
2606
2607 { "IF3 DAC", NULL, "AIF3RX" },
2608 { "IF3 DAC", NULL, "I2S3" },
2609
2610 { "IF4 DAC", NULL, "AIF4RX" },
2611 { "IF4 DAC", NULL, "I2S4" },
2612
2613 { "IF3 DAC L", NULL, "IF3 DAC" },
2614 { "IF3 DAC R", NULL, "IF3 DAC" },
2615
2616 { "IF4 DAC L", NULL, "IF4 DAC" },
2617 { "IF4 DAC R", NULL, "IF4 DAC" },
2618
2619 { "SLB DAC0", NULL, "SLBRX" },
2620 { "SLB DAC1", NULL, "SLBRX" },
2621 { "SLB DAC2", NULL, "SLBRX" },
2622 { "SLB DAC3", NULL, "SLBRX" },
2623 { "SLB DAC4", NULL, "SLBRX" },
2624 { "SLB DAC5", NULL, "SLBRX" },
2625 { "SLB DAC6", NULL, "SLBRX" },
2626 { "SLB DAC7", NULL, "SLBRX" },
2627 { "SLB DAC0", NULL, "SLB" },
2628 { "SLB DAC1", NULL, "SLB" },
2629 { "SLB DAC2", NULL, "SLB" },
2630 { "SLB DAC3", NULL, "SLB" },
2631 { "SLB DAC4", NULL, "SLB" },
2632 { "SLB DAC5", NULL, "SLB" },
2633 { "SLB DAC6", NULL, "SLB" },
2634 { "SLB DAC7", NULL, "SLB" },
2635
2636 { "SLB DAC01", NULL, "SLB DAC0" },
2637 { "SLB DAC01", NULL, "SLB DAC1" },
2638 { "SLB DAC23", NULL, "SLB DAC2" },
2639 { "SLB DAC23", NULL, "SLB DAC3" },
2640 { "SLB DAC45", NULL, "SLB DAC4" },
2641 { "SLB DAC45", NULL, "SLB DAC5" },
2642 { "SLB DAC67", NULL, "SLB DAC6" },
2643 { "SLB DAC67", NULL, "SLB DAC7" },
2644
2645 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2646 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2647 { "ADDA1 Mux", "OB 67", "OB67" },
2648
2649 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
2650 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
2651 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
2652 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
2653 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
2654 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
2655
2656 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
2657 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
2658 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
2659 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
2660 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
2661 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
2662
2663 { "DAC1 FS", NULL, "DAC1 MIXL" },
2664 { "DAC1 FS", NULL, "DAC1 MIXR" },
2665
2666 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2" },
2667 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2" },
2668 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
2669 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
2670 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
2671 { "DAC2 L Mux", "OB 2", "OutBound2" },
2672
2673 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3" },
2674 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3" },
2675 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
2676 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
2677 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
2678 { "DAC2 R Mux", "OB 3", "OutBound3" },
2679 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
2680 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
2681
2682 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4" },
2683 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4" },
2684 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
2685 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
2686 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
2687 { "DAC3 L Mux", "OB 4", "OutBound4" },
2688
2689 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC4" },
2690 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC4" },
2691 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
2692 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
2693 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
2694 { "DAC3 R Mux", "OB 5", "OutBound5" },
2695
2696 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6" },
2697 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6" },
2698 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
2699 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
2700 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
2701 { "DAC4 L Mux", "OB 6", "OutBound6" },
2702
2703 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7" },
2704 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7" },
2705 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
2706 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
2707 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
2708 { "DAC4 R Mux", "OB 7", "OutBound7" },
2709
2710 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
2711 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
2712 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
2713 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
2714 { "Sidetone Mux", "ADC1", "ADC 1" },
2715 { "Sidetone Mux", "ADC2", "ADC 2" },
90bdbb46 2716 { "Sidetone Mux", NULL, "Sidetone Power" },
0e826e86
OC		 2717
2718 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
2719 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
2720 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
2721 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
2722 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
2723 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
2724 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
2725 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
2726 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
2727 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
2728
2729 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
2730 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
2731 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
2732 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
2733 { "Mono DAC MIXL", NULL, "dac mono left filter" },
2734 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
2735 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
2736 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
2737 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
2738 { "Mono DAC MIXR", NULL, "dac mono right filter" },
2739
2740 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2741 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
2742 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
2743 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
2744 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2745 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
2746 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
2747 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
2748
2749 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2750 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
2751 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
2752 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
2753 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2754 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
2755 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
2756 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
2757
2758 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
2759 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
2760 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
2761 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
2762 { "DD1 MIX", NULL, "DD1 MIXL" },
2763 { "DD1 MIX", NULL, "DD1 MIXR" },
2764 { "DD2 MIX", NULL, "DD2 MIXL" },
2765 { "DD2 MIX", NULL, "DD2 MIXR" },
2766
2767 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
2768 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
2769 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
2770 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
2771
2772 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2773 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2774 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
2775 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
2776
2777 { "DAC 1", NULL, "DAC12 SRC Mux" },
2778 { "DAC 1", NULL, "PLL1", is_sys_clk_from_pll },
2779 { "DAC 2", NULL, "DAC12 SRC Mux" },
2780 { "DAC 2", NULL, "PLL1", is_sys_clk_from_pll },
2781 { "DAC 3", NULL, "DAC3 SRC Mux" },
2782 { "DAC 3", NULL, "PLL1", is_sys_clk_from_pll },
2783
2784 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
2785 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
2786 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
2787 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
2788 { "PDM1 L Mux", NULL, "PDM1 Power" },
2789 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
2790 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
2791 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
2792 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
2793 { "PDM1 R Mux", NULL, "PDM1 Power" },
2794 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
2795 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
2796 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
2797 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
2798 { "PDM2 L Mux", NULL, "PDM2 Power" },
2799 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
2800 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
2801 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
2802 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
2803 { "PDM2 R Mux", NULL, "PDM2 Power" },
2804
2805 { "LOUT1 amp", NULL, "DAC 1" },
2806 { "LOUT2 amp", NULL, "DAC 2" },
2807 { "LOUT3 amp", NULL, "DAC 3" },
2808
2809 { "LOUT1", NULL, "LOUT1 amp" },
2810 { "LOUT2", NULL, "LOUT2 amp" },
2811 { "LOUT3", NULL, "LOUT3 amp" },
2812
2813 { "PDM1L", NULL, "PDM1 L Mux" },
2814 { "PDM1R", NULL, "PDM1 R Mux" },
2815 { "PDM2L", NULL, "PDM2 L Mux" },
2816 { "PDM2R", NULL, "PDM2 R Mux" },
2817};
2818
2d15d974
BL		 2819static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
2820 { "DMIC L2", NULL, "DMIC1 power" },
2821 { "DMIC R2", NULL, "DMIC1 power" },
2822};
2823
2824static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
2825 { "DMIC L2", NULL, "DMIC2 power" },
2826 { "DMIC R2", NULL, "DMIC2 power" },
2827};
2828
0e826e86
OC		 2829static int rt5677_hw_params(struct snd_pcm_substream *substream,
2830 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2831{
2832 struct snd_soc_codec *codec = dai->codec;
2833 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2834 unsigned int val_len = 0, val_clk, mask_clk;
2835 int pre_div, bclk_ms, frame_size;
2836
2837 rt5677->lrck[dai->id] = params_rate(params);
30f14b43 2838 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
0e826e86
OC		 2839 if (pre_div < 0) {
2840 dev_err(codec->dev, "Unsupported clock setting\n");
2841 return -EINVAL;
2842 }
2843 frame_size = snd_soc_params_to_frame_size(params);
2844 if (frame_size < 0) {
2845 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2846 return -EINVAL;
2847 }
2848 bclk_ms = frame_size > 32;
2849 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
2850
2851 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2852 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
2853 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2854 bclk_ms, pre_div, dai->id);
2855
2856 switch (params_width(params)) {
2857 case 16:
2858 break;
2859 case 20:
2860 val_len |= RT5677_I2S_DL_20;
2861 break;
2862 case 24:
2863 val_len |= RT5677_I2S_DL_24;
2864 break;
2865 case 8:
2866 val_len |= RT5677_I2S_DL_8;
2867 break;
2868 default:
2869 return -EINVAL;
2870 }
2871
2872 switch (dai->id) {
2873 case RT5677_AIF1:
2874 mask_clk = RT5677_I2S_PD1_MASK;
2875 val_clk = pre_div << RT5677_I2S_PD1_SFT;
2876 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
2877 RT5677_I2S_DL_MASK, val_len);
2878 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2879 mask_clk, val_clk);
2880 break;
2881 case RT5677_AIF2:
2882 mask_clk = RT5677_I2S_PD2_MASK;
2883 val_clk = pre_div << RT5677_I2S_PD2_SFT;
2884 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
2885 RT5677_I2S_DL_MASK, val_len);
2886 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2887 mask_clk, val_clk);
2888 break;
2889 case RT5677_AIF3:
2890 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
2891 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
2892 pre_div << RT5677_I2S_PD3_SFT;
2893 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
2894 RT5677_I2S_DL_MASK, val_len);
2895 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2896 mask_clk, val_clk);
2897 break;
2898 case RT5677_AIF4:
2899 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
2900 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
2901 pre_div << RT5677_I2S_PD4_SFT;
2902 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
2903 RT5677_I2S_DL_MASK, val_len);
2904 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2905 mask_clk, val_clk);
2906 break;
2907 default:
2908 break;
2909 }
2910
2911 return 0;
2912}
2913
2914static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2915{
2916 struct snd_soc_codec *codec = dai->codec;
2917 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2918 unsigned int reg_val = 0;
2919
2920 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2921 case SND_SOC_DAIFMT_CBM_CFM:
2922 rt5677->master[dai->id] = 1;
2923 break;
2924 case SND_SOC_DAIFMT_CBS_CFS:
2925 reg_val |= RT5677_I2S_MS_S;
2926 rt5677->master[dai->id] = 0;
2927 break;
2928 default:
2929 return -EINVAL;
2930 }
2931
2932 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2933 case SND_SOC_DAIFMT_NB_NF:
2934 break;
2935 case SND_SOC_DAIFMT_IB_NF:
2936 reg_val |= RT5677_I2S_BP_INV;
2937 break;
2938 default:
2939 return -EINVAL;
2940 }
2941
2942 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2943 case SND_SOC_DAIFMT_I2S:
2944 break;
2945 case SND_SOC_DAIFMT_LEFT_J:
2946 reg_val |= RT5677_I2S_DF_LEFT;
2947 break;
2948 case SND_SOC_DAIFMT_DSP_A:
2949 reg_val |= RT5677_I2S_DF_PCM_A;
2950 break;
2951 case SND_SOC_DAIFMT_DSP_B:
2952 reg_val |= RT5677_I2S_DF_PCM_B;
2953 break;
2954 default:
2955 return -EINVAL;
2956 }
2957
2958 switch (dai->id) {
2959 case RT5677_AIF1:
2960 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
2961 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2962 RT5677_I2S_DF_MASK, reg_val);
2963 break;
2964 case RT5677_AIF2:
2965 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
2966 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2967 RT5677_I2S_DF_MASK, reg_val);
2968 break;
2969 case RT5677_AIF3:
2970 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
2971 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2972 RT5677_I2S_DF_MASK, reg_val);
2973 break;
2974 case RT5677_AIF4:
2975 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
2976 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2977 RT5677_I2S_DF_MASK, reg_val);
2978 break;
2979 default:
2980 break;
2981 }
2982
2983
2984 return 0;
2985}
2986
2987static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
2988 int clk_id, unsigned int freq, int dir)
2989{
2990 struct snd_soc_codec *codec = dai->codec;
2991 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2992 unsigned int reg_val = 0;
2993
2994 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
2995 return 0;
2996
2997 switch (clk_id) {
2998 case RT5677_SCLK_S_MCLK:
2999 reg_val |= RT5677_SCLK_SRC_MCLK;
3000 break;
3001 case RT5677_SCLK_S_PLL1:
3002 reg_val |= RT5677_SCLK_SRC_PLL1;
3003 break;
3004 case RT5677_SCLK_S_RCCLK:
3005 reg_val |= RT5677_SCLK_SRC_RCCLK;
3006 break;
3007 default:
3008 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
3009 return -EINVAL;
3010 }
3011 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3012 RT5677_SCLK_SRC_MASK, reg_val);
3013 rt5677->sysclk = freq;
3014 rt5677->sysclk_src = clk_id;
3015
3016 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
3017
3018 return 0;
3019}
3020
3021/**
3022 * rt5677_pll_calc - Calcualte PLL M/N/K code.
3023 * @freq_in: external clock provided to codec.
3024 * @freq_out: target clock which codec works on.
3025 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
3026 *
3027 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
3028 *
3029 * Returns 0 for success or negative error code.
3030 */
3031static int rt5677_pll_calc(const unsigned int freq_in,
099d334e 3032 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
0e826e86 3033{
099d334e 3034 if (RT5677_PLL_INP_MIN > freq_in)
0e826e86
OC		 3035 return -EINVAL;
3036
099d334e 3037 return rl6231_pll_calc(freq_in, freq_out, pll_code);
0e826e86
OC		 3038}
3039
3040static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
3041 unsigned int freq_in, unsigned int freq_out)
3042{
3043 struct snd_soc_codec *codec = dai->codec;
3044 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
099d334e 3045 struct rl6231_pll_code pll_code;
0e826e86
OC		 3046 int ret;
3047
3048 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
3049 freq_out == rt5677->pll_out)
3050 return 0;
3051
3052 if (!freq_in || !freq_out) {
3053 dev_dbg(codec->dev, "PLL disabled\n");
3054
3055 rt5677->pll_in = 0;
3056 rt5677->pll_out = 0;
3057 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3058 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
3059 return 0;
3060 }
3061
3062 switch (source) {
3063 case RT5677_PLL1_S_MCLK:
3064 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3065 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
3066 break;
3067 case RT5677_PLL1_S_BCLK1:
3068 case RT5677_PLL1_S_BCLK2:
3069 case RT5677_PLL1_S_BCLK3:
3070 case RT5677_PLL1_S_BCLK4:
3071 switch (dai->id) {
3072 case RT5677_AIF1:
3073 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3074 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
3075 break;
3076 case RT5677_AIF2:
3077 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3078 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
3079 break;
3080 case RT5677_AIF3:
3081 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3082 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
3083 break;
3084 case RT5677_AIF4:
3085 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3086 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
3087 break;
3088 default:
3089 break;
3090 }
3091 break;
3092 default:
3093 dev_err(codec->dev, "Unknown PLL source %d\n", source);
3094 return -EINVAL;
3095 }
3096
3097 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
3098 if (ret < 0) {
3099 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
3100 return ret;
3101 }
3102
099d334e
AL		 3103 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
3104 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
3105 pll_code.n_code, pll_code.k_code);
0e826e86
OC		 3106
3107 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
099d334e 3108 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
0e826e86
OC		 3109 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
3110 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
3111 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
3112
3113 rt5677->pll_in = freq_in;
3114 rt5677->pll_out = freq_out;
3115 rt5677->pll_src = source;
3116
3117 return 0;
3118}
3119
48561afe
OC		 3120static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
3121 unsigned int rx_mask, int slots, int slot_width)
3122{
3123 struct snd_soc_codec *codec = dai->codec;
3124 unsigned int val = 0;
3125
3126 if (rx_mask || tx_mask)
3127 val |= (1 << 12);
3128
3129 switch (slots) {
3130 case 4:
3131 val |= (1 << 10);
3132 break;
3133 case 6:
3134 val |= (2 << 10);
3135 break;
3136 case 8:
3137 val |= (3 << 10);
3138 break;
3139 case 2:
3140 default:
3141 break;
3142 }
3143
3144 switch (slot_width) {
3145 case 20:
3146 val |= (1 << 8);
3147 break;
3148 case 24:
3149 val |= (2 << 8);
3150 break;
3151 case 32:
3152 val |= (3 << 8);
3153 break;
3154 case 16:
3155 default:
3156 break;
3157 }
3158
3159 switch (dai->id) {
3160 case RT5677_AIF1:
3161 snd_soc_update_bits(codec, RT5677_TDM1_CTRL1, 0x1f00, val);
3162 break;
3163 case RT5677_AIF2:
3164 snd_soc_update_bits(codec, RT5677_TDM2_CTRL1, 0x1f00, val);
3165 break;
3166 default:
3167 break;
3168 }
3169
3170 return 0;
3171}
3172
0e826e86
OC		 3173static int rt5677_set_bias_level(struct snd_soc_codec *codec,
3174 enum snd_soc_bias_level level)
3175{
3176 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3177
3178 switch (level) {
3179 case SND_SOC_BIAS_ON:
3180 break;
3181
3182 case SND_SOC_BIAS_PREPARE:
3183 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
3184 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3185 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
3186 0x0055);
3187 regmap_update_bits(rt5677->regmap,
3188 RT5677_PR_BASE + RT5677_BIAS_CUR4,
3189 0x0f00, 0x0f00);
3190 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3191 RT5677_PWR_VREF1 | RT5677_PWR_MB |
3192 RT5677_PWR_BG | RT5677_PWR_VREF2,
3193 RT5677_PWR_VREF1 | RT5677_PWR_MB |
3194 RT5677_PWR_BG | RT5677_PWR_VREF2);
3195 mdelay(20);
3196 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3197 RT5677_PWR_FV1 | RT5677_PWR_FV2,
3198 RT5677_PWR_FV1 | RT5677_PWR_FV2);
3199 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
3200 RT5677_PWR_CORE, RT5677_PWR_CORE);
3201 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
3202 0x1, 0x1);
3203 }
3204 break;
3205
3206 case SND_SOC_BIAS_STANDBY:
3207 break;
3208
3209 case SND_SOC_BIAS_OFF:
3210 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
3211 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
3212 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
f18803a3 3213 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
0e826e86
OC		 3214 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
3215 regmap_update_bits(rt5677->regmap,
3216 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
3217 break;
3218
3219 default:
3220 break;
3221 }
3222 codec->dapm.bias_level = level;
3223
3224 return 0;
3225}
3226
44caf764
OC		 3227#ifdef CONFIG_GPIOLIB
3228static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip)
3229{
3230 return container_of(chip, struct rt5677_priv, gpio_chip);
3231}
3232
3233static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3234{
3235 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3236
3237 switch (offset) {
3238 case RT5677_GPIO1 ... RT5677_GPIO5:
3239 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
3240 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
3241 break;
3242
3243 case RT5677_GPIO6:
3244 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
3245 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
3246 break;
3247
3248 default:
3249 break;
3250 }
3251}
3252
3253static int rt5677_gpio_direction_out(struct gpio_chip *chip,
3254 unsigned offset, int value)
3255{
3256 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3257
3258 switch (offset) {
3259 case RT5677_GPIO1 ... RT5677_GPIO5:
3260 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
3261 0x3 << (offset * 3 + 1),
3262 (0x2 | !!value) << (offset * 3 + 1));
3263 break;
3264
3265 case RT5677_GPIO6:
3266 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
3267 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
3268 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
3269 break;
3270
3271 default:
3272 break;
3273 }
3274
3275 return 0;
3276}
3277
3278static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
3279{
3280 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3281 int value, ret;
3282
3283 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
3284 if (ret < 0)
3285 return ret;
3286
3287 return (value & (0x1 << offset)) >> offset;
3288}
3289
3290static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
3291{
3292 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3293
3294 switch (offset) {
3295 case RT5677_GPIO1 ... RT5677_GPIO5:
3296 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
3297 0x1 << (offset * 3 + 2), 0x0);
3298 break;
3299
3300 case RT5677_GPIO6:
3301 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
3302 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
3303 break;
3304
3305 default:
3306 break;
3307 }
3308
3309 return 0;
3310}
3311
40eb90a1
AP		 3312/** Configures the gpio as
3313 * 0 - floating
3314 * 1 - pull down
3315 * 2 - pull up
3316 */
3317static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
3318 int value)
3319{
3320 int shift;
3321
3322 switch (offset) {
3323 case RT5677_GPIO1 ... RT5677_GPIO2:
3324 shift = 2 * (1 - offset);
3325 regmap_update_bits(rt5677->regmap,
3326 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
3327 0x3 << shift,
3328 (value & 0x3) << shift);
3329 break;
3330
3331 case RT5677_GPIO3 ... RT5677_GPIO6:
3332 shift = 2 * (9 - offset);
3333 regmap_update_bits(rt5677->regmap,
3334 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
3335 0x3 << shift,
3336 (value & 0x3) << shift);
3337 break;
3338
3339 default:
3340 break;
3341 }
3342}
3343
44caf764
OC		 3344static struct gpio_chip rt5677_template_chip = {
3345 .label = "rt5677",
3346 .owner = THIS_MODULE,
3347 .direction_output = rt5677_gpio_direction_out,
3348 .set = rt5677_gpio_set,
3349 .direction_input = rt5677_gpio_direction_in,
3350 .get = rt5677_gpio_get,
3351 .can_sleep = 1,
3352};
3353
3354static void rt5677_init_gpio(struct i2c_client *i2c)
3355{
3356 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
3357 int ret;
3358
3359 rt5677->gpio_chip = rt5677_template_chip;
3360 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
3361 rt5677->gpio_chip.dev = &i2c->dev;
3362 rt5677->gpio_chip.base = -1;
3363
3364 ret = gpiochip_add(&rt5677->gpio_chip);
3365 if (ret != 0)
3366 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
3367}
3368
3369static void rt5677_free_gpio(struct i2c_client *i2c)
3370{
3371 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
44caf764 3372
5d5e63af 3373 gpiochip_remove(&rt5677->gpio_chip);
44caf764
OC		 3374}
3375#else
3376static void rt5677_init_gpio(struct i2c_client *i2c)
3377{
3378}
3379
3380static void rt5677_free_gpio(struct i2c_client *i2c)
3381{
3382}
3383#endif
3384
0e826e86
OC		 3385static int rt5677_probe(struct snd_soc_codec *codec)
3386{
3387 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
40eb90a1 3388 int i;
0e826e86
OC		 3389
3390 rt5677->codec = codec;
3391
2d15d974
BL		 3392 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
3393 snd_soc_dapm_add_routes(&codec->dapm,
3394 rt5677_dmic2_clk_2,
3395 ARRAY_SIZE(rt5677_dmic2_clk_2));
3396 } else { /*use dmic1 clock by default*/
3397 snd_soc_dapm_add_routes(&codec->dapm,
3398 rt5677_dmic2_clk_1,
3399 ARRAY_SIZE(rt5677_dmic2_clk_1));
3400 }
3401
0e826e86
OC		 3402 rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF);
3403
3404 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
3405 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
3406
40eb90a1
AP		 3407 for (i = 0; i < RT5677_GPIO_NUM; i++)
3408 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
3409
0e826e86
OC		 3410 return 0;
3411}
3412
3413static int rt5677_remove(struct snd_soc_codec *codec)
3414{
3415 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3416
3417 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
f9f6a592
AP		 3418 if (gpio_is_valid(rt5677->pow_ldo2))
3419 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
0e826e86
OC		 3420
3421 return 0;
3422}
3423
3424#ifdef CONFIG_PM
3425static int rt5677_suspend(struct snd_soc_codec *codec)
3426{
3427 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3428
3429 regcache_cache_only(rt5677->regmap, true);
3430 regcache_mark_dirty(rt5677->regmap);
f9f6a592
AP		 3431 if (gpio_is_valid(rt5677->pow_ldo2))
3432 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
0e826e86
OC		 3433
3434 return 0;
3435}
3436
3437static int rt5677_resume(struct snd_soc_codec *codec)
3438{
3439 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3440
f9f6a592
AP		 3441 if (gpio_is_valid(rt5677->pow_ldo2)) {
3442 gpio_set_value_cansleep(rt5677->pow_ldo2, 1);
3443 msleep(10);
3444 }
0e826e86
OC		 3445 regcache_cache_only(rt5677->regmap, false);
3446 regcache_sync(rt5677->regmap);
3447
3448 return 0;
3449}
3450#else
3451#define rt5677_suspend NULL
3452#define rt5677_resume NULL
3453#endif
3454
3455#define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3456#define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3457 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3458
3459static struct snd_soc_dai_ops rt5677_aif_dai_ops = {
3460 .hw_params = rt5677_hw_params,
3461 .set_fmt = rt5677_set_dai_fmt,
3462 .set_sysclk = rt5677_set_dai_sysclk,
3463 .set_pll = rt5677_set_dai_pll,
48561afe 3464 .set_tdm_slot = rt5677_set_tdm_slot,
0e826e86
OC		 3465};
3466
3467static struct snd_soc_dai_driver rt5677_dai[] = {
3468 {
3469 .name = "rt5677-aif1",
3470 .id = RT5677_AIF1,
3471 .playback = {
3472 .stream_name = "AIF1 Playback",
3473 .channels_min = 1,
3474 .channels_max = 2,
3475 .rates = RT5677_STEREO_RATES,
3476 .formats = RT5677_FORMATS,
3477 },
3478 .capture = {
3479 .stream_name = "AIF1 Capture",
3480 .channels_min = 1,
3481 .channels_max = 2,
3482 .rates = RT5677_STEREO_RATES,
3483 .formats = RT5677_FORMATS,
3484 },
3485 .ops = &rt5677_aif_dai_ops,
3486 },
3487 {
3488 .name = "rt5677-aif2",
3489 .id = RT5677_AIF2,
3490 .playback = {
3491 .stream_name = "AIF2 Playback",
3492 .channels_min = 1,
3493 .channels_max = 2,
3494 .rates = RT5677_STEREO_RATES,
3495 .formats = RT5677_FORMATS,
3496 },
3497 .capture = {
3498 .stream_name = "AIF2 Capture",
3499 .channels_min = 1,
3500 .channels_max = 2,
3501 .rates = RT5677_STEREO_RATES,
3502 .formats = RT5677_FORMATS,
3503 },
3504 .ops = &rt5677_aif_dai_ops,
3505 },
3506 {
3507 .name = "rt5677-aif3",
3508 .id = RT5677_AIF3,
3509 .playback = {
3510 .stream_name = "AIF3 Playback",
3511 .channels_min = 1,
3512 .channels_max = 2,
3513 .rates = RT5677_STEREO_RATES,
3514 .formats = RT5677_FORMATS,
3515 },
3516 .capture = {
3517 .stream_name = "AIF3 Capture",
3518 .channels_min = 1,
3519 .channels_max = 2,
3520 .rates = RT5677_STEREO_RATES,
3521 .formats = RT5677_FORMATS,
3522 },
3523 .ops = &rt5677_aif_dai_ops,
3524 },
3525 {
3526 .name = "rt5677-aif4",
3527 .id = RT5677_AIF4,
3528 .playback = {
3529 .stream_name = "AIF4 Playback",
3530 .channels_min = 1,
3531 .channels_max = 2,
3532 .rates = RT5677_STEREO_RATES,
3533 .formats = RT5677_FORMATS,
3534 },
3535 .capture = {
3536 .stream_name = "AIF4 Capture",
3537 .channels_min = 1,
3538 .channels_max = 2,
3539 .rates = RT5677_STEREO_RATES,
3540 .formats = RT5677_FORMATS,
3541 },
3542 .ops = &rt5677_aif_dai_ops,
3543 },
3544 {
3545 .name = "rt5677-slimbus",
3546 .id = RT5677_AIF5,
3547 .playback = {
3548 .stream_name = "SLIMBus Playback",
3549 .channels_min = 1,
3550 .channels_max = 2,
3551 .rates = RT5677_STEREO_RATES,
3552 .formats = RT5677_FORMATS,
3553 },
3554 .capture = {
3555 .stream_name = "SLIMBus Capture",
3556 .channels_min = 1,
3557 .channels_max = 2,
3558 .rates = RT5677_STEREO_RATES,
3559 .formats = RT5677_FORMATS,
3560 },
3561 .ops = &rt5677_aif_dai_ops,
3562 },
3563};
3564
3565static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
3566 .probe = rt5677_probe,
3567 .remove = rt5677_remove,
3568 .suspend = rt5677_suspend,
3569 .resume = rt5677_resume,
3570 .set_bias_level = rt5677_set_bias_level,
3571 .idle_bias_off = true,
3572 .controls = rt5677_snd_controls,
3573 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
3574 .dapm_widgets = rt5677_dapm_widgets,
3575 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
3576 .dapm_routes = rt5677_dapm_routes,
3577 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
3578};
3579
3580static const struct regmap_config rt5677_regmap = {
3581 .reg_bits = 8,
3582 .val_bits = 16,
3583
3584 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
3585 RT5677_PR_SPACING),
3586
3587 .volatile_reg = rt5677_volatile_register,
3588 .readable_reg = rt5677_readable_register,
3589
3590 .cache_type = REGCACHE_RBTREE,
3591 .reg_defaults = rt5677_reg,
3592 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
3593 .ranges = rt5677_ranges,
3594 .num_ranges = ARRAY_SIZE(rt5677_ranges),
3595};
3596
3597static const struct i2c_device_id rt5677_i2c_id[] = {
3598 { "rt5677", 0 },
3599 { }
3600};
3601MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
3602
f9f6a592
AP		 3603static int rt5677_parse_dt(struct rt5677_priv *rt5677, struct device_node *np)
3604{
6f67c380
AP		 3605 rt5677->pdata.in1_diff = of_property_read_bool(np,
3606 "realtek,in1-differential");
3607 rt5677->pdata.in2_diff = of_property_read_bool(np,
3608 "realtek,in2-differential");
3609 rt5677->pdata.lout1_diff = of_property_read_bool(np,
3610 "realtek,lout1-differential");
3611 rt5677->pdata.lout2_diff = of_property_read_bool(np,
3612 "realtek,lout2-differential");
3613 rt5677->pdata.lout3_diff = of_property_read_bool(np,
3614 "realtek,lout3-differential");
3615
f9f6a592
AP		 3616 rt5677->pow_ldo2 = of_get_named_gpio(np,
3617 "realtek,pow-ldo2-gpio", 0);
3618
3619 /*
3620 * POW_LDO2 is optional (it may be statically tied on the board).
3621 * -ENOENT means that the property doesn't exist, i.e. there is no
3622 * GPIO, so is not an error. Any other error code means the property
3623 * exists, but could not be parsed.
3624 */
3625 if (!gpio_is_valid(rt5677->pow_ldo2) &&
3626 (rt5677->pow_ldo2 != -ENOENT))
3627 return rt5677->pow_ldo2;
3628
40eb90a1
AP		 3629 of_property_read_u8_array(np, "realtek,gpio-config",
3630 rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
3631
f9f6a592
AP		 3632 return 0;
3633}
3634
0e826e86
OC		 3635static int rt5677_i2c_probe(struct i2c_client *i2c,
3636 const struct i2c_device_id *id)
3637{
3638 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
3639 struct rt5677_priv *rt5677;
3640 int ret;
3641 unsigned int val;
3642
3643 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
3644 GFP_KERNEL);
3645 if (rt5677 == NULL)
3646 return -ENOMEM;
3647
3648 i2c_set_clientdata(i2c, rt5677);
3649
3650 if (pdata)
3651 rt5677->pdata = *pdata;
3652
f9f6a592
AP		 3653 if (i2c->dev.of_node) {
3654 ret = rt5677_parse_dt(rt5677, i2c->dev.of_node);
3655 if (ret) {
3656 dev_err(&i2c->dev, "Failed to parse device tree: %d\n",
3657 ret);
3658 return ret;
3659 }
3660 } else {
3661 rt5677->pow_ldo2 = -EINVAL;
3662 }
3663
3664 if (gpio_is_valid(rt5677->pow_ldo2)) {
3665 ret = devm_gpio_request_one(&i2c->dev, rt5677->pow_ldo2,
3666 GPIOF_OUT_INIT_HIGH,
3667 "RT5677 POW_LDO2");
3668 if (ret < 0) {
3669 dev_err(&i2c->dev, "Failed to request POW_LDO2 %d: %d\n",
3670 rt5677->pow_ldo2, ret);
3671 return ret;
3672 }
3673 /* Wait a while until I2C bus becomes available. The datasheet
3674 * does not specify the exact we should wait but startup
3675 * sequence mentiones at least a few milliseconds.
3676 */
3677 msleep(10);
3678 }
3679
0e826e86
OC		 3680 rt5677->regmap = devm_regmap_init_i2c(i2c, &rt5677_regmap);
3681 if (IS_ERR(rt5677->regmap)) {
3682 ret = PTR_ERR(rt5677->regmap);
3683 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3684 ret);
3685 return ret;
3686 }
3687
3688 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
3689 if (val != RT5677_DEVICE_ID) {
3690 dev_err(&i2c->dev,
3691 "Device with ID register %x is not rt5677\n", val);
3692 return -ENODEV;
3693 }
3694
3695 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
3696
3697 ret = regmap_register_patch(rt5677->regmap, init_list,
3698 ARRAY_SIZE(init_list));
3699 if (ret != 0)
3700 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
3701
3702 if (rt5677->pdata.in1_diff)
3703 regmap_update_bits(rt5677->regmap, RT5677_IN1,
3704 RT5677_IN_DF1, RT5677_IN_DF1);
3705
3706 if (rt5677->pdata.in2_diff)
3707 regmap_update_bits(rt5677->regmap, RT5677_IN1,
3708 RT5677_IN_DF2, RT5677_IN_DF2);
3709
6f67c380
AP		 3710 if (rt5677->pdata.lout1_diff)
3711 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
3712 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
3713
3714 if (rt5677->pdata.lout2_diff)
3715 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
3716 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
3717
3718 if (rt5677->pdata.lout3_diff)
3719 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
3720 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
3721
2d15d974
BL		 3722 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
3723 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
3724 RT5677_GPIO5_FUNC_MASK,
3725 RT5677_GPIO5_FUNC_DMIC);
3726 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
3727 RT5677_GPIO5_DIR_MASK,
3728 RT5677_GPIO5_DIR_OUT);
3729 }
3730
44caf764
OC		 3731 rt5677_init_gpio(i2c);
3732
d0bdcb91
AL		 3733 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
3734 rt5677_dai, ARRAY_SIZE(rt5677_dai));
0e826e86
OC		 3735}
3736
3737static int rt5677_i2c_remove(struct i2c_client *i2c)
3738{
3739 snd_soc_unregister_codec(&i2c->dev);
44caf764 3740 rt5677_free_gpio(i2c);
0e826e86
OC		 3741
3742 return 0;
3743}
3744
3745static struct i2c_driver rt5677_i2c_driver = {
3746 .driver = {
3747 .name = "rt5677",
3748 .owner = THIS_MODULE,
3749 },
3750 .probe = rt5677_i2c_probe,
3751 .remove = rt5677_i2c_remove,
3752 .id_table = rt5677_i2c_id,
3753};
c8cfbec8 3754module_i2c_driver(rt5677_i2c_driver);
0e826e86
OC		 3755
3756MODULE_DESCRIPTION("ASoC RT5677 driver");
3757MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
3758MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)