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ASoC: rt5645: add register setting for TDM
[linux-2.6-block.git] / sound / soc / codecs / rt5645.c
CommitLineData
1319b2f6
OC		 1/*
2 * rt5645.c -- RT5645 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
f3fa1bbd 20#include <linux/gpio.h>
1319b2f6
OC		 21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/jack.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29
49ef7925 30#include "rl6231.h"
1319b2f6
OC		 31#include "rt5645.h"
32
33#define RT5645_DEVICE_ID 0x6308
34
35#define RT5645_PR_RANGE_BASE (0xff + 1)
36#define RT5645_PR_SPACING 0x100
37
38#define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
39
40static const struct regmap_range_cfg rt5645_ranges[] = {
41 {
42 .name = "PR",
43 .range_min = RT5645_PR_BASE,
44 .range_max = RT5645_PR_BASE + 0xf8,
45 .selector_reg = RT5645_PRIV_INDEX,
46 .selector_mask = 0xff,
47 .selector_shift = 0x0,
48 .window_start = RT5645_PRIV_DATA,
49 .window_len = 0x1,
50 },
51};
52
53static const struct reg_default init_list[] = {
54 {RT5645_PR_BASE + 0x3d, 0x3600},
4809b96e
OC		 55 {RT5645_PR_BASE + 0x1c, 0xfd20},
56 {RT5645_PR_BASE + 0x20, 0x611f},
57 {RT5645_PR_BASE + 0x21, 0x4040},
58 {RT5645_PR_BASE + 0x23, 0x0004},
1319b2f6
OC		 59};
60#define RT5645_INIT_REG_LEN ARRAY_SIZE(init_list)
61
62static const struct reg_default rt5645_reg[] = {
63 { 0x00, 0x0000 },
64 { 0x01, 0xc8c8 },
65 { 0x02, 0xc8c8 },
66 { 0x03, 0xc8c8 },
67 { 0x0a, 0x0002 },
68 { 0x0b, 0x2827 },
69 { 0x0c, 0xe000 },
70 { 0x0d, 0x0000 },
71 { 0x0e, 0x0000 },
72 { 0x0f, 0x0808 },
73 { 0x14, 0x3333 },
74 { 0x16, 0x4b00 },
75 { 0x18, 0x018b },
76 { 0x19, 0xafaf },
77 { 0x1a, 0xafaf },
78 { 0x1b, 0x0001 },
79 { 0x1c, 0x2f2f },
80 { 0x1d, 0x2f2f },
81 { 0x1e, 0x0000 },
82 { 0x20, 0x0000 },
83 { 0x27, 0x7060 },
84 { 0x28, 0x7070 },
85 { 0x29, 0x8080 },
86 { 0x2a, 0x5656 },
87 { 0x2b, 0x5454 },
88 { 0x2c, 0xaaa0 },
89 { 0x2f, 0x1002 },
90 { 0x31, 0x5000 },
91 { 0x32, 0x0000 },
92 { 0x33, 0x0000 },
93 { 0x34, 0x0000 },
94 { 0x35, 0x0000 },
95 { 0x3b, 0x0000 },
96 { 0x3c, 0x007f },
97 { 0x3d, 0x0000 },
98 { 0x3e, 0x007f },
99 { 0x3f, 0x0000 },
100 { 0x40, 0x001f },
101 { 0x41, 0x0000 },
102 { 0x42, 0x001f },
103 { 0x45, 0x6000 },
104 { 0x46, 0x003e },
105 { 0x47, 0x003e },
106 { 0x48, 0xf807 },
107 { 0x4a, 0x0004 },
108 { 0x4d, 0x0000 },
109 { 0x4e, 0x0000 },
110 { 0x4f, 0x01ff },
111 { 0x50, 0x0000 },
112 { 0x51, 0x0000 },
113 { 0x52, 0x01ff },
114 { 0x53, 0xf000 },
115 { 0x56, 0x0111 },
116 { 0x57, 0x0064 },
117 { 0x58, 0xef0e },
118 { 0x59, 0xf0f0 },
119 { 0x5a, 0xef0e },
120 { 0x5b, 0xf0f0 },
121 { 0x5c, 0xef0e },
122 { 0x5d, 0xf0f0 },
123 { 0x5e, 0xf000 },
124 { 0x5f, 0x0000 },
125 { 0x61, 0x0300 },
126 { 0x62, 0x0000 },
127 { 0x63, 0x00c2 },
128 { 0x64, 0x0000 },
129 { 0x65, 0x0000 },
130 { 0x66, 0x0000 },
131 { 0x6a, 0x0000 },
132 { 0x6c, 0x0aaa },
133 { 0x70, 0x8000 },
134 { 0x71, 0x8000 },
135 { 0x72, 0x8000 },
136 { 0x73, 0x7770 },
137 { 0x74, 0x3e00 },
138 { 0x75, 0x2409 },
139 { 0x76, 0x000a },
140 { 0x77, 0x0c00 },
141 { 0x78, 0x0000 },
142 { 0x80, 0x0000 },
143 { 0x81, 0x0000 },
144 { 0x82, 0x0000 },
145 { 0x83, 0x0000 },
146 { 0x84, 0x0000 },
147 { 0x85, 0x0000 },
148 { 0x8a, 0x0000 },
149 { 0x8e, 0x0004 },
150 { 0x8f, 0x1100 },
151 { 0x90, 0x0646 },
152 { 0x91, 0x0c06 },
153 { 0x93, 0x0000 },
154 { 0x94, 0x0200 },
155 { 0x95, 0x0000 },
156 { 0x9a, 0x2184 },
157 { 0x9b, 0x010a },
158 { 0x9c, 0x0aea },
159 { 0x9d, 0x000c },
160 { 0x9e, 0x0400 },
161 { 0xa0, 0xa0a8 },
162 { 0xa1, 0x0059 },
163 { 0xa2, 0x0001 },
164 { 0xae, 0x6000 },
165 { 0xaf, 0x0000 },
166 { 0xb0, 0x6000 },
167 { 0xb1, 0x0000 },
168 { 0xb2, 0x0000 },
169 { 0xb3, 0x001f },
170 { 0xb4, 0x020c },
171 { 0xb5, 0x1f00 },
172 { 0xb6, 0x0000 },
173 { 0xbb, 0x0000 },
174 { 0xbc, 0x0000 },
175 { 0xbd, 0x0000 },
176 { 0xbe, 0x0000 },
177 { 0xbf, 0x3100 },
178 { 0xc0, 0x0000 },
179 { 0xc1, 0x0000 },
180 { 0xc2, 0x0000 },
181 { 0xc3, 0x2000 },
182 { 0xcd, 0x0000 },
183 { 0xce, 0x0000 },
184 { 0xcf, 0x1813 },
185 { 0xd0, 0x0690 },
186 { 0xd1, 0x1c17 },
187 { 0xd3, 0xb320 },
188 { 0xd4, 0x0000 },
189 { 0xd6, 0x0400 },
190 { 0xd9, 0x0809 },
191 { 0xda, 0x0000 },
192 { 0xdb, 0x0003 },
193 { 0xdc, 0x0049 },
194 { 0xdd, 0x001b },
195 { 0xe6, 0x8000 },
196 { 0xe7, 0x0200 },
197 { 0xec, 0xb300 },
198 { 0xed, 0x0000 },
199 { 0xf0, 0x001f },
200 { 0xf1, 0x020c },
201 { 0xf2, 0x1f00 },
202 { 0xf3, 0x0000 },
203 { 0xf4, 0x4000 },
204 { 0xf8, 0x0000 },
205 { 0xf9, 0x0000 },
206 { 0xfa, 0x2060 },
207 { 0xfb, 0x4040 },
208 { 0xfc, 0x0000 },
209 { 0xfd, 0x0002 },
210 { 0xfe, 0x10ec },
211 { 0xff, 0x6308 },
212};
213
214static int rt5645_reset(struct snd_soc_codec *codec)
215{
216 return snd_soc_write(codec, RT5645_RESET, 0);
217}
218
219static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
220{
221 int i;
222
223 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
224 if (reg >= rt5645_ranges[i].range_min &&
225 reg <= rt5645_ranges[i].range_max) {
226 return true;
227 }
228 }
229
230 switch (reg) {
231 case RT5645_RESET:
232 case RT5645_PRIV_DATA:
233 case RT5645_IN1_CTRL1:
234 case RT5645_IN1_CTRL2:
235 case RT5645_IN1_CTRL3:
236 case RT5645_A_JD_CTRL1:
237 case RT5645_ADC_EQ_CTRL1:
238 case RT5645_EQ_CTRL1:
239 case RT5645_ALC_CTRL_1:
240 case RT5645_IRQ_CTRL2:
241 case RT5645_IRQ_CTRL3:
242 case RT5645_INT_IRQ_ST:
243 case RT5645_IL_CMD:
244 case RT5645_VENDOR_ID:
245 case RT5645_VENDOR_ID1:
246 case RT5645_VENDOR_ID2:
71bfa9b4 247 return true;
1319b2f6 248 default:
71bfa9b4 249 return false;
1319b2f6
OC		 250 }
251}
252
253static bool rt5645_readable_register(struct device *dev, unsigned int reg)
254{
255 int i;
256
257 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
258 if (reg >= rt5645_ranges[i].range_min &&
259 reg <= rt5645_ranges[i].range_max) {
260 return true;
261 }
262 }
263
264 switch (reg) {
265 case RT5645_RESET:
266 case RT5645_SPK_VOL:
267 case RT5645_HP_VOL:
268 case RT5645_LOUT1:
269 case RT5645_IN1_CTRL1:
270 case RT5645_IN1_CTRL2:
271 case RT5645_IN1_CTRL3:
272 case RT5645_IN2_CTRL:
273 case RT5645_INL1_INR1_VOL:
274 case RT5645_SPK_FUNC_LIM:
275 case RT5645_ADJ_HPF_CTRL:
276 case RT5645_DAC1_DIG_VOL:
277 case RT5645_DAC2_DIG_VOL:
278 case RT5645_DAC_CTRL:
279 case RT5645_STO1_ADC_DIG_VOL:
280 case RT5645_MONO_ADC_DIG_VOL:
281 case RT5645_ADC_BST_VOL1:
282 case RT5645_ADC_BST_VOL2:
283 case RT5645_STO1_ADC_MIXER:
284 case RT5645_MONO_ADC_MIXER:
285 case RT5645_AD_DA_MIXER:
286 case RT5645_STO_DAC_MIXER:
287 case RT5645_MONO_DAC_MIXER:
288 case RT5645_DIG_MIXER:
289 case RT5645_DIG_INF1_DATA:
290 case RT5645_PDM_OUT_CTRL:
291 case RT5645_REC_L1_MIXER:
292 case RT5645_REC_L2_MIXER:
293 case RT5645_REC_R1_MIXER:
294 case RT5645_REC_R2_MIXER:
295 case RT5645_HPMIXL_CTRL:
296 case RT5645_HPOMIXL_CTRL:
297 case RT5645_HPMIXR_CTRL:
298 case RT5645_HPOMIXR_CTRL:
299 case RT5645_HPO_MIXER:
300 case RT5645_SPK_L_MIXER:
301 case RT5645_SPK_R_MIXER:
302 case RT5645_SPO_MIXER:
303 case RT5645_SPO_CLSD_RATIO:
304 case RT5645_OUT_L1_MIXER:
305 case RT5645_OUT_R1_MIXER:
306 case RT5645_OUT_L_GAIN1:
307 case RT5645_OUT_L_GAIN2:
308 case RT5645_OUT_R_GAIN1:
309 case RT5645_OUT_R_GAIN2:
310 case RT5645_LOUT_MIXER:
311 case RT5645_HAPTIC_CTRL1:
312 case RT5645_HAPTIC_CTRL2:
313 case RT5645_HAPTIC_CTRL3:
314 case RT5645_HAPTIC_CTRL4:
315 case RT5645_HAPTIC_CTRL5:
316 case RT5645_HAPTIC_CTRL6:
317 case RT5645_HAPTIC_CTRL7:
318 case RT5645_HAPTIC_CTRL8:
319 case RT5645_HAPTIC_CTRL9:
320 case RT5645_HAPTIC_CTRL10:
321 case RT5645_PWR_DIG1:
322 case RT5645_PWR_DIG2:
323 case RT5645_PWR_ANLG1:
324 case RT5645_PWR_ANLG2:
325 case RT5645_PWR_MIXER:
326 case RT5645_PWR_VOL:
327 case RT5645_PRIV_INDEX:
328 case RT5645_PRIV_DATA:
329 case RT5645_I2S1_SDP:
330 case RT5645_I2S2_SDP:
331 case RT5645_ADDA_CLK1:
332 case RT5645_ADDA_CLK2:
333 case RT5645_DMIC_CTRL1:
334 case RT5645_DMIC_CTRL2:
335 case RT5645_TDM_CTRL_1:
336 case RT5645_TDM_CTRL_2:
337 case RT5645_GLB_CLK:
338 case RT5645_PLL_CTRL1:
339 case RT5645_PLL_CTRL2:
340 case RT5645_ASRC_1:
341 case RT5645_ASRC_2:
342 case RT5645_ASRC_3:
343 case RT5645_ASRC_4:
344 case RT5645_DEPOP_M1:
345 case RT5645_DEPOP_M2:
346 case RT5645_DEPOP_M3:
347 case RT5645_MICBIAS:
348 case RT5645_A_JD_CTRL1:
349 case RT5645_VAD_CTRL4:
350 case RT5645_CLSD_OUT_CTRL:
351 case RT5645_ADC_EQ_CTRL1:
352 case RT5645_ADC_EQ_CTRL2:
353 case RT5645_EQ_CTRL1:
354 case RT5645_EQ_CTRL2:
355 case RT5645_ALC_CTRL_1:
356 case RT5645_ALC_CTRL_2:
357 case RT5645_ALC_CTRL_3:
358 case RT5645_ALC_CTRL_4:
359 case RT5645_ALC_CTRL_5:
360 case RT5645_JD_CTRL:
361 case RT5645_IRQ_CTRL1:
362 case RT5645_IRQ_CTRL2:
363 case RT5645_IRQ_CTRL3:
364 case RT5645_INT_IRQ_ST:
365 case RT5645_GPIO_CTRL1:
366 case RT5645_GPIO_CTRL2:
367 case RT5645_GPIO_CTRL3:
368 case RT5645_BASS_BACK:
369 case RT5645_MP3_PLUS1:
370 case RT5645_MP3_PLUS2:
371 case RT5645_ADJ_HPF1:
372 case RT5645_ADJ_HPF2:
373 case RT5645_HP_CALIB_AMP_DET:
374 case RT5645_SV_ZCD1:
375 case RT5645_SV_ZCD2:
376 case RT5645_IL_CMD:
377 case RT5645_IL_CMD2:
378 case RT5645_IL_CMD3:
379 case RT5645_DRC1_HL_CTRL1:
380 case RT5645_DRC2_HL_CTRL1:
381 case RT5645_ADC_MONO_HP_CTRL1:
382 case RT5645_ADC_MONO_HP_CTRL2:
383 case RT5645_DRC2_CTRL1:
384 case RT5645_DRC2_CTRL2:
385 case RT5645_DRC2_CTRL3:
386 case RT5645_DRC2_CTRL4:
387 case RT5645_DRC2_CTRL5:
388 case RT5645_JD_CTRL3:
389 case RT5645_JD_CTRL4:
390 case RT5645_GEN_CTRL1:
391 case RT5645_GEN_CTRL2:
392 case RT5645_GEN_CTRL3:
393 case RT5645_VENDOR_ID:
394 case RT5645_VENDOR_ID1:
395 case RT5645_VENDOR_ID2:
71bfa9b4 396 return true;
1319b2f6 397 default:
71bfa9b4 398 return false;
1319b2f6
OC		 399 }
400}
401
402static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
403static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
404static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
405static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
406static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
407
408/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
409static unsigned int bst_tlv[] = {
410 TLV_DB_RANGE_HEAD(7),
411 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
412 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
413 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
414 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
415 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
416 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
417 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
418};
419
420static const char * const rt5645_tdm_data_swap_select[] = {
421 "L/R", "R/L", "L/L", "R/R"
422};
423
424static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
425 RT5645_TDM_CTRL_1, 6, rt5645_tdm_data_swap_select);
426
427static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
428 RT5645_TDM_CTRL_1, 4, rt5645_tdm_data_swap_select);
429
430static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
431 RT5645_TDM_CTRL_1, 2, rt5645_tdm_data_swap_select);
432
433static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot6_7_enum,
434 RT5645_TDM_CTRL_1, 0, rt5645_tdm_data_swap_select);
435
436static const char * const rt5645_tdm_adc_data_select[] = {
437 "1/2/R", "2/1/R", "R/1/2", "R/2/1"
438};
439
440static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_sel_enum,
441 RT5645_TDM_CTRL_1, 8,
442 rt5645_tdm_adc_data_select);
443
444static const struct snd_kcontrol_new rt5645_snd_controls[] = {
445 /* Speaker Output Volume */
446 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
447 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
448 SOC_DOUBLE_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
449 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
450
451 /* Headphone Output Volume */
452 SOC_DOUBLE("HP Channel Switch", RT5645_HP_VOL,
453 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
454 SOC_DOUBLE_TLV("HP Playback Volume", RT5645_HP_VOL,
455 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
456
457 /* OUTPUT Control */
458 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
459 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
460 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
461 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
462 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
463 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
464
465 /* DAC Digital Volume */
466 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
467 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
468 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
469 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 175, 0, dac_vol_tlv),
470 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
471 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 175, 0, dac_vol_tlv),
472
473 /* IN1/IN2 Control */
474 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
475 RT5645_BST_SFT1, 8, 0, bst_tlv),
476 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
477 RT5645_BST_SFT2, 8, 0, bst_tlv),
478
479 /* INL/INR Volume Control */
480 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
481 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
482
483 /* ADC Digital Volume Control */
484 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
485 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
486 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
487 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 127, 0, adc_vol_tlv),
488 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
489 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
490 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
491 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 127, 0, adc_vol_tlv),
492
493 /* ADC Boost Volume Control */
494 SOC_DOUBLE_TLV("STO1 ADC Boost Gain", RT5645_ADC_BST_VOL1,
495 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
496 adc_bst_tlv),
497 SOC_DOUBLE_TLV("STO2 ADC Boost Gain", RT5645_ADC_BST_VOL1,
498 RT5645_STO2_ADC_L_BST_SFT, RT5645_STO2_ADC_R_BST_SFT, 3, 0,
499 adc_bst_tlv),
500
501 /* I2S2 function select */
502 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
503 1, 1),
504
505 /* TDM */
506 SOC_ENUM("TDM Adc Slot0 1 Data", rt5645_tdm_adc_slot0_1_enum),
507 SOC_ENUM("TDM Adc Slot2 3 Data", rt5645_tdm_adc_slot2_3_enum),
508 SOC_ENUM("TDM Adc Slot4 5 Data", rt5645_tdm_adc_slot4_5_enum),
509 SOC_ENUM("TDM Adc Slot6 7 Data", rt5645_tdm_adc_slot6_7_enum),
510 SOC_ENUM("TDM IF1 ADC DATA Sel", rt5645_tdm_adc_sel_enum),
511 SOC_SINGLE("TDM IF1_DAC1_L Sel", RT5645_TDM_CTRL_3, 12, 7, 0),
512 SOC_SINGLE("TDM IF1_DAC1_R Sel", RT5645_TDM_CTRL_3, 8, 7, 0),
513 SOC_SINGLE("TDM IF1_DAC2_L Sel", RT5645_TDM_CTRL_3, 4, 7, 0),
514 SOC_SINGLE("TDM IF1_DAC2_R Sel", RT5645_TDM_CTRL_3, 0, 7, 0),
515};
516
517/**
518 * set_dmic_clk - Set parameter of dmic.
519 *
520 * @w: DAPM widget.
521 * @kcontrol: The kcontrol of this widget.
522 * @event: Event id.
523 *
1319b2f6
OC		 524 */
525static int set_dmic_clk(struct snd_soc_dapm_widget *w,
526 struct snd_kcontrol *kcontrol, int event)
527{
528 struct snd_soc_codec *codec = w->codec;
529 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
49ef7925
OC		 530 int idx = -EINVAL;
531
532 idx = rl6231_calc_dmic_clk(rt5645->sysclk);
1319b2f6
OC		 533
534 if (idx < 0)
535 dev_err(codec->dev, "Failed to set DMIC clock\n");
536 else
537 snd_soc_update_bits(codec, RT5645_DMIC_CTRL1,
538 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
539 return idx;
540}
541
542static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
543 struct snd_soc_dapm_widget *sink)
544{
545 unsigned int val;
546
547 val = snd_soc_read(source->codec, RT5645_GLB_CLK);
548 val &= RT5645_SCLK_SRC_MASK;
549 if (val == RT5645_SCLK_SRC_PLL1)
550 return 1;
551 else
552 return 0;
553}
554
9e268353
BL		 555static int is_using_asrc(struct snd_soc_dapm_widget *source,
556 struct snd_soc_dapm_widget *sink)
557{
558 unsigned int reg, shift, val;
559
560 switch (source->shift) {
561 case 0:
562 reg = RT5645_ASRC_3;
563 shift = 0;
564 break;
565 case 1:
566 reg = RT5645_ASRC_3;
567 shift = 4;
568 break;
569 case 3:
570 reg = RT5645_ASRC_2;
571 shift = 0;
572 break;
573 case 8:
574 reg = RT5645_ASRC_2;
575 shift = 4;
576 break;
577 case 9:
578 reg = RT5645_ASRC_2;
579 shift = 8;
580 break;
581 case 10:
582 reg = RT5645_ASRC_2;
583 shift = 12;
584 break;
585 default:
586 return 0;
587 }
588
589 val = (snd_soc_read(source->codec, reg) >> shift) & 0xf;
590 switch (val) {
591 case 1:
592 case 2:
593 case 3:
594 case 4:
595 return 1;
596 default:
597 return 0;
598 }
599
600}
601
1319b2f6
OC		 602/* Digital Mixer */
603static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
604 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
605 RT5645_M_ADC_L1_SFT, 1, 1),
606 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
607 RT5645_M_ADC_L2_SFT, 1, 1),
608};
609
610static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
611 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
612 RT5645_M_ADC_R1_SFT, 1, 1),
613 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
614 RT5645_M_ADC_R2_SFT, 1, 1),
615};
616
617static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
618 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
619 RT5645_M_MONO_ADC_L1_SFT, 1, 1),
620 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
621 RT5645_M_MONO_ADC_L2_SFT, 1, 1),
622};
623
624static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
625 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
626 RT5645_M_MONO_ADC_R1_SFT, 1, 1),
627 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
628 RT5645_M_MONO_ADC_R2_SFT, 1, 1),
629};
630
631static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
632 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
633 RT5645_M_ADCMIX_L_SFT, 1, 1),
634 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
635 RT5645_M_DAC1_L_SFT, 1, 1),
636};
637
638static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
639 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
640 RT5645_M_ADCMIX_R_SFT, 1, 1),
641 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
642 RT5645_M_DAC1_R_SFT, 1, 1),
643};
644
645static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
646 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
647 RT5645_M_DAC_L1_SFT, 1, 1),
648 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
649 RT5645_M_DAC_L2_SFT, 1, 1),
650 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
651 RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
652};
653
654static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
655 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
656 RT5645_M_DAC_R1_SFT, 1, 1),
657 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
658 RT5645_M_DAC_R2_SFT, 1, 1),
659 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
660 RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
661};
662
663static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
664 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
665 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
666 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
667 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
668 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
669 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
670};
671
672static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
673 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
674 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
675 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
676 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
677 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
678 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
679};
680
681static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
682 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
683 RT5645_M_STO_L_DAC_L_SFT, 1, 1),
684 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
685 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
686 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
687 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
688};
689
690static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
691 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
692 RT5645_M_STO_R_DAC_R_SFT, 1, 1),
693 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
694 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
695 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
696 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
697};
698
699/* Analog Input Mixer */
700static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
701 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
702 RT5645_M_HP_L_RM_L_SFT, 1, 1),
703 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
704 RT5645_M_IN_L_RM_L_SFT, 1, 1),
705 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
706 RT5645_M_BST2_RM_L_SFT, 1, 1),
707 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
708 RT5645_M_BST1_RM_L_SFT, 1, 1),
709 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
710 RT5645_M_OM_L_RM_L_SFT, 1, 1),
711};
712
713static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
714 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
715 RT5645_M_HP_R_RM_R_SFT, 1, 1),
716 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
717 RT5645_M_IN_R_RM_R_SFT, 1, 1),
718 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
719 RT5645_M_BST2_RM_R_SFT, 1, 1),
720 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
721 RT5645_M_BST1_RM_R_SFT, 1, 1),
722 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
723 RT5645_M_OM_R_RM_R_SFT, 1, 1),
724};
725
726static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
727 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
728 RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
729 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
730 RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
731 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
732 RT5645_M_IN_L_SM_L_SFT, 1, 1),
733 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
734 RT5645_M_BST1_L_SM_L_SFT, 1, 1),
735};
736
737static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
738 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
739 RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
740 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
741 RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
742 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
743 RT5645_M_IN_R_SM_R_SFT, 1, 1),
744 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
745 RT5645_M_BST2_R_SM_R_SFT, 1, 1),
746};
747
748static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
749 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
750 RT5645_M_BST1_OM_L_SFT, 1, 1),
751 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
752 RT5645_M_IN_L_OM_L_SFT, 1, 1),
753 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
754 RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
755 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
756 RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
757};
758
759static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
760 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
761 RT5645_M_BST2_OM_R_SFT, 1, 1),
762 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
763 RT5645_M_IN_R_OM_R_SFT, 1, 1),
764 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
765 RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
766 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
767 RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
768};
769
770static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
771 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
772 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
773 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
774 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
775 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
776 RT5645_M_SV_R_SPM_L_SFT, 1, 1),
777 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
778 RT5645_M_SV_L_SPM_L_SFT, 1, 1),
779};
780
781static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
782 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
783 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
784 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
785 RT5645_M_SV_R_SPM_R_SFT, 1, 1),
786};
787
788static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
789 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
790 RT5645_M_DAC1_HM_SFT, 1, 1),
791 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
792 RT5645_M_HPVOL_HM_SFT, 1, 1),
793};
794
795static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
796 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
797 RT5645_M_DAC1_HV_SFT, 1, 1),
798 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
799 RT5645_M_DAC2_HV_SFT, 1, 1),
800 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
801 RT5645_M_IN_HV_SFT, 1, 1),
802 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
803 RT5645_M_BST1_HV_SFT, 1, 1),
804};
805
806static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
807 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
808 RT5645_M_DAC1_HV_SFT, 1, 1),
809 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
810 RT5645_M_DAC2_HV_SFT, 1, 1),
811 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
812 RT5645_M_IN_HV_SFT, 1, 1),
813 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
814 RT5645_M_BST2_HV_SFT, 1, 1),
815};
816
817static const struct snd_kcontrol_new rt5645_lout_mix[] = {
818 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
819 RT5645_M_DAC_L1_LM_SFT, 1, 1),
820 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
821 RT5645_M_DAC_R1_LM_SFT, 1, 1),
822 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
823 RT5645_M_OV_L_LM_SFT, 1, 1),
824 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
825 RT5645_M_OV_R_LM_SFT, 1, 1),
826};
827
828/*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
829static const char * const rt5645_dac1_src[] = {
830 "IF1 DAC", "IF2 DAC", "IF3 DAC"
831};
832
833static SOC_ENUM_SINGLE_DECL(
834 rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
835 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
836
837static const struct snd_kcontrol_new rt5645_dac1l_mux =
838 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
839
840static SOC_ENUM_SINGLE_DECL(
841 rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
842 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
843
844static const struct snd_kcontrol_new rt5645_dac1r_mux =
845 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
846
847/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
848static const char * const rt5645_dac12_src[] = {
849 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
850};
851
852static SOC_ENUM_SINGLE_DECL(
853 rt5645_dac2l_enum, RT5645_DAC_CTRL,
854 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
855
856static const struct snd_kcontrol_new rt5645_dac_l2_mux =
857 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
858
859static const char * const rt5645_dacr2_src[] = {
860 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
861};
862
863static SOC_ENUM_SINGLE_DECL(
864 rt5645_dac2r_enum, RT5645_DAC_CTRL,
865 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
866
867static const struct snd_kcontrol_new rt5645_dac_r2_mux =
868 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
869
870
871/* INL/R source */
872static const char * const rt5645_inl_src[] = {
873 "IN2P", "MonoP"
874};
875
876static SOC_ENUM_SINGLE_DECL(
877 rt5645_inl_enum, RT5645_INL1_INR1_VOL,
878 RT5645_INL_SEL_SFT, rt5645_inl_src);
879
880static const struct snd_kcontrol_new rt5645_inl_mux =
881 SOC_DAPM_ENUM("INL source", rt5645_inl_enum);
882
883static const char * const rt5645_inr_src[] = {
884 "IN2N", "MonoN"
885};
886
887static SOC_ENUM_SINGLE_DECL(
888 rt5645_inr_enum, RT5645_INL1_INR1_VOL,
889 RT5645_INR_SEL_SFT, rt5645_inr_src);
890
891static const struct snd_kcontrol_new rt5645_inr_mux =
892 SOC_DAPM_ENUM("INR source", rt5645_inr_enum);
893
894/* Stereo1 ADC source */
895/* MX-27 [12] */
896static const char * const rt5645_stereo_adc1_src[] = {
897 "DAC MIX", "ADC"
898};
899
900static SOC_ENUM_SINGLE_DECL(
901 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
902 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
903
904static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
905 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
906
907/* MX-27 [11] */
908static const char * const rt5645_stereo_adc2_src[] = {
909 "DAC MIX", "DMIC"
910};
911
912static SOC_ENUM_SINGLE_DECL(
913 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
914 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
915
916static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
917 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
918
919/* MX-27 [8] */
920static const char * const rt5645_stereo_dmic_src[] = {
921 "DMIC1", "DMIC2"
922};
923
924static SOC_ENUM_SINGLE_DECL(
925 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
926 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
927
928static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
929 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
930
931/* Mono ADC source */
932/* MX-28 [12] */
933static const char * const rt5645_mono_adc_l1_src[] = {
934 "Mono DAC MIXL", "ADC"
935};
936
937static SOC_ENUM_SINGLE_DECL(
938 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
939 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
940
941static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
942 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
943/* MX-28 [11] */
944static const char * const rt5645_mono_adc_l2_src[] = {
945 "Mono DAC MIXL", "DMIC"
946};
947
948static SOC_ENUM_SINGLE_DECL(
949 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
950 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
951
952static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
953 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
954
955/* MX-28 [8] */
956static const char * const rt5645_mono_dmic_src[] = {
957 "DMIC1", "DMIC2"
958};
959
960static SOC_ENUM_SINGLE_DECL(
961 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
962 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
963
964static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
965 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
966/* MX-28 [1:0] */
967static SOC_ENUM_SINGLE_DECL(
968 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
969 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
970
971static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
972 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
973/* MX-28 [4] */
974static const char * const rt5645_mono_adc_r1_src[] = {
975 "Mono DAC MIXR", "ADC"
976};
977
978static SOC_ENUM_SINGLE_DECL(
979 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
980 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
981
982static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
983 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
984/* MX-28 [3] */
985static const char * const rt5645_mono_adc_r2_src[] = {
986 "Mono DAC MIXR", "DMIC"
987};
988
989static SOC_ENUM_SINGLE_DECL(
990 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
991 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
992
993static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
994 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
995
996/* MX-77 [9:8] */
997static const char * const rt5645_if1_adc_in_src[] = {
998 "IF_ADC1", "IF_ADC2", "VAD_ADC"
999};
1000
1001static SOC_ENUM_SINGLE_DECL(
1002 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
1003 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
1004
1005static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
1006 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
1007
1008/* MX-2F [13:12] */
1009static const char * const rt5645_if2_adc_in_src[] = {
1010 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1011};
1012
1013static SOC_ENUM_SINGLE_DECL(
1014 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
1015 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
1016
1017static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
1018 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
1019
1020/* MX-2F [1:0] */
1021static const char * const rt5645_if3_adc_in_src[] = {
1022 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1023};
1024
1025static SOC_ENUM_SINGLE_DECL(
1026 rt5645_if3_adc_in_enum, RT5645_DIG_INF1_DATA,
1027 RT5645_IF3_ADC_IN_SFT, rt5645_if3_adc_in_src);
1028
1029static const struct snd_kcontrol_new rt5645_if3_adc_in_mux =
1030 SOC_DAPM_ENUM("IF3 ADC IN source", rt5645_if3_adc_in_enum);
1031
1032/* MX-31 [15] [13] [11] [9] */
1033static const char * const rt5645_pdm_src[] = {
1034 "Mono DAC", "Stereo DAC"
1035};
1036
1037static SOC_ENUM_SINGLE_DECL(
1038 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
1039 RT5645_PDM1_L_SFT, rt5645_pdm_src);
1040
1041static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
1042 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
1043
1044static SOC_ENUM_SINGLE_DECL(
1045 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
1046 RT5645_PDM1_R_SFT, rt5645_pdm_src);
1047
1048static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
1049 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
1050
1051/* MX-9D [9:8] */
1052static const char * const rt5645_vad_adc_src[] = {
1053 "Sto1 ADC L", "Mono ADC L", "Mono ADC R"
1054};
1055
1056static SOC_ENUM_SINGLE_DECL(
1057 rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
1058 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
1059
1060static const struct snd_kcontrol_new rt5645_vad_adc_mux =
1061 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
1062
1063static const struct snd_kcontrol_new spk_l_vol_control =
1064 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1065 RT5645_L_MUTE_SFT, 1, 1);
1066
1067static const struct snd_kcontrol_new spk_r_vol_control =
1068 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1069 RT5645_R_MUTE_SFT, 1, 1);
1070
1071static const struct snd_kcontrol_new hp_l_vol_control =
1072 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1073 RT5645_L_MUTE_SFT, 1, 1);
1074
1075static const struct snd_kcontrol_new hp_r_vol_control =
1076 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1077 RT5645_R_MUTE_SFT, 1, 1);
1078
1079static const struct snd_kcontrol_new pdm1_l_vol_control =
1080 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1081 RT5645_M_PDM1_L, 1, 1);
1082
1083static const struct snd_kcontrol_new pdm1_r_vol_control =
1084 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1085 RT5645_M_PDM1_R, 1, 1);
1086
1087static void hp_amp_power(struct snd_soc_codec *codec, int on)
1088{
1089 static int hp_amp_power_count;
1090 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1091
1092 if (on) {
1093 if (hp_amp_power_count <= 0) {
1094 /* depop parameters */
1095 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1096 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
1097 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d);
1098 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1099 RT5645_HP_DCC_INT1, 0x9f01);
1100 mdelay(150);
1101 /* headphone amp power on */
1102 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1103 RT5645_PWR_FV1 | RT5645_PWR_FV2 , 0);
1104 snd_soc_update_bits(codec, RT5645_PWR_VOL,
1105 RT5645_PWR_HV_L | RT5645_PWR_HV_R,
1106 RT5645_PWR_HV_L | RT5645_PWR_HV_R);
1107 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1108 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1109 RT5645_PWR_HA,
1110 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1111 RT5645_PWR_HA);
1112 mdelay(5);
1113 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1114 RT5645_PWR_FV1 | RT5645_PWR_FV2,
1115 RT5645_PWR_FV1 | RT5645_PWR_FV2);
1116
1117 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1118 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
1119 RT5645_HP_CO_EN | RT5645_HP_SG_EN);
1120 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1121 0x14, 0x1aaa);
1122 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1123 0x24, 0x0430);
1124 }
1125 hp_amp_power_count++;
1126 } else {
1127 hp_amp_power_count--;
1128 if (hp_amp_power_count <= 0) {
1129 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1130 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1131 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1132 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1133 /* headphone amp power down */
1134 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0000);
1135 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1136 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1137 RT5645_PWR_HA, 0);
1138 }
1139 }
1140}
1141
1142static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
1143 struct snd_kcontrol *kcontrol, int event)
1144{
1145 struct snd_soc_codec *codec = w->codec;
1146 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1147
1148 switch (event) {
1149 case SND_SOC_DAPM_POST_PMU:
1150 hp_amp_power(codec, 1);
1151 /* headphone unmute sequence */
1152 snd_soc_update_bits(codec, RT5645_DEPOP_M3, RT5645_CP_FQ1_MASK |
1153 RT5645_CP_FQ2_MASK | RT5645_CP_FQ3_MASK,
1154 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
1155 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1156 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
1157 regmap_write(rt5645->regmap,
1158 RT5645_PR_BASE + RT5645_MAMP_INT_REG2, 0xfc00);
1159 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1160 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1161 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1162 RT5645_RSTN_MASK, RT5645_RSTN_EN);
1163 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1164 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1165 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1166 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1167 msleep(40);
1168 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1169 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1170 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1171 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1172 break;
1173
1174 case SND_SOC_DAPM_PRE_PMD:
1175 /* headphone mute sequence */
1176 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1177 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1178 RT5645_CP_FQ3_MASK,
1179 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
1180 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1181 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
1182 regmap_write(rt5645->regmap,
1183 RT5645_PR_BASE + RT5645_MAMP_INT_REG2, 0xfc00);
1184 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1185 RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1186 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1187 RT5645_RSTP_MASK, RT5645_RSTP_EN);
1188 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1189 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1190 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1191 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1192 msleep(30);
1193 hp_amp_power(codec, 0);
1194 break;
1195
1196 default:
1197 return 0;
1198 }
1199
1200 return 0;
1201}
1202
1203static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
1204 struct snd_kcontrol *kcontrol, int event)
1205{
1206 struct snd_soc_codec *codec = w->codec;
1319b2f6
OC		 1207
1208 switch (event) {
1209 case SND_SOC_DAPM_POST_PMU:
1210 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1211 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1212 RT5645_PWR_CLS_D_L,
1213 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1214 RT5645_PWR_CLS_D_L);
1215 break;
1216
1217 case SND_SOC_DAPM_PRE_PMD:
1218 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1219 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1220 RT5645_PWR_CLS_D_L, 0);
1221 break;
1222
1223 default:
1224 return 0;
1225 }
1226
1227 return 0;
1228}
1229
1230static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
1231 struct snd_kcontrol *kcontrol, int event)
1232{
1233 struct snd_soc_codec *codec = w->codec;
1234
1235 switch (event) {
1236 case SND_SOC_DAPM_POST_PMU:
1237 hp_amp_power(codec, 1);
1238 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1239 RT5645_PWR_LM, RT5645_PWR_LM);
1240 snd_soc_update_bits(codec, RT5645_LOUT1,
1241 RT5645_L_MUTE | RT5645_R_MUTE, 0);
1242 break;
1243
1244 case SND_SOC_DAPM_PRE_PMD:
1245 snd_soc_update_bits(codec, RT5645_LOUT1,
1246 RT5645_L_MUTE | RT5645_R_MUTE,
1247 RT5645_L_MUTE | RT5645_R_MUTE);
1248 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1249 RT5645_PWR_LM, 0);
1250 hp_amp_power(codec, 0);
1251 break;
1252
1253 default:
1254 return 0;
1255 }
1256
1257 return 0;
1258}
1259
1260static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
1261 struct snd_kcontrol *kcontrol, int event)
1262{
1263 struct snd_soc_codec *codec = w->codec;
1264
1265 switch (event) {
1266 case SND_SOC_DAPM_POST_PMU:
1267 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1268 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
1269 break;
1270
1271 case SND_SOC_DAPM_PRE_PMD:
1272 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1273 RT5645_PWR_BST2_P, 0);
1274 break;
1275
1276 default:
1277 return 0;
1278 }
1279
1280 return 0;
1281}
1282
1283static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
1284 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
1285 RT5645_PWR_LDO2_BIT, 0, NULL, 0),
1286 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
1287 RT5645_PWR_PLL_BIT, 0, NULL, 0),
1288
1289 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
1290 RT5645_PWR_JD1_BIT, 0, NULL, 0),
1291 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
1292 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
1293
9e268353
BL		 1294 /* ASRC */
1295 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1,
1296 11, 0, NULL, 0),
1297 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1,
1298 12, 0, NULL, 0),
1299 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1,
1300 10, 0, NULL, 0),
1301 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1,
1302 9, 0, NULL, 0),
1303 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1,
1304 8, 0, NULL, 0),
1305 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1,
1306 7, 0, NULL, 0),
1307 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1,
1308 5, 0, NULL, 0),
1309 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1,
1310 4, 0, NULL, 0),
1311 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1,
1312 3, 0, NULL, 0),
1313 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1,
1314 1, 0, NULL, 0),
1315 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1,
1316 0, 0, NULL, 0),
1317
1319b2f6
OC		 1318 /* Input Side */
1319 /* micbias */
1320 SND_SOC_DAPM_MICBIAS("micbias1", RT5645_PWR_ANLG2,
1321 RT5645_PWR_MB1_BIT, 0),
1322 SND_SOC_DAPM_MICBIAS("micbias2", RT5645_PWR_ANLG2,
1323 RT5645_PWR_MB2_BIT, 0),
1324 /* Input Lines */
1325 SND_SOC_DAPM_INPUT("DMIC L1"),
1326 SND_SOC_DAPM_INPUT("DMIC R1"),
1327 SND_SOC_DAPM_INPUT("DMIC L2"),
1328 SND_SOC_DAPM_INPUT("DMIC R2"),
1329
1330 SND_SOC_DAPM_INPUT("IN1P"),
1331 SND_SOC_DAPM_INPUT("IN1N"),
1332 SND_SOC_DAPM_INPUT("IN2P"),
1333 SND_SOC_DAPM_INPUT("IN2N"),
1334
1335 SND_SOC_DAPM_INPUT("Haptic Generator"),
1336
1337 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1338 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1339 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1340 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1341 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
1342 RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
1343 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
1344 RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
1345 /* Boost */
1346 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
1347 RT5645_PWR_BST1_BIT, 0, NULL, 0),
1348 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
1349 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
1350 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1351 /* Input Volume */
1352 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
1353 RT5645_PWR_IN_L_BIT, 0, NULL, 0),
1354 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
1355 RT5645_PWR_IN_R_BIT, 0, NULL, 0),
1356 /* REC Mixer */
1357 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
1358 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
1359 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
1360 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
1361 /* ADCs */
1362 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
1363 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
1364
1365 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
1366 RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
1367 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
1368 RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
1369
1370 /* ADC Mux */
1371 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1372 &rt5645_sto1_dmic_mux),
1373 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1374 &rt5645_sto_adc2_mux),
1375 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1376 &rt5645_sto_adc2_mux),
1377 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1378 &rt5645_sto_adc1_mux),
1379 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1380 &rt5645_sto_adc1_mux),
1381 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1382 &rt5645_mono_dmic_l_mux),
1383 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1384 &rt5645_mono_dmic_r_mux),
1385 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1386 &rt5645_mono_adc_l2_mux),
1387 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1388 &rt5645_mono_adc_l1_mux),
1389 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1390 &rt5645_mono_adc_r1_mux),
1391 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1392 &rt5645_mono_adc_r2_mux),
1393 /* ADC Mixer */
1394
1395 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
1396 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
1397 SND_SOC_DAPM_SUPPLY_S("adc stereo2 filter", 1, RT5645_PWR_DIG2,
1398 RT5645_PWR_ADC_S2F_BIT, 0, NULL, 0),
1399 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1400 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
1401 NULL, 0),
1402 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
1403 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
1404 NULL, 0),
1405 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
1406 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1407 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1408 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
1409 NULL, 0),
1410 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
1411 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1412 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1413 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
1414 NULL, 0),
1415
1416 /* ADC PGA */
1417 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1418 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1419 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1420 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1421 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1422 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1423 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1424 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1425 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1426 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1427
1428 /* IF1 2 Mux */
1429 SND_SOC_DAPM_MUX("IF1 ADC Mux", SND_SOC_NOPM,
1430 0, 0, &rt5645_if1_adc_in_mux),
1431 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
1432 0, 0, &rt5645_if2_adc_in_mux),
1433
1434 /* Digital Interface */
1435 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
1436 RT5645_PWR_I2S1_BIT, 0, NULL, 0),
1437 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1438 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1439 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1440 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1441 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1442 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1443 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1444 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1445 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1446 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
1447 RT5645_PWR_I2S2_BIT, 0, NULL, 0),
1448 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1449 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1450 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1451 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1452
1453 /* Digital Interface Select */
1454 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
1455 0, 0, &rt5645_vad_adc_mux),
1456
1457 /* Audio Interface */
1458 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1459 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1460 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1461 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1462
1463 /* Output Side */
1464 /* DAC mixer before sound effect */
1465 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1466 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
1467 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1468 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
1469
1470 /* DAC2 channel Mux */
1471 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
1472 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
1473 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
1474 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
1475 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
1476 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
1477
1478 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
1479 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
1480
1481 /* DAC Mixer */
1482 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
1483 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
1484 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
1485 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
1486 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
1487 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
1488 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1489 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
1490 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1491 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
1492 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
1493 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
1494 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
1495 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
1496 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1497 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
1498 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1499 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
1500
1501 /* DACs */
1502 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
1503 0),
1504 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
1505 0),
1506 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
1507 0),
1508 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
1509 0),
1510 /* OUT Mixer */
1511 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
1512 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
1513 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
1514 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
1515 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
1516 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
1517 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
1518 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
1519 /* Ouput Volume */
1520 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
1521 &spk_l_vol_control),
1522 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
1523 &spk_r_vol_control),
1524 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
1525 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
1526 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
1527 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
1528 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
1529 RT5645_PWR_HM_L_BIT, 0, NULL, 0),
1530 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
1531 RT5645_PWR_HM_R_BIT, 0, NULL, 0),
1532 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
1533 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
1534 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
1535 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
1536 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
1537
1538 /* HPO/LOUT/Mono Mixer */
1539 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
1540 ARRAY_SIZE(rt5645_spo_l_mix)),
1541 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
1542 ARRAY_SIZE(rt5645_spo_r_mix)),
1543 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
1544 ARRAY_SIZE(rt5645_hpo_mix)),
1545 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
1546 ARRAY_SIZE(rt5645_lout_mix)),
1547
1548 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
1549 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1550 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
1551 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1552 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
1553 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1554
1555 /* PDM */
1556 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
1557 0, NULL, 0),
1558 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
1559 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
1560
1561 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
1562 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
1563
1564 /* Output Lines */
1565 SND_SOC_DAPM_OUTPUT("HPOL"),
1566 SND_SOC_DAPM_OUTPUT("HPOR"),
1567 SND_SOC_DAPM_OUTPUT("LOUTL"),
1568 SND_SOC_DAPM_OUTPUT("LOUTR"),
1569 SND_SOC_DAPM_OUTPUT("PDM1L"),
1570 SND_SOC_DAPM_OUTPUT("PDM1R"),
1571 SND_SOC_DAPM_OUTPUT("SPOL"),
1572 SND_SOC_DAPM_OUTPUT("SPOR"),
1573};
1574
1575static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
9e268353
BL		 1576 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
1577 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
1578 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
1579 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
1580 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc },
1581 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc },
1582 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
1583
1584 { "I2S1", NULL, "I2S1 ASRC" },
1585 { "I2S2", NULL, "I2S2 ASRC" },
1586
1319b2f6
OC		 1587 { "IN1P", NULL, "LDO2" },
1588 { "IN2P", NULL, "LDO2" },
1589
1590 { "DMIC1", NULL, "DMIC L1" },
1591 { "DMIC1", NULL, "DMIC R1" },
1592 { "DMIC2", NULL, "DMIC L2" },
1593 { "DMIC2", NULL, "DMIC R2" },
1594
1595 { "BST1", NULL, "IN1P" },
1596 { "BST1", NULL, "IN1N" },
1597 { "BST1", NULL, "JD Power" },
1598 { "BST1", NULL, "Mic Det Power" },
1599 { "BST2", NULL, "IN2P" },
1600 { "BST2", NULL, "IN2N" },
1601
1602 { "INL VOL", NULL, "IN2P" },
1603 { "INR VOL", NULL, "IN2N" },
1604
1605 { "RECMIXL", "HPOL Switch", "HPOL" },
1606 { "RECMIXL", "INL Switch", "INL VOL" },
1607 { "RECMIXL", "BST2 Switch", "BST2" },
1608 { "RECMIXL", "BST1 Switch", "BST1" },
1609 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
1610
1611 { "RECMIXR", "HPOR Switch", "HPOR" },
1612 { "RECMIXR", "INR Switch", "INR VOL" },
1613 { "RECMIXR", "BST2 Switch", "BST2" },
1614 { "RECMIXR", "BST1 Switch", "BST1" },
1615 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
1616
1617 { "ADC L", NULL, "RECMIXL" },
1618 { "ADC L", NULL, "ADC L power" },
1619 { "ADC R", NULL, "RECMIXR" },
1620 { "ADC R", NULL, "ADC R power" },
1621
1622 {"DMIC L1", NULL, "DMIC CLK"},
1623 {"DMIC L1", NULL, "DMIC1 Power"},
1624 {"DMIC R1", NULL, "DMIC CLK"},
1625 {"DMIC R1", NULL, "DMIC1 Power"},
1626 {"DMIC L2", NULL, "DMIC CLK"},
1627 {"DMIC L2", NULL, "DMIC2 Power"},
1628 {"DMIC R2", NULL, "DMIC CLK"},
1629 {"DMIC R2", NULL, "DMIC2 Power"},
1630
1631 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
1632 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
9e268353 1633 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" },
1319b2f6
OC		 1634
1635 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
1636 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
9e268353 1637 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" },
1319b2f6
OC		 1638
1639 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
1640 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
9e268353 1641 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" },
1319b2f6
OC		 1642
1643 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1644 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
1645 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
1646 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
1647
1648 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
1649 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
1650 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1651 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
1652
1653 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
1654 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1655 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1656 { "Mono ADC L1 Mux", "ADC", "ADC L" },
1657
1658 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1659 { "Mono ADC R1 Mux", "ADC", "ADC R" },
1660 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
1661 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1662
1663 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
1664 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
1665 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
1666 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
1667
1668 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
1669 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
1670 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
1671
1672 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
1673 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
1674 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
1675
1676 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
1677 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
1678 { "Mono ADC MIXL", NULL, "adc mono left filter" },
1679 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
1680
1681 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
1682 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
1683 { "Mono ADC MIXR", NULL, "adc mono right filter" },
1684 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
1685
1686 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
1687 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
1688 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
1689
1690 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
1691 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
1692 { "IF_ADC2", NULL, "Mono ADC MIXL" },
1693 { "IF_ADC2", NULL, "Mono ADC MIXR" },
1694 { "VAD_ADC", NULL, "VAD ADC Mux" },
1695
1696 { "IF1 ADC Mux", "IF_ADC1", "IF_ADC1" },
1697 { "IF1 ADC Mux", "IF_ADC2", "IF_ADC2" },
1698 { "IF1 ADC Mux", "VAD_ADC", "VAD_ADC" },
1699
1700 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
1701 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
1702 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
1703
1704 { "IF1 ADC", NULL, "I2S1" },
1705 { "IF1 ADC", NULL, "IF1 ADC Mux" },
1706 { "IF2 ADC", NULL, "I2S2" },
1707 { "IF2 ADC", NULL, "IF2 ADC Mux" },
1708
1709 { "AIF1TX", NULL, "IF1 ADC" },
1710 { "AIF1TX", NULL, "IF2 ADC" },
1711 { "AIF2TX", NULL, "IF2 ADC" },
1712
1713 { "IF1 DAC1", NULL, "AIF1RX" },
1714 { "IF1 DAC2", NULL, "AIF1RX" },
1715 { "IF2 DAC", NULL, "AIF2RX" },
1716
1717 { "IF1 DAC1", NULL, "I2S1" },
1718 { "IF1 DAC2", NULL, "I2S1" },
1719 { "IF2 DAC", NULL, "I2S2" },
1720
1721 { "IF1 DAC2 L", NULL, "IF1 DAC2" },
1722 { "IF1 DAC2 R", NULL, "IF1 DAC2" },
1723 { "IF1 DAC1 L", NULL, "IF1 DAC1" },
1724 { "IF1 DAC1 R", NULL, "IF1 DAC1" },
1725 { "IF2 DAC L", NULL, "IF2 DAC" },
1726 { "IF2 DAC R", NULL, "IF2 DAC" },
1727
1728 { "DAC1 L Mux", "IF1 DAC", "IF1 DAC1 L" },
1729 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
1730
1731 { "DAC1 R Mux", "IF1 DAC", "IF1 DAC1 R" },
1732 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
1733
1734 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
1735 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
1736 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
1737 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
1738 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
1739 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
1740
1741 { "DAC L2 Mux", "IF1 DAC", "IF1 DAC2 L" },
1742 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
1743 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
1744 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
1745 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
1746 { "DAC L2 Volume", NULL, "dac mono left filter" },
1747
1748 { "DAC R2 Mux", "IF1 DAC", "IF1 DAC2 R" },
1749 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
1750 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
1751 { "DAC R2 Mux", "Haptic", "Haptic Generator" },
1752 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
1753 { "DAC R2 Volume", NULL, "dac mono right filter" },
1754
1755 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
1756 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
1757 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1758 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
1759 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
1760 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
1761 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1762 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
1763
1764 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
1765 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1766 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
1767 { "Mono DAC MIXL", NULL, "dac mono left filter" },
1768 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
1769 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1770 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
1771 { "Mono DAC MIXR", NULL, "dac mono right filter" },
1772
1773 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
1774 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1775 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
1776 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
1777 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1778 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
1779
1780 { "DAC L1", NULL, "Stereo DAC MIXL" },
1781 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
1782 { "DAC R1", NULL, "Stereo DAC MIXR" },
1783 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
1784 { "DAC L2", NULL, "Mono DAC MIXL" },
1785 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
1786 { "DAC R2", NULL, "Mono DAC MIXR" },
1787 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
1788
1789 { "SPK MIXL", "BST1 Switch", "BST1" },
1790 { "SPK MIXL", "INL Switch", "INL VOL" },
1791 { "SPK MIXL", "DAC L1 Switch", "DAC L1" },
1792 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
1793 { "SPK MIXR", "BST2 Switch", "BST2" },
1794 { "SPK MIXR", "INR Switch", "INR VOL" },
1795 { "SPK MIXR", "DAC R1 Switch", "DAC R1" },
1796 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
1797
1798 { "OUT MIXL", "BST1 Switch", "BST1" },
1799 { "OUT MIXL", "INL Switch", "INL VOL" },
1800 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
1801 { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
1802
1803 { "OUT MIXR", "BST2 Switch", "BST2" },
1804 { "OUT MIXR", "INR Switch", "INR VOL" },
1805 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
1806 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
1807
1808 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
1809 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
1810 { "HPOVOL MIXL", "INL Switch", "INL VOL" },
1811 { "HPOVOL MIXL", "BST1 Switch", "BST1" },
1812 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
1813 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
1814 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
1815 { "HPOVOL MIXR", "INR Switch", "INR VOL" },
1816 { "HPOVOL MIXR", "BST2 Switch", "BST2" },
1817 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
1818
1819 { "DAC 2", NULL, "DAC L2" },
1820 { "DAC 2", NULL, "DAC R2" },
1821 { "DAC 1", NULL, "DAC L1" },
1822 { "DAC 1", NULL, "DAC R1" },
1823 { "HPOVOL L", "Switch", "HPOVOL MIXL" },
1824 { "HPOVOL R", "Switch", "HPOVOL MIXR" },
1825 { "HPOVOL", NULL, "HPOVOL L" },
1826 { "HPOVOL", NULL, "HPOVOL R" },
1827 { "HPO MIX", "DAC1 Switch", "DAC 1" },
1828 { "HPO MIX", "HPVOL Switch", "HPOVOL" },
1829
1830 { "SPKVOL L", "Switch", "SPK MIXL" },
1831 { "SPKVOL R", "Switch", "SPK MIXR" },
1832
1833 { "SPOL MIX", "DAC R1 Switch", "DAC R1" },
1834 { "SPOL MIX", "DAC L1 Switch", "DAC L1" },
1835 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
1836 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
1837 { "SPOR MIX", "DAC R1 Switch", "DAC R1" },
1838 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
1839
1840 { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
1841 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
1842 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
1843 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
1844
1845 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
1846 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
1847 { "PDM1 L Mux", NULL, "PDM1 Power" },
1848 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
1849 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
1850 { "PDM1 R Mux", NULL, "PDM1 Power" },
1851
1852 { "HP amp", NULL, "HPO MIX" },
1853 { "HP amp", NULL, "JD Power" },
1854 { "HP amp", NULL, "Mic Det Power" },
1855 { "HP amp", NULL, "LDO2" },
1856 { "HPOL", NULL, "HP amp" },
1857 { "HPOR", NULL, "HP amp" },
1858
1859 { "LOUT amp", NULL, "LOUT MIX" },
1860 { "LOUTL", NULL, "LOUT amp" },
1861 { "LOUTR", NULL, "LOUT amp" },
1862
1863 { "PDM1 L", "Switch", "PDM1 L Mux" },
1864 { "PDM1 R", "Switch", "PDM1 R Mux" },
1865
1866 { "PDM1L", NULL, "PDM1 L" },
1867 { "PDM1R", NULL, "PDM1 R" },
1868
1869 { "SPK amp", NULL, "SPOL MIX" },
1870 { "SPK amp", NULL, "SPOR MIX" },
1871 { "SPOL", NULL, "SPK amp" },
1872 { "SPOR", NULL, "SPK amp" },
1873};
1874
1319b2f6
OC		 1875static int rt5645_hw_params(struct snd_pcm_substream *substream,
1876 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1877{
1878 struct snd_soc_codec *codec = dai->codec;
1879 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1880 unsigned int val_len = 0, val_clk, mask_clk;
1881 int pre_div, bclk_ms, frame_size;
1882
1883 rt5645->lrck[dai->id] = params_rate(params);
d92950e7 1884 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
1319b2f6
OC		 1885 if (pre_div < 0) {
1886 dev_err(codec->dev, "Unsupported clock setting\n");
1887 return -EINVAL;
1888 }
1889 frame_size = snd_soc_params_to_frame_size(params);
1890 if (frame_size < 0) {
1891 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
1892 return -EINVAL;
1893 }
1894 bclk_ms = frame_size > 32;
1895 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
1896
1897 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
1898 rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
1899 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1900 bclk_ms, pre_div, dai->id);
1901
1902 switch (params_width(params)) {
1903 case 16:
1904 break;
1905 case 20:
1906 val_len |= RT5645_I2S_DL_20;
1907 break;
1908 case 24:
1909 val_len |= RT5645_I2S_DL_24;
1910 break;
1911 case 8:
1912 val_len |= RT5645_I2S_DL_8;
1913 break;
1914 default:
1915 return -EINVAL;
1916 }
1917
1918 switch (dai->id) {
1919 case RT5645_AIF1:
1920 mask_clk = RT5645_I2S_BCLK_MS1_MASK | RT5645_I2S_PD1_MASK;
1921 val_clk = bclk_ms << RT5645_I2S_BCLK_MS1_SFT |
1922 pre_div << RT5645_I2S_PD1_SFT;
1923 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
1924 RT5645_I2S_DL_MASK, val_len);
1925 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
1926 break;
1927 case RT5645_AIF2:
1928 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
1929 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
1930 pre_div << RT5645_I2S_PD2_SFT;
1931 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
1932 RT5645_I2S_DL_MASK, val_len);
1933 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
1934 break;
1935 default:
1936 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
1937 return -EINVAL;
1938 }
1939
1940 return 0;
1941}
1942
1943static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1944{
1945 struct snd_soc_codec *codec = dai->codec;
1946 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1947 unsigned int reg_val = 0;
1948
1949 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1950 case SND_SOC_DAIFMT_CBM_CFM:
1951 rt5645->master[dai->id] = 1;
1952 break;
1953 case SND_SOC_DAIFMT_CBS_CFS:
1954 reg_val |= RT5645_I2S_MS_S;
1955 rt5645->master[dai->id] = 0;
1956 break;
1957 default:
1958 return -EINVAL;
1959 }
1960
1961 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1962 case SND_SOC_DAIFMT_NB_NF:
1963 break;
1964 case SND_SOC_DAIFMT_IB_NF:
1965 reg_val |= RT5645_I2S_BP_INV;
1966 break;
1967 default:
1968 return -EINVAL;
1969 }
1970
1971 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1972 case SND_SOC_DAIFMT_I2S:
1973 break;
1974 case SND_SOC_DAIFMT_LEFT_J:
1975 reg_val |= RT5645_I2S_DF_LEFT;
1976 break;
1977 case SND_SOC_DAIFMT_DSP_A:
1978 reg_val |= RT5645_I2S_DF_PCM_A;
1979 break;
1980 case SND_SOC_DAIFMT_DSP_B:
1981 reg_val |= RT5645_I2S_DF_PCM_B;
1982 break;
1983 default:
1984 return -EINVAL;
1985 }
1986 switch (dai->id) {
1987 case RT5645_AIF1:
1988 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
1989 RT5645_I2S_MS_MASK | RT5645_I2S_BP_MASK |
1990 RT5645_I2S_DF_MASK, reg_val);
1991 break;
8c325704
AL		 1992 case RT5645_AIF2:
1993 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
1319b2f6
OC		 1994 RT5645_I2S_MS_MASK | RT5645_I2S_BP_MASK |
1995 RT5645_I2S_DF_MASK, reg_val);
1996 break;
1997 default:
1998 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
1999 return -EINVAL;
2000 }
2001 return 0;
2002}
2003
2004static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
2005 int clk_id, unsigned int freq, int dir)
2006{
2007 struct snd_soc_codec *codec = dai->codec;
2008 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2009 unsigned int reg_val = 0;
2010
2011 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
2012 return 0;
2013
2014 switch (clk_id) {
2015 case RT5645_SCLK_S_MCLK:
2016 reg_val |= RT5645_SCLK_SRC_MCLK;
2017 break;
2018 case RT5645_SCLK_S_PLL1:
2019 reg_val |= RT5645_SCLK_SRC_PLL1;
2020 break;
2021 case RT5645_SCLK_S_RCCLK:
2022 reg_val |= RT5645_SCLK_SRC_RCCLK;
2023 break;
2024 default:
2025 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2026 return -EINVAL;
2027 }
2028 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2029 RT5645_SCLK_SRC_MASK, reg_val);
2030 rt5645->sysclk = freq;
2031 rt5645->sysclk_src = clk_id;
2032
2033 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2034
2035 return 0;
2036}
2037
1319b2f6
OC		 2038static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2039 unsigned int freq_in, unsigned int freq_out)
2040{
2041 struct snd_soc_codec *codec = dai->codec;
2042 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
71c7a2d6 2043 struct rl6231_pll_code pll_code;
1319b2f6
OC		 2044 int ret;
2045
2046 if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
2047 freq_out == rt5645->pll_out)
2048 return 0;
2049
2050 if (!freq_in || !freq_out) {
2051 dev_dbg(codec->dev, "PLL disabled\n");
2052
2053 rt5645->pll_in = 0;
2054 rt5645->pll_out = 0;
2055 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2056 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
2057 return 0;
2058 }
2059
2060 switch (source) {
2061 case RT5645_PLL1_S_MCLK:
2062 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2063 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
2064 break;
2065 case RT5645_PLL1_S_BCLK1:
2066 case RT5645_PLL1_S_BCLK2:
2067 switch (dai->id) {
2068 case RT5645_AIF1:
2069 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2070 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
2071 break;
2072 case RT5645_AIF2:
2073 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2074 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
2075 break;
2076 default:
2077 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2078 return -EINVAL;
2079 }
2080 break;
2081 default:
2082 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2083 return -EINVAL;
2084 }
2085
71c7a2d6 2086 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1319b2f6
OC		 2087 if (ret < 0) {
2088 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2089 return ret;
2090 }
2091
2092 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
2093 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2094 pll_code.n_code, pll_code.k_code);
2095
2096 snd_soc_write(codec, RT5645_PLL_CTRL1,
2097 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
2098 snd_soc_write(codec, RT5645_PLL_CTRL2,
2099 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT |
2100 pll_code.m_bp << RT5645_PLL_M_BP_SFT);
2101
2102 rt5645->pll_in = freq_in;
2103 rt5645->pll_out = freq_out;
2104 rt5645->pll_src = source;
2105
2106 return 0;
2107}
2108
2109static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2110 unsigned int rx_mask, int slots, int slot_width)
2111{
2112 struct snd_soc_codec *codec = dai->codec;
2113 unsigned int val = 0;
2114
850577db 2115 if (rx_mask || tx_mask) {
1319b2f6 2116 val |= (1 << 14);
850577db
BL		 2117 snd_soc_update_bits(codec, RT5645_BASS_BACK,
2118 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB);
2119 }
1319b2f6
OC		 2120
2121 switch (slots) {
2122 case 4:
2123 val |= (1 << 12);
2124 break;
2125 case 6:
2126 val |= (2 << 12);
2127 break;
2128 case 8:
2129 val |= (3 << 12);
2130 break;
2131 case 2:
2132 default:
2133 break;
2134 }
2135
2136 switch (slot_width) {
2137 case 20:
2138 val |= (1 << 10);
2139 break;
2140 case 24:
2141 val |= (2 << 10);
2142 break;
2143 case 32:
2144 val |= (3 << 10);
2145 break;
2146 case 16:
2147 default:
2148 break;
2149 }
2150
2151 snd_soc_update_bits(codec, RT5645_TDM_CTRL_1, 0x7c00, val);
2152
2153 return 0;
2154}
2155
2156static int rt5645_set_bias_level(struct snd_soc_codec *codec,
2157 enum snd_soc_bias_level level)
2158{
2159 switch (level) {
0b2e4959
BL		 2160 case SND_SOC_BIAS_PREPARE:
2161 if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
1319b2f6
OC		 2162 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2163 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2164 RT5645_PWR_BG | RT5645_PWR_VREF2,
2165 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2166 RT5645_PWR_BG | RT5645_PWR_VREF2);
2167 mdelay(10);
2168 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2169 RT5645_PWR_FV1 | RT5645_PWR_FV2,
2170 RT5645_PWR_FV1 | RT5645_PWR_FV2);
2171 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
2172 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
2173 }
2174 break;
2175
0b2e4959
BL		 2176 case SND_SOC_BIAS_STANDBY:
2177 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2178 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2179 RT5645_PWR_BG | RT5645_PWR_VREF2,
2180 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2181 RT5645_PWR_BG | RT5645_PWR_VREF2);
2182 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2183 RT5645_PWR_FV1 | RT5645_PWR_FV2,
2184 RT5645_PWR_FV1 | RT5645_PWR_FV2);
2185 break;
2186
1319b2f6
OC		 2187 case SND_SOC_BIAS_OFF:
2188 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1100);
2189 snd_soc_write(codec, RT5645_GEN_CTRL1, 0x0128);
0b2e4959
BL		 2190 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2191 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2192 RT5645_PWR_BG | RT5645_PWR_VREF2 |
2193 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0);
1319b2f6
OC		 2194 break;
2195
2196 default:
2197 break;
2198 }
2199 codec->dapm.bias_level = level;
2200
2201 return 0;
2202}
2203
f3fa1bbd
OC		 2204static int rt5645_jack_detect(struct snd_soc_codec *codec,
2205 struct snd_soc_jack *jack)
2206{
2207 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2208 int gpio_state, jack_type = 0;
2209 unsigned int val;
2210
2211 gpio_state = gpio_get_value(rt5645->pdata.hp_det_gpio);
2212
2213 dev_dbg(codec->dev, "gpio = %d(%d)\n", rt5645->pdata.hp_det_gpio,
2214 gpio_state);
2215
2216 if ((rt5645->pdata.gpio_hp_det_active_high && gpio_state) ||
2217 (!rt5645->pdata.gpio_hp_det_active_high && !gpio_state)) {
2218 snd_soc_dapm_force_enable_pin(&codec->dapm, "micbias1");
2219 snd_soc_dapm_force_enable_pin(&codec->dapm, "micbias2");
2220 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2221 snd_soc_dapm_force_enable_pin(&codec->dapm, "Mic Det Power");
2222 snd_soc_dapm_sync(&codec->dapm);
2223
2224 snd_soc_write(codec, RT5645_IN1_CTRL1, 0x0006);
2225 snd_soc_write(codec, RT5645_JD_CTRL3, 0x00b0);
2226
2227 snd_soc_update_bits(codec, RT5645_IN1_CTRL2,
2228 RT5645_CBJ_MN_JD, 0);
2229 snd_soc_update_bits(codec, RT5645_IN1_CTRL2,
2230 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
2231
2232 msleep(400);
2233 val = snd_soc_read(codec, RT5645_IN1_CTRL3) & 0x7;
2234 dev_dbg(codec->dev, "val = %d\n", val);
2235
2236 if (val == 1 || val == 2)
2237 jack_type = SND_JACK_HEADSET;
2238 else
2239 jack_type = SND_JACK_HEADPHONE;
2240
2241 snd_soc_dapm_disable_pin(&codec->dapm, "micbias1");
2242 snd_soc_dapm_disable_pin(&codec->dapm, "micbias2");
2243 snd_soc_dapm_disable_pin(&codec->dapm, "LDO2");
2244 snd_soc_dapm_disable_pin(&codec->dapm, "Mic Det Power");
2245 snd_soc_dapm_sync(&codec->dapm);
2246 }
2247
2248 snd_soc_jack_report(rt5645->jack, jack_type, SND_JACK_HEADSET);
2249
2250 return 0;
2251}
2252
2253int rt5645_set_jack_detect(struct snd_soc_codec *codec,
2254 struct snd_soc_jack *jack)
2255{
2256 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2257
2258 rt5645->jack = jack;
2259
2260 rt5645_jack_detect(codec, rt5645->jack);
2261
2262 return 0;
2263}
2264EXPORT_SYMBOL_GPL(rt5645_set_jack_detect);
2265
cd6e82b8
OC		 2266static void rt5645_jack_detect_work(struct work_struct *work)
2267{
2268 struct rt5645_priv *rt5645 =
2269 container_of(work, struct rt5645_priv, jack_detect_work.work);
2270
2271 rt5645_jack_detect(rt5645->codec, rt5645->jack);
2272}
2273
f3fa1bbd
OC		 2274static irqreturn_t rt5645_irq(int irq, void *data)
2275{
2276 struct rt5645_priv *rt5645 = data;
2277
cd6e82b8
OC		 2278 queue_delayed_work(system_power_efficient_wq,
2279 &rt5645->jack_detect_work, msecs_to_jiffies(250));
f3fa1bbd
OC		 2280
2281 return IRQ_HANDLED;
2282}
2283
1319b2f6
OC		 2284static int rt5645_probe(struct snd_soc_codec *codec)
2285{
2286 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2287
2288 rt5645->codec = codec;
2289
2290 rt5645_set_bias_level(codec, SND_SOC_BIAS_OFF);
2291
2292 snd_soc_update_bits(codec, RT5645_CHARGE_PUMP, 0x0300, 0x0200);
1319b2f6 2293
bb656add
BL		 2294 /* for JD function */
2295 if (rt5645->pdata.en_jd_func) {
2296 snd_soc_dapm_force_enable_pin(&codec->dapm, "JD Power");
2297 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2298 snd_soc_dapm_sync(&codec->dapm);
2299 }
2300
1319b2f6
OC		 2301 return 0;
2302}
2303
2304static int rt5645_remove(struct snd_soc_codec *codec)
2305{
2306 rt5645_reset(codec);
2307 return 0;
2308}
2309
2310#ifdef CONFIG_PM
2311static int rt5645_suspend(struct snd_soc_codec *codec)
2312{
2313 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2314
2315 regcache_cache_only(rt5645->regmap, true);
2316 regcache_mark_dirty(rt5645->regmap);
2317
2318 return 0;
2319}
2320
2321static int rt5645_resume(struct snd_soc_codec *codec)
2322{
2323 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2324
2325 regcache_cache_only(rt5645->regmap, false);
0f776efd 2326 regcache_sync(rt5645->regmap);
1319b2f6
OC		 2327
2328 return 0;
2329}
2330#else
2331#define rt5645_suspend NULL
2332#define rt5645_resume NULL
2333#endif
2334
2335#define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
2336#define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2337 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2338
9e22f782 2339static struct snd_soc_dai_ops rt5645_aif_dai_ops = {
1319b2f6
OC		 2340 .hw_params = rt5645_hw_params,
2341 .set_fmt = rt5645_set_dai_fmt,
2342 .set_sysclk = rt5645_set_dai_sysclk,
2343 .set_tdm_slot = rt5645_set_tdm_slot,
2344 .set_pll = rt5645_set_dai_pll,
2345};
2346
9e22f782 2347static struct snd_soc_dai_driver rt5645_dai[] = {
1319b2f6
OC		 2348 {
2349 .name = "rt5645-aif1",
2350 .id = RT5645_AIF1,
2351 .playback = {
2352 .stream_name = "AIF1 Playback",
2353 .channels_min = 1,
2354 .channels_max = 2,
2355 .rates = RT5645_STEREO_RATES,
2356 .formats = RT5645_FORMATS,
2357 },
2358 .capture = {
2359 .stream_name = "AIF1 Capture",
2360 .channels_min = 1,
2361 .channels_max = 2,
2362 .rates = RT5645_STEREO_RATES,
2363 .formats = RT5645_FORMATS,
2364 },
2365 .ops = &rt5645_aif_dai_ops,
2366 },
2367 {
2368 .name = "rt5645-aif2",
2369 .id = RT5645_AIF2,
2370 .playback = {
2371 .stream_name = "AIF2 Playback",
2372 .channels_min = 1,
2373 .channels_max = 2,
2374 .rates = RT5645_STEREO_RATES,
2375 .formats = RT5645_FORMATS,
2376 },
2377 .capture = {
2378 .stream_name = "AIF2 Capture",
2379 .channels_min = 1,
2380 .channels_max = 2,
2381 .rates = RT5645_STEREO_RATES,
2382 .formats = RT5645_FORMATS,
2383 },
2384 .ops = &rt5645_aif_dai_ops,
2385 },
2386};
2387
2388static struct snd_soc_codec_driver soc_codec_dev_rt5645 = {
2389 .probe = rt5645_probe,
2390 .remove = rt5645_remove,
2391 .suspend = rt5645_suspend,
2392 .resume = rt5645_resume,
2393 .set_bias_level = rt5645_set_bias_level,
2394 .idle_bias_off = true,
2395 .controls = rt5645_snd_controls,
2396 .num_controls = ARRAY_SIZE(rt5645_snd_controls),
2397 .dapm_widgets = rt5645_dapm_widgets,
2398 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets),
2399 .dapm_routes = rt5645_dapm_routes,
2400 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes),
2401};
2402
2403static const struct regmap_config rt5645_regmap = {
2404 .reg_bits = 8,
2405 .val_bits = 16,
2406
2407 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
2408 RT5645_PR_SPACING),
2409 .volatile_reg = rt5645_volatile_register,
2410 .readable_reg = rt5645_readable_register,
2411
2412 .cache_type = REGCACHE_RBTREE,
2413 .reg_defaults = rt5645_reg,
2414 .num_reg_defaults = ARRAY_SIZE(rt5645_reg),
2415 .ranges = rt5645_ranges,
2416 .num_ranges = ARRAY_SIZE(rt5645_ranges),
2417};
2418
2419static const struct i2c_device_id rt5645_i2c_id[] = {
2420 { "rt5645", 0 },
2421 { }
2422};
2423MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
2424
2425static int rt5645_i2c_probe(struct i2c_client *i2c,
2426 const struct i2c_device_id *id)
2427{
2428 struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev);
2429 struct rt5645_priv *rt5645;
2430 int ret;
2431 unsigned int val;
2432
2433 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
2434 GFP_KERNEL);
2435 if (rt5645 == NULL)
2436 return -ENOMEM;
2437
f3fa1bbd 2438 rt5645->i2c = i2c;
1319b2f6
OC		 2439 i2c_set_clientdata(i2c, rt5645);
2440
2441 if (pdata)
2442 rt5645->pdata = *pdata;
2443
2444 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
2445 if (IS_ERR(rt5645->regmap)) {
2446 ret = PTR_ERR(rt5645->regmap);
2447 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2448 ret);
2449 return ret;
2450 }
2451
2452 regmap_read(rt5645->regmap, RT5645_VENDOR_ID2, &val);
2453 if (val != RT5645_DEVICE_ID) {
2454 dev_err(&i2c->dev,
2455 "Device with ID register %x is not rt5645\n", val);
2456 return -ENODEV;
2457 }
2458
2459 regmap_write(rt5645->regmap, RT5645_RESET, 0);
2460
2461 ret = regmap_register_patch(rt5645->regmap, init_list,
2462 ARRAY_SIZE(init_list));
2463 if (ret != 0)
2464 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
2465
2466 if (rt5645->pdata.in2_diff)
2467 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
2468 RT5645_IN_DF2, RT5645_IN_DF2);
2469
2470 if (rt5645->pdata.dmic_en) {
2471 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2472 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
2473
2474 switch (rt5645->pdata.dmic1_data_pin) {
2475 case RT5645_DMIC_DATA_IN2N:
2476 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2477 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
2478 break;
2479
2480 case RT5645_DMIC_DATA_GPIO5:
2481 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2482 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
2483 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2484 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
2485 break;
2486
2487 case RT5645_DMIC_DATA_GPIO11:
2488 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2489 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
2490 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2491 RT5645_GP11_PIN_MASK,
2492 RT5645_GP11_PIN_DMIC1_SDA);
2493 break;
2494
2495 default:
2496 break;
2497 }
2498
2499 switch (rt5645->pdata.dmic2_data_pin) {
2500 case RT5645_DMIC_DATA_IN2P:
2501 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2502 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
2503 break;
2504
2505 case RT5645_DMIC_DATA_GPIO6:
2506 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2507 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
2508 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2509 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
2510 break;
2511
2512 case RT5645_DMIC_DATA_GPIO10:
2513 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2514 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
2515 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2516 RT5645_GP10_PIN_MASK,
2517 RT5645_GP10_PIN_DMIC2_SDA);
2518 break;
2519
2520 case RT5645_DMIC_DATA_GPIO12:
2521 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2522 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
2523 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2524 RT5645_GP12_PIN_MASK,
2525 RT5645_GP12_PIN_DMIC2_SDA);
2526 break;
2527
2528 default:
2529 break;
2530 }
2531
2532 }
2533
bb656add
BL		 2534 if (rt5645->pdata.en_jd_func) {
2535 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
2536 RT5645_IRQ_CLK_GATE_CTRL | RT5645_MICINDET_MANU,
2537 RT5645_IRQ_CLK_GATE_CTRL | RT5645_MICINDET_MANU);
2538 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
2539 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);
2540 regmap_update_bits(rt5645->regmap, RT5645_JD_CTRL3,
2541 RT5645_JD_CBJ_EN | RT5645_JD_CBJ_POL,
2542 RT5645_JD_CBJ_EN | RT5645_JD_CBJ_POL);
2543 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
2544 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
2545 }
2546
f3fa1bbd
OC		 2547 if (rt5645->i2c->irq) {
2548 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,
2549 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2550 | IRQF_ONESHOT, "rt5645", rt5645);
2551 if (ret)
2552 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
2553 }
2554
2555 if (gpio_is_valid(rt5645->pdata.hp_det_gpio)) {
2556 ret = gpio_request(rt5645->pdata.hp_det_gpio, "rt5645");
2557 if (ret)
2558 dev_err(&i2c->dev, "Fail gpio_request hp_det_gpio\n");
2559
2560 ret = gpio_direction_input(rt5645->pdata.hp_det_gpio);
2561 if (ret)
2562 dev_err(&i2c->dev, "Fail gpio_direction hp_det_gpio\n");
2563 }
2564
cd6e82b8
OC		 2565 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work);
2566
dd56ebad
AL		 2567 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5645,
2568 rt5645_dai, ARRAY_SIZE(rt5645_dai));
1319b2f6
OC		 2569}
2570
2571static int rt5645_i2c_remove(struct i2c_client *i2c)
2572{
f3fa1bbd
OC		 2573 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
2574
2575 if (i2c->irq)
2576 free_irq(i2c->irq, rt5645);
2577
cd6e82b8
OC		 2578 cancel_delayed_work_sync(&rt5645->jack_detect_work);
2579
f3fa1bbd
OC		 2580 if (gpio_is_valid(rt5645->pdata.hp_det_gpio))
2581 gpio_free(rt5645->pdata.hp_det_gpio);
2582
1319b2f6
OC		 2583 snd_soc_unregister_codec(&i2c->dev);
2584
2585 return 0;
2586}
2587
9e22f782 2588static struct i2c_driver rt5645_i2c_driver = {
1319b2f6
OC		 2589 .driver = {
2590 .name = "rt5645",
2591 .owner = THIS_MODULE,
2592 },
2593 .probe = rt5645_i2c_probe,
2594 .remove = rt5645_i2c_remove,
2595 .id_table = rt5645_i2c_id,
2596};
2597module_i2c_driver(rt5645_i2c_driver);
2598
2599MODULE_DESCRIPTION("ASoC RT5645 driver");
2600MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
2601MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)