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1319b2f6 OC |
1 | /* |
2 | * rt5645.c -- RT5645 ALSA SoC audio codec driver | |
3 | * | |
4 | * Copyright 2013 Realtek Semiconductor Corp. | |
5 | * Author: Bard Liao <bardliao@realtek.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/moduleparam.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/pm.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/spi/spi.h> | |
f3fa1bbd | 20 | #include <linux/gpio.h> |
baf2a0e1 | 21 | #include <linux/gpio/consumer.h> |
3168c201 | 22 | #include <linux/acpi.h> |
78c34fd4 | 23 | #include <linux/dmi.h> |
1319b2f6 OC |
24 | #include <sound/core.h> |
25 | #include <sound/pcm.h> | |
26 | #include <sound/pcm_params.h> | |
27 | #include <sound/jack.h> | |
28 | #include <sound/soc.h> | |
29 | #include <sound/soc-dapm.h> | |
30 | #include <sound/initval.h> | |
31 | #include <sound/tlv.h> | |
32 | ||
49ef7925 | 33 | #include "rl6231.h" |
1319b2f6 OC |
34 | #include "rt5645.h" |
35 | ||
36 | #define RT5645_DEVICE_ID 0x6308 | |
5c4ca99d | 37 | #define RT5650_DEVICE_ID 0x6419 |
1319b2f6 OC |
38 | |
39 | #define RT5645_PR_RANGE_BASE (0xff + 1) | |
40 | #define RT5645_PR_SPACING 0x100 | |
41 | ||
42 | #define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING)) | |
43 | ||
44 | static const struct regmap_range_cfg rt5645_ranges[] = { | |
45 | { | |
46 | .name = "PR", | |
47 | .range_min = RT5645_PR_BASE, | |
48 | .range_max = RT5645_PR_BASE + 0xf8, | |
49 | .selector_reg = RT5645_PRIV_INDEX, | |
50 | .selector_mask = 0xff, | |
51 | .selector_shift = 0x0, | |
52 | .window_start = RT5645_PRIV_DATA, | |
53 | .window_len = 0x1, | |
54 | }, | |
55 | }; | |
56 | ||
57 | static const struct reg_default init_list[] = { | |
58 | {RT5645_PR_BASE + 0x3d, 0x3600}, | |
4809b96e OC |
59 | {RT5645_PR_BASE + 0x1c, 0xfd20}, |
60 | {RT5645_PR_BASE + 0x20, 0x611f}, | |
61 | {RT5645_PR_BASE + 0x21, 0x4040}, | |
62 | {RT5645_PR_BASE + 0x23, 0x0004}, | |
1319b2f6 OC |
63 | }; |
64 | #define RT5645_INIT_REG_LEN ARRAY_SIZE(init_list) | |
65 | ||
5c4ca99d BL |
66 | static const struct reg_default rt5650_init_list[] = { |
67 | {0xf6, 0x0100}, | |
68 | }; | |
69 | ||
1319b2f6 OC |
70 | static const struct reg_default rt5645_reg[] = { |
71 | { 0x00, 0x0000 }, | |
72 | { 0x01, 0xc8c8 }, | |
73 | { 0x02, 0xc8c8 }, | |
74 | { 0x03, 0xc8c8 }, | |
75 | { 0x0a, 0x0002 }, | |
76 | { 0x0b, 0x2827 }, | |
77 | { 0x0c, 0xe000 }, | |
78 | { 0x0d, 0x0000 }, | |
79 | { 0x0e, 0x0000 }, | |
80 | { 0x0f, 0x0808 }, | |
81 | { 0x14, 0x3333 }, | |
82 | { 0x16, 0x4b00 }, | |
83 | { 0x18, 0x018b }, | |
84 | { 0x19, 0xafaf }, | |
85 | { 0x1a, 0xafaf }, | |
86 | { 0x1b, 0x0001 }, | |
87 | { 0x1c, 0x2f2f }, | |
88 | { 0x1d, 0x2f2f }, | |
89 | { 0x1e, 0x0000 }, | |
90 | { 0x20, 0x0000 }, | |
91 | { 0x27, 0x7060 }, | |
92 | { 0x28, 0x7070 }, | |
93 | { 0x29, 0x8080 }, | |
94 | { 0x2a, 0x5656 }, | |
95 | { 0x2b, 0x5454 }, | |
96 | { 0x2c, 0xaaa0 }, | |
5c4ca99d | 97 | { 0x2d, 0x0000 }, |
1319b2f6 OC |
98 | { 0x2f, 0x1002 }, |
99 | { 0x31, 0x5000 }, | |
100 | { 0x32, 0x0000 }, | |
101 | { 0x33, 0x0000 }, | |
102 | { 0x34, 0x0000 }, | |
103 | { 0x35, 0x0000 }, | |
104 | { 0x3b, 0x0000 }, | |
105 | { 0x3c, 0x007f }, | |
106 | { 0x3d, 0x0000 }, | |
107 | { 0x3e, 0x007f }, | |
108 | { 0x3f, 0x0000 }, | |
109 | { 0x40, 0x001f }, | |
110 | { 0x41, 0x0000 }, | |
111 | { 0x42, 0x001f }, | |
112 | { 0x45, 0x6000 }, | |
113 | { 0x46, 0x003e }, | |
114 | { 0x47, 0x003e }, | |
115 | { 0x48, 0xf807 }, | |
116 | { 0x4a, 0x0004 }, | |
117 | { 0x4d, 0x0000 }, | |
118 | { 0x4e, 0x0000 }, | |
119 | { 0x4f, 0x01ff }, | |
120 | { 0x50, 0x0000 }, | |
121 | { 0x51, 0x0000 }, | |
122 | { 0x52, 0x01ff }, | |
123 | { 0x53, 0xf000 }, | |
124 | { 0x56, 0x0111 }, | |
125 | { 0x57, 0x0064 }, | |
126 | { 0x58, 0xef0e }, | |
127 | { 0x59, 0xf0f0 }, | |
128 | { 0x5a, 0xef0e }, | |
129 | { 0x5b, 0xf0f0 }, | |
130 | { 0x5c, 0xef0e }, | |
131 | { 0x5d, 0xf0f0 }, | |
132 | { 0x5e, 0xf000 }, | |
133 | { 0x5f, 0x0000 }, | |
134 | { 0x61, 0x0300 }, | |
135 | { 0x62, 0x0000 }, | |
136 | { 0x63, 0x00c2 }, | |
137 | { 0x64, 0x0000 }, | |
138 | { 0x65, 0x0000 }, | |
139 | { 0x66, 0x0000 }, | |
140 | { 0x6a, 0x0000 }, | |
141 | { 0x6c, 0x0aaa }, | |
142 | { 0x70, 0x8000 }, | |
143 | { 0x71, 0x8000 }, | |
144 | { 0x72, 0x8000 }, | |
145 | { 0x73, 0x7770 }, | |
146 | { 0x74, 0x3e00 }, | |
147 | { 0x75, 0x2409 }, | |
148 | { 0x76, 0x000a }, | |
149 | { 0x77, 0x0c00 }, | |
150 | { 0x78, 0x0000 }, | |
df078d29 | 151 | { 0x79, 0x0123 }, |
1319b2f6 OC |
152 | { 0x80, 0x0000 }, |
153 | { 0x81, 0x0000 }, | |
154 | { 0x82, 0x0000 }, | |
155 | { 0x83, 0x0000 }, | |
156 | { 0x84, 0x0000 }, | |
157 | { 0x85, 0x0000 }, | |
158 | { 0x8a, 0x0000 }, | |
159 | { 0x8e, 0x0004 }, | |
160 | { 0x8f, 0x1100 }, | |
161 | { 0x90, 0x0646 }, | |
162 | { 0x91, 0x0c06 }, | |
163 | { 0x93, 0x0000 }, | |
164 | { 0x94, 0x0200 }, | |
165 | { 0x95, 0x0000 }, | |
166 | { 0x9a, 0x2184 }, | |
167 | { 0x9b, 0x010a }, | |
168 | { 0x9c, 0x0aea }, | |
169 | { 0x9d, 0x000c }, | |
170 | { 0x9e, 0x0400 }, | |
171 | { 0xa0, 0xa0a8 }, | |
172 | { 0xa1, 0x0059 }, | |
173 | { 0xa2, 0x0001 }, | |
174 | { 0xae, 0x6000 }, | |
175 | { 0xaf, 0x0000 }, | |
176 | { 0xb0, 0x6000 }, | |
177 | { 0xb1, 0x0000 }, | |
178 | { 0xb2, 0x0000 }, | |
179 | { 0xb3, 0x001f }, | |
180 | { 0xb4, 0x020c }, | |
181 | { 0xb5, 0x1f00 }, | |
182 | { 0xb6, 0x0000 }, | |
183 | { 0xbb, 0x0000 }, | |
184 | { 0xbc, 0x0000 }, | |
185 | { 0xbd, 0x0000 }, | |
186 | { 0xbe, 0x0000 }, | |
187 | { 0xbf, 0x3100 }, | |
188 | { 0xc0, 0x0000 }, | |
189 | { 0xc1, 0x0000 }, | |
190 | { 0xc2, 0x0000 }, | |
191 | { 0xc3, 0x2000 }, | |
192 | { 0xcd, 0x0000 }, | |
193 | { 0xce, 0x0000 }, | |
194 | { 0xcf, 0x1813 }, | |
195 | { 0xd0, 0x0690 }, | |
196 | { 0xd1, 0x1c17 }, | |
197 | { 0xd3, 0xb320 }, | |
198 | { 0xd4, 0x0000 }, | |
199 | { 0xd6, 0x0400 }, | |
200 | { 0xd9, 0x0809 }, | |
201 | { 0xda, 0x0000 }, | |
202 | { 0xdb, 0x0003 }, | |
203 | { 0xdc, 0x0049 }, | |
204 | { 0xdd, 0x001b }, | |
5c4ca99d BL |
205 | { 0xdf, 0x0008 }, |
206 | { 0xe0, 0x4000 }, | |
1319b2f6 OC |
207 | { 0xe6, 0x8000 }, |
208 | { 0xe7, 0x0200 }, | |
209 | { 0xec, 0xb300 }, | |
210 | { 0xed, 0x0000 }, | |
211 | { 0xf0, 0x001f }, | |
212 | { 0xf1, 0x020c }, | |
213 | { 0xf2, 0x1f00 }, | |
214 | { 0xf3, 0x0000 }, | |
215 | { 0xf4, 0x4000 }, | |
216 | { 0xf8, 0x0000 }, | |
217 | { 0xf9, 0x0000 }, | |
218 | { 0xfa, 0x2060 }, | |
219 | { 0xfb, 0x4040 }, | |
220 | { 0xfc, 0x0000 }, | |
221 | { 0xfd, 0x0002 }, | |
222 | { 0xfe, 0x10ec }, | |
223 | { 0xff, 0x6308 }, | |
224 | }; | |
225 | ||
226 | static int rt5645_reset(struct snd_soc_codec *codec) | |
227 | { | |
228 | return snd_soc_write(codec, RT5645_RESET, 0); | |
229 | } | |
230 | ||
231 | static bool rt5645_volatile_register(struct device *dev, unsigned int reg) | |
232 | { | |
233 | int i; | |
234 | ||
235 | for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) { | |
236 | if (reg >= rt5645_ranges[i].range_min && | |
237 | reg <= rt5645_ranges[i].range_max) { | |
238 | return true; | |
239 | } | |
240 | } | |
241 | ||
242 | switch (reg) { | |
243 | case RT5645_RESET: | |
244 | case RT5645_PRIV_DATA: | |
245 | case RT5645_IN1_CTRL1: | |
246 | case RT5645_IN1_CTRL2: | |
247 | case RT5645_IN1_CTRL3: | |
248 | case RT5645_A_JD_CTRL1: | |
249 | case RT5645_ADC_EQ_CTRL1: | |
250 | case RT5645_EQ_CTRL1: | |
251 | case RT5645_ALC_CTRL_1: | |
252 | case RT5645_IRQ_CTRL2: | |
253 | case RT5645_IRQ_CTRL3: | |
254 | case RT5645_INT_IRQ_ST: | |
255 | case RT5645_IL_CMD: | |
5c4ca99d | 256 | case RT5650_4BTN_IL_CMD1: |
1319b2f6 OC |
257 | case RT5645_VENDOR_ID: |
258 | case RT5645_VENDOR_ID1: | |
259 | case RT5645_VENDOR_ID2: | |
71bfa9b4 | 260 | return true; |
1319b2f6 | 261 | default: |
71bfa9b4 | 262 | return false; |
1319b2f6 OC |
263 | } |
264 | } | |
265 | ||
266 | static bool rt5645_readable_register(struct device *dev, unsigned int reg) | |
267 | { | |
268 | int i; | |
269 | ||
270 | for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) { | |
271 | if (reg >= rt5645_ranges[i].range_min && | |
272 | reg <= rt5645_ranges[i].range_max) { | |
273 | return true; | |
274 | } | |
275 | } | |
276 | ||
277 | switch (reg) { | |
278 | case RT5645_RESET: | |
279 | case RT5645_SPK_VOL: | |
280 | case RT5645_HP_VOL: | |
281 | case RT5645_LOUT1: | |
282 | case RT5645_IN1_CTRL1: | |
283 | case RT5645_IN1_CTRL2: | |
284 | case RT5645_IN1_CTRL3: | |
285 | case RT5645_IN2_CTRL: | |
286 | case RT5645_INL1_INR1_VOL: | |
287 | case RT5645_SPK_FUNC_LIM: | |
288 | case RT5645_ADJ_HPF_CTRL: | |
289 | case RT5645_DAC1_DIG_VOL: | |
290 | case RT5645_DAC2_DIG_VOL: | |
291 | case RT5645_DAC_CTRL: | |
292 | case RT5645_STO1_ADC_DIG_VOL: | |
293 | case RT5645_MONO_ADC_DIG_VOL: | |
294 | case RT5645_ADC_BST_VOL1: | |
295 | case RT5645_ADC_BST_VOL2: | |
296 | case RT5645_STO1_ADC_MIXER: | |
297 | case RT5645_MONO_ADC_MIXER: | |
298 | case RT5645_AD_DA_MIXER: | |
299 | case RT5645_STO_DAC_MIXER: | |
300 | case RT5645_MONO_DAC_MIXER: | |
301 | case RT5645_DIG_MIXER: | |
5c4ca99d | 302 | case RT5650_A_DAC_SOUR: |
1319b2f6 OC |
303 | case RT5645_DIG_INF1_DATA: |
304 | case RT5645_PDM_OUT_CTRL: | |
305 | case RT5645_REC_L1_MIXER: | |
306 | case RT5645_REC_L2_MIXER: | |
307 | case RT5645_REC_R1_MIXER: | |
308 | case RT5645_REC_R2_MIXER: | |
309 | case RT5645_HPMIXL_CTRL: | |
310 | case RT5645_HPOMIXL_CTRL: | |
311 | case RT5645_HPMIXR_CTRL: | |
312 | case RT5645_HPOMIXR_CTRL: | |
313 | case RT5645_HPO_MIXER: | |
314 | case RT5645_SPK_L_MIXER: | |
315 | case RT5645_SPK_R_MIXER: | |
316 | case RT5645_SPO_MIXER: | |
317 | case RT5645_SPO_CLSD_RATIO: | |
318 | case RT5645_OUT_L1_MIXER: | |
319 | case RT5645_OUT_R1_MIXER: | |
320 | case RT5645_OUT_L_GAIN1: | |
321 | case RT5645_OUT_L_GAIN2: | |
322 | case RT5645_OUT_R_GAIN1: | |
323 | case RT5645_OUT_R_GAIN2: | |
324 | case RT5645_LOUT_MIXER: | |
325 | case RT5645_HAPTIC_CTRL1: | |
326 | case RT5645_HAPTIC_CTRL2: | |
327 | case RT5645_HAPTIC_CTRL3: | |
328 | case RT5645_HAPTIC_CTRL4: | |
329 | case RT5645_HAPTIC_CTRL5: | |
330 | case RT5645_HAPTIC_CTRL6: | |
331 | case RT5645_HAPTIC_CTRL7: | |
332 | case RT5645_HAPTIC_CTRL8: | |
333 | case RT5645_HAPTIC_CTRL9: | |
334 | case RT5645_HAPTIC_CTRL10: | |
335 | case RT5645_PWR_DIG1: | |
336 | case RT5645_PWR_DIG2: | |
337 | case RT5645_PWR_ANLG1: | |
338 | case RT5645_PWR_ANLG2: | |
339 | case RT5645_PWR_MIXER: | |
340 | case RT5645_PWR_VOL: | |
341 | case RT5645_PRIV_INDEX: | |
342 | case RT5645_PRIV_DATA: | |
343 | case RT5645_I2S1_SDP: | |
344 | case RT5645_I2S2_SDP: | |
345 | case RT5645_ADDA_CLK1: | |
346 | case RT5645_ADDA_CLK2: | |
347 | case RT5645_DMIC_CTRL1: | |
348 | case RT5645_DMIC_CTRL2: | |
349 | case RT5645_TDM_CTRL_1: | |
350 | case RT5645_TDM_CTRL_2: | |
df078d29 | 351 | case RT5645_TDM_CTRL_3: |
1fcb76db | 352 | case RT5650_TDM_CTRL_4: |
1319b2f6 OC |
353 | case RT5645_GLB_CLK: |
354 | case RT5645_PLL_CTRL1: | |
355 | case RT5645_PLL_CTRL2: | |
356 | case RT5645_ASRC_1: | |
357 | case RT5645_ASRC_2: | |
358 | case RT5645_ASRC_3: | |
359 | case RT5645_ASRC_4: | |
360 | case RT5645_DEPOP_M1: | |
361 | case RT5645_DEPOP_M2: | |
362 | case RT5645_DEPOP_M3: | |
363 | case RT5645_MICBIAS: | |
364 | case RT5645_A_JD_CTRL1: | |
365 | case RT5645_VAD_CTRL4: | |
366 | case RT5645_CLSD_OUT_CTRL: | |
367 | case RT5645_ADC_EQ_CTRL1: | |
368 | case RT5645_ADC_EQ_CTRL2: | |
369 | case RT5645_EQ_CTRL1: | |
370 | case RT5645_EQ_CTRL2: | |
371 | case RT5645_ALC_CTRL_1: | |
372 | case RT5645_ALC_CTRL_2: | |
373 | case RT5645_ALC_CTRL_3: | |
374 | case RT5645_ALC_CTRL_4: | |
375 | case RT5645_ALC_CTRL_5: | |
376 | case RT5645_JD_CTRL: | |
377 | case RT5645_IRQ_CTRL1: | |
378 | case RT5645_IRQ_CTRL2: | |
379 | case RT5645_IRQ_CTRL3: | |
380 | case RT5645_INT_IRQ_ST: | |
381 | case RT5645_GPIO_CTRL1: | |
382 | case RT5645_GPIO_CTRL2: | |
383 | case RT5645_GPIO_CTRL3: | |
384 | case RT5645_BASS_BACK: | |
385 | case RT5645_MP3_PLUS1: | |
386 | case RT5645_MP3_PLUS2: | |
387 | case RT5645_ADJ_HPF1: | |
388 | case RT5645_ADJ_HPF2: | |
389 | case RT5645_HP_CALIB_AMP_DET: | |
390 | case RT5645_SV_ZCD1: | |
391 | case RT5645_SV_ZCD2: | |
392 | case RT5645_IL_CMD: | |
393 | case RT5645_IL_CMD2: | |
394 | case RT5645_IL_CMD3: | |
5c4ca99d BL |
395 | case RT5650_4BTN_IL_CMD1: |
396 | case RT5650_4BTN_IL_CMD2: | |
1319b2f6 OC |
397 | case RT5645_DRC1_HL_CTRL1: |
398 | case RT5645_DRC2_HL_CTRL1: | |
399 | case RT5645_ADC_MONO_HP_CTRL1: | |
400 | case RT5645_ADC_MONO_HP_CTRL2: | |
401 | case RT5645_DRC2_CTRL1: | |
402 | case RT5645_DRC2_CTRL2: | |
403 | case RT5645_DRC2_CTRL3: | |
404 | case RT5645_DRC2_CTRL4: | |
405 | case RT5645_DRC2_CTRL5: | |
406 | case RT5645_JD_CTRL3: | |
407 | case RT5645_JD_CTRL4: | |
408 | case RT5645_GEN_CTRL1: | |
409 | case RT5645_GEN_CTRL2: | |
410 | case RT5645_GEN_CTRL3: | |
411 | case RT5645_VENDOR_ID: | |
412 | case RT5645_VENDOR_ID1: | |
413 | case RT5645_VENDOR_ID2: | |
71bfa9b4 | 414 | return true; |
1319b2f6 | 415 | default: |
71bfa9b4 | 416 | return false; |
1319b2f6 OC |
417 | } |
418 | } | |
419 | ||
420 | static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0); | |
177e1e1f | 421 | static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); |
1319b2f6 | 422 | static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0); |
177e1e1f | 423 | static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); |
1319b2f6 OC |
424 | static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); |
425 | ||
426 | /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ | |
6d698a83 | 427 | static const DECLARE_TLV_DB_RANGE(bst_tlv, |
1319b2f6 OC |
428 | 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), |
429 | 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), | |
430 | 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), | |
431 | 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), | |
432 | 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), | |
433 | 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), | |
6d698a83 LPC |
434 | 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) |
435 | ); | |
1319b2f6 | 436 | |
1319b2f6 OC |
437 | static const struct snd_kcontrol_new rt5645_snd_controls[] = { |
438 | /* Speaker Output Volume */ | |
439 | SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL, | |
440 | RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), | |
441 | SOC_DOUBLE_TLV("Speaker Playback Volume", RT5645_SPK_VOL, | |
442 | RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv), | |
443 | ||
444 | /* Headphone Output Volume */ | |
692768c4 | 445 | SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL, |
1319b2f6 | 446 | RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), |
692768c4 | 447 | SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL, |
1319b2f6 OC |
448 | RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv), |
449 | ||
450 | /* OUTPUT Control */ | |
451 | SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1, | |
452 | RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), | |
453 | SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1, | |
454 | RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), | |
455 | SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1, | |
456 | RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv), | |
457 | ||
458 | /* DAC Digital Volume */ | |
459 | SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL, | |
460 | RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1), | |
461 | SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL, | |
177e1e1f | 462 | RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), |
1319b2f6 | 463 | SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL, |
177e1e1f | 464 | RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), |
1319b2f6 OC |
465 | |
466 | /* IN1/IN2 Control */ | |
467 | SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1, | |
468 | RT5645_BST_SFT1, 8, 0, bst_tlv), | |
469 | SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL, | |
470 | RT5645_BST_SFT2, 8, 0, bst_tlv), | |
471 | ||
472 | /* INL/INR Volume Control */ | |
473 | SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL, | |
474 | RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv), | |
475 | ||
476 | /* ADC Digital Volume Control */ | |
477 | SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL, | |
478 | RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), | |
479 | SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL, | |
177e1e1f | 480 | RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), |
1319b2f6 OC |
481 | SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL, |
482 | RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), | |
483 | SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL, | |
177e1e1f | 484 | RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), |
1319b2f6 OC |
485 | |
486 | /* ADC Boost Volume Control */ | |
487 | SOC_DOUBLE_TLV("STO1 ADC Boost Gain", RT5645_ADC_BST_VOL1, | |
488 | RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0, | |
489 | adc_bst_tlv), | |
490 | SOC_DOUBLE_TLV("STO2 ADC Boost Gain", RT5645_ADC_BST_VOL1, | |
491 | RT5645_STO2_ADC_L_BST_SFT, RT5645_STO2_ADC_R_BST_SFT, 3, 0, | |
492 | adc_bst_tlv), | |
493 | ||
494 | /* I2S2 function select */ | |
495 | SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT, | |
496 | 1, 1), | |
1319b2f6 OC |
497 | }; |
498 | ||
499 | /** | |
500 | * set_dmic_clk - Set parameter of dmic. | |
501 | * | |
502 | * @w: DAPM widget. | |
503 | * @kcontrol: The kcontrol of this widget. | |
504 | * @event: Event id. | |
505 | * | |
1319b2f6 OC |
506 | */ |
507 | static int set_dmic_clk(struct snd_soc_dapm_widget *w, | |
508 | struct snd_kcontrol *kcontrol, int event) | |
509 | { | |
c5f596cb | 510 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
1319b2f6 | 511 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); |
49ef7925 OC |
512 | int idx = -EINVAL; |
513 | ||
514 | idx = rl6231_calc_dmic_clk(rt5645->sysclk); | |
1319b2f6 OC |
515 | |
516 | if (idx < 0) | |
517 | dev_err(codec->dev, "Failed to set DMIC clock\n"); | |
518 | else | |
519 | snd_soc_update_bits(codec, RT5645_DMIC_CTRL1, | |
520 | RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT); | |
521 | return idx; | |
522 | } | |
523 | ||
524 | static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, | |
525 | struct snd_soc_dapm_widget *sink) | |
526 | { | |
c5f596cb | 527 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); |
1319b2f6 OC |
528 | unsigned int val; |
529 | ||
c5f596cb | 530 | val = snd_soc_read(codec, RT5645_GLB_CLK); |
1319b2f6 OC |
531 | val &= RT5645_SCLK_SRC_MASK; |
532 | if (val == RT5645_SCLK_SRC_PLL1) | |
533 | return 1; | |
534 | else | |
535 | return 0; | |
536 | } | |
537 | ||
9e268353 BL |
538 | static int is_using_asrc(struct snd_soc_dapm_widget *source, |
539 | struct snd_soc_dapm_widget *sink) | |
540 | { | |
c5f596cb | 541 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); |
9e268353 BL |
542 | unsigned int reg, shift, val; |
543 | ||
544 | switch (source->shift) { | |
545 | case 0: | |
546 | reg = RT5645_ASRC_3; | |
547 | shift = 0; | |
548 | break; | |
549 | case 1: | |
550 | reg = RT5645_ASRC_3; | |
551 | shift = 4; | |
552 | break; | |
553 | case 3: | |
554 | reg = RT5645_ASRC_2; | |
555 | shift = 0; | |
556 | break; | |
557 | case 8: | |
558 | reg = RT5645_ASRC_2; | |
559 | shift = 4; | |
560 | break; | |
561 | case 9: | |
562 | reg = RT5645_ASRC_2; | |
563 | shift = 8; | |
564 | break; | |
565 | case 10: | |
566 | reg = RT5645_ASRC_2; | |
567 | shift = 12; | |
568 | break; | |
569 | default: | |
570 | return 0; | |
571 | } | |
572 | ||
c5f596cb | 573 | val = (snd_soc_read(codec, reg) >> shift) & 0xf; |
9e268353 BL |
574 | switch (val) { |
575 | case 1: | |
576 | case 2: | |
577 | case 3: | |
578 | case 4: | |
579 | return 1; | |
580 | default: | |
581 | return 0; | |
582 | } | |
583 | ||
584 | } | |
585 | ||
79080a8b FY |
586 | /** |
587 | * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters | |
588 | * @codec: SoC audio codec device. | |
589 | * @filter_mask: mask of filters. | |
590 | * @clk_src: clock source | |
591 | * | |
592 | * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can | |
593 | * only support standard 32fs or 64fs i2s format, ASRC should be enabled to | |
594 | * support special i2s clock format such as Intel's 100fs(100 * sampling rate). | |
595 | * ASRC function will track i2s clock and generate a corresponding system clock | |
596 | * for codec. This function provides an API to select the clock source for a | |
597 | * set of filters specified by the mask. And the codec driver will turn on ASRC | |
598 | * for these filters if ASRC is selected as their clock source. | |
599 | */ | |
600 | int rt5645_sel_asrc_clk_src(struct snd_soc_codec *codec, | |
601 | unsigned int filter_mask, unsigned int clk_src) | |
602 | { | |
603 | unsigned int asrc2_mask = 0; | |
604 | unsigned int asrc2_value = 0; | |
605 | unsigned int asrc3_mask = 0; | |
606 | unsigned int asrc3_value = 0; | |
607 | ||
608 | switch (clk_src) { | |
609 | case RT5645_CLK_SEL_SYS: | |
610 | case RT5645_CLK_SEL_I2S1_ASRC: | |
611 | case RT5645_CLK_SEL_I2S2_ASRC: | |
612 | case RT5645_CLK_SEL_SYS2: | |
613 | break; | |
614 | ||
615 | default: | |
616 | return -EINVAL; | |
617 | } | |
618 | ||
619 | if (filter_mask & RT5645_DA_STEREO_FILTER) { | |
620 | asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK; | |
621 | asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK) | |
622 | | (clk_src << RT5645_DA_STO_CLK_SEL_SFT); | |
623 | } | |
624 | ||
625 | if (filter_mask & RT5645_DA_MONO_L_FILTER) { | |
626 | asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK; | |
627 | asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK) | |
628 | | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT); | |
629 | } | |
630 | ||
631 | if (filter_mask & RT5645_DA_MONO_R_FILTER) { | |
632 | asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK; | |
633 | asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK) | |
634 | | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT); | |
635 | } | |
636 | ||
637 | if (filter_mask & RT5645_AD_STEREO_FILTER) { | |
638 | asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK; | |
639 | asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK) | |
640 | | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT); | |
641 | } | |
642 | ||
643 | if (filter_mask & RT5645_AD_MONO_L_FILTER) { | |
644 | asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK; | |
645 | asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK) | |
646 | | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT); | |
647 | } | |
648 | ||
649 | if (filter_mask & RT5645_AD_MONO_R_FILTER) { | |
650 | asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK; | |
651 | asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK) | |
652 | | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT); | |
653 | } | |
654 | ||
655 | if (asrc2_mask) | |
656 | snd_soc_update_bits(codec, RT5645_ASRC_2, | |
657 | asrc2_mask, asrc2_value); | |
658 | ||
659 | if (asrc3_mask) | |
660 | snd_soc_update_bits(codec, RT5645_ASRC_3, | |
661 | asrc3_mask, asrc3_value); | |
662 | ||
663 | return 0; | |
664 | } | |
665 | EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src); | |
666 | ||
1319b2f6 OC |
667 | /* Digital Mixer */ |
668 | static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = { | |
669 | SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER, | |
670 | RT5645_M_ADC_L1_SFT, 1, 1), | |
671 | SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER, | |
672 | RT5645_M_ADC_L2_SFT, 1, 1), | |
673 | }; | |
674 | ||
675 | static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = { | |
676 | SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER, | |
677 | RT5645_M_ADC_R1_SFT, 1, 1), | |
678 | SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER, | |
679 | RT5645_M_ADC_R2_SFT, 1, 1), | |
680 | }; | |
681 | ||
682 | static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = { | |
683 | SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER, | |
684 | RT5645_M_MONO_ADC_L1_SFT, 1, 1), | |
685 | SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER, | |
686 | RT5645_M_MONO_ADC_L2_SFT, 1, 1), | |
687 | }; | |
688 | ||
689 | static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = { | |
690 | SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER, | |
691 | RT5645_M_MONO_ADC_R1_SFT, 1, 1), | |
692 | SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER, | |
693 | RT5645_M_MONO_ADC_R2_SFT, 1, 1), | |
694 | }; | |
695 | ||
696 | static const struct snd_kcontrol_new rt5645_dac_l_mix[] = { | |
697 | SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER, | |
698 | RT5645_M_ADCMIX_L_SFT, 1, 1), | |
699 | SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER, | |
700 | RT5645_M_DAC1_L_SFT, 1, 1), | |
701 | }; | |
702 | ||
703 | static const struct snd_kcontrol_new rt5645_dac_r_mix[] = { | |
704 | SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER, | |
705 | RT5645_M_ADCMIX_R_SFT, 1, 1), | |
706 | SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER, | |
707 | RT5645_M_DAC1_R_SFT, 1, 1), | |
708 | }; | |
709 | ||
710 | static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = { | |
711 | SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER, | |
712 | RT5645_M_DAC_L1_SFT, 1, 1), | |
713 | SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER, | |
714 | RT5645_M_DAC_L2_SFT, 1, 1), | |
715 | SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER, | |
716 | RT5645_M_DAC_R1_STO_L_SFT, 1, 1), | |
717 | }; | |
718 | ||
719 | static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = { | |
720 | SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER, | |
721 | RT5645_M_DAC_R1_SFT, 1, 1), | |
722 | SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER, | |
723 | RT5645_M_DAC_R2_SFT, 1, 1), | |
724 | SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER, | |
725 | RT5645_M_DAC_L1_STO_R_SFT, 1, 1), | |
726 | }; | |
727 | ||
728 | static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = { | |
729 | SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER, | |
730 | RT5645_M_DAC_L1_MONO_L_SFT, 1, 1), | |
731 | SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER, | |
732 | RT5645_M_DAC_L2_MONO_L_SFT, 1, 1), | |
733 | SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER, | |
734 | RT5645_M_DAC_R2_MONO_L_SFT, 1, 1), | |
735 | }; | |
736 | ||
737 | static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = { | |
738 | SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER, | |
739 | RT5645_M_DAC_R1_MONO_R_SFT, 1, 1), | |
740 | SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER, | |
741 | RT5645_M_DAC_R2_MONO_R_SFT, 1, 1), | |
742 | SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER, | |
743 | RT5645_M_DAC_L2_MONO_R_SFT, 1, 1), | |
744 | }; | |
745 | ||
746 | static const struct snd_kcontrol_new rt5645_dig_l_mix[] = { | |
747 | SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER, | |
748 | RT5645_M_STO_L_DAC_L_SFT, 1, 1), | |
749 | SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER, | |
750 | RT5645_M_DAC_L2_DAC_L_SFT, 1, 1), | |
751 | SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER, | |
752 | RT5645_M_DAC_R2_DAC_L_SFT, 1, 1), | |
753 | }; | |
754 | ||
755 | static const struct snd_kcontrol_new rt5645_dig_r_mix[] = { | |
756 | SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER, | |
757 | RT5645_M_STO_R_DAC_R_SFT, 1, 1), | |
758 | SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER, | |
759 | RT5645_M_DAC_R2_DAC_R_SFT, 1, 1), | |
760 | SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER, | |
761 | RT5645_M_DAC_L2_DAC_R_SFT, 1, 1), | |
762 | }; | |
763 | ||
764 | /* Analog Input Mixer */ | |
765 | static const struct snd_kcontrol_new rt5645_rec_l_mix[] = { | |
766 | SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER, | |
767 | RT5645_M_HP_L_RM_L_SFT, 1, 1), | |
768 | SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER, | |
769 | RT5645_M_IN_L_RM_L_SFT, 1, 1), | |
770 | SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER, | |
771 | RT5645_M_BST2_RM_L_SFT, 1, 1), | |
772 | SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER, | |
773 | RT5645_M_BST1_RM_L_SFT, 1, 1), | |
774 | SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER, | |
775 | RT5645_M_OM_L_RM_L_SFT, 1, 1), | |
776 | }; | |
777 | ||
778 | static const struct snd_kcontrol_new rt5645_rec_r_mix[] = { | |
779 | SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER, | |
780 | RT5645_M_HP_R_RM_R_SFT, 1, 1), | |
781 | SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER, | |
782 | RT5645_M_IN_R_RM_R_SFT, 1, 1), | |
783 | SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER, | |
784 | RT5645_M_BST2_RM_R_SFT, 1, 1), | |
785 | SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER, | |
786 | RT5645_M_BST1_RM_R_SFT, 1, 1), | |
787 | SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER, | |
788 | RT5645_M_OM_R_RM_R_SFT, 1, 1), | |
789 | }; | |
790 | ||
791 | static const struct snd_kcontrol_new rt5645_spk_l_mix[] = { | |
792 | SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER, | |
793 | RT5645_M_DAC_L1_SM_L_SFT, 1, 1), | |
794 | SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER, | |
795 | RT5645_M_DAC_L2_SM_L_SFT, 1, 1), | |
796 | SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER, | |
797 | RT5645_M_IN_L_SM_L_SFT, 1, 1), | |
798 | SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER, | |
799 | RT5645_M_BST1_L_SM_L_SFT, 1, 1), | |
800 | }; | |
801 | ||
802 | static const struct snd_kcontrol_new rt5645_spk_r_mix[] = { | |
803 | SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER, | |
804 | RT5645_M_DAC_R1_SM_R_SFT, 1, 1), | |
805 | SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER, | |
806 | RT5645_M_DAC_R2_SM_R_SFT, 1, 1), | |
807 | SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER, | |
808 | RT5645_M_IN_R_SM_R_SFT, 1, 1), | |
809 | SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER, | |
810 | RT5645_M_BST2_R_SM_R_SFT, 1, 1), | |
811 | }; | |
812 | ||
813 | static const struct snd_kcontrol_new rt5645_out_l_mix[] = { | |
814 | SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER, | |
815 | RT5645_M_BST1_OM_L_SFT, 1, 1), | |
816 | SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER, | |
817 | RT5645_M_IN_L_OM_L_SFT, 1, 1), | |
818 | SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER, | |
819 | RT5645_M_DAC_L2_OM_L_SFT, 1, 1), | |
820 | SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER, | |
821 | RT5645_M_DAC_L1_OM_L_SFT, 1, 1), | |
822 | }; | |
823 | ||
824 | static const struct snd_kcontrol_new rt5645_out_r_mix[] = { | |
825 | SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER, | |
826 | RT5645_M_BST2_OM_R_SFT, 1, 1), | |
827 | SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER, | |
828 | RT5645_M_IN_R_OM_R_SFT, 1, 1), | |
829 | SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER, | |
830 | RT5645_M_DAC_R2_OM_R_SFT, 1, 1), | |
831 | SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER, | |
832 | RT5645_M_DAC_R1_OM_R_SFT, 1, 1), | |
833 | }; | |
834 | ||
835 | static const struct snd_kcontrol_new rt5645_spo_l_mix[] = { | |
836 | SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER, | |
837 | RT5645_M_DAC_R1_SPM_L_SFT, 1, 1), | |
838 | SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER, | |
839 | RT5645_M_DAC_L1_SPM_L_SFT, 1, 1), | |
840 | SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER, | |
841 | RT5645_M_SV_R_SPM_L_SFT, 1, 1), | |
842 | SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER, | |
843 | RT5645_M_SV_L_SPM_L_SFT, 1, 1), | |
844 | }; | |
845 | ||
846 | static const struct snd_kcontrol_new rt5645_spo_r_mix[] = { | |
847 | SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER, | |
848 | RT5645_M_DAC_R1_SPM_R_SFT, 1, 1), | |
849 | SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER, | |
850 | RT5645_M_SV_R_SPM_R_SFT, 1, 1), | |
851 | }; | |
852 | ||
853 | static const struct snd_kcontrol_new rt5645_hpo_mix[] = { | |
854 | SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER, | |
855 | RT5645_M_DAC1_HM_SFT, 1, 1), | |
856 | SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER, | |
857 | RT5645_M_HPVOL_HM_SFT, 1, 1), | |
858 | }; | |
859 | ||
860 | static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = { | |
861 | SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL, | |
862 | RT5645_M_DAC1_HV_SFT, 1, 1), | |
863 | SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL, | |
864 | RT5645_M_DAC2_HV_SFT, 1, 1), | |
865 | SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL, | |
866 | RT5645_M_IN_HV_SFT, 1, 1), | |
867 | SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL, | |
868 | RT5645_M_BST1_HV_SFT, 1, 1), | |
869 | }; | |
870 | ||
871 | static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = { | |
872 | SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL, | |
873 | RT5645_M_DAC1_HV_SFT, 1, 1), | |
874 | SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL, | |
875 | RT5645_M_DAC2_HV_SFT, 1, 1), | |
876 | SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL, | |
877 | RT5645_M_IN_HV_SFT, 1, 1), | |
878 | SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL, | |
879 | RT5645_M_BST2_HV_SFT, 1, 1), | |
880 | }; | |
881 | ||
882 | static const struct snd_kcontrol_new rt5645_lout_mix[] = { | |
883 | SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER, | |
884 | RT5645_M_DAC_L1_LM_SFT, 1, 1), | |
885 | SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER, | |
886 | RT5645_M_DAC_R1_LM_SFT, 1, 1), | |
887 | SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER, | |
888 | RT5645_M_OV_L_LM_SFT, 1, 1), | |
889 | SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER, | |
890 | RT5645_M_OV_R_LM_SFT, 1, 1), | |
891 | }; | |
892 | ||
893 | /*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */ | |
894 | static const char * const rt5645_dac1_src[] = { | |
895 | "IF1 DAC", "IF2 DAC", "IF3 DAC" | |
896 | }; | |
897 | ||
898 | static SOC_ENUM_SINGLE_DECL( | |
899 | rt5645_dac1l_enum, RT5645_AD_DA_MIXER, | |
900 | RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src); | |
901 | ||
902 | static const struct snd_kcontrol_new rt5645_dac1l_mux = | |
903 | SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum); | |
904 | ||
905 | static SOC_ENUM_SINGLE_DECL( | |
906 | rt5645_dac1r_enum, RT5645_AD_DA_MIXER, | |
907 | RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src); | |
908 | ||
909 | static const struct snd_kcontrol_new rt5645_dac1r_mux = | |
910 | SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum); | |
911 | ||
912 | /*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */ | |
913 | static const char * const rt5645_dac12_src[] = { | |
914 | "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC" | |
915 | }; | |
916 | ||
917 | static SOC_ENUM_SINGLE_DECL( | |
918 | rt5645_dac2l_enum, RT5645_DAC_CTRL, | |
919 | RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src); | |
920 | ||
921 | static const struct snd_kcontrol_new rt5645_dac_l2_mux = | |
922 | SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum); | |
923 | ||
924 | static const char * const rt5645_dacr2_src[] = { | |
925 | "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic" | |
926 | }; | |
927 | ||
928 | static SOC_ENUM_SINGLE_DECL( | |
929 | rt5645_dac2r_enum, RT5645_DAC_CTRL, | |
930 | RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src); | |
931 | ||
932 | static const struct snd_kcontrol_new rt5645_dac_r2_mux = | |
933 | SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum); | |
934 | ||
935 | ||
936 | /* INL/R source */ | |
937 | static const char * const rt5645_inl_src[] = { | |
938 | "IN2P", "MonoP" | |
939 | }; | |
940 | ||
941 | static SOC_ENUM_SINGLE_DECL( | |
942 | rt5645_inl_enum, RT5645_INL1_INR1_VOL, | |
943 | RT5645_INL_SEL_SFT, rt5645_inl_src); | |
944 | ||
945 | static const struct snd_kcontrol_new rt5645_inl_mux = | |
946 | SOC_DAPM_ENUM("INL source", rt5645_inl_enum); | |
947 | ||
948 | static const char * const rt5645_inr_src[] = { | |
949 | "IN2N", "MonoN" | |
950 | }; | |
951 | ||
952 | static SOC_ENUM_SINGLE_DECL( | |
953 | rt5645_inr_enum, RT5645_INL1_INR1_VOL, | |
954 | RT5645_INR_SEL_SFT, rt5645_inr_src); | |
955 | ||
956 | static const struct snd_kcontrol_new rt5645_inr_mux = | |
957 | SOC_DAPM_ENUM("INR source", rt5645_inr_enum); | |
958 | ||
959 | /* Stereo1 ADC source */ | |
960 | /* MX-27 [12] */ | |
961 | static const char * const rt5645_stereo_adc1_src[] = { | |
962 | "DAC MIX", "ADC" | |
963 | }; | |
964 | ||
965 | static SOC_ENUM_SINGLE_DECL( | |
966 | rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER, | |
967 | RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src); | |
968 | ||
969 | static const struct snd_kcontrol_new rt5645_sto_adc1_mux = | |
970 | SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum); | |
971 | ||
972 | /* MX-27 [11] */ | |
973 | static const char * const rt5645_stereo_adc2_src[] = { | |
974 | "DAC MIX", "DMIC" | |
975 | }; | |
976 | ||
977 | static SOC_ENUM_SINGLE_DECL( | |
978 | rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER, | |
979 | RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src); | |
980 | ||
981 | static const struct snd_kcontrol_new rt5645_sto_adc2_mux = | |
982 | SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum); | |
983 | ||
984 | /* MX-27 [8] */ | |
985 | static const char * const rt5645_stereo_dmic_src[] = { | |
986 | "DMIC1", "DMIC2" | |
987 | }; | |
988 | ||
989 | static SOC_ENUM_SINGLE_DECL( | |
990 | rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER, | |
991 | RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src); | |
992 | ||
993 | static const struct snd_kcontrol_new rt5645_sto1_dmic_mux = | |
994 | SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum); | |
995 | ||
996 | /* Mono ADC source */ | |
997 | /* MX-28 [12] */ | |
998 | static const char * const rt5645_mono_adc_l1_src[] = { | |
999 | "Mono DAC MIXL", "ADC" | |
1000 | }; | |
1001 | ||
1002 | static SOC_ENUM_SINGLE_DECL( | |
1003 | rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER, | |
1004 | RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src); | |
1005 | ||
1006 | static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux = | |
1007 | SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum); | |
1008 | /* MX-28 [11] */ | |
1009 | static const char * const rt5645_mono_adc_l2_src[] = { | |
1010 | "Mono DAC MIXL", "DMIC" | |
1011 | }; | |
1012 | ||
1013 | static SOC_ENUM_SINGLE_DECL( | |
1014 | rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER, | |
1015 | RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src); | |
1016 | ||
1017 | static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux = | |
1018 | SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum); | |
1019 | ||
1020 | /* MX-28 [8] */ | |
1021 | static const char * const rt5645_mono_dmic_src[] = { | |
1022 | "DMIC1", "DMIC2" | |
1023 | }; | |
1024 | ||
1025 | static SOC_ENUM_SINGLE_DECL( | |
1026 | rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER, | |
1027 | RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src); | |
1028 | ||
1029 | static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux = | |
1030 | SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum); | |
1031 | /* MX-28 [1:0] */ | |
1032 | static SOC_ENUM_SINGLE_DECL( | |
1033 | rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER, | |
1034 | RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src); | |
1035 | ||
1036 | static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux = | |
1037 | SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum); | |
1038 | /* MX-28 [4] */ | |
1039 | static const char * const rt5645_mono_adc_r1_src[] = { | |
1040 | "Mono DAC MIXR", "ADC" | |
1041 | }; | |
1042 | ||
1043 | static SOC_ENUM_SINGLE_DECL( | |
1044 | rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER, | |
1045 | RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src); | |
1046 | ||
1047 | static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux = | |
1048 | SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum); | |
1049 | /* MX-28 [3] */ | |
1050 | static const char * const rt5645_mono_adc_r2_src[] = { | |
1051 | "Mono DAC MIXR", "DMIC" | |
1052 | }; | |
1053 | ||
1054 | static SOC_ENUM_SINGLE_DECL( | |
1055 | rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER, | |
1056 | RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src); | |
1057 | ||
1058 | static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux = | |
1059 | SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum); | |
1060 | ||
1061 | /* MX-77 [9:8] */ | |
1062 | static const char * const rt5645_if1_adc_in_src[] = { | |
21ab3f2b BL |
1063 | "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC", |
1064 | "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1" | |
1319b2f6 OC |
1065 | }; |
1066 | ||
1067 | static SOC_ENUM_SINGLE_DECL( | |
1068 | rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1, | |
1069 | RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src); | |
1070 | ||
1071 | static const struct snd_kcontrol_new rt5645_if1_adc_in_mux = | |
1072 | SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum); | |
1073 | ||
21ab3f2b BL |
1074 | /* MX-78 [4:0] */ |
1075 | static const char * const rt5650_if1_adc_in_src[] = { | |
1076 | "IF_ADC1/IF_ADC2/DAC_REF/Null", | |
1077 | "IF_ADC1/IF_ADC2/Null/DAC_REF", | |
1078 | "IF_ADC1/DAC_REF/IF_ADC2/Null", | |
1079 | "IF_ADC1/DAC_REF/Null/IF_ADC2", | |
1080 | "IF_ADC1/Null/DAC_REF/IF_ADC2", | |
1081 | "IF_ADC1/Null/IF_ADC2/DAC_REF", | |
1082 | ||
1083 | "IF_ADC2/IF_ADC1/DAC_REF/Null", | |
1084 | "IF_ADC2/IF_ADC1/Null/DAC_REF", | |
1085 | "IF_ADC2/DAC_REF/IF_ADC1/Null", | |
1086 | "IF_ADC2/DAC_REF/Null/IF_ADC1", | |
1087 | "IF_ADC2/Null/DAC_REF/IF_ADC1", | |
1088 | "IF_ADC2/Null/IF_ADC1/DAC_REF", | |
1089 | ||
1090 | "DAC_REF/IF_ADC1/IF_ADC2/Null", | |
1091 | "DAC_REF/IF_ADC1/Null/IF_ADC2", | |
1092 | "DAC_REF/IF_ADC2/IF_ADC1/Null", | |
1093 | "DAC_REF/IF_ADC2/Null/IF_ADC1", | |
1094 | "DAC_REF/Null/IF_ADC1/IF_ADC2", | |
1095 | "DAC_REF/Null/IF_ADC2/IF_ADC1", | |
1096 | ||
1097 | "Null/IF_ADC1/IF_ADC2/DAC_REF", | |
1098 | "Null/IF_ADC1/DAC_REF/IF_ADC2", | |
1099 | "Null/IF_ADC2/IF_ADC1/DAC_REF", | |
1100 | "Null/IF_ADC2/DAC_REF/IF_ADC1", | |
1101 | "Null/DAC_REF/IF_ADC1/IF_ADC2", | |
1102 | "Null/DAC_REF/IF_ADC2/IF_ADC1", | |
1103 | }; | |
1104 | ||
1105 | static SOC_ENUM_SINGLE_DECL( | |
1106 | rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2, | |
1107 | 0, rt5650_if1_adc_in_src); | |
1108 | ||
1109 | static const struct snd_kcontrol_new rt5650_if1_adc_in_mux = | |
1110 | SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum); | |
1111 | ||
1112 | /* MX-78 [15:14][13:12][11:10] */ | |
1113 | static const char * const rt5645_tdm_adc_swap_select[] = { | |
1114 | "L/R", "R/L", "L/L", "R/R" | |
1115 | }; | |
1116 | ||
1117 | static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum, | |
1118 | RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select); | |
1119 | ||
1120 | static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux = | |
1121 | SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum); | |
1122 | ||
1123 | static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum, | |
1124 | RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select); | |
1125 | ||
1126 | static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux = | |
1127 | SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum); | |
1128 | ||
1129 | static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum, | |
1130 | RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select); | |
1131 | ||
1132 | static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux = | |
1133 | SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum); | |
1134 | ||
1135 | /* MX-77 [7:6][5:4][3:2] */ | |
1136 | static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum, | |
1137 | RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select); | |
1138 | ||
1139 | static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux = | |
1140 | SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum); | |
1141 | ||
1142 | static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum, | |
1143 | RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select); | |
1144 | ||
1145 | static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux = | |
1146 | SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum); | |
1147 | ||
1148 | static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum, | |
1149 | RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select); | |
1150 | ||
1151 | static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux = | |
1152 | SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum); | |
1153 | ||
1154 | /* MX-79 [14:12][10:8][6:4][2:0] */ | |
1155 | static const char * const rt5645_tdm_dac_swap_select[] = { | |
1156 | "Slot0", "Slot1", "Slot2", "Slot3" | |
1157 | }; | |
1158 | ||
1159 | static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum, | |
1160 | RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select); | |
1161 | ||
1162 | static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux = | |
1163 | SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum); | |
1164 | ||
1165 | static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum, | |
1166 | RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select); | |
1167 | ||
1168 | static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux = | |
1169 | SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum); | |
1170 | ||
1171 | static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum, | |
1172 | RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select); | |
1173 | ||
1174 | static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux = | |
1175 | SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum); | |
1176 | ||
1177 | static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum, | |
1178 | RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select); | |
1179 | ||
1180 | static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux = | |
1181 | SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum); | |
1182 | ||
1183 | /* MX-7a [14:12][10:8][6:4][2:0] */ | |
1184 | static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum, | |
1185 | RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select); | |
1186 | ||
1187 | static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux = | |
1188 | SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum); | |
1189 | ||
1190 | static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum, | |
1191 | RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select); | |
1192 | ||
1193 | static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux = | |
1194 | SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum); | |
1195 | ||
1196 | static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum, | |
1197 | RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select); | |
1198 | ||
1199 | static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux = | |
1200 | SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum); | |
1201 | ||
1202 | static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum, | |
1203 | RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select); | |
1204 | ||
1205 | static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux = | |
1206 | SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum); | |
1207 | ||
5c4ca99d BL |
1208 | /* MX-2d [3] [2] */ |
1209 | static const char * const rt5650_a_dac1_src[] = { | |
1210 | "DAC1", "Stereo DAC Mixer" | |
1211 | }; | |
1212 | ||
1213 | static SOC_ENUM_SINGLE_DECL( | |
1214 | rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR, | |
1215 | RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src); | |
1216 | ||
1217 | static const struct snd_kcontrol_new rt5650_a_dac1_l_mux = | |
1218 | SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum); | |
1219 | ||
1220 | static SOC_ENUM_SINGLE_DECL( | |
1221 | rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR, | |
1222 | RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src); | |
1223 | ||
1224 | static const struct snd_kcontrol_new rt5650_a_dac1_r_mux = | |
1225 | SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum); | |
1226 | ||
1227 | /* MX-2d [1] [0] */ | |
1228 | static const char * const rt5650_a_dac2_src[] = { | |
1229 | "Stereo DAC Mixer", "Mono DAC Mixer" | |
1230 | }; | |
1231 | ||
1232 | static SOC_ENUM_SINGLE_DECL( | |
1233 | rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR, | |
1234 | RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src); | |
1235 | ||
1236 | static const struct snd_kcontrol_new rt5650_a_dac2_l_mux = | |
1237 | SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum); | |
1238 | ||
1239 | static SOC_ENUM_SINGLE_DECL( | |
1240 | rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR, | |
1241 | RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src); | |
1242 | ||
1243 | static const struct snd_kcontrol_new rt5650_a_dac2_r_mux = | |
1244 | SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum); | |
1245 | ||
1319b2f6 OC |
1246 | /* MX-2F [13:12] */ |
1247 | static const char * const rt5645_if2_adc_in_src[] = { | |
1248 | "IF_ADC1", "IF_ADC2", "VAD_ADC" | |
1249 | }; | |
1250 | ||
1251 | static SOC_ENUM_SINGLE_DECL( | |
1252 | rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA, | |
1253 | RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src); | |
1254 | ||
1255 | static const struct snd_kcontrol_new rt5645_if2_adc_in_mux = | |
1256 | SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum); | |
1257 | ||
1258 | /* MX-2F [1:0] */ | |
1259 | static const char * const rt5645_if3_adc_in_src[] = { | |
1260 | "IF_ADC1", "IF_ADC2", "VAD_ADC" | |
1261 | }; | |
1262 | ||
1263 | static SOC_ENUM_SINGLE_DECL( | |
1264 | rt5645_if3_adc_in_enum, RT5645_DIG_INF1_DATA, | |
1265 | RT5645_IF3_ADC_IN_SFT, rt5645_if3_adc_in_src); | |
1266 | ||
1267 | static const struct snd_kcontrol_new rt5645_if3_adc_in_mux = | |
1268 | SOC_DAPM_ENUM("IF3 ADC IN source", rt5645_if3_adc_in_enum); | |
1269 | ||
1270 | /* MX-31 [15] [13] [11] [9] */ | |
1271 | static const char * const rt5645_pdm_src[] = { | |
1272 | "Mono DAC", "Stereo DAC" | |
1273 | }; | |
1274 | ||
1275 | static SOC_ENUM_SINGLE_DECL( | |
1276 | rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL, | |
1277 | RT5645_PDM1_L_SFT, rt5645_pdm_src); | |
1278 | ||
1279 | static const struct snd_kcontrol_new rt5645_pdm1_l_mux = | |
1280 | SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum); | |
1281 | ||
1282 | static SOC_ENUM_SINGLE_DECL( | |
1283 | rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL, | |
1284 | RT5645_PDM1_R_SFT, rt5645_pdm_src); | |
1285 | ||
1286 | static const struct snd_kcontrol_new rt5645_pdm1_r_mux = | |
1287 | SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum); | |
1288 | ||
1289 | /* MX-9D [9:8] */ | |
1290 | static const char * const rt5645_vad_adc_src[] = { | |
1291 | "Sto1 ADC L", "Mono ADC L", "Mono ADC R" | |
1292 | }; | |
1293 | ||
1294 | static SOC_ENUM_SINGLE_DECL( | |
1295 | rt5645_vad_adc_enum, RT5645_VAD_CTRL4, | |
1296 | RT5645_VAD_SEL_SFT, rt5645_vad_adc_src); | |
1297 | ||
1298 | static const struct snd_kcontrol_new rt5645_vad_adc_mux = | |
1299 | SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum); | |
1300 | ||
1301 | static const struct snd_kcontrol_new spk_l_vol_control = | |
1302 | SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL, | |
1303 | RT5645_L_MUTE_SFT, 1, 1); | |
1304 | ||
1305 | static const struct snd_kcontrol_new spk_r_vol_control = | |
1306 | SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL, | |
1307 | RT5645_R_MUTE_SFT, 1, 1); | |
1308 | ||
1309 | static const struct snd_kcontrol_new hp_l_vol_control = | |
1310 | SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL, | |
1311 | RT5645_L_MUTE_SFT, 1, 1); | |
1312 | ||
1313 | static const struct snd_kcontrol_new hp_r_vol_control = | |
1314 | SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL, | |
1315 | RT5645_R_MUTE_SFT, 1, 1); | |
1316 | ||
1317 | static const struct snd_kcontrol_new pdm1_l_vol_control = | |
1318 | SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL, | |
1319 | RT5645_M_PDM1_L, 1, 1); | |
1320 | ||
1321 | static const struct snd_kcontrol_new pdm1_r_vol_control = | |
1322 | SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL, | |
1323 | RT5645_M_PDM1_R, 1, 1); | |
1324 | ||
1325 | static void hp_amp_power(struct snd_soc_codec *codec, int on) | |
1326 | { | |
1327 | static int hp_amp_power_count; | |
1328 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); | |
1329 | ||
1330 | if (on) { | |
1331 | if (hp_amp_power_count <= 0) { | |
d12d6c4e JL |
1332 | if (rt5645->codec_type == CODEC_TYPE_RT5650) { |
1333 | snd_soc_write(codec, RT5645_CHARGE_PUMP, | |
1334 | 0x0e06); | |
1335 | snd_soc_write(codec, RT5645_DEPOP_M1, 0x001d); | |
1336 | regmap_write(rt5645->regmap, RT5645_PR_BASE + | |
1337 | 0x3e, 0x7400); | |
1338 | snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737); | |
1339 | regmap_write(rt5645->regmap, RT5645_PR_BASE + | |
1340 | RT5645_MAMP_INT_REG2, 0xfc00); | |
1341 | snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140); | |
1342 | } else { | |
1343 | /* depop parameters */ | |
1344 | snd_soc_update_bits(codec, RT5645_DEPOP_M2, | |
1345 | RT5645_DEPOP_MASK, RT5645_DEPOP_MAN); | |
1346 | snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d); | |
1347 | regmap_write(rt5645->regmap, RT5645_PR_BASE + | |
1348 | RT5645_HP_DCC_INT1, 0x9f01); | |
1349 | mdelay(150); | |
1350 | /* headphone amp power on */ | |
1351 | snd_soc_update_bits(codec, RT5645_PWR_ANLG1, | |
1352 | RT5645_PWR_FV1 | RT5645_PWR_FV2, 0); | |
1353 | snd_soc_update_bits(codec, RT5645_PWR_VOL, | |
1354 | RT5645_PWR_HV_L | RT5645_PWR_HV_R, | |
1355 | RT5645_PWR_HV_L | RT5645_PWR_HV_R); | |
1356 | snd_soc_update_bits(codec, RT5645_PWR_ANLG1, | |
1357 | RT5645_PWR_HP_L | RT5645_PWR_HP_R | | |
1358 | RT5645_PWR_HA, | |
1359 | RT5645_PWR_HP_L | RT5645_PWR_HP_R | | |
1360 | RT5645_PWR_HA); | |
1361 | mdelay(5); | |
1362 | snd_soc_update_bits(codec, RT5645_PWR_ANLG1, | |
1363 | RT5645_PWR_FV1 | RT5645_PWR_FV2, | |
1364 | RT5645_PWR_FV1 | RT5645_PWR_FV2); | |
1365 | ||
1366 | snd_soc_update_bits(codec, RT5645_DEPOP_M1, | |
1367 | RT5645_HP_CO_MASK | RT5645_HP_SG_MASK, | |
1368 | RT5645_HP_CO_EN | RT5645_HP_SG_EN); | |
1369 | regmap_write(rt5645->regmap, RT5645_PR_BASE + | |
1370 | 0x14, 0x1aaa); | |
1371 | regmap_write(rt5645->regmap, RT5645_PR_BASE + | |
1372 | 0x24, 0x0430); | |
1373 | } | |
1319b2f6 OC |
1374 | } |
1375 | hp_amp_power_count++; | |
1376 | } else { | |
1377 | hp_amp_power_count--; | |
1378 | if (hp_amp_power_count <= 0) { | |
d12d6c4e JL |
1379 | if (rt5645->codec_type == CODEC_TYPE_RT5650) { |
1380 | regmap_write(rt5645->regmap, RT5645_PR_BASE + | |
1381 | 0x3e, 0x7400); | |
1382 | snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737); | |
1383 | regmap_write(rt5645->regmap, RT5645_PR_BASE + | |
1384 | RT5645_MAMP_INT_REG2, 0xfc00); | |
1385 | snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140); | |
1386 | msleep(100); | |
1387 | snd_soc_write(codec, RT5645_DEPOP_M1, 0x0001); | |
1388 | ||
1389 | } else { | |
1390 | snd_soc_update_bits(codec, RT5645_DEPOP_M1, | |
1391 | RT5645_HP_SG_MASK | | |
1392 | RT5645_HP_L_SMT_MASK | | |
1393 | RT5645_HP_R_SMT_MASK, | |
1394 | RT5645_HP_SG_DIS | | |
1395 | RT5645_HP_L_SMT_DIS | | |
1396 | RT5645_HP_R_SMT_DIS); | |
1397 | /* headphone amp power down */ | |
1398 | snd_soc_write(codec, RT5645_DEPOP_M1, 0x0000); | |
1399 | snd_soc_update_bits(codec, RT5645_PWR_ANLG1, | |
1400 | RT5645_PWR_HP_L | RT5645_PWR_HP_R | | |
1401 | RT5645_PWR_HA, 0); | |
1402 | snd_soc_update_bits(codec, RT5645_DEPOP_M2, | |
1403 | RT5645_DEPOP_MASK, 0); | |
1404 | } | |
1319b2f6 OC |
1405 | } |
1406 | } | |
1407 | } | |
1408 | ||
1409 | static int rt5645_hp_event(struct snd_soc_dapm_widget *w, | |
1410 | struct snd_kcontrol *kcontrol, int event) | |
1411 | { | |
c5f596cb | 1412 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
1319b2f6 OC |
1413 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); |
1414 | ||
1415 | switch (event) { | |
1416 | case SND_SOC_DAPM_POST_PMU: | |
1417 | hp_amp_power(codec, 1); | |
1418 | /* headphone unmute sequence */ | |
d12d6c4e | 1419 | if (rt5645->codec_type == CODEC_TYPE_RT5645) { |
5c4ca99d BL |
1420 | snd_soc_update_bits(codec, RT5645_DEPOP_M3, |
1421 | RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK | | |
1422 | RT5645_CP_FQ3_MASK, | |
1423 | (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) | | |
1424 | (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) | | |
1425 | (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT)); | |
d12d6c4e JL |
1426 | regmap_write(rt5645->regmap, RT5645_PR_BASE + |
1427 | RT5645_MAMP_INT_REG2, 0xfc00); | |
1428 | snd_soc_update_bits(codec, RT5645_DEPOP_M1, | |
1429 | RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN); | |
1430 | snd_soc_update_bits(codec, RT5645_DEPOP_M1, | |
1431 | RT5645_RSTN_MASK, RT5645_RSTN_EN); | |
1432 | snd_soc_update_bits(codec, RT5645_DEPOP_M1, | |
1433 | RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK | | |
1434 | RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS | | |
1435 | RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN); | |
1436 | msleep(40); | |
1437 | snd_soc_update_bits(codec, RT5645_DEPOP_M1, | |
1438 | RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK | | |
1439 | RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS | | |
1440 | RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS); | |
5c4ca99d | 1441 | } |
1319b2f6 OC |
1442 | break; |
1443 | ||
1444 | case SND_SOC_DAPM_PRE_PMD: | |
1445 | /* headphone mute sequence */ | |
d12d6c4e | 1446 | if (rt5645->codec_type == CODEC_TYPE_RT5645) { |
5c4ca99d BL |
1447 | snd_soc_update_bits(codec, RT5645_DEPOP_M3, |
1448 | RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK | | |
1449 | RT5645_CP_FQ3_MASK, | |
1450 | (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) | | |
1451 | (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) | | |
1452 | (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT)); | |
d12d6c4e JL |
1453 | regmap_write(rt5645->regmap, RT5645_PR_BASE + |
1454 | RT5645_MAMP_INT_REG2, 0xfc00); | |
1455 | snd_soc_update_bits(codec, RT5645_DEPOP_M1, | |
1456 | RT5645_HP_SG_MASK, RT5645_HP_SG_EN); | |
1457 | snd_soc_update_bits(codec, RT5645_DEPOP_M1, | |
1458 | RT5645_RSTP_MASK, RT5645_RSTP_EN); | |
1459 | snd_soc_update_bits(codec, RT5645_DEPOP_M1, | |
1460 | RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK | | |
1461 | RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS | | |
1462 | RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN); | |
1463 | msleep(30); | |
5c4ca99d | 1464 | } |
1319b2f6 OC |
1465 | hp_amp_power(codec, 0); |
1466 | break; | |
1467 | ||
1468 | default: | |
1469 | return 0; | |
1470 | } | |
1471 | ||
1472 | return 0; | |
1473 | } | |
1474 | ||
1475 | static int rt5645_spk_event(struct snd_soc_dapm_widget *w, | |
1476 | struct snd_kcontrol *kcontrol, int event) | |
1477 | { | |
c5f596cb | 1478 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
1319b2f6 OC |
1479 | |
1480 | switch (event) { | |
1481 | case SND_SOC_DAPM_POST_PMU: | |
1482 | snd_soc_update_bits(codec, RT5645_PWR_DIG1, | |
1483 | RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | | |
1484 | RT5645_PWR_CLS_D_L, | |
1485 | RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | | |
1486 | RT5645_PWR_CLS_D_L); | |
1487 | break; | |
1488 | ||
1489 | case SND_SOC_DAPM_PRE_PMD: | |
1490 | snd_soc_update_bits(codec, RT5645_PWR_DIG1, | |
1491 | RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | | |
1492 | RT5645_PWR_CLS_D_L, 0); | |
1493 | break; | |
1494 | ||
1495 | default: | |
1496 | return 0; | |
1497 | } | |
1498 | ||
1499 | return 0; | |
1500 | } | |
1501 | ||
1502 | static int rt5645_lout_event(struct snd_soc_dapm_widget *w, | |
1503 | struct snd_kcontrol *kcontrol, int event) | |
1504 | { | |
c5f596cb | 1505 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
1319b2f6 OC |
1506 | |
1507 | switch (event) { | |
1508 | case SND_SOC_DAPM_POST_PMU: | |
1509 | hp_amp_power(codec, 1); | |
1510 | snd_soc_update_bits(codec, RT5645_PWR_ANLG1, | |
1511 | RT5645_PWR_LM, RT5645_PWR_LM); | |
1512 | snd_soc_update_bits(codec, RT5645_LOUT1, | |
1513 | RT5645_L_MUTE | RT5645_R_MUTE, 0); | |
1514 | break; | |
1515 | ||
1516 | case SND_SOC_DAPM_PRE_PMD: | |
1517 | snd_soc_update_bits(codec, RT5645_LOUT1, | |
1518 | RT5645_L_MUTE | RT5645_R_MUTE, | |
1519 | RT5645_L_MUTE | RT5645_R_MUTE); | |
1520 | snd_soc_update_bits(codec, RT5645_PWR_ANLG1, | |
1521 | RT5645_PWR_LM, 0); | |
1522 | hp_amp_power(codec, 0); | |
1523 | break; | |
1524 | ||
1525 | default: | |
1526 | return 0; | |
1527 | } | |
1528 | ||
1529 | return 0; | |
1530 | } | |
1531 | ||
1532 | static int rt5645_bst2_event(struct snd_soc_dapm_widget *w, | |
1533 | struct snd_kcontrol *kcontrol, int event) | |
1534 | { | |
c5f596cb | 1535 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
1319b2f6 OC |
1536 | |
1537 | switch (event) { | |
1538 | case SND_SOC_DAPM_POST_PMU: | |
1539 | snd_soc_update_bits(codec, RT5645_PWR_ANLG2, | |
1540 | RT5645_PWR_BST2_P, RT5645_PWR_BST2_P); | |
1541 | break; | |
1542 | ||
1543 | case SND_SOC_DAPM_PRE_PMD: | |
1544 | snd_soc_update_bits(codec, RT5645_PWR_ANLG2, | |
1545 | RT5645_PWR_BST2_P, 0); | |
1546 | break; | |
1547 | ||
1548 | default: | |
1549 | return 0; | |
1550 | } | |
1551 | ||
1552 | return 0; | |
1553 | } | |
1554 | ||
1555 | static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = { | |
1556 | SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER, | |
1557 | RT5645_PWR_LDO2_BIT, 0, NULL, 0), | |
1558 | SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2, | |
1559 | RT5645_PWR_PLL_BIT, 0, NULL, 0), | |
1560 | ||
1561 | SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2, | |
1562 | RT5645_PWR_JD1_BIT, 0, NULL, 0), | |
1563 | SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL, | |
1564 | RT5645_PWR_MIC_DET_BIT, 0, NULL, 0), | |
1565 | ||
9e268353 BL |
1566 | /* ASRC */ |
1567 | SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1, | |
1568 | 11, 0, NULL, 0), | |
1569 | SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1, | |
1570 | 12, 0, NULL, 0), | |
1571 | SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1, | |
1572 | 10, 0, NULL, 0), | |
1573 | SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1, | |
1574 | 9, 0, NULL, 0), | |
1575 | SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1, | |
1576 | 8, 0, NULL, 0), | |
1577 | SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1, | |
1578 | 7, 0, NULL, 0), | |
1579 | SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1, | |
1580 | 5, 0, NULL, 0), | |
1581 | SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1, | |
1582 | 4, 0, NULL, 0), | |
1583 | SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1, | |
1584 | 3, 0, NULL, 0), | |
1585 | SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1, | |
1586 | 1, 0, NULL, 0), | |
1587 | SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1, | |
1588 | 0, 0, NULL, 0), | |
1589 | ||
1319b2f6 OC |
1590 | /* Input Side */ |
1591 | /* micbias */ | |
1592 | SND_SOC_DAPM_MICBIAS("micbias1", RT5645_PWR_ANLG2, | |
1593 | RT5645_PWR_MB1_BIT, 0), | |
1594 | SND_SOC_DAPM_MICBIAS("micbias2", RT5645_PWR_ANLG2, | |
1595 | RT5645_PWR_MB2_BIT, 0), | |
1596 | /* Input Lines */ | |
1597 | SND_SOC_DAPM_INPUT("DMIC L1"), | |
1598 | SND_SOC_DAPM_INPUT("DMIC R1"), | |
1599 | SND_SOC_DAPM_INPUT("DMIC L2"), | |
1600 | SND_SOC_DAPM_INPUT("DMIC R2"), | |
1601 | ||
1602 | SND_SOC_DAPM_INPUT("IN1P"), | |
1603 | SND_SOC_DAPM_INPUT("IN1N"), | |
1604 | SND_SOC_DAPM_INPUT("IN2P"), | |
1605 | SND_SOC_DAPM_INPUT("IN2N"), | |
1606 | ||
1607 | SND_SOC_DAPM_INPUT("Haptic Generator"), | |
1608 | ||
1609 | SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1610 | SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1611 | SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, | |
1612 | set_dmic_clk, SND_SOC_DAPM_PRE_PMU), | |
1613 | SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1, | |
1614 | RT5645_DMIC_1_EN_SFT, 0, NULL, 0), | |
1615 | SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1, | |
1616 | RT5645_DMIC_2_EN_SFT, 0, NULL, 0), | |
1617 | /* Boost */ | |
1618 | SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2, | |
1619 | RT5645_PWR_BST1_BIT, 0, NULL, 0), | |
1620 | SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2, | |
1621 | RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event, | |
1622 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), | |
1623 | /* Input Volume */ | |
1624 | SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL, | |
1625 | RT5645_PWR_IN_L_BIT, 0, NULL, 0), | |
1626 | SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL, | |
1627 | RT5645_PWR_IN_R_BIT, 0, NULL, 0), | |
1628 | /* REC Mixer */ | |
1629 | SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT, | |
1630 | 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)), | |
1631 | SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT, | |
1632 | 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)), | |
1633 | /* ADCs */ | |
1634 | SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), | |
1635 | SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), | |
1636 | ||
1637 | SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1, | |
1638 | RT5645_PWR_ADC_L_BIT, 0, NULL, 0), | |
1639 | SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1, | |
1640 | RT5645_PWR_ADC_R_BIT, 0, NULL, 0), | |
1641 | ||
1642 | /* ADC Mux */ | |
1643 | SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0, | |
1644 | &rt5645_sto1_dmic_mux), | |
1645 | SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, | |
1646 | &rt5645_sto_adc2_mux), | |
1647 | SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, | |
1648 | &rt5645_sto_adc2_mux), | |
1649 | SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, | |
1650 | &rt5645_sto_adc1_mux), | |
1651 | SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, | |
1652 | &rt5645_sto_adc1_mux), | |
1653 | SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0, | |
1654 | &rt5645_mono_dmic_l_mux), | |
1655 | SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0, | |
1656 | &rt5645_mono_dmic_r_mux), | |
1657 | SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0, | |
1658 | &rt5645_mono_adc_l2_mux), | |
1659 | SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0, | |
1660 | &rt5645_mono_adc_l1_mux), | |
1661 | SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0, | |
1662 | &rt5645_mono_adc_r1_mux), | |
1663 | SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0, | |
1664 | &rt5645_mono_adc_r2_mux), | |
1665 | /* ADC Mixer */ | |
1666 | ||
1667 | SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2, | |
1668 | RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0), | |
1319b2f6 OC |
1669 | SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0, |
1670 | rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix), | |
1671 | NULL, 0), | |
1672 | SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0, | |
1673 | rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix), | |
1674 | NULL, 0), | |
1675 | SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2, | |
1676 | RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0), | |
1677 | SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0, | |
1678 | rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix), | |
1679 | NULL, 0), | |
1680 | SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2, | |
1681 | RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0), | |
1682 | SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0, | |
1683 | rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix), | |
1684 | NULL, 0), | |
1685 | ||
1686 | /* ADC PGA */ | |
1687 | SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1688 | SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1689 | SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1690 | SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1691 | SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1692 | SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1693 | SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1694 | SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1695 | SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1696 | SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1697 | ||
1698 | /* IF1 2 Mux */ | |
21ab3f2b BL |
1699 | SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM, |
1700 | 0, 0, &rt5645_if1_adc1_in_mux), | |
1701 | SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM, | |
1702 | 0, 0, &rt5645_if1_adc2_in_mux), | |
1703 | SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM, | |
1704 | 0, 0, &rt5645_if1_adc3_in_mux), | |
1705 | SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM, | |
1319b2f6 | 1706 | 0, 0, &rt5645_if1_adc_in_mux), |
21ab3f2b | 1707 | |
1319b2f6 OC |
1708 | SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, |
1709 | 0, 0, &rt5645_if2_adc_in_mux), | |
1710 | ||
1711 | /* Digital Interface */ | |
1712 | SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1, | |
1713 | RT5645_PWR_I2S1_BIT, 0, NULL, 0), | |
786aa09b | 1714 | SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), |
1319b2f6 OC |
1715 | SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), |
1716 | SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), | |
786aa09b | 1717 | SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), |
21ab3f2b BL |
1718 | SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0, |
1719 | &rt5645_if1_dac0_tdm_sel_mux), | |
1720 | SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0, | |
1721 | &rt5645_if1_dac1_tdm_sel_mux), | |
1722 | SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0, | |
1723 | &rt5645_if1_dac2_tdm_sel_mux), | |
1724 | SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0, | |
1725 | &rt5645_if1_dac3_tdm_sel_mux), | |
1319b2f6 OC |
1726 | SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), |
1727 | SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1728 | SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1729 | SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1, | |
1730 | RT5645_PWR_I2S2_BIT, 0, NULL, 0), | |
1731 | SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1732 | SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1733 | SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1734 | SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1735 | ||
1736 | /* Digital Interface Select */ | |
1737 | SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, | |
1738 | 0, 0, &rt5645_vad_adc_mux), | |
1739 | ||
1740 | /* Audio Interface */ | |
1741 | SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), | |
1742 | SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), | |
1743 | SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), | |
1744 | SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), | |
1745 | ||
1746 | /* Output Side */ | |
1747 | /* DAC mixer before sound effect */ | |
1748 | SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, | |
1749 | rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)), | |
1750 | SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, | |
1751 | rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)), | |
1752 | ||
1753 | /* DAC2 channel Mux */ | |
1754 | SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux), | |
1755 | SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux), | |
1756 | SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1, | |
1757 | RT5645_PWR_DAC_L2_BIT, 0, NULL, 0), | |
1758 | SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1, | |
1759 | RT5645_PWR_DAC_R2_BIT, 0, NULL, 0), | |
1760 | ||
1761 | SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux), | |
1762 | SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux), | |
1763 | ||
1764 | /* DAC Mixer */ | |
1765 | SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2, | |
1766 | RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0), | |
1767 | SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2, | |
1768 | RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0), | |
1769 | SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2, | |
1770 | RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0), | |
1771 | SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0, | |
1772 | rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)), | |
1773 | SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0, | |
1774 | rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)), | |
1775 | SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0, | |
1776 | rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)), | |
1777 | SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0, | |
1778 | rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)), | |
1779 | SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0, | |
1780 | rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)), | |
1781 | SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0, | |
1782 | rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)), | |
1783 | ||
1784 | /* DACs */ | |
1785 | SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT, | |
1786 | 0), | |
1787 | SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT, | |
1788 | 0), | |
1789 | SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT, | |
1790 | 0), | |
1791 | SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT, | |
1792 | 0), | |
1793 | /* OUT Mixer */ | |
1794 | SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT, | |
1795 | 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)), | |
1796 | SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT, | |
1797 | 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)), | |
1798 | SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT, | |
1799 | 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)), | |
1800 | SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT, | |
1801 | 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)), | |
1802 | /* Ouput Volume */ | |
1803 | SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0, | |
1804 | &spk_l_vol_control), | |
1805 | SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0, | |
1806 | &spk_r_vol_control), | |
1807 | SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT, | |
1808 | 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)), | |
1809 | SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT, | |
1810 | 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)), | |
1811 | SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER, | |
1812 | RT5645_PWR_HM_L_BIT, 0, NULL, 0), | |
1813 | SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER, | |
1814 | RT5645_PWR_HM_R_BIT, 0, NULL, 0), | |
1815 | SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1816 | SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1817 | SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1818 | SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control), | |
1819 | SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control), | |
1820 | ||
1821 | /* HPO/LOUT/Mono Mixer */ | |
1822 | SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix, | |
1823 | ARRAY_SIZE(rt5645_spo_l_mix)), | |
1824 | SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix, | |
1825 | ARRAY_SIZE(rt5645_spo_r_mix)), | |
1826 | SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix, | |
1827 | ARRAY_SIZE(rt5645_hpo_mix)), | |
1828 | SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix, | |
1829 | ARRAY_SIZE(rt5645_lout_mix)), | |
1830 | ||
1831 | SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event, | |
1832 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), | |
1833 | SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event, | |
1834 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), | |
1835 | SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event, | |
1836 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), | |
1837 | ||
1838 | /* PDM */ | |
1839 | SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT, | |
1840 | 0, NULL, 0), | |
1841 | SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux), | |
1842 | SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux), | |
1843 | ||
1844 | SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control), | |
1845 | SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control), | |
1846 | ||
1847 | /* Output Lines */ | |
1848 | SND_SOC_DAPM_OUTPUT("HPOL"), | |
1849 | SND_SOC_DAPM_OUTPUT("HPOR"), | |
1850 | SND_SOC_DAPM_OUTPUT("LOUTL"), | |
1851 | SND_SOC_DAPM_OUTPUT("LOUTR"), | |
1852 | SND_SOC_DAPM_OUTPUT("PDM1L"), | |
1853 | SND_SOC_DAPM_OUTPUT("PDM1R"), | |
1854 | SND_SOC_DAPM_OUTPUT("SPOL"), | |
1855 | SND_SOC_DAPM_OUTPUT("SPOR"), | |
1856 | }; | |
1857 | ||
5c4ca99d BL |
1858 | static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = { |
1859 | SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM, | |
1860 | 0, 0, &rt5650_a_dac1_l_mux), | |
1861 | SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM, | |
1862 | 0, 0, &rt5650_a_dac1_r_mux), | |
1863 | SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM, | |
1864 | 0, 0, &rt5650_a_dac2_l_mux), | |
1865 | SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM, | |
1866 | 0, 0, &rt5650_a_dac2_r_mux), | |
851b81e8 MC |
1867 | |
1868 | SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM, | |
1869 | 0, 0, &rt5650_if1_adc1_in_mux), | |
1870 | SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM, | |
1871 | 0, 0, &rt5650_if1_adc2_in_mux), | |
1872 | SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM, | |
1873 | 0, 0, &rt5650_if1_adc3_in_mux), | |
1874 | SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM, | |
1875 | 0, 0, &rt5650_if1_adc_in_mux), | |
1876 | ||
1877 | SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0, | |
1878 | &rt5650_if1_dac0_tdm_sel_mux), | |
1879 | SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0, | |
1880 | &rt5650_if1_dac1_tdm_sel_mux), | |
1881 | SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0, | |
1882 | &rt5650_if1_dac2_tdm_sel_mux), | |
1883 | SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0, | |
1884 | &rt5650_if1_dac3_tdm_sel_mux), | |
5c4ca99d BL |
1885 | }; |
1886 | ||
1319b2f6 | 1887 | static const struct snd_soc_dapm_route rt5645_dapm_routes[] = { |
9e268353 | 1888 | { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc }, |
9e268353 BL |
1889 | { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc }, |
1890 | { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc }, | |
1891 | { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc }, | |
1892 | { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc }, | |
1893 | { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc }, | |
1894 | ||
1895 | { "I2S1", NULL, "I2S1 ASRC" }, | |
1896 | { "I2S2", NULL, "I2S2 ASRC" }, | |
1897 | ||
1319b2f6 OC |
1898 | { "IN1P", NULL, "LDO2" }, |
1899 | { "IN2P", NULL, "LDO2" }, | |
1900 | ||
1901 | { "DMIC1", NULL, "DMIC L1" }, | |
1902 | { "DMIC1", NULL, "DMIC R1" }, | |
1903 | { "DMIC2", NULL, "DMIC L2" }, | |
1904 | { "DMIC2", NULL, "DMIC R2" }, | |
1905 | ||
1906 | { "BST1", NULL, "IN1P" }, | |
1907 | { "BST1", NULL, "IN1N" }, | |
1908 | { "BST1", NULL, "JD Power" }, | |
1909 | { "BST1", NULL, "Mic Det Power" }, | |
1910 | { "BST2", NULL, "IN2P" }, | |
1911 | { "BST2", NULL, "IN2N" }, | |
1912 | ||
1913 | { "INL VOL", NULL, "IN2P" }, | |
1914 | { "INR VOL", NULL, "IN2N" }, | |
1915 | ||
1916 | { "RECMIXL", "HPOL Switch", "HPOL" }, | |
1917 | { "RECMIXL", "INL Switch", "INL VOL" }, | |
1918 | { "RECMIXL", "BST2 Switch", "BST2" }, | |
1919 | { "RECMIXL", "BST1 Switch", "BST1" }, | |
1920 | { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" }, | |
1921 | ||
1922 | { "RECMIXR", "HPOR Switch", "HPOR" }, | |
1923 | { "RECMIXR", "INR Switch", "INR VOL" }, | |
1924 | { "RECMIXR", "BST2 Switch", "BST2" }, | |
1925 | { "RECMIXR", "BST1 Switch", "BST1" }, | |
1926 | { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" }, | |
1927 | ||
1928 | { "ADC L", NULL, "RECMIXL" }, | |
1929 | { "ADC L", NULL, "ADC L power" }, | |
1930 | { "ADC R", NULL, "RECMIXR" }, | |
1931 | { "ADC R", NULL, "ADC R power" }, | |
1932 | ||
1933 | {"DMIC L1", NULL, "DMIC CLK"}, | |
1934 | {"DMIC L1", NULL, "DMIC1 Power"}, | |
1935 | {"DMIC R1", NULL, "DMIC CLK"}, | |
1936 | {"DMIC R1", NULL, "DMIC1 Power"}, | |
1937 | {"DMIC L2", NULL, "DMIC CLK"}, | |
1938 | {"DMIC L2", NULL, "DMIC2 Power"}, | |
1939 | {"DMIC R2", NULL, "DMIC CLK"}, | |
1940 | {"DMIC R2", NULL, "DMIC2 Power"}, | |
1941 | ||
1942 | { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" }, | |
1943 | { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" }, | |
9e268353 | 1944 | { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" }, |
1319b2f6 OC |
1945 | |
1946 | { "Mono DMIC L Mux", "DMIC1", "DMIC L1" }, | |
1947 | { "Mono DMIC L Mux", "DMIC2", "DMIC L2" }, | |
9e268353 | 1948 | { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" }, |
1319b2f6 OC |
1949 | |
1950 | { "Mono DMIC R Mux", "DMIC1", "DMIC R1" }, | |
1951 | { "Mono DMIC R Mux", "DMIC2", "DMIC R2" }, | |
9e268353 | 1952 | { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" }, |
1319b2f6 OC |
1953 | |
1954 | { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" }, | |
1955 | { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" }, | |
1956 | { "Stereo1 ADC L1 Mux", "ADC", "ADC L" }, | |
1957 | { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" }, | |
1958 | ||
1959 | { "Stereo1 ADC R1 Mux", "ADC", "ADC R" }, | |
1960 | { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" }, | |
1961 | { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" }, | |
1962 | { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" }, | |
1963 | ||
1964 | { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" }, | |
1965 | { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" }, | |
1966 | { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" }, | |
1967 | { "Mono ADC L1 Mux", "ADC", "ADC L" }, | |
1968 | ||
1969 | { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" }, | |
1970 | { "Mono ADC R1 Mux", "ADC", "ADC R" }, | |
1971 | { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" }, | |
1972 | { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" }, | |
1973 | ||
1974 | { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" }, | |
1975 | { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" }, | |
1976 | { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" }, | |
1977 | { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" }, | |
1978 | ||
1979 | { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" }, | |
1980 | { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" }, | |
1981 | { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, | |
1982 | ||
1983 | { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" }, | |
1984 | { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" }, | |
1985 | { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, | |
1986 | ||
1987 | { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" }, | |
1988 | { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" }, | |
1989 | { "Mono ADC MIXL", NULL, "adc mono left filter" }, | |
1990 | { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll }, | |
1991 | ||
1992 | { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" }, | |
1993 | { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" }, | |
1994 | { "Mono ADC MIXR", NULL, "adc mono right filter" }, | |
1995 | { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll }, | |
1996 | ||
1997 | { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" }, | |
1998 | { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" }, | |
1999 | { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" }, | |
2000 | ||
2001 | { "IF_ADC1", NULL, "Stereo1 ADC MIXL" }, | |
2002 | { "IF_ADC1", NULL, "Stereo1 ADC MIXR" }, | |
2003 | { "IF_ADC2", NULL, "Mono ADC MIXL" }, | |
2004 | { "IF_ADC2", NULL, "Mono ADC MIXR" }, | |
2005 | { "VAD_ADC", NULL, "VAD ADC Mux" }, | |
2006 | ||
1319b2f6 OC |
2007 | { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" }, |
2008 | { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" }, | |
2009 | { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" }, | |
2010 | ||
2011 | { "IF1 ADC", NULL, "I2S1" }, | |
1319b2f6 OC |
2012 | { "IF2 ADC", NULL, "I2S2" }, |
2013 | { "IF2 ADC", NULL, "IF2 ADC Mux" }, | |
2014 | ||
1319b2f6 OC |
2015 | { "AIF2TX", NULL, "IF2 ADC" }, |
2016 | ||
21ab3f2b | 2017 | { "IF1 DAC0", NULL, "AIF1RX" }, |
1319b2f6 OC |
2018 | { "IF1 DAC1", NULL, "AIF1RX" }, |
2019 | { "IF1 DAC2", NULL, "AIF1RX" }, | |
21ab3f2b | 2020 | { "IF1 DAC3", NULL, "AIF1RX" }, |
1319b2f6 OC |
2021 | { "IF2 DAC", NULL, "AIF2RX" }, |
2022 | ||
21ab3f2b | 2023 | { "IF1 DAC0", NULL, "I2S1" }, |
1319b2f6 OC |
2024 | { "IF1 DAC1", NULL, "I2S1" }, |
2025 | { "IF1 DAC2", NULL, "I2S1" }, | |
21ab3f2b | 2026 | { "IF1 DAC3", NULL, "I2S1" }, |
1319b2f6 OC |
2027 | { "IF2 DAC", NULL, "I2S2" }, |
2028 | ||
1319b2f6 OC |
2029 | { "IF2 DAC L", NULL, "IF2 DAC" }, |
2030 | { "IF2 DAC R", NULL, "IF2 DAC" }, | |
2031 | ||
1319b2f6 | 2032 | { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" }, |
1319b2f6 OC |
2033 | { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" }, |
2034 | ||
2035 | { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" }, | |
2036 | { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" }, | |
2037 | { "DAC1 MIXL", NULL, "dac stereo1 filter" }, | |
2038 | { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" }, | |
2039 | { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" }, | |
2040 | { "DAC1 MIXR", NULL, "dac stereo1 filter" }, | |
2041 | ||
1319b2f6 OC |
2042 | { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" }, |
2043 | { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" }, | |
2044 | { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" }, | |
2045 | { "DAC L2 Volume", NULL, "DAC L2 Mux" }, | |
2046 | { "DAC L2 Volume", NULL, "dac mono left filter" }, | |
2047 | ||
1319b2f6 OC |
2048 | { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" }, |
2049 | { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" }, | |
2050 | { "DAC R2 Mux", "Haptic", "Haptic Generator" }, | |
2051 | { "DAC R2 Volume", NULL, "DAC R2 Mux" }, | |
2052 | { "DAC R2 Volume", NULL, "dac mono right filter" }, | |
2053 | ||
2054 | { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" }, | |
2055 | { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" }, | |
2056 | { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, | |
2057 | { "Stereo DAC MIXL", NULL, "dac stereo1 filter" }, | |
2058 | { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" }, | |
2059 | { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" }, | |
2060 | { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, | |
2061 | { "Stereo DAC MIXR", NULL, "dac stereo1 filter" }, | |
2062 | ||
2063 | { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" }, | |
2064 | { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, | |
2065 | { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" }, | |
2066 | { "Mono DAC MIXL", NULL, "dac mono left filter" }, | |
2067 | { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" }, | |
2068 | { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, | |
2069 | { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" }, | |
2070 | { "Mono DAC MIXR", NULL, "dac mono right filter" }, | |
2071 | ||
2072 | { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, | |
2073 | { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, | |
2074 | { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" }, | |
2075 | { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, | |
2076 | { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, | |
2077 | { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" }, | |
2078 | ||
1319b2f6 | 2079 | { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll }, |
1319b2f6 | 2080 | { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll }, |
1319b2f6 | 2081 | { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll }, |
1319b2f6 OC |
2082 | { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll }, |
2083 | ||
2084 | { "SPK MIXL", "BST1 Switch", "BST1" }, | |
2085 | { "SPK MIXL", "INL Switch", "INL VOL" }, | |
2086 | { "SPK MIXL", "DAC L1 Switch", "DAC L1" }, | |
2087 | { "SPK MIXL", "DAC L2 Switch", "DAC L2" }, | |
2088 | { "SPK MIXR", "BST2 Switch", "BST2" }, | |
2089 | { "SPK MIXR", "INR Switch", "INR VOL" }, | |
2090 | { "SPK MIXR", "DAC R1 Switch", "DAC R1" }, | |
2091 | { "SPK MIXR", "DAC R2 Switch", "DAC R2" }, | |
2092 | ||
2093 | { "OUT MIXL", "BST1 Switch", "BST1" }, | |
2094 | { "OUT MIXL", "INL Switch", "INL VOL" }, | |
2095 | { "OUT MIXL", "DAC L2 Switch", "DAC L2" }, | |
2096 | { "OUT MIXL", "DAC L1 Switch", "DAC L1" }, | |
2097 | ||
2098 | { "OUT MIXR", "BST2 Switch", "BST2" }, | |
2099 | { "OUT MIXR", "INR Switch", "INR VOL" }, | |
2100 | { "OUT MIXR", "DAC R2 Switch", "DAC R2" }, | |
2101 | { "OUT MIXR", "DAC R1 Switch", "DAC R1" }, | |
2102 | ||
2103 | { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" }, | |
2104 | { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" }, | |
2105 | { "HPOVOL MIXL", "INL Switch", "INL VOL" }, | |
2106 | { "HPOVOL MIXL", "BST1 Switch", "BST1" }, | |
2107 | { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" }, | |
2108 | { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" }, | |
2109 | { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" }, | |
2110 | { "HPOVOL MIXR", "INR Switch", "INR VOL" }, | |
2111 | { "HPOVOL MIXR", "BST2 Switch", "BST2" }, | |
2112 | { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" }, | |
2113 | ||
2114 | { "DAC 2", NULL, "DAC L2" }, | |
2115 | { "DAC 2", NULL, "DAC R2" }, | |
2116 | { "DAC 1", NULL, "DAC L1" }, | |
2117 | { "DAC 1", NULL, "DAC R1" }, | |
2118 | { "HPOVOL L", "Switch", "HPOVOL MIXL" }, | |
2119 | { "HPOVOL R", "Switch", "HPOVOL MIXR" }, | |
2120 | { "HPOVOL", NULL, "HPOVOL L" }, | |
2121 | { "HPOVOL", NULL, "HPOVOL R" }, | |
2122 | { "HPO MIX", "DAC1 Switch", "DAC 1" }, | |
2123 | { "HPO MIX", "HPVOL Switch", "HPOVOL" }, | |
2124 | ||
2125 | { "SPKVOL L", "Switch", "SPK MIXL" }, | |
2126 | { "SPKVOL R", "Switch", "SPK MIXR" }, | |
2127 | ||
2128 | { "SPOL MIX", "DAC R1 Switch", "DAC R1" }, | |
2129 | { "SPOL MIX", "DAC L1 Switch", "DAC L1" }, | |
2130 | { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" }, | |
2131 | { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" }, | |
2132 | { "SPOR MIX", "DAC R1 Switch", "DAC R1" }, | |
2133 | { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" }, | |
2134 | ||
2135 | { "LOUT MIX", "DAC L1 Switch", "DAC L1" }, | |
2136 | { "LOUT MIX", "DAC R1 Switch", "DAC R1" }, | |
2137 | { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" }, | |
2138 | { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" }, | |
2139 | ||
2140 | { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" }, | |
2141 | { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" }, | |
2142 | { "PDM1 L Mux", NULL, "PDM1 Power" }, | |
2143 | { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" }, | |
2144 | { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" }, | |
2145 | { "PDM1 R Mux", NULL, "PDM1 Power" }, | |
2146 | ||
2147 | { "HP amp", NULL, "HPO MIX" }, | |
2148 | { "HP amp", NULL, "JD Power" }, | |
2149 | { "HP amp", NULL, "Mic Det Power" }, | |
2150 | { "HP amp", NULL, "LDO2" }, | |
2151 | { "HPOL", NULL, "HP amp" }, | |
2152 | { "HPOR", NULL, "HP amp" }, | |
2153 | ||
2154 | { "LOUT amp", NULL, "LOUT MIX" }, | |
2155 | { "LOUTL", NULL, "LOUT amp" }, | |
2156 | { "LOUTR", NULL, "LOUT amp" }, | |
2157 | ||
2158 | { "PDM1 L", "Switch", "PDM1 L Mux" }, | |
2159 | { "PDM1 R", "Switch", "PDM1 R Mux" }, | |
2160 | ||
2161 | { "PDM1L", NULL, "PDM1 L" }, | |
2162 | { "PDM1R", NULL, "PDM1 R" }, | |
2163 | ||
2164 | { "SPK amp", NULL, "SPOL MIX" }, | |
2165 | { "SPK amp", NULL, "SPOR MIX" }, | |
2166 | { "SPOL", NULL, "SPK amp" }, | |
2167 | { "SPOR", NULL, "SPK amp" }, | |
2168 | }; | |
2169 | ||
5c4ca99d BL |
2170 | static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = { |
2171 | { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"}, | |
2172 | { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"}, | |
2173 | { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"}, | |
2174 | { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"}, | |
2175 | ||
2176 | { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"}, | |
2177 | { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"}, | |
2178 | { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"}, | |
2179 | { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"}, | |
2180 | ||
2181 | { "DAC L1", NULL, "A DAC1 L Mux" }, | |
2182 | { "DAC R1", NULL, "A DAC1 R Mux" }, | |
2183 | { "DAC L2", NULL, "A DAC2 L Mux" }, | |
2184 | { "DAC R2", NULL, "A DAC2 R Mux" }, | |
21ab3f2b BL |
2185 | |
2186 | { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" }, | |
2187 | { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" }, | |
2188 | { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" }, | |
2189 | { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" }, | |
2190 | ||
2191 | { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" }, | |
2192 | { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" }, | |
2193 | { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" }, | |
2194 | { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" }, | |
2195 | ||
2196 | { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" }, | |
2197 | { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" }, | |
2198 | { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" }, | |
2199 | { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" }, | |
2200 | ||
2201 | { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" }, | |
2202 | { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" }, | |
2203 | { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" }, | |
2204 | ||
2205 | { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" }, | |
2206 | { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" }, | |
2207 | { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" }, | |
2208 | { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" }, | |
2209 | { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" }, | |
2210 | { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" }, | |
2211 | ||
2212 | { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" }, | |
2213 | { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" }, | |
2214 | { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" }, | |
2215 | { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" }, | |
2216 | { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" }, | |
2217 | { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" }, | |
2218 | ||
2219 | { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" }, | |
2220 | { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" }, | |
2221 | { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" }, | |
2222 | { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" }, | |
2223 | { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" }, | |
2224 | { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" }, | |
2225 | ||
2226 | { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" }, | |
2227 | { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" }, | |
2228 | { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" }, | |
2229 | { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" }, | |
2230 | { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" }, | |
2231 | { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" }, | |
2232 | { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" }, | |
2233 | ||
2234 | { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" }, | |
2235 | { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" }, | |
2236 | { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" }, | |
2237 | { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" }, | |
2238 | ||
2239 | { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" }, | |
2240 | { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" }, | |
2241 | { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" }, | |
2242 | { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" }, | |
2243 | ||
2244 | { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" }, | |
2245 | { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" }, | |
2246 | { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" }, | |
2247 | { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" }, | |
2248 | ||
2249 | { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" }, | |
2250 | { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" }, | |
2251 | { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" }, | |
2252 | { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" }, | |
2253 | ||
2254 | { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" }, | |
2255 | { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" }, | |
2256 | ||
2257 | { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" }, | |
2258 | { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" }, | |
5c4ca99d BL |
2259 | }; |
2260 | ||
2261 | static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = { | |
2262 | { "DAC L1", NULL, "Stereo DAC MIXL" }, | |
2263 | { "DAC R1", NULL, "Stereo DAC MIXR" }, | |
2264 | { "DAC L2", NULL, "Mono DAC MIXL" }, | |
2265 | { "DAC R2", NULL, "Mono DAC MIXR" }, | |
21ab3f2b BL |
2266 | |
2267 | { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" }, | |
2268 | { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" }, | |
2269 | { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" }, | |
2270 | { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" }, | |
2271 | ||
2272 | { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" }, | |
2273 | { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" }, | |
2274 | { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" }, | |
2275 | { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" }, | |
2276 | ||
2277 | { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" }, | |
2278 | { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" }, | |
2279 | { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" }, | |
2280 | { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" }, | |
2281 | ||
2282 | { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" }, | |
2283 | { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" }, | |
2284 | { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" }, | |
2285 | ||
2286 | { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" }, | |
2287 | { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" }, | |
2288 | { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" }, | |
2289 | { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" }, | |
2290 | { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" }, | |
2291 | ||
2292 | { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" }, | |
2293 | { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" }, | |
2294 | { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" }, | |
2295 | { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" }, | |
2296 | ||
2297 | { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" }, | |
2298 | { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" }, | |
2299 | { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" }, | |
2300 | { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" }, | |
2301 | ||
2302 | { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" }, | |
2303 | { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" }, | |
2304 | { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" }, | |
2305 | { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" }, | |
2306 | ||
2307 | { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" }, | |
2308 | { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" }, | |
2309 | { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" }, | |
2310 | { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" }, | |
2311 | ||
2312 | { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" }, | |
2313 | { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" }, | |
2314 | ||
2315 | { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" }, | |
2316 | { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" }, | |
5c4ca99d BL |
2317 | }; |
2318 | ||
1319b2f6 OC |
2319 | static int rt5645_hw_params(struct snd_pcm_substream *substream, |
2320 | struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) | |
2321 | { | |
2322 | struct snd_soc_codec *codec = dai->codec; | |
2323 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); | |
57bf2736 | 2324 | unsigned int val_len = 0, val_clk, mask_clk, dl_sft; |
1319b2f6 OC |
2325 | int pre_div, bclk_ms, frame_size; |
2326 | ||
2327 | rt5645->lrck[dai->id] = params_rate(params); | |
d92950e7 | 2328 | pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]); |
1319b2f6 OC |
2329 | if (pre_div < 0) { |
2330 | dev_err(codec->dev, "Unsupported clock setting\n"); | |
2331 | return -EINVAL; | |
2332 | } | |
2333 | frame_size = snd_soc_params_to_frame_size(params); | |
2334 | if (frame_size < 0) { | |
2335 | dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size); | |
2336 | return -EINVAL; | |
2337 | } | |
57bf2736 BL |
2338 | |
2339 | switch (rt5645->codec_type) { | |
2340 | case CODEC_TYPE_RT5650: | |
2341 | dl_sft = 4; | |
2342 | break; | |
2343 | default: | |
2344 | dl_sft = 2; | |
2345 | break; | |
2346 | } | |
2347 | ||
1319b2f6 OC |
2348 | bclk_ms = frame_size > 32; |
2349 | rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms); | |
2350 | ||
2351 | dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", | |
2352 | rt5645->bclk[dai->id], rt5645->lrck[dai->id]); | |
2353 | dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", | |
2354 | bclk_ms, pre_div, dai->id); | |
2355 | ||
2356 | switch (params_width(params)) { | |
2357 | case 16: | |
2358 | break; | |
2359 | case 20: | |
57bf2736 | 2360 | val_len = 0x1; |
1319b2f6 OC |
2361 | break; |
2362 | case 24: | |
57bf2736 | 2363 | val_len = 0x2; |
1319b2f6 OC |
2364 | break; |
2365 | case 8: | |
57bf2736 | 2366 | val_len = 0x3; |
1319b2f6 OC |
2367 | break; |
2368 | default: | |
2369 | return -EINVAL; | |
2370 | } | |
2371 | ||
2372 | switch (dai->id) { | |
2373 | case RT5645_AIF1: | |
33de3d54 BL |
2374 | mask_clk = RT5645_I2S_PD1_MASK; |
2375 | val_clk = pre_div << RT5645_I2S_PD1_SFT; | |
1319b2f6 | 2376 | snd_soc_update_bits(codec, RT5645_I2S1_SDP, |
57bf2736 | 2377 | (0x3 << dl_sft), (val_len << dl_sft)); |
1319b2f6 OC |
2378 | snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk); |
2379 | break; | |
2380 | case RT5645_AIF2: | |
2381 | mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK; | |
2382 | val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT | | |
2383 | pre_div << RT5645_I2S_PD2_SFT; | |
2384 | snd_soc_update_bits(codec, RT5645_I2S2_SDP, | |
57bf2736 | 2385 | (0x3 << dl_sft), (val_len << dl_sft)); |
1319b2f6 OC |
2386 | snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk); |
2387 | break; | |
2388 | default: | |
2389 | dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id); | |
2390 | return -EINVAL; | |
2391 | } | |
2392 | ||
2393 | return 0; | |
2394 | } | |
2395 | ||
2396 | static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
2397 | { | |
2398 | struct snd_soc_codec *codec = dai->codec; | |
2399 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); | |
57bf2736 BL |
2400 | unsigned int reg_val = 0, pol_sft; |
2401 | ||
2402 | switch (rt5645->codec_type) { | |
2403 | case CODEC_TYPE_RT5650: | |
2404 | pol_sft = 8; | |
2405 | break; | |
2406 | default: | |
2407 | pol_sft = 7; | |
2408 | break; | |
2409 | } | |
1319b2f6 OC |
2410 | |
2411 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
2412 | case SND_SOC_DAIFMT_CBM_CFM: | |
2413 | rt5645->master[dai->id] = 1; | |
2414 | break; | |
2415 | case SND_SOC_DAIFMT_CBS_CFS: | |
2416 | reg_val |= RT5645_I2S_MS_S; | |
2417 | rt5645->master[dai->id] = 0; | |
2418 | break; | |
2419 | default: | |
2420 | return -EINVAL; | |
2421 | } | |
2422 | ||
2423 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
2424 | case SND_SOC_DAIFMT_NB_NF: | |
2425 | break; | |
2426 | case SND_SOC_DAIFMT_IB_NF: | |
57bf2736 | 2427 | reg_val |= (1 << pol_sft); |
1319b2f6 OC |
2428 | break; |
2429 | default: | |
2430 | return -EINVAL; | |
2431 | } | |
2432 | ||
2433 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
2434 | case SND_SOC_DAIFMT_I2S: | |
2435 | break; | |
2436 | case SND_SOC_DAIFMT_LEFT_J: | |
2437 | reg_val |= RT5645_I2S_DF_LEFT; | |
2438 | break; | |
2439 | case SND_SOC_DAIFMT_DSP_A: | |
2440 | reg_val |= RT5645_I2S_DF_PCM_A; | |
2441 | break; | |
2442 | case SND_SOC_DAIFMT_DSP_B: | |
2443 | reg_val |= RT5645_I2S_DF_PCM_B; | |
2444 | break; | |
2445 | default: | |
2446 | return -EINVAL; | |
2447 | } | |
2448 | switch (dai->id) { | |
2449 | case RT5645_AIF1: | |
2450 | snd_soc_update_bits(codec, RT5645_I2S1_SDP, | |
57bf2736 | 2451 | RT5645_I2S_MS_MASK | (1 << pol_sft) | |
1319b2f6 OC |
2452 | RT5645_I2S_DF_MASK, reg_val); |
2453 | break; | |
8c325704 AL |
2454 | case RT5645_AIF2: |
2455 | snd_soc_update_bits(codec, RT5645_I2S2_SDP, | |
57bf2736 | 2456 | RT5645_I2S_MS_MASK | (1 << pol_sft) | |
1319b2f6 OC |
2457 | RT5645_I2S_DF_MASK, reg_val); |
2458 | break; | |
2459 | default: | |
2460 | dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id); | |
2461 | return -EINVAL; | |
2462 | } | |
2463 | return 0; | |
2464 | } | |
2465 | ||
2466 | static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai, | |
2467 | int clk_id, unsigned int freq, int dir) | |
2468 | { | |
2469 | struct snd_soc_codec *codec = dai->codec; | |
2470 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); | |
2471 | unsigned int reg_val = 0; | |
2472 | ||
2473 | if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src) | |
2474 | return 0; | |
2475 | ||
2476 | switch (clk_id) { | |
2477 | case RT5645_SCLK_S_MCLK: | |
2478 | reg_val |= RT5645_SCLK_SRC_MCLK; | |
2479 | break; | |
2480 | case RT5645_SCLK_S_PLL1: | |
2481 | reg_val |= RT5645_SCLK_SRC_PLL1; | |
2482 | break; | |
2483 | case RT5645_SCLK_S_RCCLK: | |
2484 | reg_val |= RT5645_SCLK_SRC_RCCLK; | |
2485 | break; | |
2486 | default: | |
2487 | dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id); | |
2488 | return -EINVAL; | |
2489 | } | |
2490 | snd_soc_update_bits(codec, RT5645_GLB_CLK, | |
2491 | RT5645_SCLK_SRC_MASK, reg_val); | |
2492 | rt5645->sysclk = freq; | |
2493 | rt5645->sysclk_src = clk_id; | |
2494 | ||
2495 | dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); | |
2496 | ||
2497 | return 0; | |
2498 | } | |
2499 | ||
1319b2f6 OC |
2500 | static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, |
2501 | unsigned int freq_in, unsigned int freq_out) | |
2502 | { | |
2503 | struct snd_soc_codec *codec = dai->codec; | |
2504 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); | |
71c7a2d6 | 2505 | struct rl6231_pll_code pll_code; |
1319b2f6 OC |
2506 | int ret; |
2507 | ||
2508 | if (source == rt5645->pll_src && freq_in == rt5645->pll_in && | |
2509 | freq_out == rt5645->pll_out) | |
2510 | return 0; | |
2511 | ||
2512 | if (!freq_in || !freq_out) { | |
2513 | dev_dbg(codec->dev, "PLL disabled\n"); | |
2514 | ||
2515 | rt5645->pll_in = 0; | |
2516 | rt5645->pll_out = 0; | |
2517 | snd_soc_update_bits(codec, RT5645_GLB_CLK, | |
2518 | RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK); | |
2519 | return 0; | |
2520 | } | |
2521 | ||
2522 | switch (source) { | |
2523 | case RT5645_PLL1_S_MCLK: | |
2524 | snd_soc_update_bits(codec, RT5645_GLB_CLK, | |
2525 | RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK); | |
2526 | break; | |
2527 | case RT5645_PLL1_S_BCLK1: | |
2528 | case RT5645_PLL1_S_BCLK2: | |
2529 | switch (dai->id) { | |
2530 | case RT5645_AIF1: | |
2531 | snd_soc_update_bits(codec, RT5645_GLB_CLK, | |
2532 | RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1); | |
2533 | break; | |
2534 | case RT5645_AIF2: | |
2535 | snd_soc_update_bits(codec, RT5645_GLB_CLK, | |
2536 | RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2); | |
2537 | break; | |
2538 | default: | |
2539 | dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id); | |
2540 | return -EINVAL; | |
2541 | } | |
2542 | break; | |
2543 | default: | |
2544 | dev_err(codec->dev, "Unknown PLL source %d\n", source); | |
2545 | return -EINVAL; | |
2546 | } | |
2547 | ||
71c7a2d6 | 2548 | ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); |
1319b2f6 OC |
2549 | if (ret < 0) { |
2550 | dev_err(codec->dev, "Unsupport input clock %d\n", freq_in); | |
2551 | return ret; | |
2552 | } | |
2553 | ||
2554 | dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n", | |
2555 | pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), | |
2556 | pll_code.n_code, pll_code.k_code); | |
2557 | ||
2558 | snd_soc_write(codec, RT5645_PLL_CTRL1, | |
2559 | pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code); | |
2560 | snd_soc_write(codec, RT5645_PLL_CTRL2, | |
2561 | (pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT | | |
2562 | pll_code.m_bp << RT5645_PLL_M_BP_SFT); | |
2563 | ||
2564 | rt5645->pll_in = freq_in; | |
2565 | rt5645->pll_out = freq_out; | |
2566 | rt5645->pll_src = source; | |
2567 | ||
2568 | return 0; | |
2569 | } | |
2570 | ||
2571 | static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, | |
2572 | unsigned int rx_mask, int slots, int slot_width) | |
2573 | { | |
2574 | struct snd_soc_codec *codec = dai->codec; | |
42ce5b8a BL |
2575 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); |
2576 | unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft; | |
2577 | unsigned int mask, val = 0; | |
2578 | ||
2579 | switch (rt5645->codec_type) { | |
2580 | case CODEC_TYPE_RT5650: | |
2581 | en_sft = 15; | |
2582 | i_slot_sft = 10; | |
2583 | o_slot_sft = 8; | |
2584 | i_width_sht = 6; | |
2585 | o_width_sht = 4; | |
2586 | mask = 0x8ff0; | |
2587 | break; | |
2588 | default: | |
2589 | en_sft = 14; | |
2590 | i_slot_sft = o_slot_sft = 12; | |
2591 | i_width_sht = o_width_sht = 10; | |
2592 | mask = 0x7c00; | |
2593 | break; | |
2594 | } | |
850577db | 2595 | if (rx_mask || tx_mask) { |
42ce5b8a BL |
2596 | val |= (1 << en_sft); |
2597 | if (rt5645->codec_type == CODEC_TYPE_RT5645) | |
2598 | snd_soc_update_bits(codec, RT5645_BASS_BACK, | |
2599 | RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB); | |
850577db | 2600 | } |
1319b2f6 OC |
2601 | |
2602 | switch (slots) { | |
2603 | case 4: | |
42ce5b8a | 2604 | val |= (1 << i_slot_sft) | (1 << o_slot_sft); |
1319b2f6 OC |
2605 | break; |
2606 | case 6: | |
42ce5b8a | 2607 | val |= (2 << i_slot_sft) | (2 << o_slot_sft); |
1319b2f6 OC |
2608 | break; |
2609 | case 8: | |
42ce5b8a | 2610 | val |= (3 << i_slot_sft) | (3 << o_slot_sft); |
1319b2f6 OC |
2611 | break; |
2612 | case 2: | |
2613 | default: | |
2614 | break; | |
2615 | } | |
2616 | ||
2617 | switch (slot_width) { | |
2618 | case 20: | |
42ce5b8a | 2619 | val |= (1 << i_width_sht) | (1 << o_width_sht); |
1319b2f6 OC |
2620 | break; |
2621 | case 24: | |
42ce5b8a | 2622 | val |= (2 << i_width_sht) | (2 << o_width_sht); |
1319b2f6 OC |
2623 | break; |
2624 | case 32: | |
42ce5b8a | 2625 | val |= (3 << i_width_sht) | (3 << o_width_sht); |
1319b2f6 OC |
2626 | break; |
2627 | case 16: | |
2628 | default: | |
2629 | break; | |
2630 | } | |
2631 | ||
42ce5b8a | 2632 | snd_soc_update_bits(codec, RT5645_TDM_CTRL_1, mask, val); |
1319b2f6 OC |
2633 | |
2634 | return 0; | |
2635 | } | |
2636 | ||
2637 | static int rt5645_set_bias_level(struct snd_soc_codec *codec, | |
2638 | enum snd_soc_bias_level level) | |
2639 | { | |
6e747d53 BL |
2640 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); |
2641 | ||
1319b2f6 | 2642 | switch (level) { |
0b2e4959 BL |
2643 | case SND_SOC_BIAS_PREPARE: |
2644 | if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) { | |
1319b2f6 OC |
2645 | snd_soc_update_bits(codec, RT5645_PWR_ANLG1, |
2646 | RT5645_PWR_VREF1 | RT5645_PWR_MB | | |
2647 | RT5645_PWR_BG | RT5645_PWR_VREF2, | |
2648 | RT5645_PWR_VREF1 | RT5645_PWR_MB | | |
2649 | RT5645_PWR_BG | RT5645_PWR_VREF2); | |
2650 | mdelay(10); | |
2651 | snd_soc_update_bits(codec, RT5645_PWR_ANLG1, | |
2652 | RT5645_PWR_FV1 | RT5645_PWR_FV2, | |
2653 | RT5645_PWR_FV1 | RT5645_PWR_FV2); | |
2654 | snd_soc_update_bits(codec, RT5645_GEN_CTRL1, | |
2655 | RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL); | |
2656 | } | |
2657 | break; | |
2658 | ||
0b2e4959 BL |
2659 | case SND_SOC_BIAS_STANDBY: |
2660 | snd_soc_update_bits(codec, RT5645_PWR_ANLG1, | |
2661 | RT5645_PWR_VREF1 | RT5645_PWR_MB | | |
2662 | RT5645_PWR_BG | RT5645_PWR_VREF2, | |
2663 | RT5645_PWR_VREF1 | RT5645_PWR_MB | | |
2664 | RT5645_PWR_BG | RT5645_PWR_VREF2); | |
2665 | snd_soc_update_bits(codec, RT5645_PWR_ANLG1, | |
2666 | RT5645_PWR_FV1 | RT5645_PWR_FV2, | |
2667 | RT5645_PWR_FV1 | RT5645_PWR_FV2); | |
2668 | break; | |
2669 | ||
1319b2f6 OC |
2670 | case SND_SOC_BIAS_OFF: |
2671 | snd_soc_write(codec, RT5645_DEPOP_M2, 0x1100); | |
6e747d53 BL |
2672 | if (!rt5645->en_button_func) |
2673 | snd_soc_update_bits(codec, RT5645_GEN_CTRL1, | |
2674 | RT5645_DIG_GATE_CTRL, 0); | |
0b2e4959 BL |
2675 | snd_soc_update_bits(codec, RT5645_PWR_ANLG1, |
2676 | RT5645_PWR_VREF1 | RT5645_PWR_MB | | |
2677 | RT5645_PWR_BG | RT5645_PWR_VREF2 | | |
2678 | RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0); | |
1319b2f6 OC |
2679 | break; |
2680 | ||
2681 | default: | |
2682 | break; | |
2683 | } | |
1319b2f6 OC |
2684 | |
2685 | return 0; | |
2686 | } | |
2687 | ||
d12d6c4e JL |
2688 | static int rt5650_calibration(struct rt5645_priv *rt5645) |
2689 | { | |
2690 | int val, i; | |
2691 | int ret = -1; | |
2692 | ||
2693 | regcache_cache_bypass(rt5645->regmap, true); | |
2694 | regmap_write(rt5645->regmap, RT5645_RESET, 0); | |
2695 | regmap_write(rt5645->regmap, RT5645_GEN_CTRL3, 0x0800); | |
2696 | regmap_write(rt5645->regmap, RT5645_PR_BASE + RT5645_CHOP_DAC_ADC, | |
2697 | 0x3600); | |
2698 | regmap_write(rt5645->regmap, RT5645_PR_BASE + 0x25, 0x7000); | |
2699 | regmap_write(rt5645->regmap, RT5645_I2S1_SDP, 0x8008); | |
2700 | /* headset type */ | |
2701 | regmap_write(rt5645->regmap, RT5645_GEN_CTRL1, 0x2061); | |
2702 | regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0006); | |
2703 | regmap_write(rt5645->regmap, RT5645_PWR_ANLG1, 0x2012); | |
2704 | regmap_write(rt5645->regmap, RT5645_PWR_MIXER, 0x0002); | |
2705 | regmap_write(rt5645->regmap, RT5645_PWR_VOL, 0x0020); | |
2706 | regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0); | |
2707 | regmap_write(rt5645->regmap, RT5645_IN1_CTRL1, 0x0006); | |
2708 | regmap_write(rt5645->regmap, RT5645_IN1_CTRL2, 0x1827); | |
2709 | regmap_write(rt5645->regmap, RT5645_IN1_CTRL2, 0x0827); | |
2710 | msleep(400); | |
2711 | /* Inline command */ | |
2712 | regmap_write(rt5645->regmap, RT5645_DEPOP_M1, 0x0001); | |
2713 | regmap_write(rt5645->regmap, RT5650_4BTN_IL_CMD2, 0xc000); | |
2714 | regmap_write(rt5645->regmap, RT5650_4BTN_IL_CMD1, 0x0008); | |
2715 | /* Calbration */ | |
2716 | regmap_write(rt5645->regmap, RT5645_GLB_CLK, 0x8000); | |
2717 | regmap_write(rt5645->regmap, RT5645_DEPOP_M1, 0x0000); | |
2718 | regmap_write(rt5645->regmap, RT5650_4BTN_IL_CMD2, 0xc000); | |
2719 | regmap_write(rt5645->regmap, RT5650_4BTN_IL_CMD1, 0x0008); | |
2720 | regmap_write(rt5645->regmap, RT5645_PWR_DIG2, 0x8800); | |
2721 | regmap_write(rt5645->regmap, RT5645_PWR_ANLG1, 0xe8fa); | |
2722 | regmap_write(rt5645->regmap, RT5645_PWR_ANLG2, 0x8c04); | |
2723 | regmap_write(rt5645->regmap, RT5645_DEPOP_M2, 0x3100); | |
2724 | regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0e06); | |
2725 | regmap_write(rt5645->regmap, RT5645_BASS_BACK, 0x8a13); | |
2726 | regmap_write(rt5645->regmap, RT5645_GEN_CTRL3, 0x0820); | |
2727 | regmap_write(rt5645->regmap, RT5645_DEPOP_M1, 0x000d); | |
2728 | /* Power on and Calbration */ | |
2729 | regmap_write(rt5645->regmap, RT5645_PR_BASE + RT5645_HP_DCC_INT1, | |
2730 | 0x9f01); | |
2731 | msleep(200); | |
2732 | for (i = 0; i < 5; i++) { | |
2733 | regmap_read(rt5645->regmap, RT5645_PR_BASE + 0x7a, &val); | |
2734 | if (val != 0 && val != 0x3f3f) { | |
2735 | ret = 0; | |
2736 | break; | |
2737 | } | |
2738 | msleep(50); | |
2739 | } | |
2740 | pr_debug("%s: PR-7A = 0x%x\n", __func__, val); | |
2741 | ||
2742 | /* mute */ | |
2743 | regmap_write(rt5645->regmap, RT5645_PR_BASE + 0x3e, 0x7400); | |
2744 | regmap_write(rt5645->regmap, RT5645_DEPOP_M3, 0x0737); | |
2745 | regmap_write(rt5645->regmap, RT5645_PR_BASE + RT5645_MAMP_INT_REG2, | |
2746 | 0xfc00); | |
2747 | regmap_write(rt5645->regmap, RT5645_DEPOP_M2, 0x1140); | |
2748 | regmap_write(rt5645->regmap, RT5645_DEPOP_M1, 0x0000); | |
2749 | regmap_write(rt5645->regmap, RT5645_GEN_CTRL2, 0x4020); | |
2750 | regmap_write(rt5645->regmap, RT5645_PWR_ANLG2, 0x0006); | |
2751 | regmap_write(rt5645->regmap, RT5645_PWR_DIG2, 0x0000); | |
2752 | msleep(350); | |
2753 | ||
2754 | regcache_cache_bypass(rt5645->regmap, false); | |
2755 | ||
2756 | return ret; | |
2757 | } | |
2758 | ||
6e747d53 BL |
2759 | static void rt5645_enable_push_button_irq(struct snd_soc_codec *codec, |
2760 | bool enable) | |
f3fa1bbd OC |
2761 | { |
2762 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); | |
f3fa1bbd | 2763 | |
6e747d53 | 2764 | if (enable) { |
22f5d9f8 | 2765 | snd_soc_dapm_mutex_lock(&codec->dapm); |
6e747d53 BL |
2766 | snd_soc_dapm_force_enable_pin_unlocked(&codec->dapm, |
2767 | "ADC L power"); | |
2768 | snd_soc_dapm_force_enable_pin_unlocked(&codec->dapm, | |
2769 | "ADC R power"); | |
2770 | snd_soc_dapm_force_enable_pin_unlocked(&codec->dapm, | |
2771 | "LDO2"); | |
2772 | snd_soc_dapm_force_enable_pin_unlocked(&codec->dapm, | |
2773 | "Mic Det Power"); | |
2774 | snd_soc_dapm_sync_unlocked(&codec->dapm); | |
22f5d9f8 NB |
2775 | snd_soc_dapm_mutex_unlock(&codec->dapm); |
2776 | ||
6e747d53 BL |
2777 | snd_soc_update_bits(codec, |
2778 | RT5645_INT_IRQ_ST, 0x8, 0x8); | |
2779 | snd_soc_update_bits(codec, | |
2780 | RT5650_4BTN_IL_CMD2, 0x8000, 0x8000); | |
2781 | snd_soc_read(codec, RT5650_4BTN_IL_CMD1); | |
2782 | pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1, | |
2783 | snd_soc_read(codec, RT5650_4BTN_IL_CMD1)); | |
2784 | } else { | |
2785 | snd_soc_update_bits(codec, RT5650_4BTN_IL_CMD2, 0x8000, 0x0); | |
2786 | snd_soc_update_bits(codec, RT5645_INT_IRQ_ST, 0x8, 0x0); | |
22f5d9f8 NB |
2787 | |
2788 | snd_soc_dapm_mutex_lock(&codec->dapm); | |
6e747d53 BL |
2789 | snd_soc_dapm_disable_pin_unlocked(&codec->dapm, |
2790 | "ADC L power"); | |
2791 | snd_soc_dapm_disable_pin_unlocked(&codec->dapm, | |
2792 | "ADC R power"); | |
2793 | if (rt5645->pdata.jd_mode == 0) | |
2794 | snd_soc_dapm_disable_pin_unlocked(&codec->dapm, | |
2795 | "LDO2"); | |
2796 | snd_soc_dapm_disable_pin_unlocked(&codec->dapm, | |
2797 | "Mic Det Power"); | |
2798 | snd_soc_dapm_sync_unlocked(&codec->dapm); | |
22f5d9f8 | 2799 | snd_soc_dapm_mutex_unlock(&codec->dapm); |
75945896 | 2800 | } |
6e747d53 | 2801 | } |
f3fa1bbd | 2802 | |
6e747d53 BL |
2803 | static int rt5645_jack_detect(struct snd_soc_codec *codec, int jack_insert) |
2804 | { | |
2805 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); | |
2806 | unsigned int val; | |
f3fa1bbd | 2807 | |
6e747d53 | 2808 | if (jack_insert) { |
05a9b46a JL |
2809 | regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0006); |
2810 | ||
6e747d53 | 2811 | if (codec->component.card->instantiated) { |
05a9b46a JL |
2812 | /* for jack type detect */ |
2813 | snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2"); | |
6e747d53 BL |
2814 | snd_soc_dapm_force_enable_pin(&codec->dapm, |
2815 | "Mic Det Power"); | |
2816 | snd_soc_dapm_sync(&codec->dapm); | |
2817 | } else { | |
2818 | /* Power up necessary bits for JD if dapm is | |
2819 | not ready yet */ | |
05a9b46a JL |
2820 | regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1, |
2821 | RT5645_PWR_MB | RT5645_PWR_VREF2, | |
2822 | RT5645_PWR_MB | RT5645_PWR_VREF2); | |
2823 | regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER, | |
6e747d53 | 2824 | RT5645_PWR_LDO2, RT5645_PWR_LDO2); |
05a9b46a | 2825 | regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL, |
6e747d53 BL |
2826 | RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET); |
2827 | } | |
f3fa1bbd | 2828 | |
05a9b46a JL |
2829 | regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0); |
2830 | regmap_write(rt5645->regmap, RT5645_IN1_CTRL1, 0x0006); | |
2831 | regmap_update_bits(rt5645->regmap, | |
2832 | RT5645_IN1_CTRL2, 0x1000, 0x1000); | |
2833 | msleep(100); | |
2834 | regmap_update_bits(rt5645->regmap, | |
2835 | RT5645_IN1_CTRL2, 0x1000, 0x0000); | |
2836 | ||
2837 | msleep(450); | |
2838 | regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val); | |
2839 | val &= 0x7; | |
f3fa1bbd OC |
2840 | dev_dbg(codec->dev, "val = %d\n", val); |
2841 | ||
6e747d53 BL |
2842 | if (val == 1 || val == 2) { |
2843 | rt5645->jack_type = SND_JACK_HEADSET; | |
2844 | if (rt5645->en_button_func) { | |
6e747d53 BL |
2845 | rt5645_enable_push_button_irq(codec, true); |
2846 | } | |
2847 | } else { | |
b7f22478 JL |
2848 | if (codec->component.card->instantiated) { |
2849 | snd_soc_dapm_disable_pin(&codec->dapm, | |
2850 | "Mic Det Power"); | |
2851 | snd_soc_dapm_sync(&codec->dapm); | |
2852 | } else | |
2853 | regmap_update_bits(rt5645->regmap, | |
2854 | RT5645_PWR_VOL, RT5645_PWR_MIC_DET, 0); | |
6e747d53 BL |
2855 | rt5645->jack_type = SND_JACK_HEADPHONE; |
2856 | } | |
2857 | ||
2858 | } else { /* jack out */ | |
2859 | rt5645->jack_type = 0; | |
2860 | if (rt5645->en_button_func) | |
2861 | rt5645_enable_push_button_irq(codec, false); | |
b7f22478 JL |
2862 | else { |
2863 | if (codec->component.card->instantiated) { | |
2864 | if (rt5645->pdata.jd_mode == 0) | |
2865 | snd_soc_dapm_disable_pin(&codec->dapm, | |
2866 | "LDO2"); | |
2867 | snd_soc_dapm_disable_pin(&codec->dapm, | |
2868 | "Mic Det Power"); | |
2869 | snd_soc_dapm_sync(&codec->dapm); | |
2870 | } else { | |
2871 | if (rt5645->pdata.jd_mode == 0) | |
2872 | regmap_update_bits(rt5645->regmap, | |
2873 | RT5645_PWR_MIXER, | |
2874 | RT5645_PWR_LDO2, 0); | |
2875 | regmap_update_bits(rt5645->regmap, | |
2876 | RT5645_PWR_VOL, RT5645_PWR_MIC_DET, 0); | |
2877 | } | |
2878 | } | |
f3fa1bbd OC |
2879 | } |
2880 | ||
6e747d53 | 2881 | return rt5645->jack_type; |
f3fa1bbd OC |
2882 | } |
2883 | ||
d5660422 | 2884 | static int rt5645_irq_detection(struct rt5645_priv *rt5645); |
345b0f50 | 2885 | static irqreturn_t rt5645_irq(int irq, void *data); |
d5660422 | 2886 | |
f3fa1bbd | 2887 | int rt5645_set_jack_detect(struct snd_soc_codec *codec, |
6e747d53 BL |
2888 | struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack, |
2889 | struct snd_soc_jack *btn_jack) | |
f3fa1bbd OC |
2890 | { |
2891 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); | |
2892 | ||
471f208a BL |
2893 | rt5645->hp_jack = hp_jack; |
2894 | rt5645->mic_jack = mic_jack; | |
6e747d53 BL |
2895 | rt5645->btn_jack = btn_jack; |
2896 | if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) { | |
2897 | rt5645->en_button_func = true; | |
2898 | regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, | |
2899 | RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ); | |
2900 | regmap_update_bits(rt5645->regmap, RT5645_DEPOP_M1, | |
2901 | RT5645_HP_CB_MASK, RT5645_HP_CB_PU); | |
2902 | regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1, | |
2903 | RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL); | |
2904 | } | |
345b0f50 | 2905 | rt5645_irq(0, rt5645); |
f3fa1bbd OC |
2906 | |
2907 | return 0; | |
2908 | } | |
2909 | EXPORT_SYMBOL_GPL(rt5645_set_jack_detect); | |
2910 | ||
cd6e82b8 OC |
2911 | static void rt5645_jack_detect_work(struct work_struct *work) |
2912 | { | |
2913 | struct rt5645_priv *rt5645 = | |
2914 | container_of(work, struct rt5645_priv, jack_detect_work.work); | |
2915 | ||
6e747d53 | 2916 | rt5645_irq_detection(rt5645); |
cd6e82b8 OC |
2917 | } |
2918 | ||
f3fa1bbd OC |
2919 | static irqreturn_t rt5645_irq(int irq, void *data) |
2920 | { | |
2921 | struct rt5645_priv *rt5645 = data; | |
2922 | ||
cd6e82b8 OC |
2923 | queue_delayed_work(system_power_efficient_wq, |
2924 | &rt5645->jack_detect_work, msecs_to_jiffies(250)); | |
f3fa1bbd OC |
2925 | |
2926 | return IRQ_HANDLED; | |
2927 | } | |
2928 | ||
6e747d53 BL |
2929 | static int rt5645_button_detect(struct snd_soc_codec *codec) |
2930 | { | |
2931 | int btn_type, val; | |
2932 | ||
2933 | val = snd_soc_read(codec, RT5650_4BTN_IL_CMD1); | |
2934 | pr_debug("val=0x%x\n", val); | |
2935 | btn_type = val & 0xfff0; | |
2936 | snd_soc_write(codec, RT5650_4BTN_IL_CMD1, val); | |
2937 | ||
2938 | return btn_type; | |
2939 | } | |
2940 | ||
2941 | static int rt5645_irq_detection(struct rt5645_priv *rt5645) | |
2942 | { | |
2943 | int val, btn_type, gpio_state = 0, report = 0; | |
2944 | ||
2945 | switch (rt5645->pdata.jd_mode) { | |
2946 | case 0: /* Not using rt5645 JD */ | |
0b0cefc8 OC |
2947 | if (rt5645->gpiod_hp_det) { |
2948 | gpio_state = gpiod_get_value(rt5645->gpiod_hp_det); | |
2949 | dev_dbg(rt5645->codec->dev, "gpio_state = %d\n", | |
2950 | gpio_state); | |
2951 | report = rt5645_jack_detect(rt5645->codec, gpio_state); | |
6e747d53 BL |
2952 | } |
2953 | snd_soc_jack_report(rt5645->hp_jack, | |
2954 | report, SND_JACK_HEADPHONE); | |
2955 | snd_soc_jack_report(rt5645->mic_jack, | |
2956 | report, SND_JACK_MICROPHONE); | |
2957 | return report; | |
2958 | case 1: /* 2 port */ | |
2959 | val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0070; | |
2960 | break; | |
2961 | default: /* 1 port */ | |
2962 | val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0020; | |
2963 | break; | |
2964 | ||
2965 | } | |
2966 | ||
2967 | switch (val) { | |
2968 | /* jack in */ | |
2969 | case 0x30: /* 2 port */ | |
2970 | case 0x0: /* 1 port or 2 port */ | |
2971 | if (rt5645->jack_type == 0) { | |
2972 | report = rt5645_jack_detect(rt5645->codec, 1); | |
2973 | /* for push button and jack out */ | |
2974 | break; | |
2975 | } | |
2976 | btn_type = 0; | |
2977 | if (snd_soc_read(rt5645->codec, RT5645_INT_IRQ_ST) & 0x4) { | |
2978 | /* button pressed */ | |
2979 | report = SND_JACK_HEADSET; | |
2980 | btn_type = rt5645_button_detect(rt5645->codec); | |
2981 | /* rt5650 can report three kinds of button behavior, | |
2982 | one click, double click and hold. However, | |
2983 | currently we will report button pressed/released | |
2984 | event. So all the three button behaviors are | |
2985 | treated as button pressed. */ | |
2986 | switch (btn_type) { | |
2987 | case 0x8000: | |
2988 | case 0x4000: | |
2989 | case 0x2000: | |
2990 | report |= SND_JACK_BTN_0; | |
2991 | break; | |
2992 | case 0x1000: | |
2993 | case 0x0800: | |
2994 | case 0x0400: | |
2995 | report |= SND_JACK_BTN_1; | |
2996 | break; | |
2997 | case 0x0200: | |
2998 | case 0x0100: | |
2999 | case 0x0080: | |
3000 | report |= SND_JACK_BTN_2; | |
3001 | break; | |
3002 | case 0x0040: | |
3003 | case 0x0020: | |
3004 | case 0x0010: | |
3005 | report |= SND_JACK_BTN_3; | |
3006 | break; | |
3007 | case 0x0000: /* unpressed */ | |
3008 | break; | |
3009 | default: | |
3010 | dev_err(rt5645->codec->dev, | |
3011 | "Unexpected button code 0x%04x\n", | |
3012 | btn_type); | |
3013 | break; | |
3014 | } | |
3015 | } | |
3016 | if (btn_type == 0)/* button release */ | |
3017 | report = rt5645->jack_type; | |
3018 | ||
3019 | break; | |
3020 | /* jack out */ | |
3021 | case 0x70: /* 2 port */ | |
3022 | case 0x10: /* 2 port */ | |
3023 | case 0x20: /* 1 port */ | |
3024 | report = 0; | |
3025 | snd_soc_update_bits(rt5645->codec, | |
3026 | RT5645_INT_IRQ_ST, 0x1, 0x0); | |
3027 | rt5645_jack_detect(rt5645->codec, 0); | |
3028 | break; | |
3029 | default: | |
3030 | break; | |
3031 | } | |
3032 | ||
3033 | snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE); | |
3034 | snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE); | |
3035 | if (rt5645->en_button_func) | |
3036 | snd_soc_jack_report(rt5645->btn_jack, | |
e0b5d906 BL |
3037 | report, SND_JACK_BTN_0 | SND_JACK_BTN_1 | |
3038 | SND_JACK_BTN_2 | SND_JACK_BTN_3); | |
6e747d53 BL |
3039 | |
3040 | return report; | |
3041 | } | |
3042 | ||
1319b2f6 OC |
3043 | static int rt5645_probe(struct snd_soc_codec *codec) |
3044 | { | |
3045 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); | |
3046 | ||
3047 | rt5645->codec = codec; | |
3048 | ||
5c4ca99d BL |
3049 | switch (rt5645->codec_type) { |
3050 | case CODEC_TYPE_RT5645: | |
3051 | snd_soc_dapm_add_routes(&codec->dapm, | |
3052 | rt5645_specific_dapm_routes, | |
3053 | ARRAY_SIZE(rt5645_specific_dapm_routes)); | |
3054 | break; | |
3055 | case CODEC_TYPE_RT5650: | |
3056 | snd_soc_dapm_new_controls(&codec->dapm, | |
3057 | rt5650_specific_dapm_widgets, | |
3058 | ARRAY_SIZE(rt5650_specific_dapm_widgets)); | |
3059 | snd_soc_dapm_add_routes(&codec->dapm, | |
3060 | rt5650_specific_dapm_routes, | |
3061 | ARRAY_SIZE(rt5650_specific_dapm_routes)); | |
3062 | break; | |
3063 | } | |
3064 | ||
bd1204cb | 3065 | snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF); |
1319b2f6 | 3066 | |
bb656add | 3067 | /* for JD function */ |
ac4fc3ee | 3068 | if (rt5645->pdata.jd_mode) { |
bb656add BL |
3069 | snd_soc_dapm_force_enable_pin(&codec->dapm, "JD Power"); |
3070 | snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2"); | |
3071 | snd_soc_dapm_sync(&codec->dapm); | |
3072 | } | |
3073 | ||
1319b2f6 OC |
3074 | return 0; |
3075 | } | |
3076 | ||
3077 | static int rt5645_remove(struct snd_soc_codec *codec) | |
3078 | { | |
3079 | rt5645_reset(codec); | |
3080 | return 0; | |
3081 | } | |
3082 | ||
3083 | #ifdef CONFIG_PM | |
3084 | static int rt5645_suspend(struct snd_soc_codec *codec) | |
3085 | { | |
3086 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); | |
3087 | ||
3088 | regcache_cache_only(rt5645->regmap, true); | |
3089 | regcache_mark_dirty(rt5645->regmap); | |
3090 | ||
3091 | return 0; | |
3092 | } | |
3093 | ||
3094 | static int rt5645_resume(struct snd_soc_codec *codec) | |
3095 | { | |
3096 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); | |
3097 | ||
3098 | regcache_cache_only(rt5645->regmap, false); | |
0f776efd | 3099 | regcache_sync(rt5645->regmap); |
1319b2f6 OC |
3100 | |
3101 | return 0; | |
3102 | } | |
3103 | #else | |
3104 | #define rt5645_suspend NULL | |
3105 | #define rt5645_resume NULL | |
3106 | #endif | |
3107 | ||
3108 | #define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000 | |
3109 | #define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
3110 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) | |
3111 | ||
9e22f782 | 3112 | static struct snd_soc_dai_ops rt5645_aif_dai_ops = { |
1319b2f6 OC |
3113 | .hw_params = rt5645_hw_params, |
3114 | .set_fmt = rt5645_set_dai_fmt, | |
3115 | .set_sysclk = rt5645_set_dai_sysclk, | |
3116 | .set_tdm_slot = rt5645_set_tdm_slot, | |
3117 | .set_pll = rt5645_set_dai_pll, | |
3118 | }; | |
3119 | ||
9e22f782 | 3120 | static struct snd_soc_dai_driver rt5645_dai[] = { |
1319b2f6 OC |
3121 | { |
3122 | .name = "rt5645-aif1", | |
3123 | .id = RT5645_AIF1, | |
3124 | .playback = { | |
3125 | .stream_name = "AIF1 Playback", | |
3126 | .channels_min = 1, | |
3127 | .channels_max = 2, | |
3128 | .rates = RT5645_STEREO_RATES, | |
3129 | .formats = RT5645_FORMATS, | |
3130 | }, | |
3131 | .capture = { | |
3132 | .stream_name = "AIF1 Capture", | |
3133 | .channels_min = 1, | |
3134 | .channels_max = 2, | |
3135 | .rates = RT5645_STEREO_RATES, | |
3136 | .formats = RT5645_FORMATS, | |
3137 | }, | |
3138 | .ops = &rt5645_aif_dai_ops, | |
3139 | }, | |
3140 | { | |
3141 | .name = "rt5645-aif2", | |
3142 | .id = RT5645_AIF2, | |
3143 | .playback = { | |
3144 | .stream_name = "AIF2 Playback", | |
3145 | .channels_min = 1, | |
3146 | .channels_max = 2, | |
3147 | .rates = RT5645_STEREO_RATES, | |
3148 | .formats = RT5645_FORMATS, | |
3149 | }, | |
3150 | .capture = { | |
3151 | .stream_name = "AIF2 Capture", | |
3152 | .channels_min = 1, | |
3153 | .channels_max = 2, | |
3154 | .rates = RT5645_STEREO_RATES, | |
3155 | .formats = RT5645_FORMATS, | |
3156 | }, | |
3157 | .ops = &rt5645_aif_dai_ops, | |
3158 | }, | |
3159 | }; | |
3160 | ||
3161 | static struct snd_soc_codec_driver soc_codec_dev_rt5645 = { | |
3162 | .probe = rt5645_probe, | |
3163 | .remove = rt5645_remove, | |
3164 | .suspend = rt5645_suspend, | |
3165 | .resume = rt5645_resume, | |
3166 | .set_bias_level = rt5645_set_bias_level, | |
3167 | .idle_bias_off = true, | |
3168 | .controls = rt5645_snd_controls, | |
3169 | .num_controls = ARRAY_SIZE(rt5645_snd_controls), | |
3170 | .dapm_widgets = rt5645_dapm_widgets, | |
3171 | .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets), | |
3172 | .dapm_routes = rt5645_dapm_routes, | |
3173 | .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes), | |
3174 | }; | |
3175 | ||
3176 | static const struct regmap_config rt5645_regmap = { | |
3177 | .reg_bits = 8, | |
3178 | .val_bits = 16, | |
afefc128 | 3179 | .use_single_rw = true, |
1319b2f6 OC |
3180 | .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) * |
3181 | RT5645_PR_SPACING), | |
3182 | .volatile_reg = rt5645_volatile_register, | |
3183 | .readable_reg = rt5645_readable_register, | |
3184 | ||
3185 | .cache_type = REGCACHE_RBTREE, | |
3186 | .reg_defaults = rt5645_reg, | |
3187 | .num_reg_defaults = ARRAY_SIZE(rt5645_reg), | |
3188 | .ranges = rt5645_ranges, | |
3189 | .num_ranges = ARRAY_SIZE(rt5645_ranges), | |
3190 | }; | |
3191 | ||
3192 | static const struct i2c_device_id rt5645_i2c_id[] = { | |
3193 | { "rt5645", 0 }, | |
5c4ca99d | 3194 | { "rt5650", 0 }, |
1319b2f6 OC |
3195 | { } |
3196 | }; | |
3197 | MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id); | |
3198 | ||
3168c201 FY |
3199 | #ifdef CONFIG_ACPI |
3200 | static struct acpi_device_id rt5645_acpi_match[] = { | |
3201 | { "10EC5645", 0 }, | |
3202 | { "10EC5650", 0 }, | |
3203 | {}, | |
3204 | }; | |
3205 | MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match); | |
3206 | #endif | |
3207 | ||
78c34fd4 FY |
3208 | static struct rt5645_platform_data *rt5645_pdata; |
3209 | ||
3210 | static struct rt5645_platform_data strago_platform_data = { | |
ac4fc3ee | 3211 | .dmic1_data_pin = RT5645_DMIC1_DISABLE, |
78c34fd4 | 3212 | .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, |
78c34fd4 FY |
3213 | .jd_mode = 3, |
3214 | }; | |
3215 | ||
3216 | static int strago_quirk_cb(const struct dmi_system_id *id) | |
3217 | { | |
3218 | rt5645_pdata = &strago_platform_data; | |
3219 | ||
3220 | return 1; | |
3221 | } | |
3222 | ||
c0d44e59 | 3223 | static struct dmi_system_id dmi_platform_intel_braswell[] = { |
78c34fd4 FY |
3224 | { |
3225 | .ident = "Intel Strago", | |
3226 | .callback = strago_quirk_cb, | |
3227 | .matches = { | |
3228 | DMI_MATCH(DMI_PRODUCT_NAME, "Strago"), | |
3229 | }, | |
3230 | }, | |
3231 | { } | |
3232 | }; | |
3233 | ||
48edaa4b OC |
3234 | static int rt5645_parse_dt(struct rt5645_priv *rt5645, struct device *dev) |
3235 | { | |
3236 | rt5645->pdata.in2_diff = device_property_read_bool(dev, | |
3237 | "realtek,in2-differential"); | |
3238 | device_property_read_u32(dev, | |
3239 | "realtek,dmic1-data-pin", &rt5645->pdata.dmic1_data_pin); | |
3240 | device_property_read_u32(dev, | |
3241 | "realtek,dmic2-data-pin", &rt5645->pdata.dmic2_data_pin); | |
3242 | device_property_read_u32(dev, | |
3243 | "realtek,jd-mode", &rt5645->pdata.jd_mode); | |
3244 | ||
3245 | return 0; | |
3246 | } | |
3247 | ||
1319b2f6 OC |
3248 | static int rt5645_i2c_probe(struct i2c_client *i2c, |
3249 | const struct i2c_device_id *id) | |
3250 | { | |
3251 | struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev); | |
3252 | struct rt5645_priv *rt5645; | |
3253 | int ret; | |
3254 | unsigned int val; | |
3255 | ||
3256 | rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv), | |
3257 | GFP_KERNEL); | |
3258 | if (rt5645 == NULL) | |
3259 | return -ENOMEM; | |
3260 | ||
f3fa1bbd | 3261 | rt5645->i2c = i2c; |
1319b2f6 OC |
3262 | i2c_set_clientdata(i2c, rt5645); |
3263 | ||
48edaa4b | 3264 | if (pdata) |
1319b2f6 | 3265 | rt5645->pdata = *pdata; |
48edaa4b OC |
3266 | else if (dmi_check_system(dmi_platform_intel_braswell)) |
3267 | rt5645->pdata = *rt5645_pdata; | |
3268 | else | |
3269 | rt5645_parse_dt(rt5645, &i2c->dev); | |
1319b2f6 | 3270 | |
25c8888a AL |
3271 | rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect", |
3272 | GPIOD_IN); | |
0b0cefc8 OC |
3273 | |
3274 | if (IS_ERR(rt5645->gpiod_hp_det)) { | |
0b0cefc8 | 3275 | dev_err(&i2c->dev, "failed to initialize gpiod\n"); |
25c8888a | 3276 | return PTR_ERR(rt5645->gpiod_hp_det); |
0b0cefc8 OC |
3277 | } |
3278 | ||
1319b2f6 OC |
3279 | rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap); |
3280 | if (IS_ERR(rt5645->regmap)) { | |
3281 | ret = PTR_ERR(rt5645->regmap); | |
3282 | dev_err(&i2c->dev, "Failed to allocate register map: %d\n", | |
3283 | ret); | |
3284 | return ret; | |
3285 | } | |
3286 | ||
3287 | regmap_read(rt5645->regmap, RT5645_VENDOR_ID2, &val); | |
5c4ca99d BL |
3288 | |
3289 | switch (val) { | |
3290 | case RT5645_DEVICE_ID: | |
3291 | rt5645->codec_type = CODEC_TYPE_RT5645; | |
3292 | break; | |
3293 | case RT5650_DEVICE_ID: | |
3294 | rt5645->codec_type = CODEC_TYPE_RT5650; | |
3295 | break; | |
3296 | default: | |
1319b2f6 | 3297 | dev_err(&i2c->dev, |
5c4ca99d BL |
3298 | "Device with ID register %x is not rt5645 or rt5650\n", |
3299 | val); | |
1319b2f6 OC |
3300 | return -ENODEV; |
3301 | } | |
3302 | ||
d12d6c4e JL |
3303 | if (rt5645->codec_type == CODEC_TYPE_RT5650) { |
3304 | ret = rt5650_calibration(rt5645); | |
3305 | ||
3306 | if (ret < 0) | |
3307 | pr_err("calibration failed!\n"); | |
3308 | } | |
3309 | ||
1319b2f6 OC |
3310 | regmap_write(rt5645->regmap, RT5645_RESET, 0); |
3311 | ||
3312 | ret = regmap_register_patch(rt5645->regmap, init_list, | |
3313 | ARRAY_SIZE(init_list)); | |
3314 | if (ret != 0) | |
3315 | dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); | |
3316 | ||
5c4ca99d BL |
3317 | if (rt5645->codec_type == CODEC_TYPE_RT5650) { |
3318 | ret = regmap_register_patch(rt5645->regmap, rt5650_init_list, | |
3319 | ARRAY_SIZE(rt5650_init_list)); | |
3320 | if (ret != 0) | |
3321 | dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n", | |
3322 | ret); | |
3323 | } | |
3324 | ||
1319b2f6 OC |
3325 | if (rt5645->pdata.in2_diff) |
3326 | regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL, | |
3327 | RT5645_IN_DF2, RT5645_IN_DF2); | |
3328 | ||
ac4fc3ee | 3329 | if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) { |
1319b2f6 OC |
3330 | regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, |
3331 | RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL); | |
ac4fc3ee BL |
3332 | } |
3333 | switch (rt5645->pdata.dmic1_data_pin) { | |
3334 | case RT5645_DMIC_DATA_IN2N: | |
3335 | regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, | |
3336 | RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N); | |
3337 | break; | |
1319b2f6 | 3338 | |
ac4fc3ee BL |
3339 | case RT5645_DMIC_DATA_GPIO5: |
3340 | regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, | |
3341 | RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5); | |
3342 | regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, | |
3343 | RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA); | |
3344 | break; | |
1319b2f6 | 3345 | |
ac4fc3ee BL |
3346 | case RT5645_DMIC_DATA_GPIO11: |
3347 | regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, | |
3348 | RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11); | |
3349 | regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, | |
3350 | RT5645_GP11_PIN_MASK, | |
3351 | RT5645_GP11_PIN_DMIC1_SDA); | |
3352 | break; | |
1319b2f6 | 3353 | |
ac4fc3ee BL |
3354 | default: |
3355 | break; | |
3356 | } | |
1319b2f6 | 3357 | |
ac4fc3ee BL |
3358 | switch (rt5645->pdata.dmic2_data_pin) { |
3359 | case RT5645_DMIC_DATA_IN2P: | |
3360 | regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, | |
3361 | RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P); | |
3362 | break; | |
1319b2f6 | 3363 | |
ac4fc3ee BL |
3364 | case RT5645_DMIC_DATA_GPIO6: |
3365 | regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, | |
3366 | RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6); | |
3367 | regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, | |
3368 | RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA); | |
3369 | break; | |
1319b2f6 | 3370 | |
ac4fc3ee BL |
3371 | case RT5645_DMIC_DATA_GPIO10: |
3372 | regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, | |
3373 | RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10); | |
3374 | regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, | |
3375 | RT5645_GP10_PIN_MASK, | |
3376 | RT5645_GP10_PIN_DMIC2_SDA); | |
3377 | break; | |
1319b2f6 | 3378 | |
ac4fc3ee BL |
3379 | case RT5645_DMIC_DATA_GPIO12: |
3380 | regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, | |
3381 | RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12); | |
3382 | regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, | |
3383 | RT5645_GP12_PIN_MASK, | |
3384 | RT5645_GP12_PIN_DMIC2_SDA); | |
3385 | break; | |
1319b2f6 | 3386 | |
ac4fc3ee BL |
3387 | default: |
3388 | break; | |
1319b2f6 OC |
3389 | } |
3390 | ||
ac4fc3ee | 3391 | if (rt5645->pdata.jd_mode) { |
bb656add | 3392 | regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, |
ac4fc3ee BL |
3393 | RT5645_IRQ_CLK_GATE_CTRL, |
3394 | RT5645_IRQ_CLK_GATE_CTRL); | |
bb656add | 3395 | regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, |
ac4fc3ee | 3396 | RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN); |
bb656add | 3397 | regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, |
ac4fc3ee | 3398 | RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT); |
2d4e2d02 BL |
3399 | regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, |
3400 | RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN); | |
3401 | regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, | |
3402 | RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE); | |
3403 | regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER, | |
3404 | RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE); | |
3405 | regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, | |
3406 | RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN); | |
3407 | regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, | |
3408 | RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ); | |
3409 | switch (rt5645->pdata.jd_mode) { | |
3410 | case 1: | |
3411 | regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, | |
3412 | RT5645_JD1_MODE_MASK, | |
3413 | RT5645_JD1_MODE_0); | |
3414 | break; | |
3415 | case 2: | |
3416 | regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, | |
3417 | RT5645_JD1_MODE_MASK, | |
3418 | RT5645_JD1_MODE_1); | |
3419 | break; | |
3420 | case 3: | |
3421 | regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, | |
3422 | RT5645_JD1_MODE_MASK, | |
3423 | RT5645_JD1_MODE_2); | |
3424 | break; | |
3425 | default: | |
3426 | break; | |
3427 | } | |
3428 | } | |
3429 | ||
7ea3470a NB |
3430 | INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work); |
3431 | ||
f3fa1bbd OC |
3432 | if (rt5645->i2c->irq) { |
3433 | ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq, | |
3434 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | |
3435 | | IRQF_ONESHOT, "rt5645", rt5645); | |
3436 | if (ret) | |
3437 | dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret); | |
3438 | } | |
3439 | ||
dd56ebad AL |
3440 | return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5645, |
3441 | rt5645_dai, ARRAY_SIZE(rt5645_dai)); | |
1319b2f6 OC |
3442 | } |
3443 | ||
3444 | static int rt5645_i2c_remove(struct i2c_client *i2c) | |
3445 | { | |
f3fa1bbd OC |
3446 | struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c); |
3447 | ||
3448 | if (i2c->irq) | |
3449 | free_irq(i2c->irq, rt5645); | |
3450 | ||
cd6e82b8 OC |
3451 | cancel_delayed_work_sync(&rt5645->jack_detect_work); |
3452 | ||
1319b2f6 OC |
3453 | snd_soc_unregister_codec(&i2c->dev); |
3454 | ||
3455 | return 0; | |
3456 | } | |
3457 | ||
9e22f782 | 3458 | static struct i2c_driver rt5645_i2c_driver = { |
1319b2f6 OC |
3459 | .driver = { |
3460 | .name = "rt5645", | |
3461 | .owner = THIS_MODULE, | |
3168c201 | 3462 | .acpi_match_table = ACPI_PTR(rt5645_acpi_match), |
1319b2f6 OC |
3463 | }, |
3464 | .probe = rt5645_i2c_probe, | |
3465 | .remove = rt5645_i2c_remove, | |
3466 | .id_table = rt5645_i2c_id, | |
3467 | }; | |
3468 | module_i2c_driver(rt5645_i2c_driver); | |
3469 | ||
3470 | MODULE_DESCRIPTION("ASoC RT5645 driver"); | |
3471 | MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); | |
3472 | MODULE_LICENSE("GPL v2"); |