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ALSA: rme96: Use snd_pcm_hw_constraint_single()
[linux-2.6-block.git] / sound / pci / rme96.c
CommitLineData
1da177e4
LT		 1/*
2 * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
3 * interfaces
4 *
5 * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
6 *
7 * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
8 * code.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
1da177e4
LT		 26#include <linux/delay.h>
27#include <linux/init.h>
28#include <linux/interrupt.h>
29#include <linux/pci.h>
65a77217 30#include <linux/module.h>
a8cc2099 31#include <linux/vmalloc.h>
6cbbfe1c 32#include <linux/io.h>
1da177e4
LT		 33
34#include <sound/core.h>
35#include <sound/info.h>
36#include <sound/control.h>
37#include <sound/pcm.h>
38#include <sound/pcm_params.h>
39#include <sound/asoundef.h>
40#include <sound/initval.h>
41
1da177e4
LT		 42/* note, two last pcis should be equal, it is not a bug */
43
44MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
45MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
46 "Digi96/8 PAD");
47MODULE_LICENSE("GPL");
48MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
49 "{RME,Digi96/8},"
50 "{RME,Digi96/8 PRO},"
51 "{RME,Digi96/8 PST},"
52 "{RME,Digi96/8 PAD}}");
53
54static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
55static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
a67ff6a5 56static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
1da177e4
LT		 57
58module_param_array(index, int, NULL, 0444);
59MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
60module_param_array(id, charp, NULL, 0444);
61MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
62module_param_array(enable, bool, NULL, 0444);
63MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
64
65/*
66 * Defines for RME Digi96 series, from internal RME reference documents
67 * dated 12.01.00
68 */
69
70#define RME96_SPDIF_NCHANNELS 2
71
72/* Playback and capture buffer size */
73#define RME96_BUFFER_SIZE 0x10000
74
75/* IO area size */
76#define RME96_IO_SIZE 0x60000
77
78/* IO area offsets */
79#define RME96_IO_PLAY_BUFFER 0x0
80#define RME96_IO_REC_BUFFER 0x10000
81#define RME96_IO_CONTROL_REGISTER 0x20000
82#define RME96_IO_ADDITIONAL_REG 0x20004
83#define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
84#define RME96_IO_CONFIRM_REC_IRQ 0x2000C
85#define RME96_IO_SET_PLAY_POS 0x40000
86#define RME96_IO_RESET_PLAY_POS 0x4FFFC
87#define RME96_IO_SET_REC_POS 0x50000
88#define RME96_IO_RESET_REC_POS 0x5FFFC
89#define RME96_IO_GET_PLAY_POS 0x20000
90#define RME96_IO_GET_REC_POS 0x30000
91
92/* Write control register bits */
93#define RME96_WCR_START (1 << 0)
94#define RME96_WCR_START_2 (1 << 1)
95#define RME96_WCR_GAIN_0 (1 << 2)
96#define RME96_WCR_GAIN_1 (1 << 3)
97#define RME96_WCR_MODE24 (1 << 4)
98#define RME96_WCR_MODE24_2 (1 << 5)
99#define RME96_WCR_BM (1 << 6)
100#define RME96_WCR_BM_2 (1 << 7)
101#define RME96_WCR_ADAT (1 << 8)
102#define RME96_WCR_FREQ_0 (1 << 9)
103#define RME96_WCR_FREQ_1 (1 << 10)
104#define RME96_WCR_DS (1 << 11)
105#define RME96_WCR_PRO (1 << 12)
106#define RME96_WCR_EMP (1 << 13)
107#define RME96_WCR_SEL (1 << 14)
108#define RME96_WCR_MASTER (1 << 15)
109#define RME96_WCR_PD (1 << 16)
110#define RME96_WCR_INP_0 (1 << 17)
111#define RME96_WCR_INP_1 (1 << 18)
112#define RME96_WCR_THRU_0 (1 << 19)
113#define RME96_WCR_THRU_1 (1 << 20)
114#define RME96_WCR_THRU_2 (1 << 21)
115#define RME96_WCR_THRU_3 (1 << 22)
116#define RME96_WCR_THRU_4 (1 << 23)
117#define RME96_WCR_THRU_5 (1 << 24)
118#define RME96_WCR_THRU_6 (1 << 25)
119#define RME96_WCR_THRU_7 (1 << 26)
120#define RME96_WCR_DOLBY (1 << 27)
121#define RME96_WCR_MONITOR_0 (1 << 28)
122#define RME96_WCR_MONITOR_1 (1 << 29)
123#define RME96_WCR_ISEL (1 << 30)
124#define RME96_WCR_IDIS (1 << 31)
125
126#define RME96_WCR_BITPOS_GAIN_0 2
127#define RME96_WCR_BITPOS_GAIN_1 3
128#define RME96_WCR_BITPOS_FREQ_0 9
129#define RME96_WCR_BITPOS_FREQ_1 10
130#define RME96_WCR_BITPOS_INP_0 17
131#define RME96_WCR_BITPOS_INP_1 18
132#define RME96_WCR_BITPOS_MONITOR_0 28
133#define RME96_WCR_BITPOS_MONITOR_1 29
134
135/* Read control register bits */
136#define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
137#define RME96_RCR_IRQ_2 (1 << 16)
138#define RME96_RCR_T_OUT (1 << 17)
139#define RME96_RCR_DEV_ID_0 (1 << 21)
140#define RME96_RCR_DEV_ID_1 (1 << 22)
141#define RME96_RCR_LOCK (1 << 23)
142#define RME96_RCR_VERF (1 << 26)
143#define RME96_RCR_F0 (1 << 27)
144#define RME96_RCR_F1 (1 << 28)
145#define RME96_RCR_F2 (1 << 29)
146#define RME96_RCR_AUTOSYNC (1 << 30)
147#define RME96_RCR_IRQ (1 << 31)
148
149#define RME96_RCR_BITPOS_F0 27
150#define RME96_RCR_BITPOS_F1 28
151#define RME96_RCR_BITPOS_F2 29
152
25985edc 153/* Additional register bits */
1da177e4
LT		 154#define RME96_AR_WSEL (1 << 0)
155#define RME96_AR_ANALOG (1 << 1)
156#define RME96_AR_FREQPAD_0 (1 << 2)
157#define RME96_AR_FREQPAD_1 (1 << 3)
158#define RME96_AR_FREQPAD_2 (1 << 4)
159#define RME96_AR_PD2 (1 << 5)
160#define RME96_AR_DAC_EN (1 << 6)
161#define RME96_AR_CLATCH (1 << 7)
162#define RME96_AR_CCLK (1 << 8)
163#define RME96_AR_CDATA (1 << 9)
164
165#define RME96_AR_BITPOS_F0 2
166#define RME96_AR_BITPOS_F1 3
167#define RME96_AR_BITPOS_F2 4
168
169/* Monitor tracks */
170#define RME96_MONITOR_TRACKS_1_2 0
171#define RME96_MONITOR_TRACKS_3_4 1
172#define RME96_MONITOR_TRACKS_5_6 2
173#define RME96_MONITOR_TRACKS_7_8 3
174
175/* Attenuation */
176#define RME96_ATTENUATION_0 0
177#define RME96_ATTENUATION_6 1
178#define RME96_ATTENUATION_12 2
179#define RME96_ATTENUATION_18 3
180
181/* Input types */
182#define RME96_INPUT_OPTICAL 0
183#define RME96_INPUT_COAXIAL 1
184#define RME96_INPUT_INTERNAL 2
185#define RME96_INPUT_XLR 3
186#define RME96_INPUT_ANALOG 4
187
188/* Clock modes */
189#define RME96_CLOCKMODE_SLAVE 0
190#define RME96_CLOCKMODE_MASTER 1
191#define RME96_CLOCKMODE_WORDCLOCK 2
192
193/* Block sizes in bytes */
194#define RME96_SMALL_BLOCK_SIZE 2048
195#define RME96_LARGE_BLOCK_SIZE 8192
196
197/* Volume control */
198#define RME96_AD1852_VOL_BITS 14
199#define RME96_AD1855_VOL_BITS 10
200
b892ca1c
KP		 201/* Defines for snd_rme96_trigger */
202#define RME96_TB_START_PLAYBACK 1
203#define RME96_TB_START_CAPTURE 2
204#define RME96_TB_STOP_PLAYBACK 4
205#define RME96_TB_STOP_CAPTURE 8
206#define RME96_TB_RESET_PLAYPOS 16
207#define RME96_TB_RESET_CAPTUREPOS 32
208#define RME96_TB_CLEAR_PLAYBACK_IRQ 64
209#define RME96_TB_CLEAR_CAPTURE_IRQ 128
210#define RME96_RESUME_PLAYBACK (RME96_TB_START_PLAYBACK)
211#define RME96_RESUME_CAPTURE (RME96_TB_START_CAPTURE)
212#define RME96_RESUME_BOTH (RME96_RESUME_PLAYBACK \
213 | RME96_RESUME_CAPTURE)
214#define RME96_START_PLAYBACK (RME96_TB_START_PLAYBACK \
215 | RME96_TB_RESET_PLAYPOS)
216#define RME96_START_CAPTURE (RME96_TB_START_CAPTURE \
217 | RME96_TB_RESET_CAPTUREPOS)
218#define RME96_START_BOTH (RME96_START_PLAYBACK \
219 | RME96_START_CAPTURE)
220#define RME96_STOP_PLAYBACK (RME96_TB_STOP_PLAYBACK \
221 | RME96_TB_CLEAR_PLAYBACK_IRQ)
222#define RME96_STOP_CAPTURE (RME96_TB_STOP_CAPTURE \
223 | RME96_TB_CLEAR_CAPTURE_IRQ)
224#define RME96_STOP_BOTH (RME96_STOP_PLAYBACK \
225 | RME96_STOP_CAPTURE)
1da177e4 226
a3aefd88 227struct rme96 {
1da177e4
LT		 228 spinlock_t lock;
229 int irq;
230 unsigned long port;
231 void __iomem *iobase;
232
233 u32 wcreg; /* cached write control register value */
234 u32 wcreg_spdif; /* S/PDIF setup */
235 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
236 u32 rcreg; /* cached read control register value */
237 u32 areg; /* cached additional register value */
238 u16 vol[2]; /* cached volume of analog output */
239
240 u8 rev; /* card revision number */
241
a932be91 242#ifdef CONFIG_PM_SLEEP
528ba522
KP		 243 u32 playback_pointer;
244 u32 capture_pointer;
245 void *playback_suspend_buffer;
246 void *capture_suspend_buffer;
247#endif
248
a3aefd88
TI		 249 struct snd_pcm_substream *playback_substream;
250 struct snd_pcm_substream *capture_substream;
1da177e4
LT		 251
252 int playback_frlog; /* log2 of framesize */
253 int capture_frlog;
254
255 size_t playback_periodsize; /* in bytes, zero if not used */
256 size_t capture_periodsize; /* in bytes, zero if not used */
257
a3aefd88
TI		 258 struct snd_card *card;
259 struct snd_pcm *spdif_pcm;
260 struct snd_pcm *adat_pcm;
1da177e4 261 struct pci_dev *pci;
a3aefd88
TI		 262 struct snd_kcontrol *spdif_ctl;
263};
1da177e4 264
9baa3c34 265static const struct pci_device_id snd_rme96_ids[] = {
28d27aae
JP		 266 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, },
267 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, },
268 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, },
269 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, },
1da177e4
LT		 270 { 0, }
271};
272
273MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
274
275#define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
276#define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
8b7fc421
RD		 277#define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
278#define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
279 (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
1da177e4 280#define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
8b7fc421
RD		 281#define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
282 ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
1da177e4
LT		 283#define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
284
285static int
a3aefd88 286snd_rme96_playback_prepare(struct snd_pcm_substream *substream);
1da177e4
LT		 287
288static int
a3aefd88 289snd_rme96_capture_prepare(struct snd_pcm_substream *substream);
1da177e4
LT		 290
291static int
a3aefd88 292snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 293 int cmd);
294
295static int
a3aefd88 296snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 297 int cmd);
298
299static snd_pcm_uframes_t
a3aefd88 300snd_rme96_playback_pointer(struct snd_pcm_substream *substream);
1da177e4
LT		 301
302static snd_pcm_uframes_t
a3aefd88 303snd_rme96_capture_pointer(struct snd_pcm_substream *substream);
1da177e4 304
e23e7a14 305static void snd_rme96_proc_init(struct rme96 *rme96);
1da177e4
LT		 306
307static int
a3aefd88
TI		 308snd_rme96_create_switches(struct snd_card *card,
309 struct rme96 *rme96);
1da177e4
LT		 310
311static int
a3aefd88 312snd_rme96_getinputtype(struct rme96 *rme96);
1da177e4
LT		 313
314static inline unsigned int
a3aefd88 315snd_rme96_playback_ptr(struct rme96 *rme96)
1da177e4
LT		 316{
317 return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
318 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
319}
320
321static inline unsigned int
a3aefd88 322snd_rme96_capture_ptr(struct rme96 *rme96)
1da177e4
LT		 323{
324 return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
325 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
326}
327
1da177e4 328static int
a3aefd88 329snd_rme96_playback_silence(struct snd_pcm_substream *substream,
1da177e4
LT		 330 int channel, /* not used (interleaved data) */
331 snd_pcm_uframes_t pos,
332 snd_pcm_uframes_t count)
333{
a3aefd88 334 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 335 count <<= rme96->playback_frlog;
336 pos <<= rme96->playback_frlog;
337 memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
338 0, count);
339 return 0;
340}
341
342static int
a3aefd88 343snd_rme96_playback_copy(struct snd_pcm_substream *substream,
1da177e4
LT		 344 int channel, /* not used (interleaved data) */
345 snd_pcm_uframes_t pos,
346 void __user *src,
347 snd_pcm_uframes_t count)
348{
a3aefd88 349 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 350 count <<= rme96->playback_frlog;
351 pos <<= rme96->playback_frlog;
2026d24e
TI		 352 return copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src,
353 count);
1da177e4
LT		 354}
355
356static int
a3aefd88 357snd_rme96_capture_copy(struct snd_pcm_substream *substream,
1da177e4
LT		 358 int channel, /* not used (interleaved data) */
359 snd_pcm_uframes_t pos,
360 void __user *dst,
361 snd_pcm_uframes_t count)
362{
a3aefd88 363 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 364 count <<= rme96->capture_frlog;
365 pos <<= rme96->capture_frlog;
2026d24e
TI		 366 return copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos,
367 count);
1da177e4
LT		 368}
369
370/*
7f927fcc 371 * Digital output capabilities (S/PDIF)
1da177e4 372 */
a3aefd88 373static struct snd_pcm_hardware snd_rme96_playback_spdif_info =
1da177e4
LT		 374{
375 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
376 SNDRV_PCM_INFO_MMAP_VALID |
b892ca1c 377 SNDRV_PCM_INFO_SYNC_START |
528ba522 378 SNDRV_PCM_INFO_RESUME |
1da177e4
LT		 379 SNDRV_PCM_INFO_INTERLEAVED |
380 SNDRV_PCM_INFO_PAUSE),
381 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
382 SNDRV_PCM_FMTBIT_S32_LE),
383 .rates = (SNDRV_PCM_RATE_32000 |
384 SNDRV_PCM_RATE_44100 |
385 SNDRV_PCM_RATE_48000 |
386 SNDRV_PCM_RATE_64000 |
387 SNDRV_PCM_RATE_88200 |
388 SNDRV_PCM_RATE_96000),
389 .rate_min = 32000,
390 .rate_max = 96000,
391 .channels_min = 2,
392 .channels_max = 2,
393 .buffer_bytes_max = RME96_BUFFER_SIZE,
394 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
395 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
396 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
397 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
398 .fifo_size = 0,
399};
400
401/*
7f927fcc 402 * Digital input capabilities (S/PDIF)
1da177e4 403 */
a3aefd88 404static struct snd_pcm_hardware snd_rme96_capture_spdif_info =
1da177e4
LT		 405{
406 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
407 SNDRV_PCM_INFO_MMAP_VALID |
b892ca1c 408 SNDRV_PCM_INFO_SYNC_START |
528ba522 409 SNDRV_PCM_INFO_RESUME |
1da177e4
LT		 410 SNDRV_PCM_INFO_INTERLEAVED |
411 SNDRV_PCM_INFO_PAUSE),
412 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
413 SNDRV_PCM_FMTBIT_S32_LE),
414 .rates = (SNDRV_PCM_RATE_32000 |
415 SNDRV_PCM_RATE_44100 |
416 SNDRV_PCM_RATE_48000 |
417 SNDRV_PCM_RATE_64000 |
418 SNDRV_PCM_RATE_88200 |
419 SNDRV_PCM_RATE_96000),
420 .rate_min = 32000,
421 .rate_max = 96000,
422 .channels_min = 2,
423 .channels_max = 2,
424 .buffer_bytes_max = RME96_BUFFER_SIZE,
425 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
426 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
427 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
428 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
429 .fifo_size = 0,
430};
431
432/*
7f927fcc 433 * Digital output capabilities (ADAT)
1da177e4 434 */
a3aefd88 435static struct snd_pcm_hardware snd_rme96_playback_adat_info =
1da177e4
LT		 436{
437 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
438 SNDRV_PCM_INFO_MMAP_VALID |
b892ca1c 439 SNDRV_PCM_INFO_SYNC_START |
528ba522 440 SNDRV_PCM_INFO_RESUME |
1da177e4
LT		 441 SNDRV_PCM_INFO_INTERLEAVED |
442 SNDRV_PCM_INFO_PAUSE),
443 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
444 SNDRV_PCM_FMTBIT_S32_LE),
445 .rates = (SNDRV_PCM_RATE_44100 |
446 SNDRV_PCM_RATE_48000),
447 .rate_min = 44100,
448 .rate_max = 48000,
449 .channels_min = 8,
450 .channels_max = 8,
451 .buffer_bytes_max = RME96_BUFFER_SIZE,
452 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
453 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
454 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
455 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
456 .fifo_size = 0,
457};
458
459/*
7f927fcc 460 * Digital input capabilities (ADAT)
1da177e4 461 */
a3aefd88 462static struct snd_pcm_hardware snd_rme96_capture_adat_info =
1da177e4
LT		 463{
464 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
465 SNDRV_PCM_INFO_MMAP_VALID |
b892ca1c 466 SNDRV_PCM_INFO_SYNC_START |
528ba522 467 SNDRV_PCM_INFO_RESUME |
1da177e4
LT		 468 SNDRV_PCM_INFO_INTERLEAVED |
469 SNDRV_PCM_INFO_PAUSE),
470 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
471 SNDRV_PCM_FMTBIT_S32_LE),
472 .rates = (SNDRV_PCM_RATE_44100 |
473 SNDRV_PCM_RATE_48000),
474 .rate_min = 44100,
475 .rate_max = 48000,
476 .channels_min = 8,
477 .channels_max = 8,
478 .buffer_bytes_max = RME96_BUFFER_SIZE,
479 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
480 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
481 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
482 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
483 .fifo_size = 0,
484};
485
486/*
487 * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
488 * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up
489 * on the falling edge of CCLK and be stable on the rising edge. The rising
490 * edge of CLATCH after the last data bit clocks in the whole data word.
491 * A fast processor could probably drive the SPI interface faster than the
492 * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1)
493 * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
494 *
495 * NOTE: increased delay from 1 to 10, since there where problems setting
496 * the volume.
497 */
498static void
a3aefd88 499snd_rme96_write_SPI(struct rme96 *rme96, u16 val)
1da177e4
LT		 500{
501 int i;
502
503 for (i = 0; i < 16; i++) {
504 if (val & 0x8000) {
505 rme96->areg |= RME96_AR_CDATA;
506 } else {
507 rme96->areg &= ~RME96_AR_CDATA;
508 }
509 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
510 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
511 udelay(10);
512 rme96->areg |= RME96_AR_CCLK;
513 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
514 udelay(10);
515 val <<= 1;
516 }
517 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
518 rme96->areg |= RME96_AR_CLATCH;
519 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
520 udelay(10);
521 rme96->areg &= ~RME96_AR_CLATCH;
522 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
523}
524
525static void
a3aefd88 526snd_rme96_apply_dac_volume(struct rme96 *rme96)
1da177e4
LT		 527{
528 if (RME96_DAC_IS_1852(rme96)) {
529 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
530 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
531 } else if (RME96_DAC_IS_1855(rme96)) {
532 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
533 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
534 }
535}
536
537static void
a3aefd88 538snd_rme96_reset_dac(struct rme96 *rme96)
1da177e4
LT		 539{
540 writel(rme96->wcreg | RME96_WCR_PD,
541 rme96->iobase + RME96_IO_CONTROL_REGISTER);
542 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
543}
544
545static int
a3aefd88 546snd_rme96_getmontracks(struct rme96 *rme96)
1da177e4
LT		 547{
548 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
549 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
550}
551
552static int
a3aefd88 553snd_rme96_setmontracks(struct rme96 *rme96,
1da177e4
LT		 554 int montracks)
555{
556 if (montracks & 1) {
557 rme96->wcreg |= RME96_WCR_MONITOR_0;
558 } else {
559 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
560 }
561 if (montracks & 2) {
562 rme96->wcreg |= RME96_WCR_MONITOR_1;
563 } else {
564 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
565 }
566 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
567 return 0;
568}
569
570static int
a3aefd88 571snd_rme96_getattenuation(struct rme96 *rme96)
1da177e4
LT		 572{
573 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
574 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
575}
576
577static int
a3aefd88 578snd_rme96_setattenuation(struct rme96 *rme96,
1da177e4
LT		 579 int attenuation)
580{
581 switch (attenuation) {
582 case 0:
583 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
584 ~RME96_WCR_GAIN_1;
585 break;
586 case 1:
587 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
588 ~RME96_WCR_GAIN_1;
589 break;
590 case 2:
591 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
592 RME96_WCR_GAIN_1;
593 break;
594 case 3:
595 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
596 RME96_WCR_GAIN_1;
597 break;
598 default:
599 return -EINVAL;
600 }
601 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
602 return 0;
603}
604
605static int
a3aefd88 606snd_rme96_capture_getrate(struct rme96 *rme96,
1da177e4
LT		 607 int *is_adat)
608{
609 int n, rate;
610
611 *is_adat = 0;
612 if (rme96->areg & RME96_AR_ANALOG) {
613 /* Analog input, overrides S/PDIF setting */
614 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
615 (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
616 switch (n) {
617 case 1:
618 rate = 32000;
619 break;
620 case 2:
621 rate = 44100;
622 break;
623 case 3:
624 rate = 48000;
625 break;
626 default:
627 return -1;
628 }
629 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
630 }
631
632 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
633 if (rme96->rcreg & RME96_RCR_LOCK) {
634 /* ADAT rate */
635 *is_adat = 1;
636 if (rme96->rcreg & RME96_RCR_T_OUT) {
637 return 48000;
638 }
639 return 44100;
640 }
641
642 if (rme96->rcreg & RME96_RCR_VERF) {
643 return -1;
644 }
645
646 /* S/PDIF rate */
647 n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
648 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
649 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
650
651 switch (n) {
652 case 0:
653 if (rme96->rcreg & RME96_RCR_T_OUT) {
654 return 64000;
655 }
656 return -1;
657 case 3: return 96000;
658 case 4: return 88200;
659 case 5: return 48000;
660 case 6: return 44100;
661 case 7: return 32000;
662 default:
663 break;
664 }
665 return -1;
666}
667
668static int
a3aefd88 669snd_rme96_playback_getrate(struct rme96 *rme96)
1da177e4
LT		 670{
671 int rate, dummy;
672
673 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
674 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
675 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
676 {
677 /* slave clock */
678 return rate;
679 }
680 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
681 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
682 switch (rate) {
683 case 1:
684 rate = 32000;
685 break;
686 case 2:
687 rate = 44100;
688 break;
689 case 3:
690 rate = 48000;
691 break;
692 default:
693 return -1;
694 }
695 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
696}
697
698static int
a3aefd88 699snd_rme96_playback_setrate(struct rme96 *rme96,
1da177e4
LT		 700 int rate)
701{
702 int ds;
703
704 ds = rme96->wcreg & RME96_WCR_DS;
705 switch (rate) {
706 case 32000:
707 rme96->wcreg &= ~RME96_WCR_DS;
708 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
709 ~RME96_WCR_FREQ_1;
710 break;
711 case 44100:
712 rme96->wcreg &= ~RME96_WCR_DS;
713 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
714 ~RME96_WCR_FREQ_0;
715 break;
716 case 48000:
717 rme96->wcreg &= ~RME96_WCR_DS;
718 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
719 RME96_WCR_FREQ_1;
720 break;
721 case 64000:
722 rme96->wcreg |= RME96_WCR_DS;
723 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
724 ~RME96_WCR_FREQ_1;
725 break;
726 case 88200:
727 rme96->wcreg |= RME96_WCR_DS;
728 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
729 ~RME96_WCR_FREQ_0;
730 break;
731 case 96000:
732 rme96->wcreg |= RME96_WCR_DS;
733 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
734 RME96_WCR_FREQ_1;
735 break;
736 default:
737 return -EINVAL;
738 }
739 if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
740 (ds && !(rme96->wcreg & RME96_WCR_DS)))
741 {
742 /* change to/from double-speed: reset the DAC (if available) */
743 snd_rme96_reset_dac(rme96);
744 } else {
745 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
746 }
747 return 0;
748}
749
750static int
a3aefd88 751snd_rme96_capture_analog_setrate(struct rme96 *rme96,
1da177e4
LT		 752 int rate)
753{
754 switch (rate) {
755 case 32000:
756 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
757 ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
758 break;
759 case 44100:
760 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
761 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
762 break;
763 case 48000:
764 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
765 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
766 break;
767 case 64000:
768 if (rme96->rev < 4) {
769 return -EINVAL;
770 }
771 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
772 ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
773 break;
774 case 88200:
775 if (rme96->rev < 4) {
776 return -EINVAL;
777 }
778 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
779 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
780 break;
781 case 96000:
782 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
783 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
784 break;
785 default:
786 return -EINVAL;
787 }
788 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
789 return 0;
790}
791
792static int
a3aefd88 793snd_rme96_setclockmode(struct rme96 *rme96,
1da177e4
LT		 794 int mode)
795{
796 switch (mode) {
797 case RME96_CLOCKMODE_SLAVE:
798 /* AutoSync */
799 rme96->wcreg &= ~RME96_WCR_MASTER;
800 rme96->areg &= ~RME96_AR_WSEL;
801 break;
802 case RME96_CLOCKMODE_MASTER:
803 /* Internal */
804 rme96->wcreg |= RME96_WCR_MASTER;
805 rme96->areg &= ~RME96_AR_WSEL;
806 break;
807 case RME96_CLOCKMODE_WORDCLOCK:
808 /* Word clock is a master mode */
809 rme96->wcreg |= RME96_WCR_MASTER;
810 rme96->areg |= RME96_AR_WSEL;
811 break;
812 default:
813 return -EINVAL;
814 }
815 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
816 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
817 return 0;
818}
819
820static int
a3aefd88 821snd_rme96_getclockmode(struct rme96 *rme96)
1da177e4
LT		 822{
823 if (rme96->areg & RME96_AR_WSEL) {
824 return RME96_CLOCKMODE_WORDCLOCK;
825 }
826 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
827 RME96_CLOCKMODE_SLAVE;
828}
829
830static int
a3aefd88 831snd_rme96_setinputtype(struct rme96 *rme96,
1da177e4
LT		 832 int type)
833{
834 int n;
835
836 switch (type) {
837 case RME96_INPUT_OPTICAL:
838 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
839 ~RME96_WCR_INP_1;
840 break;
841 case RME96_INPUT_COAXIAL:
842 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
843 ~RME96_WCR_INP_1;
844 break;
845 case RME96_INPUT_INTERNAL:
846 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
847 RME96_WCR_INP_1;
848 break;
849 case RME96_INPUT_XLR:
8b7fc421
RD		 850 if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
851 rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) ||
852 (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
1da177e4
LT		 853 rme96->rev > 4))
854 {
855 /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
856 return -EINVAL;
857 }
858 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
859 RME96_WCR_INP_1;
860 break;
861 case RME96_INPUT_ANALOG:
862 if (!RME96_HAS_ANALOG_IN(rme96)) {
863 return -EINVAL;
864 }
865 rme96->areg |= RME96_AR_ANALOG;
866 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
867 if (rme96->rev < 4) {
868 /*
869 * Revision less than 004 does not support 64 and
870 * 88.2 kHz
871 */
872 if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
873 snd_rme96_capture_analog_setrate(rme96, 44100);
874 }
875 if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
876 snd_rme96_capture_analog_setrate(rme96, 32000);
877 }
878 }
879 return 0;
880 default:
881 return -EINVAL;
882 }
883 if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
884 rme96->areg &= ~RME96_AR_ANALOG;
885 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
886 }
887 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
888 return 0;
889}
890
891static int
a3aefd88 892snd_rme96_getinputtype(struct rme96 *rme96)
1da177e4
LT		 893{
894 if (rme96->areg & RME96_AR_ANALOG) {
895 return RME96_INPUT_ANALOG;
896 }
897 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
898 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
899}
900
901static void
a3aefd88 902snd_rme96_setframelog(struct rme96 *rme96,
1da177e4
LT		 903 int n_channels,
904 int is_playback)
905{
906 int frlog;
907
908 if (n_channels == 2) {
909 frlog = 1;
910 } else {
911 /* assume 8 channels */
912 frlog = 3;
913 }
914 if (is_playback) {
915 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
916 rme96->playback_frlog = frlog;
917 } else {
918 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
919 rme96->capture_frlog = frlog;
920 }
921}
922
923static int
6c869d30 924snd_rme96_playback_setformat(struct rme96 *rme96, snd_pcm_format_t format)
1da177e4
LT		 925{
926 switch (format) {
927 case SNDRV_PCM_FORMAT_S16_LE:
928 rme96->wcreg &= ~RME96_WCR_MODE24;
929 break;
930 case SNDRV_PCM_FORMAT_S32_LE:
931 rme96->wcreg |= RME96_WCR_MODE24;
932 break;
933 default:
934 return -EINVAL;
935 }
936 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
937 return 0;
938}
939
940static int
6c869d30 941snd_rme96_capture_setformat(struct rme96 *rme96, snd_pcm_format_t format)
1da177e4
LT		 942{
943 switch (format) {
944 case SNDRV_PCM_FORMAT_S16_LE:
945 rme96->wcreg &= ~RME96_WCR_MODE24_2;
946 break;
947 case SNDRV_PCM_FORMAT_S32_LE:
948 rme96->wcreg |= RME96_WCR_MODE24_2;
949 break;
950 default:
951 return -EINVAL;
952 }
953 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
954 return 0;
955}
956
957static void
a3aefd88 958snd_rme96_set_period_properties(struct rme96 *rme96,
1da177e4
LT		 959 size_t period_bytes)
960{
961 switch (period_bytes) {
962 case RME96_LARGE_BLOCK_SIZE:
963 rme96->wcreg &= ~RME96_WCR_ISEL;
964 break;
965 case RME96_SMALL_BLOCK_SIZE:
966 rme96->wcreg |= RME96_WCR_ISEL;
967 break;
968 default:
969 snd_BUG();
970 break;
971 }
972 rme96->wcreg &= ~RME96_WCR_IDIS;
973 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
974}
975
976static int
a3aefd88
TI		 977snd_rme96_playback_hw_params(struct snd_pcm_substream *substream,
978 struct snd_pcm_hw_params *params)
1da177e4 979{
a3aefd88
TI		 980 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
981 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 982 int err, rate, dummy;
983
4d23359b
CL		 984 runtime->dma_area = (void __force *)(rme96->iobase +
985 RME96_IO_PLAY_BUFFER);
1da177e4
LT		 986 runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
987 runtime->dma_bytes = RME96_BUFFER_SIZE;
988
989 spin_lock_irq(&rme96->lock);
990 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
991 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
992 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
993 {
994 /* slave clock */
995 if ((int)params_rate(params) != rate) {
996 spin_unlock_irq(&rme96->lock);
997 return -EIO;
998 }
999 } else if ((err = snd_rme96_playback_setrate(rme96, params_rate(params))) < 0) {
1000 spin_unlock_irq(&rme96->lock);
1001 return err;
1002 }
1003 if ((err = snd_rme96_playback_setformat(rme96, params_format(params))) < 0) {
1004 spin_unlock_irq(&rme96->lock);
1005 return err;
1006 }
1007 snd_rme96_setframelog(rme96, params_channels(params), 1);
1008 if (rme96->capture_periodsize != 0) {
1009 if (params_period_size(params) << rme96->playback_frlog !=
1010 rme96->capture_periodsize)
1011 {
1012 spin_unlock_irq(&rme96->lock);
1013 return -EBUSY;
1014 }
1015 }
1016 rme96->playback_periodsize =
1017 params_period_size(params) << rme96->playback_frlog;
1018 snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
1019 /* S/PDIF setup */
1020 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
1021 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
1022 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1023 }
1024 spin_unlock_irq(&rme96->lock);
1025
1026 return 0;
1027}
1028
1029static int
a3aefd88
TI		 1030snd_rme96_capture_hw_params(struct snd_pcm_substream *substream,
1031 struct snd_pcm_hw_params *params)
1da177e4 1032{
a3aefd88
TI		 1033 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1034 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1035 int err, isadat, rate;
1036
4d23359b
CL		 1037 runtime->dma_area = (void __force *)(rme96->iobase +
1038 RME96_IO_REC_BUFFER);
1da177e4
LT		 1039 runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
1040 runtime->dma_bytes = RME96_BUFFER_SIZE;
1041
1042 spin_lock_irq(&rme96->lock);
1043 if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
1044 spin_unlock_irq(&rme96->lock);
1045 return err;
1046 }
1047 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1048 if ((err = snd_rme96_capture_analog_setrate(rme96,
1049 params_rate(params))) < 0)
1050 {
1051 spin_unlock_irq(&rme96->lock);
1052 return err;
1053 }
1054 } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1055 if ((int)params_rate(params) != rate) {
1056 spin_unlock_irq(&rme96->lock);
1057 return -EIO;
1058 }
1059 if ((isadat && runtime->hw.channels_min == 2) ||
1060 (!isadat && runtime->hw.channels_min == 8))
1061 {
1062 spin_unlock_irq(&rme96->lock);
1063 return -EIO;
1064 }
1065 }
1066 snd_rme96_setframelog(rme96, params_channels(params), 0);
1067 if (rme96->playback_periodsize != 0) {
1068 if (params_period_size(params) << rme96->capture_frlog !=
1069 rme96->playback_periodsize)
1070 {
1071 spin_unlock_irq(&rme96->lock);
1072 return -EBUSY;
1073 }
1074 }
1075 rme96->capture_periodsize =
1076 params_period_size(params) << rme96->capture_frlog;
1077 snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1078 spin_unlock_irq(&rme96->lock);
1079
1080 return 0;
1081}
1082
1083static void
b892ca1c
KP		 1084snd_rme96_trigger(struct rme96 *rme96,
1085 int op)
1da177e4 1086{
b892ca1c 1087 if (op & RME96_TB_RESET_PLAYPOS)
1da177e4 1088 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
b892ca1c 1089 if (op & RME96_TB_RESET_CAPTUREPOS)
1da177e4 1090 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
b892ca1c
KP		 1091 if (op & RME96_TB_CLEAR_PLAYBACK_IRQ) {
1092 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1093 if (rme96->rcreg & RME96_RCR_IRQ)
1094 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1da177e4 1095 }
b892ca1c
KP		 1096 if (op & RME96_TB_CLEAR_CAPTURE_IRQ) {
1097 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1098 if (rme96->rcreg & RME96_RCR_IRQ_2)
1099 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1100 }
1101 if (op & RME96_TB_START_PLAYBACK)
1102 rme96->wcreg |= RME96_WCR_START;
1103 if (op & RME96_TB_STOP_PLAYBACK)
1104 rme96->wcreg &= ~RME96_WCR_START;
1105 if (op & RME96_TB_START_CAPTURE)
1106 rme96->wcreg |= RME96_WCR_START_2;
1107 if (op & RME96_TB_STOP_CAPTURE)
1108 rme96->wcreg &= ~RME96_WCR_START_2;
1da177e4
LT		 1109 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1110}
1111
1da177e4 1112
1da177e4
LT		 1113
1114static irqreturn_t
1115snd_rme96_interrupt(int irq,
7d12e780 1116 void *dev_id)
1da177e4 1117{
a3aefd88 1118 struct rme96 *rme96 = (struct rme96 *)dev_id;
1da177e4
LT		 1119
1120 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1121 /* fastpath out, to ease interrupt sharing */
1122 if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1123 (rme96->rcreg & RME96_RCR_IRQ_2)))
1124 {
1125 return IRQ_NONE;
1126 }
1127
1128 if (rme96->rcreg & RME96_RCR_IRQ) {
1129 /* playback */
1130 snd_pcm_period_elapsed(rme96->playback_substream);
1131 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1132 }
1133 if (rme96->rcreg & RME96_RCR_IRQ_2) {
1134 /* capture */
1135 snd_pcm_period_elapsed(rme96->capture_substream);
1136 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1137 }
1138 return IRQ_HANDLED;
1139}
1140
1141static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1142
a3aefd88 1143static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
1da177e4
LT		 1144 .count = ARRAY_SIZE(period_bytes),
1145 .list = period_bytes,
1146 .mask = 0
1147};
1148
2ce7fb57
TI		 1149static void
1150rme96_set_buffer_size_constraint(struct rme96 *rme96,
1151 struct snd_pcm_runtime *runtime)
1152{
1153 unsigned int size;
1154
1a8e41ef
LPC		 1155 snd_pcm_hw_constraint_single(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1156 RME96_BUFFER_SIZE);
2ce7fb57
TI		 1157 if ((size = rme96->playback_periodsize) != 0 ||
1158 (size = rme96->capture_periodsize) != 0)
1a8e41ef 1159 snd_pcm_hw_constraint_single(runtime,
2ce7fb57 1160 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1a8e41ef 1161 size);
2ce7fb57
TI		 1162 else
1163 snd_pcm_hw_constraint_list(runtime, 0,
1164 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1165 &hw_constraints_period_bytes);
1166}
1167
1da177e4 1168static int
a3aefd88 1169snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1170{
1171 int rate, dummy;
a3aefd88
TI		 1172 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1173 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1174
b892ca1c 1175 snd_pcm_set_sync(substream);
1da177e4
LT		 1176 spin_lock_irq(&rme96->lock);
1177 if (rme96->playback_substream != NULL) {
1178 spin_unlock_irq(&rme96->lock);
1179 return -EBUSY;
1180 }
1181 rme96->wcreg &= ~RME96_WCR_ADAT;
1182 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1183 rme96->playback_substream = substream;
1184 spin_unlock_irq(&rme96->lock);
1185
1186 runtime->hw = snd_rme96_playback_spdif_info;
1187 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1188 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1189 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1190 {
1191 /* slave clock */
918f3a0e 1192 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 1193 runtime->hw.rate_min = rate;
1194 runtime->hw.rate_max = rate;
1195 }
2ce7fb57 1196 rme96_set_buffer_size_constraint(rme96, runtime);
1da177e4
LT		 1197
1198 rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1199 rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1200 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1201 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1202 return 0;
1203}
1204
1205static int
a3aefd88 1206snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1207{
1208 int isadat, rate;
a3aefd88
TI		 1209 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1210 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1211
b892ca1c 1212 snd_pcm_set_sync(substream);
1da177e4
LT		 1213 runtime->hw = snd_rme96_capture_spdif_info;
1214 if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1215 (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
1216 {
1217 if (isadat) {
1218 return -EIO;
1219 }
918f3a0e 1220 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 1221 runtime->hw.rate_min = rate;
1222 runtime->hw.rate_max = rate;
1223 }
1224
1225 spin_lock_irq(&rme96->lock);
1226 if (rme96->capture_substream != NULL) {
1227 spin_unlock_irq(&rme96->lock);
1228 return -EBUSY;
1229 }
1230 rme96->capture_substream = substream;
1231 spin_unlock_irq(&rme96->lock);
1232
2ce7fb57 1233 rme96_set_buffer_size_constraint(rme96, runtime);
1da177e4
LT		 1234 return 0;
1235}
1236
1237static int
a3aefd88 1238snd_rme96_playback_adat_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1239{
1240 int rate, dummy;
a3aefd88
TI		 1241 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1242 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1243
b892ca1c 1244 snd_pcm_set_sync(substream);
1da177e4
LT		 1245 spin_lock_irq(&rme96->lock);
1246 if (rme96->playback_substream != NULL) {
1247 spin_unlock_irq(&rme96->lock);
1248 return -EBUSY;
1249 }
1250 rme96->wcreg |= RME96_WCR_ADAT;
1251 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1252 rme96->playback_substream = substream;
1253 spin_unlock_irq(&rme96->lock);
1254
1255 runtime->hw = snd_rme96_playback_adat_info;
1256 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1257 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1258 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1259 {
1260 /* slave clock */
918f3a0e 1261 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 1262 runtime->hw.rate_min = rate;
1263 runtime->hw.rate_max = rate;
1264 }
2ce7fb57 1265 rme96_set_buffer_size_constraint(rme96, runtime);
1da177e4
LT		 1266 return 0;
1267}
1268
1269static int
a3aefd88 1270snd_rme96_capture_adat_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1271{
1272 int isadat, rate;
a3aefd88
TI		 1273 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1274 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1275
b892ca1c 1276 snd_pcm_set_sync(substream);
1da177e4
LT		 1277 runtime->hw = snd_rme96_capture_adat_info;
1278 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1279 /* makes no sense to use analog input. Note that analog
1280 expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1281 return -EIO;
1282 }
1283 if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1284 if (!isadat) {
1285 return -EIO;
1286 }
918f3a0e 1287 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 1288 runtime->hw.rate_min = rate;
1289 runtime->hw.rate_max = rate;
1290 }
1291
1292 spin_lock_irq(&rme96->lock);
1293 if (rme96->capture_substream != NULL) {
1294 spin_unlock_irq(&rme96->lock);
1295 return -EBUSY;
1296 }
1297 rme96->capture_substream = substream;
1298 spin_unlock_irq(&rme96->lock);
1299
2ce7fb57 1300 rme96_set_buffer_size_constraint(rme96, runtime);
1da177e4
LT		 1301 return 0;
1302}
1303
1304static int
a3aefd88 1305snd_rme96_playback_close(struct snd_pcm_substream *substream)
1da177e4 1306{
a3aefd88 1307 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1308 int spdif = 0;
1309
1310 spin_lock_irq(&rme96->lock);
1311 if (RME96_ISPLAYING(rme96)) {
b892ca1c 1312 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK);
1da177e4
LT		 1313 }
1314 rme96->playback_substream = NULL;
1315 rme96->playback_periodsize = 0;
1316 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1317 spin_unlock_irq(&rme96->lock);
1318 if (spdif) {
1319 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1320 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1321 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1322 }
1323 return 0;
1324}
1325
1326static int
a3aefd88 1327snd_rme96_capture_close(struct snd_pcm_substream *substream)
1da177e4 1328{
a3aefd88 1329 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1330
1331 spin_lock_irq(&rme96->lock);
1332 if (RME96_ISRECORDING(rme96)) {
b892ca1c 1333 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE);
1da177e4
LT		 1334 }
1335 rme96->capture_substream = NULL;
1336 rme96->capture_periodsize = 0;
1337 spin_unlock_irq(&rme96->lock);
1338 return 0;
1339}
1340
1341static int
a3aefd88 1342snd_rme96_playback_prepare(struct snd_pcm_substream *substream)
1da177e4 1343{
a3aefd88 1344 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1345
1346 spin_lock_irq(&rme96->lock);
1347 if (RME96_ISPLAYING(rme96)) {
b892ca1c 1348 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK);
1da177e4
LT		 1349 }
1350 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1351 spin_unlock_irq(&rme96->lock);
1352 return 0;
1353}
1354
1355static int
a3aefd88 1356snd_rme96_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 1357{
a3aefd88 1358 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1359
1360 spin_lock_irq(&rme96->lock);
1361 if (RME96_ISRECORDING(rme96)) {
b892ca1c 1362 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE);
1da177e4
LT		 1363 }
1364 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1365 spin_unlock_irq(&rme96->lock);
1366 return 0;
1367}
1368
1369static int
a3aefd88 1370snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 1371 int cmd)
1372{
a3aefd88 1373 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
b892ca1c
KP		 1374 struct snd_pcm_substream *s;
1375 bool sync;
1376
1377 snd_pcm_group_for_each_entry(s, substream) {
1378 if (snd_pcm_substream_chip(s) == rme96)
1379 snd_pcm_trigger_done(s, substream);
1380 }
1381
1382 sync = (rme96->playback_substream && rme96->capture_substream) &&
1383 (rme96->playback_substream->group ==
1384 rme96->capture_substream->group);
1da177e4
LT		 1385
1386 switch (cmd) {
1387 case SNDRV_PCM_TRIGGER_START:
1388 if (!RME96_ISPLAYING(rme96)) {
b892ca1c 1389 if (substream != rme96->playback_substream)
1da177e4 1390 return -EBUSY;
b892ca1c
KP		 1391 snd_rme96_trigger(rme96, sync ? RME96_START_BOTH
1392 : RME96_START_PLAYBACK);
1da177e4
LT		 1393 }
1394 break;
1395
528ba522 1396 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4
LT		 1397 case SNDRV_PCM_TRIGGER_STOP:
1398 if (RME96_ISPLAYING(rme96)) {
b892ca1c 1399 if (substream != rme96->playback_substream)
1da177e4 1400 return -EBUSY;
b892ca1c
KP		 1401 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1402 : RME96_STOP_PLAYBACK);
1da177e4
LT		 1403 }
1404 break;
1405
1406 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
b892ca1c
KP		 1407 if (RME96_ISPLAYING(rme96))
1408 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1409 : RME96_STOP_PLAYBACK);
1da177e4
LT		 1410 break;
1411
528ba522 1412 case SNDRV_PCM_TRIGGER_RESUME:
1da177e4 1413 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
b892ca1c
KP		 1414 if (!RME96_ISPLAYING(rme96))
1415 snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH
1416 : RME96_RESUME_PLAYBACK);
1da177e4 1417 break;
b892ca1c 1418
1da177e4
LT		 1419 default:
1420 return -EINVAL;
1421 }
b892ca1c 1422
1da177e4
LT		 1423 return 0;
1424}
1425
1426static int
a3aefd88 1427snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 1428 int cmd)
1429{
a3aefd88 1430 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
b892ca1c
KP		 1431 struct snd_pcm_substream *s;
1432 bool sync;
1433
1434 snd_pcm_group_for_each_entry(s, substream) {
1435 if (snd_pcm_substream_chip(s) == rme96)
1436 snd_pcm_trigger_done(s, substream);
1437 }
1438
1439 sync = (rme96->playback_substream && rme96->capture_substream) &&
1440 (rme96->playback_substream->group ==
1441 rme96->capture_substream->group);
1da177e4
LT		 1442
1443 switch (cmd) {
1444 case SNDRV_PCM_TRIGGER_START:
1445 if (!RME96_ISRECORDING(rme96)) {
b892ca1c 1446 if (substream != rme96->capture_substream)
1da177e4 1447 return -EBUSY;
b892ca1c
KP		 1448 snd_rme96_trigger(rme96, sync ? RME96_START_BOTH
1449 : RME96_START_CAPTURE);
1da177e4
LT		 1450 }
1451 break;
1452
528ba522 1453 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4
LT		 1454 case SNDRV_PCM_TRIGGER_STOP:
1455 if (RME96_ISRECORDING(rme96)) {
b892ca1c 1456 if (substream != rme96->capture_substream)
1da177e4 1457 return -EBUSY;
b892ca1c
KP		 1458 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1459 : RME96_STOP_CAPTURE);
1da177e4
LT		 1460 }
1461 break;
1462
1463 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
b892ca1c
KP		 1464 if (RME96_ISRECORDING(rme96))
1465 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1466 : RME96_STOP_CAPTURE);
1da177e4
LT		 1467 break;
1468
528ba522 1469 case SNDRV_PCM_TRIGGER_RESUME:
1da177e4 1470 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
b892ca1c
KP		 1471 if (!RME96_ISRECORDING(rme96))
1472 snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH
1473 : RME96_RESUME_CAPTURE);
1da177e4 1474 break;
b892ca1c 1475
1da177e4
LT		 1476 default:
1477 return -EINVAL;
1478 }
1479
1480 return 0;
1481}
1482
1483static snd_pcm_uframes_t
a3aefd88 1484snd_rme96_playback_pointer(struct snd_pcm_substream *substream)
1da177e4 1485{
a3aefd88 1486 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1487 return snd_rme96_playback_ptr(rme96);
1488}
1489
1490static snd_pcm_uframes_t
a3aefd88 1491snd_rme96_capture_pointer(struct snd_pcm_substream *substream)
1da177e4 1492{
a3aefd88 1493 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1494 return snd_rme96_capture_ptr(rme96);
1495}
1496
a3aefd88 1497static struct snd_pcm_ops snd_rme96_playback_spdif_ops = {
1da177e4
LT		 1498 .open = snd_rme96_playback_spdif_open,
1499 .close = snd_rme96_playback_close,
1500 .ioctl = snd_pcm_lib_ioctl,
1501 .hw_params = snd_rme96_playback_hw_params,
1502 .prepare = snd_rme96_playback_prepare,
1503 .trigger = snd_rme96_playback_trigger,
1504 .pointer = snd_rme96_playback_pointer,
1505 .copy = snd_rme96_playback_copy,
1506 .silence = snd_rme96_playback_silence,
1507 .mmap = snd_pcm_lib_mmap_iomem,
1508};
1509
a3aefd88 1510static struct snd_pcm_ops snd_rme96_capture_spdif_ops = {
1da177e4
LT		 1511 .open = snd_rme96_capture_spdif_open,
1512 .close = snd_rme96_capture_close,
1513 .ioctl = snd_pcm_lib_ioctl,
1514 .hw_params = snd_rme96_capture_hw_params,
1515 .prepare = snd_rme96_capture_prepare,
1516 .trigger = snd_rme96_capture_trigger,
1517 .pointer = snd_rme96_capture_pointer,
1518 .copy = snd_rme96_capture_copy,
1519 .mmap = snd_pcm_lib_mmap_iomem,
1520};
1521
a3aefd88 1522static struct snd_pcm_ops snd_rme96_playback_adat_ops = {
1da177e4
LT		 1523 .open = snd_rme96_playback_adat_open,
1524 .close = snd_rme96_playback_close,
1525 .ioctl = snd_pcm_lib_ioctl,
1526 .hw_params = snd_rme96_playback_hw_params,
1527 .prepare = snd_rme96_playback_prepare,
1528 .trigger = snd_rme96_playback_trigger,
1529 .pointer = snd_rme96_playback_pointer,
1530 .copy = snd_rme96_playback_copy,
1531 .silence = snd_rme96_playback_silence,
1532 .mmap = snd_pcm_lib_mmap_iomem,
1533};
1534
a3aefd88 1535static struct snd_pcm_ops snd_rme96_capture_adat_ops = {
1da177e4
LT		 1536 .open = snd_rme96_capture_adat_open,
1537 .close = snd_rme96_capture_close,
1538 .ioctl = snd_pcm_lib_ioctl,
1539 .hw_params = snd_rme96_capture_hw_params,
1540 .prepare = snd_rme96_capture_prepare,
1541 .trigger = snd_rme96_capture_trigger,
1542 .pointer = snd_rme96_capture_pointer,
1543 .copy = snd_rme96_capture_copy,
1544 .mmap = snd_pcm_lib_mmap_iomem,
1545};
1546
1547static void
1548snd_rme96_free(void *private_data)
1549{
a3aefd88 1550 struct rme96 *rme96 = (struct rme96 *)private_data;
1da177e4
LT		 1551
1552 if (rme96 == NULL) {
1553 return;
1554 }
1555 if (rme96->irq >= 0) {
b892ca1c 1556 snd_rme96_trigger(rme96, RME96_STOP_BOTH);
1da177e4
LT		 1557 rme96->areg &= ~RME96_AR_DAC_EN;
1558 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1559 free_irq(rme96->irq, (void *)rme96);
1560 rme96->irq = -1;
1561 }
1562 if (rme96->iobase) {
1563 iounmap(rme96->iobase);
1564 rme96->iobase = NULL;
1565 }
1566 if (rme96->port) {
1567 pci_release_regions(rme96->pci);
1568 rme96->port = 0;
1569 }
a932be91 1570#ifdef CONFIG_PM_SLEEP
528ba522
KP		 1571 vfree(rme96->playback_suspend_buffer);
1572 vfree(rme96->capture_suspend_buffer);
1573#endif
1da177e4
LT		 1574 pci_disable_device(rme96->pci);
1575}
1576
1577static void
a3aefd88 1578snd_rme96_free_spdif_pcm(struct snd_pcm *pcm)
1da177e4 1579{
9fe856e4 1580 struct rme96 *rme96 = pcm->private_data;
1da177e4
LT		 1581 rme96->spdif_pcm = NULL;
1582}
1583
1584static void
a3aefd88 1585snd_rme96_free_adat_pcm(struct snd_pcm *pcm)
1da177e4 1586{
9fe856e4 1587 struct rme96 *rme96 = pcm->private_data;
1da177e4
LT		 1588 rme96->adat_pcm = NULL;
1589}
1590
e23e7a14 1591static int
a3aefd88 1592snd_rme96_create(struct rme96 *rme96)
1da177e4
LT		 1593{
1594 struct pci_dev *pci = rme96->pci;
1595 int err;
1596
1597 rme96->irq = -1;
1598 spin_lock_init(&rme96->lock);
1599
1600 if ((err = pci_enable_device(pci)) < 0)
1601 return err;
1602
1603 if ((err = pci_request_regions(pci, "RME96")) < 0)
1604 return err;
1605 rme96->port = pci_resource_start(rme96->pci, 0);
1606
44977b71
HH		 1607 rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE);
1608 if (!rme96->iobase) {
342cd934
TI		 1609 dev_err(rme96->card->dev,
1610 "unable to remap memory region 0x%lx-0x%lx\n",
1611 rme96->port, rme96->port + RME96_IO_SIZE - 1);
688956f2
TI		 1612 return -ENOMEM;
1613 }
1614
437a5a46 1615 if (request_irq(pci->irq, snd_rme96_interrupt, IRQF_SHARED,
934c2b6d 1616 KBUILD_MODNAME, rme96)) {
342cd934 1617 dev_err(rme96->card->dev, "unable to grab IRQ %d\n", pci->irq);
1da177e4
LT		 1618 return -EBUSY;
1619 }
1620 rme96->irq = pci->irq;
1621
1da177e4
LT		 1622 /* read the card's revision number */
1623 pci_read_config_byte(pci, 8, &rme96->rev);
1624
1625 /* set up ALSA pcm device for S/PDIF */
1626 if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1627 1, 1, &rme96->spdif_pcm)) < 0)
1628 {
1629 return err;
1630 }
1631 rme96->spdif_pcm->private_data = rme96;
1632 rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1633 strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1634 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1635 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1636
1637 rme96->spdif_pcm->info_flags = 0;
1638
1639 /* set up ALSA pcm device for ADAT */
8b7fc421 1640 if (pci->device == PCI_DEVICE_ID_RME_DIGI96) {
1da177e4
LT		 1641 /* ADAT is not available on the base model */
1642 rme96->adat_pcm = NULL;
1643 } else {
1644 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1645 1, 1, &rme96->adat_pcm)) < 0)
1646 {
1647 return err;
1648 }
1649 rme96->adat_pcm->private_data = rme96;
1650 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1651 strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1652 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1653 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1654
1655 rme96->adat_pcm->info_flags = 0;
1656 }
1657
1658 rme96->playback_periodsize = 0;
1659 rme96->capture_periodsize = 0;
1660
1661 /* make sure playback/capture is stopped, if by some reason active */
b892ca1c 1662 snd_rme96_trigger(rme96, RME96_STOP_BOTH);
1da177e4
LT		 1663
1664 /* set default values in registers */
1665 rme96->wcreg =
1666 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1667 RME96_WCR_SEL | /* normal playback */
1668 RME96_WCR_MASTER | /* set to master clock mode */
1669 RME96_WCR_INP_0; /* set coaxial input */
1670
1671 rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1672
1673 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1674 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1675
1676 /* reset the ADC */
1677 writel(rme96->areg | RME96_AR_PD2,
1678 rme96->iobase + RME96_IO_ADDITIONAL_REG);
1679 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1680
1681 /* reset and enable the DAC (order is important). */
1682 snd_rme96_reset_dac(rme96);
1683 rme96->areg |= RME96_AR_DAC_EN;
1684 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1685
1686 /* reset playback and record buffer pointers */
1687 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1688 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1689
1690 /* reset volume */
1691 rme96->vol[0] = rme96->vol[1] = 0;
1692 if (RME96_HAS_ANALOG_OUT(rme96)) {
1693 snd_rme96_apply_dac_volume(rme96);
1694 }
1695
1696 /* init switch interface */
1697 if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
1698 return err;
1699 }
1700
1701 /* init proc interface */
1702 snd_rme96_proc_init(rme96);
1703
1704 return 0;
1705}
1706
1707/*
1708 * proc interface
1709 */
1710
1711static void
a3aefd88 1712snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1da177e4
LT		 1713{
1714 int n;
9fe856e4 1715 struct rme96 *rme96 = entry->private_data;
1da177e4
LT		 1716
1717 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1718
1719 snd_iprintf(buffer, rme96->card->longname);
1720 snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1721
1722 snd_iprintf(buffer, "\nGeneral settings\n");
1723 if (rme96->wcreg & RME96_WCR_IDIS) {
1724 snd_iprintf(buffer, " period size: N/A (interrupts "
1725 "disabled)\n");
1726 } else if (rme96->wcreg & RME96_WCR_ISEL) {
1727 snd_iprintf(buffer, " period size: 2048 bytes\n");
1728 } else {
1729 snd_iprintf(buffer, " period size: 8192 bytes\n");
1730 }
1731 snd_iprintf(buffer, "\nInput settings\n");
1732 switch (snd_rme96_getinputtype(rme96)) {
1733 case RME96_INPUT_OPTICAL:
1734 snd_iprintf(buffer, " input: optical");
1735 break;
1736 case RME96_INPUT_COAXIAL:
1737 snd_iprintf(buffer, " input: coaxial");
1738 break;
1739 case RME96_INPUT_INTERNAL:
1740 snd_iprintf(buffer, " input: internal");
1741 break;
1742 case RME96_INPUT_XLR:
1743 snd_iprintf(buffer, " input: XLR");
1744 break;
1745 case RME96_INPUT_ANALOG:
1746 snd_iprintf(buffer, " input: analog");
1747 break;
1748 }
1749 if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1750 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1751 } else {
1752 if (n) {
1753 snd_iprintf(buffer, " (8 channels)\n");
1754 } else {
1755 snd_iprintf(buffer, " (2 channels)\n");
1756 }
1757 snd_iprintf(buffer, " sample rate: %d Hz\n",
1758 snd_rme96_capture_getrate(rme96, &n));
1759 }
1760 if (rme96->wcreg & RME96_WCR_MODE24_2) {
1761 snd_iprintf(buffer, " sample format: 24 bit\n");
1762 } else {
1763 snd_iprintf(buffer, " sample format: 16 bit\n");
1764 }
1765
1766 snd_iprintf(buffer, "\nOutput settings\n");
1767 if (rme96->wcreg & RME96_WCR_SEL) {
1768 snd_iprintf(buffer, " output signal: normal playback\n");
1769 } else {
1770 snd_iprintf(buffer, " output signal: same as input\n");
1771 }
1772 snd_iprintf(buffer, " sample rate: %d Hz\n",
1773 snd_rme96_playback_getrate(rme96));
1774 if (rme96->wcreg & RME96_WCR_MODE24) {
1775 snd_iprintf(buffer, " sample format: 24 bit\n");
1776 } else {
1777 snd_iprintf(buffer, " sample format: 16 bit\n");
1778 }
1779 if (rme96->areg & RME96_AR_WSEL) {
1780 snd_iprintf(buffer, " sample clock source: word clock\n");
1781 } else if (rme96->wcreg & RME96_WCR_MASTER) {
1782 snd_iprintf(buffer, " sample clock source: internal\n");
1783 } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1784 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n");
1785 } else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1786 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n");
1787 } else {
1788 snd_iprintf(buffer, " sample clock source: autosync\n");
1789 }
1790 if (rme96->wcreg & RME96_WCR_PRO) {
1791 snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1792 } else {
1793 snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1794 }
1795 if (rme96->wcreg & RME96_WCR_EMP) {
1796 snd_iprintf(buffer, " emphasis: on\n");
1797 } else {
1798 snd_iprintf(buffer, " emphasis: off\n");
1799 }
1800 if (rme96->wcreg & RME96_WCR_DOLBY) {
1801 snd_iprintf(buffer, " non-audio (dolby): on\n");
1802 } else {
1803 snd_iprintf(buffer, " non-audio (dolby): off\n");
1804 }
1805 if (RME96_HAS_ANALOG_IN(rme96)) {
1806 snd_iprintf(buffer, "\nAnalog output settings\n");
1807 switch (snd_rme96_getmontracks(rme96)) {
1808 case RME96_MONITOR_TRACKS_1_2:
1809 snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n");
1810 break;
1811 case RME96_MONITOR_TRACKS_3_4:
1812 snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n");
1813 break;
1814 case RME96_MONITOR_TRACKS_5_6:
1815 snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n");
1816 break;
1817 case RME96_MONITOR_TRACKS_7_8:
1818 snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n");
1819 break;
1820 }
1821 switch (snd_rme96_getattenuation(rme96)) {
1822 case RME96_ATTENUATION_0:
1823 snd_iprintf(buffer, " attenuation: 0 dB\n");
1824 break;
1825 case RME96_ATTENUATION_6:
1826 snd_iprintf(buffer, " attenuation: -6 dB\n");
1827 break;
1828 case RME96_ATTENUATION_12:
1829 snd_iprintf(buffer, " attenuation: -12 dB\n");
1830 break;
1831 case RME96_ATTENUATION_18:
1832 snd_iprintf(buffer, " attenuation: -18 dB\n");
1833 break;
1834 }
1835 snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]);
1836 snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]);
1837 }
1838}
1839
e23e7a14 1840static void snd_rme96_proc_init(struct rme96 *rme96)
1da177e4 1841{
a3aefd88 1842 struct snd_info_entry *entry;
1da177e4
LT		 1843
1844 if (! snd_card_proc_new(rme96->card, "rme96", &entry))
bf850204 1845 snd_info_set_text_ops(entry, rme96, snd_rme96_proc_read);
1da177e4
LT		 1846}
1847
1848/*
1849 * control interface
1850 */
1851
a5ce8890
TI		 1852#define snd_rme96_info_loopback_control snd_ctl_boolean_mono_info
1853
1da177e4 1854static int
a3aefd88 1855snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1856{
a3aefd88 1857 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1858
1859 spin_lock_irq(&rme96->lock);
1860 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1861 spin_unlock_irq(&rme96->lock);
1862 return 0;
1863}
1864static int
a3aefd88 1865snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1866{
a3aefd88 1867 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1868 unsigned int val;
1869 int change;
1870
1871 val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1872 spin_lock_irq(&rme96->lock);
1873 val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1874 change = val != rme96->wcreg;
1875 rme96->wcreg = val;
1876 writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1877 spin_unlock_irq(&rme96->lock);
1878 return change;
1879}
1880
1881static int
a3aefd88 1882snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4 1883{
9c30d46a
TI		 1884 static const char * const _texts[5] = {
1885 "Optical", "Coaxial", "Internal", "XLR", "Analog"
1886 };
a3aefd88 1887 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
9c30d46a
TI		 1888 const char *texts[5] = {
1889 _texts[0], _texts[1], _texts[2], _texts[3], _texts[4]
1890 };
1891 int num_items;
1da177e4 1892
1da177e4 1893 switch (rme96->pci->device) {
8b7fc421
RD		 1894 case PCI_DEVICE_ID_RME_DIGI96:
1895 case PCI_DEVICE_ID_RME_DIGI96_8:
9c30d46a 1896 num_items = 3;
1da177e4 1897 break;
8b7fc421 1898 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
9c30d46a 1899 num_items = 4;
1da177e4 1900 break;
8b7fc421 1901 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1da177e4
LT		 1902 if (rme96->rev > 4) {
1903 /* PST */
9c30d46a 1904 num_items = 4;
1da177e4
LT		 1905 texts[3] = _texts[4]; /* Analog instead of XLR */
1906 } else {
1907 /* PAD */
9c30d46a 1908 num_items = 5;
1da177e4
LT		 1909 }
1910 break;
1911 default:
1912 snd_BUG();
9c30d46a 1913 return -EINVAL;
1da177e4 1914 }
9c30d46a 1915 return snd_ctl_enum_info(uinfo, 1, num_items, texts);
1da177e4
LT		 1916}
1917static int
a3aefd88 1918snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1919{
a3aefd88 1920 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1921 unsigned int items = 3;
1922
1923 spin_lock_irq(&rme96->lock);
1924 ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
1925
1926 switch (rme96->pci->device) {
8b7fc421
RD		 1927 case PCI_DEVICE_ID_RME_DIGI96:
1928 case PCI_DEVICE_ID_RME_DIGI96_8:
1da177e4
LT		 1929 items = 3;
1930 break;
8b7fc421 1931 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1da177e4
LT		 1932 items = 4;
1933 break;
8b7fc421 1934 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1da177e4
LT		 1935 if (rme96->rev > 4) {
1936 /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
1937 if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
1938 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
1939 }
1940 items = 4;
1941 } else {
1942 items = 5;
1943 }
1944 break;
1945 default:
1946 snd_BUG();
1947 break;
1948 }
1949 if (ucontrol->value.enumerated.item[0] >= items) {
1950 ucontrol->value.enumerated.item[0] = items - 1;
1951 }
1952
1953 spin_unlock_irq(&rme96->lock);
1954 return 0;
1955}
1956static int
a3aefd88 1957snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1958{
a3aefd88 1959 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1960 unsigned int val;
1961 int change, items = 3;
1962
1963 switch (rme96->pci->device) {
8b7fc421
RD		 1964 case PCI_DEVICE_ID_RME_DIGI96:
1965 case PCI_DEVICE_ID_RME_DIGI96_8:
1da177e4
LT		 1966 items = 3;
1967 break;
8b7fc421 1968 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1da177e4
LT		 1969 items = 4;
1970 break;
8b7fc421 1971 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1da177e4
LT		 1972 if (rme96->rev > 4) {
1973 items = 4;
1974 } else {
1975 items = 5;
1976 }
1977 break;
1978 default:
1979 snd_BUG();
1980 break;
1981 }
1982 val = ucontrol->value.enumerated.item[0] % items;
1983
1984 /* special case for PST */
8b7fc421 1985 if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
1da177e4
LT		 1986 if (val == RME96_INPUT_XLR) {
1987 val = RME96_INPUT_ANALOG;
1988 }
1989 }
1990
1991 spin_lock_irq(&rme96->lock);
1992 change = (int)val != snd_rme96_getinputtype(rme96);
1993 snd_rme96_setinputtype(rme96, val);
1994 spin_unlock_irq(&rme96->lock);
1995 return change;
1996}
1997
1998static int
a3aefd88 1999snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4 2000{
9c30d46a 2001 static const char * const texts[3] = { "AutoSync", "Internal", "Word" };
1da177e4 2002
9c30d46a 2003 return snd_ctl_enum_info(uinfo, 1, 3, texts);
1da177e4
LT		 2004}
2005static int
a3aefd88 2006snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2007{
a3aefd88 2008 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2009
2010 spin_lock_irq(&rme96->lock);
2011 ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
2012 spin_unlock_irq(&rme96->lock);
2013 return 0;
2014}
2015static int
a3aefd88 2016snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2017{
a3aefd88 2018 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2019 unsigned int val;
2020 int change;
2021
2022 val = ucontrol->value.enumerated.item[0] % 3;
2023 spin_lock_irq(&rme96->lock);
2024 change = (int)val != snd_rme96_getclockmode(rme96);
2025 snd_rme96_setclockmode(rme96, val);
2026 spin_unlock_irq(&rme96->lock);
2027 return change;
2028}
2029
2030static int
a3aefd88 2031snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4 2032{
9c30d46a
TI		 2033 static const char * const texts[4] = {
2034 "0 dB", "-6 dB", "-12 dB", "-18 dB"
2035 };
1da177e4 2036
9c30d46a 2037 return snd_ctl_enum_info(uinfo, 1, 4, texts);
1da177e4
LT		 2038}
2039static int
a3aefd88 2040snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2041{
a3aefd88 2042 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2043
2044 spin_lock_irq(&rme96->lock);
2045 ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2046 spin_unlock_irq(&rme96->lock);
2047 return 0;
2048}
2049static int
a3aefd88 2050snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2051{
a3aefd88 2052 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2053 unsigned int val;
2054 int change;
2055
2056 val = ucontrol->value.enumerated.item[0] % 4;
2057 spin_lock_irq(&rme96->lock);
2058
2059 change = (int)val != snd_rme96_getattenuation(rme96);
2060 snd_rme96_setattenuation(rme96, val);
2061 spin_unlock_irq(&rme96->lock);
2062 return change;
2063}
2064
2065static int
a3aefd88 2066snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4 2067{
9c30d46a 2068 static const char * const texts[4] = { "1+2", "3+4", "5+6", "7+8" };
1da177e4 2069
9c30d46a 2070 return snd_ctl_enum_info(uinfo, 1, 4, texts);
1da177e4
LT		 2071}
2072static int
a3aefd88 2073snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2074{
a3aefd88 2075 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2076
2077 spin_lock_irq(&rme96->lock);
2078 ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2079 spin_unlock_irq(&rme96->lock);
2080 return 0;
2081}
2082static int
a3aefd88 2083snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2084{
a3aefd88 2085 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2086 unsigned int val;
2087 int change;
2088
2089 val = ucontrol->value.enumerated.item[0] % 4;
2090 spin_lock_irq(&rme96->lock);
2091 change = (int)val != snd_rme96_getmontracks(rme96);
2092 snd_rme96_setmontracks(rme96, val);
2093 spin_unlock_irq(&rme96->lock);
2094 return change;
2095}
2096
a3aefd88 2097static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes)
1da177e4
LT		 2098{
2099 u32 val = 0;
2100 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2101 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2102 if (val & RME96_WCR_PRO)
2103 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2104 else
2105 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2106 return val;
2107}
2108
a3aefd88 2109static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1da177e4
LT		 2110{
2111 aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2112 ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2113 if (val & RME96_WCR_PRO)
2114 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2115 else
2116 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2117}
2118
a3aefd88 2119static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2120{
2121 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2122 uinfo->count = 1;
2123 return 0;
2124}
2125
a3aefd88 2126static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2127{
a3aefd88 2128 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2129
2130 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2131 return 0;
2132}
2133
a3aefd88 2134static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2135{
a3aefd88 2136 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2137 int change;
2138 u32 val;
2139
2140 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2141 spin_lock_irq(&rme96->lock);
2142 change = val != rme96->wcreg_spdif;
2143 rme96->wcreg_spdif = val;
2144 spin_unlock_irq(&rme96->lock);
2145 return change;
2146}
2147
a3aefd88 2148static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2149{
2150 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2151 uinfo->count = 1;
2152 return 0;
2153}
2154
a3aefd88 2155static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2156{
a3aefd88 2157 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2158
2159 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2160 return 0;
2161}
2162
a3aefd88 2163static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2164{
a3aefd88 2165 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2166 int change;
2167 u32 val;
2168
2169 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2170 spin_lock_irq(&rme96->lock);
2171 change = val != rme96->wcreg_spdif_stream;
2172 rme96->wcreg_spdif_stream = val;
2173 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2174 rme96->wcreg |= val;
2175 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2176 spin_unlock_irq(&rme96->lock);
2177 return change;
2178}
2179
a3aefd88 2180static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2181{
2182 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2183 uinfo->count = 1;
2184 return 0;
2185}
2186
a3aefd88 2187static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 2188{
2189 ucontrol->value.iec958.status[0] = kcontrol->private_value;
2190 return 0;
2191}
2192
2193static int
a3aefd88 2194snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4 2195{
a3aefd88 2196 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2197
2198 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2199 uinfo->count = 2;
2200 uinfo->value.integer.min = 0;
2201 uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2202 return 0;
2203}
2204
2205static int
a3aefd88 2206snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
1da177e4 2207{
a3aefd88 2208 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2209
2210 spin_lock_irq(&rme96->lock);
2211 u->value.integer.value[0] = rme96->vol[0];
2212 u->value.integer.value[1] = rme96->vol[1];
2213 spin_unlock_irq(&rme96->lock);
2214
2215 return 0;
2216}
2217
2218static int
a3aefd88 2219snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
1da177e4 2220{
a3aefd88 2221 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4 2222 int change = 0;
4e98d6a7 2223 unsigned int vol, maxvol;
1da177e4 2224
4e98d6a7
TI		 2225
2226 if (!RME96_HAS_ANALOG_OUT(rme96))
1da177e4 2227 return -EINVAL;
4e98d6a7 2228 maxvol = RME96_185X_MAX_OUT(rme96);
1da177e4 2229 spin_lock_irq(&rme96->lock);
4e98d6a7
TI		 2230 vol = u->value.integer.value[0];
2231 if (vol != rme96->vol[0] && vol <= maxvol) {
2232 rme96->vol[0] = vol;
2233 change = 1;
2234 }
2235 vol = u->value.integer.value[1];
2236 if (vol != rme96->vol[1] && vol <= maxvol) {
2237 rme96->vol[1] = vol;
2238 change = 1;
1da177e4 2239 }
4e98d6a7
TI		 2240 if (change)
2241 snd_rme96_apply_dac_volume(rme96);
1da177e4
LT		 2242 spin_unlock_irq(&rme96->lock);
2243
2244 return change;
2245}
2246
a3aefd88 2247static struct snd_kcontrol_new snd_rme96_controls[] = {
1da177e4
LT		 2248{
2249 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2250 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2251 .info = snd_rme96_control_spdif_info,
2252 .get = snd_rme96_control_spdif_get,
2253 .put = snd_rme96_control_spdif_put
2254},
2255{
2256 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2257 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2258 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2259 .info = snd_rme96_control_spdif_stream_info,
2260 .get = snd_rme96_control_spdif_stream_get,
2261 .put = snd_rme96_control_spdif_stream_put
2262},
2263{
2264 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 2265 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 2266 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2267 .info = snd_rme96_control_spdif_mask_info,
2268 .get = snd_rme96_control_spdif_mask_get,
2269 .private_value = IEC958_AES0_NONAUDIO |
2270 IEC958_AES0_PROFESSIONAL |
2271 IEC958_AES0_CON_EMPHASIS
2272},
2273{
2274 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 2275 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 2276 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2277 .info = snd_rme96_control_spdif_mask_info,
2278 .get = snd_rme96_control_spdif_mask_get,
2279 .private_value = IEC958_AES0_NONAUDIO |
2280 IEC958_AES0_PROFESSIONAL |
2281 IEC958_AES0_PRO_EMPHASIS
2282},
2283{
2284 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2285 .name = "Input Connector",
2286 .info = snd_rme96_info_inputtype_control,
2287 .get = snd_rme96_get_inputtype_control,
2288 .put = snd_rme96_put_inputtype_control
2289},
2290{
2291 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2292 .name = "Loopback Input",
2293 .info = snd_rme96_info_loopback_control,
2294 .get = snd_rme96_get_loopback_control,
2295 .put = snd_rme96_put_loopback_control
2296},
2297{
2298 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2299 .name = "Sample Clock Source",
2300 .info = snd_rme96_info_clockmode_control,
2301 .get = snd_rme96_get_clockmode_control,
2302 .put = snd_rme96_put_clockmode_control
2303},
2304{
2305 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2306 .name = "Monitor Tracks",
2307 .info = snd_rme96_info_montracks_control,
2308 .get = snd_rme96_get_montracks_control,
2309 .put = snd_rme96_put_montracks_control
2310},
2311{
2312 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2313 .name = "Attenuation",
2314 .info = snd_rme96_info_attenuation_control,
2315 .get = snd_rme96_get_attenuation_control,
2316 .put = snd_rme96_put_attenuation_control
2317},
2318{
2319 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2320 .name = "DAC Playback Volume",
2321 .info = snd_rme96_dac_volume_info,
2322 .get = snd_rme96_dac_volume_get,
2323 .put = snd_rme96_dac_volume_put
2324}
2325};
2326
2327static int
a3aefd88
TI		 2328snd_rme96_create_switches(struct snd_card *card,
2329 struct rme96 *rme96)
1da177e4
LT		 2330{
2331 int idx, err;
a3aefd88 2332 struct snd_kcontrol *kctl;
1da177e4
LT		 2333
2334 for (idx = 0; idx < 7; idx++) {
2335 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2336 return err;
2337 if (idx == 1) /* IEC958 (S/PDIF) Stream */
2338 rme96->spdif_ctl = kctl;
2339 }
2340
2341 if (RME96_HAS_ANALOG_OUT(rme96)) {
2342 for (idx = 7; idx < 10; idx++)
2343 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2344 return err;
2345 }
2346
2347 return 0;
2348}
2349
2350/*
2351 * Card initialisation
2352 */
2353
a932be91 2354#ifdef CONFIG_PM_SLEEP
528ba522 2355
a932be91 2356static int rme96_suspend(struct device *dev)
528ba522 2357{
a932be91 2358 struct snd_card *card = dev_get_drvdata(dev);
528ba522
KP		 2359 struct rme96 *rme96 = card->private_data;
2360
2361 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2362 snd_pcm_suspend(rme96->playback_substream);
2363 snd_pcm_suspend(rme96->capture_substream);
2364
2365 /* save capture & playback pointers */
2366 rme96->playback_pointer = readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
2367 & RME96_RCR_AUDIO_ADDR_MASK;
2368 rme96->capture_pointer = readl(rme96->iobase + RME96_IO_GET_REC_POS)
2369 & RME96_RCR_AUDIO_ADDR_MASK;
2370
2371 /* save playback and capture buffers */
2372 memcpy_fromio(rme96->playback_suspend_buffer,
2373 rme96->iobase + RME96_IO_PLAY_BUFFER, RME96_BUFFER_SIZE);
2374 memcpy_fromio(rme96->capture_suspend_buffer,
2375 rme96->iobase + RME96_IO_REC_BUFFER, RME96_BUFFER_SIZE);
2376
2377 /* disable the DAC */
2378 rme96->areg &= ~RME96_AR_DAC_EN;
2379 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
528ba522
KP		 2380 return 0;
2381}
2382
a932be91 2383static int rme96_resume(struct device *dev)
528ba522 2384{
a932be91 2385 struct snd_card *card = dev_get_drvdata(dev);
528ba522
KP		 2386 struct rme96 *rme96 = card->private_data;
2387
528ba522
KP		 2388 /* reset playback and record buffer pointers */
2389 writel(0, rme96->iobase + RME96_IO_SET_PLAY_POS
2390 + rme96->playback_pointer);
2391 writel(0, rme96->iobase + RME96_IO_SET_REC_POS
2392 + rme96->capture_pointer);
2393
2394 /* restore playback and capture buffers */
2395 memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER,
2396 rme96->playback_suspend_buffer, RME96_BUFFER_SIZE);
2397 memcpy_toio(rme96->iobase + RME96_IO_REC_BUFFER,
2398 rme96->capture_suspend_buffer, RME96_BUFFER_SIZE);
2399
2400 /* reset the ADC */
2401 writel(rme96->areg | RME96_AR_PD2,
2402 rme96->iobase + RME96_IO_ADDITIONAL_REG);
2403 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2404
2405 /* reset and enable DAC, restore analog volume */
2406 snd_rme96_reset_dac(rme96);
2407 rme96->areg |= RME96_AR_DAC_EN;
2408 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2409 if (RME96_HAS_ANALOG_OUT(rme96)) {
2410 usleep_range(3000, 10000);
2411 snd_rme96_apply_dac_volume(rme96);
2412 }
2413
2414 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2415
2416 return 0;
2417}
2418
a932be91
TI		 2419static SIMPLE_DEV_PM_OPS(rme96_pm, rme96_suspend, rme96_resume);
2420#define RME96_PM_OPS &rme96_pm
2421#else
2422#define RME96_PM_OPS NULL
2423#endif /* CONFIG_PM_SLEEP */
528ba522 2424
a3aefd88 2425static void snd_rme96_card_free(struct snd_card *card)
1da177e4
LT		 2426{
2427 snd_rme96_free(card->private_data);
2428}
2429
e23e7a14 2430static int
1da177e4
LT		 2431snd_rme96_probe(struct pci_dev *pci,
2432 const struct pci_device_id *pci_id)
2433{
2434 static int dev;
a3aefd88
TI		 2435 struct rme96 *rme96;
2436 struct snd_card *card;
1da177e4
LT		 2437 int err;
2438 u8 val;
2439
2440 if (dev >= SNDRV_CARDS) {
2441 return -ENODEV;
2442 }
2443 if (!enable[dev]) {
2444 dev++;
2445 return -ENOENT;
2446 }
60c5772b
TI		 2447 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2448 sizeof(struct rme96), &card);
e58de7ba
TI		 2449 if (err < 0)
2450 return err;
1da177e4 2451 card->private_free = snd_rme96_card_free;
9fe856e4 2452 rme96 = card->private_data;
1da177e4
LT		 2453 rme96->card = card;
2454 rme96->pci = pci;
1da177e4
LT		 2455 if ((err = snd_rme96_create(rme96)) < 0) {
2456 snd_card_free(card);
2457 return err;
2458 }
2459
a932be91 2460#ifdef CONFIG_PM_SLEEP
528ba522
KP		 2461 rme96->playback_suspend_buffer = vmalloc(RME96_BUFFER_SIZE);
2462 if (!rme96->playback_suspend_buffer) {
342cd934 2463 dev_err(card->dev,
528ba522
KP		 2464 "Failed to allocate playback suspend buffer!\n");
2465 snd_card_free(card);
2466 return -ENOMEM;
2467 }
2468 rme96->capture_suspend_buffer = vmalloc(RME96_BUFFER_SIZE);
2469 if (!rme96->capture_suspend_buffer) {
342cd934 2470 dev_err(card->dev,
528ba522
KP		 2471 "Failed to allocate capture suspend buffer!\n");
2472 snd_card_free(card);
2473 return -ENOMEM;
2474 }
2475#endif
2476
1da177e4
LT		 2477 strcpy(card->driver, "Digi96");
2478 switch (rme96->pci->device) {
8b7fc421 2479 case PCI_DEVICE_ID_RME_DIGI96:
1da177e4
LT		 2480 strcpy(card->shortname, "RME Digi96");
2481 break;
8b7fc421 2482 case PCI_DEVICE_ID_RME_DIGI96_8:
1da177e4
LT		 2483 strcpy(card->shortname, "RME Digi96/8");
2484 break;
8b7fc421 2485 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1da177e4
LT		 2486 strcpy(card->shortname, "RME Digi96/8 PRO");
2487 break;
8b7fc421 2488 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1da177e4
LT		 2489 pci_read_config_byte(rme96->pci, 8, &val);
2490 if (val < 5) {
2491 strcpy(card->shortname, "RME Digi96/8 PAD");
2492 } else {
2493 strcpy(card->shortname, "RME Digi96/8 PST");
2494 }
2495 break;
2496 }
2497 sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2498 rme96->port, rme96->irq);
2499
2500 if ((err = snd_card_register(card)) < 0) {
2501 snd_card_free(card);
2502 return err;
2503 }
2504 pci_set_drvdata(pci, card);
2505 dev++;
2506 return 0;
2507}
2508
e23e7a14 2509static void snd_rme96_remove(struct pci_dev *pci)
1da177e4
LT		 2510{
2511 snd_card_free(pci_get_drvdata(pci));
1da177e4
LT		 2512}
2513
e9f66d9b 2514static struct pci_driver rme96_driver = {
3733e424 2515 .name = KBUILD_MODNAME,
1da177e4
LT		 2516 .id_table = snd_rme96_ids,
2517 .probe = snd_rme96_probe,
e23e7a14 2518 .remove = snd_rme96_remove,
a932be91
TI		 2519 .driver = {
2520 .pm = RME96_PM_OPS,
2521 },
1da177e4
LT		 2522};
2523
e9f66d9b 2524module_pci_driver(rme96_driver);
Linux 6.x block layer and io_uring tree(s)