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[ALSA] Fix invalid assignment of PCI revision
[linux-2.6-block.git] / sound / pci / rme32.c
CommitLineData
1da177e4
LT		 1/*
2 * ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces
3 *
4 * Copyright (c) 2002-2004 Martin Langer <martin-langer@gmx.de>,
5 * Pilo Chambert <pilo.c@wanadoo.fr>
6 *
7 * Thanks to : Anders Torger <torger@ludd.luth.se>,
8 * Henk Hesselink <henk@anda.nl>
9 * for writing the digi96-driver
10 * and RME for all informations.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * ****************************************************************************
28 *
29 * Note #1 "Sek'd models" ................................... martin 2002-12-07
30 *
31 * Identical soundcards by Sek'd were labeled:
32 * RME Digi 32 = Sek'd Prodif 32
33 * RME Digi 32 Pro = Sek'd Prodif 96
34 * RME Digi 32/8 = Sek'd Prodif Gold
35 *
36 * ****************************************************************************
37 *
38 * Note #2 "full duplex mode" ............................... martin 2002-12-07
39 *
40 * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical
41 * in this mode. Rec data and play data are using the same buffer therefore. At
42 * first you have got the playing bits in the buffer and then (after playing
43 * them) they were overwitten by the captured sound of the CS8412/14. Both
44 * modes (play/record) are running harmonically hand in hand in the same buffer
45 * and you have only one start bit plus one interrupt bit to control this
46 * paired action.
47 * This is opposite to the latter rme96 where playing and capturing is totally
48 * separated and so their full duplex mode is supported by alsa (using two
49 * start bits and two interrupts for two different buffers).
50 * But due to the wrong sequence of playing and capturing ALSA shows no solved
51 * full duplex support for the rme32 at the moment. That's bad, but I'm not
52 * able to solve it. Are you motivated enough to solve this problem now? Your
53 * patch would be welcome!
54 *
55 * ****************************************************************************
56 *
57 * "The story after the long seeking" -- tiwai
58 *
59 * Ok, the situation regarding the full duplex is now improved a bit.
60 * In the fullduplex mode (given by the module parameter), the hardware buffer
61 * is split to halves for read and write directions at the DMA pointer.
62 * That is, the half above the current DMA pointer is used for write, and
63 * the half below is used for read. To mangle this strange behavior, an
64 * software intermediate buffer is introduced. This is, of course, not good
65 * from the viewpoint of the data transfer efficiency. However, this allows
66 * you to use arbitrary buffer sizes, instead of the fixed I/O buffer size.
67 *
68 * ****************************************************************************
69 */
70
71
72#include <sound/driver.h>
73#include <linux/delay.h>
74#include <linux/init.h>
75#include <linux/interrupt.h>
76#include <linux/pci.h>
77#include <linux/slab.h>
78#include <linux/moduleparam.h>
79
80#include <sound/core.h>
81#include <sound/info.h>
82#include <sound/control.h>
83#include <sound/pcm.h>
84#include <sound/pcm_params.h>
85#include <sound/pcm-indirect.h>
86#include <sound/asoundef.h>
87#include <sound/initval.h>
88
89#include <asm/io.h>
90
91static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
92static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
93static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
94static int fullduplex[SNDRV_CARDS]; // = {[0 ... (SNDRV_CARDS - 1)] = 1};
95
96module_param_array(index, int, NULL, 0444);
97MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard.");
98module_param_array(id, charp, NULL, 0444);
99MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard.");
100module_param_array(enable, bool, NULL, 0444);
101MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard.");
102module_param_array(fullduplex, bool, NULL, 0444);
103MODULE_PARM_DESC(fullduplex, "Support full-duplex mode.");
104MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>, Pilo Chambert <pilo.c@wanadoo.fr>");
105MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO");
106MODULE_LICENSE("GPL");
107MODULE_SUPPORTED_DEVICE("{{RME,Digi32}," "{RME,Digi32/8}," "{RME,Digi32 PRO}}");
108
109/* Defines for RME Digi32 series */
110#define RME32_SPDIF_NCHANNELS 2
111
112/* Playback and capture buffer size */
113#define RME32_BUFFER_SIZE 0x20000
114
115/* IO area size */
116#define RME32_IO_SIZE 0x30000
117
118/* IO area offsets */
119#define RME32_IO_DATA_BUFFER 0x0
120#define RME32_IO_CONTROL_REGISTER 0x20000
121#define RME32_IO_GET_POS 0x20000
122#define RME32_IO_CONFIRM_ACTION_IRQ 0x20004
123#define RME32_IO_RESET_POS 0x20100
124
125/* Write control register bits */
126#define RME32_WCR_START (1 << 0) /* startbit */
127#define RME32_WCR_MONO (1 << 1) /* 0=stereo, 1=mono
128 Setting the whole card to mono
129 doesn't seem to be very useful.
130 A software-solution can handle
131 full-duplex with one direction in
132 stereo and the other way in mono.
133 So, the hardware should work all
134 the time in stereo! */
135#define RME32_WCR_MODE24 (1 << 2) /* 0=16bit, 1=32bit */
136#define RME32_WCR_SEL (1 << 3) /* 0=input on output, 1=normal playback/capture */
137#define RME32_WCR_FREQ_0 (1 << 4) /* frequency (play) */
138#define RME32_WCR_FREQ_1 (1 << 5)
139#define RME32_WCR_INP_0 (1 << 6) /* input switch */
140#define RME32_WCR_INP_1 (1 << 7)
141#define RME32_WCR_RESET (1 << 8) /* Reset address */
142#define RME32_WCR_MUTE (1 << 9) /* digital mute for output */
143#define RME32_WCR_PRO (1 << 10) /* 1=professional, 0=consumer */
144#define RME32_WCR_DS_BM (1 << 11) /* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */
145#define RME32_WCR_ADAT (1 << 12) /* Adat Mode (only Adat-Version) */
146#define RME32_WCR_AUTOSYNC (1 << 13) /* AutoSync */
147#define RME32_WCR_PD (1 << 14) /* DAC Reset (only PRO-Version) */
148#define RME32_WCR_EMP (1 << 15) /* 1=Emphasis on (only PRO-Version) */
149
150#define RME32_WCR_BITPOS_FREQ_0 4
151#define RME32_WCR_BITPOS_FREQ_1 5
152#define RME32_WCR_BITPOS_INP_0 6
153#define RME32_WCR_BITPOS_INP_1 7
154
155/* Read control register bits */
156#define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff
157#define RME32_RCR_LOCK (1 << 23) /* 1=locked, 0=not locked */
158#define RME32_RCR_ERF (1 << 26) /* 1=Error, 0=no Error */
159#define RME32_RCR_FREQ_0 (1 << 27) /* CS841x frequency (record) */
160#define RME32_RCR_FREQ_1 (1 << 28)
161#define RME32_RCR_FREQ_2 (1 << 29)
162#define RME32_RCR_KMODE (1 << 30) /* card mode: 1=PLL, 0=quartz */
163#define RME32_RCR_IRQ (1 << 31) /* interrupt */
164
165#define RME32_RCR_BITPOS_F0 27
166#define RME32_RCR_BITPOS_F1 28
167#define RME32_RCR_BITPOS_F2 29
168
169/* Input types */
170#define RME32_INPUT_OPTICAL 0
171#define RME32_INPUT_COAXIAL 1
172#define RME32_INPUT_INTERNAL 2
173#define RME32_INPUT_XLR 3
174
175/* Clock modes */
176#define RME32_CLOCKMODE_SLAVE 0
177#define RME32_CLOCKMODE_MASTER_32 1
178#define RME32_CLOCKMODE_MASTER_44 2
179#define RME32_CLOCKMODE_MASTER_48 3
180
181/* Block sizes in bytes */
182#define RME32_BLOCK_SIZE 8192
183
184/* Software intermediate buffer (max) size */
185#define RME32_MID_BUFFER_SIZE (1024*1024)
186
187/* Hardware revisions */
188#define RME32_32_REVISION 192
189#define RME32_328_REVISION_OLD 100
190#define RME32_328_REVISION_NEW 101
191#define RME32_PRO_REVISION_WITH_8412 192
192#define RME32_PRO_REVISION_WITH_8414 150
193
194
017ce802 195struct rme32 {
1da177e4
LT		 196 spinlock_t lock;
197 int irq;
198 unsigned long port;
199 void __iomem *iobase;
200
201 u32 wcreg; /* cached write control register value */
202 u32 wcreg_spdif; /* S/PDIF setup */
203 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
204 u32 rcreg; /* cached read control register value */
205
206 u8 rev; /* card revision number */
207
017ce802
TI		 208 struct snd_pcm_substream *playback_substream;
209 struct snd_pcm_substream *capture_substream;
1da177e4
LT		 210
211 int playback_frlog; /* log2 of framesize */
212 int capture_frlog;
213
214 size_t playback_periodsize; /* in bytes, zero if not used */
215 size_t capture_periodsize; /* in bytes, zero if not used */
216
217 unsigned int fullduplex_mode;
218 int running;
219
017ce802
TI		 220 struct snd_pcm_indirect playback_pcm;
221 struct snd_pcm_indirect capture_pcm;
1da177e4 222
017ce802
TI		 223 struct snd_card *card;
224 struct snd_pcm *spdif_pcm;
225 struct snd_pcm *adat_pcm;
1da177e4 226 struct pci_dev *pci;
017ce802
TI		 227 struct snd_kcontrol *spdif_ctl;
228};
1da177e4 229
f40b6890 230static struct pci_device_id snd_rme32_ids[] = {
8b7fc421 231 {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_RME_DIGI32,
1da177e4 232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
8b7fc421 233 {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_8,
1da177e4 234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
8b7fc421 235 {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_PRO,
1da177e4
LT		 236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
237 {0,}
238};
239
240MODULE_DEVICE_TABLE(pci, snd_rme32_ids);
241
242#define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START)
8b7fc421 243#define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414)
1da177e4 244
017ce802 245static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream);
1da177e4 246
017ce802 247static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream);
1da177e4 248
017ce802 249static int snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd);
1da177e4 250
017ce802 251static void snd_rme32_proc_init(struct rme32 * rme32);
1da177e4 252
017ce802 253static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32);
1da177e4 254
017ce802 255static inline unsigned int snd_rme32_pcm_byteptr(struct rme32 * rme32)
1da177e4
LT		 256{
257 return (readl(rme32->iobase + RME32_IO_GET_POS)
258 & RME32_RCR_AUDIO_ADDR_MASK);
259}
260
261static int snd_rme32_ratecode(int rate)
262{
263 switch (rate) {
264 case 32000: return SNDRV_PCM_RATE_32000;
265 case 44100: return SNDRV_PCM_RATE_44100;
266 case 48000: return SNDRV_PCM_RATE_48000;
267 case 64000: return SNDRV_PCM_RATE_64000;
268 case 88200: return SNDRV_PCM_RATE_88200;
269 case 96000: return SNDRV_PCM_RATE_96000;
270 }
271 return 0;
272}
273
274/* silence callback for halfduplex mode */
017ce802 275static int snd_rme32_playback_silence(struct snd_pcm_substream *substream, int channel, /* not used (interleaved data) */
1da177e4
LT		 276 snd_pcm_uframes_t pos,
277 snd_pcm_uframes_t count)
278{
017ce802 279 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 280 count <<= rme32->playback_frlog;
281 pos <<= rme32->playback_frlog;
282 memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count);
283 return 0;
284}
285
286/* copy callback for halfduplex mode */
017ce802 287static int snd_rme32_playback_copy(struct snd_pcm_substream *substream, int channel, /* not used (interleaved data) */
1da177e4
LT		 288 snd_pcm_uframes_t pos,
289 void __user *src, snd_pcm_uframes_t count)
290{
017ce802 291 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 292 count <<= rme32->playback_frlog;
293 pos <<= rme32->playback_frlog;
294 if (copy_from_user_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos,
295 src, count))
296 return -EFAULT;
297 return 0;
298}
299
300/* copy callback for halfduplex mode */
017ce802 301static int snd_rme32_capture_copy(struct snd_pcm_substream *substream, int channel, /* not used (interleaved data) */
1da177e4
LT		 302 snd_pcm_uframes_t pos,
303 void __user *dst, snd_pcm_uframes_t count)
304{
017ce802 305 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 306 count <<= rme32->capture_frlog;
307 pos <<= rme32->capture_frlog;
308 if (copy_to_user_fromio(dst,
309 rme32->iobase + RME32_IO_DATA_BUFFER + pos,
310 count))
311 return -EFAULT;
312 return 0;
313}
314
315/*
7f927fcc 316 * SPDIF I/O capabilities (half-duplex mode)
1da177e4 317 */
017ce802 318static struct snd_pcm_hardware snd_rme32_spdif_info = {
1da177e4
LT		 319 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
320 SNDRV_PCM_INFO_MMAP_VALID |
321 SNDRV_PCM_INFO_INTERLEAVED |
322 SNDRV_PCM_INFO_PAUSE |
323 SNDRV_PCM_INFO_SYNC_START),
324 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
325 SNDRV_PCM_FMTBIT_S32_LE),
326 .rates = (SNDRV_PCM_RATE_32000 |
327 SNDRV_PCM_RATE_44100 |
328 SNDRV_PCM_RATE_48000),
329 .rate_min = 32000,
330 .rate_max = 48000,
331 .channels_min = 2,
332 .channels_max = 2,
333 .buffer_bytes_max = RME32_BUFFER_SIZE,
334 .period_bytes_min = RME32_BLOCK_SIZE,
335 .period_bytes_max = RME32_BLOCK_SIZE,
336 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
337 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
338 .fifo_size = 0,
339};
340
341/*
7f927fcc 342 * ADAT I/O capabilities (half-duplex mode)
1da177e4 343 */
017ce802 344static struct snd_pcm_hardware snd_rme32_adat_info =
1da177e4
LT		 345{
346 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
347 SNDRV_PCM_INFO_MMAP_VALID |
348 SNDRV_PCM_INFO_INTERLEAVED |
349 SNDRV_PCM_INFO_PAUSE |
350 SNDRV_PCM_INFO_SYNC_START),
351 .formats= SNDRV_PCM_FMTBIT_S16_LE,
352 .rates = (SNDRV_PCM_RATE_44100 |
353 SNDRV_PCM_RATE_48000),
354 .rate_min = 44100,
355 .rate_max = 48000,
356 .channels_min = 8,
357 .channels_max = 8,
358 .buffer_bytes_max = RME32_BUFFER_SIZE,
359 .period_bytes_min = RME32_BLOCK_SIZE,
360 .period_bytes_max = RME32_BLOCK_SIZE,
361 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
362 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
363 .fifo_size = 0,
364};
365
366/*
7f927fcc 367 * SPDIF I/O capabilities (full-duplex mode)
1da177e4 368 */
017ce802 369static struct snd_pcm_hardware snd_rme32_spdif_fd_info = {
1da177e4
LT		 370 .info = (SNDRV_PCM_INFO_MMAP |
371 SNDRV_PCM_INFO_MMAP_VALID |
372 SNDRV_PCM_INFO_INTERLEAVED |
373 SNDRV_PCM_INFO_PAUSE |
374 SNDRV_PCM_INFO_SYNC_START),
375 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
376 SNDRV_PCM_FMTBIT_S32_LE),
377 .rates = (SNDRV_PCM_RATE_32000 |
378 SNDRV_PCM_RATE_44100 |
379 SNDRV_PCM_RATE_48000),
380 .rate_min = 32000,
381 .rate_max = 48000,
382 .channels_min = 2,
383 .channels_max = 2,
384 .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
385 .period_bytes_min = RME32_BLOCK_SIZE,
386 .period_bytes_max = RME32_BLOCK_SIZE,
387 .periods_min = 2,
388 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
389 .fifo_size = 0,
390};
391
392/*
7f927fcc 393 * ADAT I/O capabilities (full-duplex mode)
1da177e4 394 */
017ce802 395static struct snd_pcm_hardware snd_rme32_adat_fd_info =
1da177e4
LT		 396{
397 .info = (SNDRV_PCM_INFO_MMAP |
398 SNDRV_PCM_INFO_MMAP_VALID |
399 SNDRV_PCM_INFO_INTERLEAVED |
400 SNDRV_PCM_INFO_PAUSE |
401 SNDRV_PCM_INFO_SYNC_START),
402 .formats= SNDRV_PCM_FMTBIT_S16_LE,
403 .rates = (SNDRV_PCM_RATE_44100 |
404 SNDRV_PCM_RATE_48000),
405 .rate_min = 44100,
406 .rate_max = 48000,
407 .channels_min = 8,
408 .channels_max = 8,
409 .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
410 .period_bytes_min = RME32_BLOCK_SIZE,
411 .period_bytes_max = RME32_BLOCK_SIZE,
412 .periods_min = 2,
413 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
414 .fifo_size = 0,
415};
416
017ce802 417static void snd_rme32_reset_dac(struct rme32 *rme32)
1da177e4
LT		 418{
419 writel(rme32->wcreg | RME32_WCR_PD,
420 rme32->iobase + RME32_IO_CONTROL_REGISTER);
421 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
422}
423
017ce802 424static int snd_rme32_playback_getrate(struct rme32 * rme32)
1da177e4
LT		 425{
426 int rate;
427
428 rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
429 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
430 switch (rate) {
431 case 1:
432 rate = 32000;
433 break;
434 case 2:
435 rate = 44100;
436 break;
437 case 3:
438 rate = 48000;
439 break;
440 default:
441 return -1;
442 }
443 return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate;
444}
445
017ce802 446static int snd_rme32_capture_getrate(struct rme32 * rme32, int *is_adat)
1da177e4
LT		 447{
448 int n;
449
450 *is_adat = 0;
451 if (rme32->rcreg & RME32_RCR_LOCK) {
452 /* ADAT rate */
453 *is_adat = 1;
454 }
455 if (rme32->rcreg & RME32_RCR_ERF) {
456 return -1;
457 }
458
459 /* S/PDIF rate */
460 n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) +
461 (((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) +
462 (((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2);
463
464 if (RME32_PRO_WITH_8414(rme32))
465 switch (n) { /* supporting the CS8414 */
466 case 0:
467 case 1:
468 case 2:
469 return -1;
470 case 3:
471 return 96000;
472 case 4:
473 return 88200;
474 case 5:
475 return 48000;
476 case 6:
477 return 44100;
478 case 7:
479 return 32000;
480 default:
481 return -1;
482 break;
483 }
484 else
485 switch (n) { /* supporting the CS8412 */
486 case 0:
487 return -1;
488 case 1:
489 return 48000;
490 case 2:
491 return 44100;
492 case 3:
493 return 32000;
494 case 4:
495 return 48000;
496 case 5:
497 return 44100;
498 case 6:
499 return 44056;
500 case 7:
501 return 32000;
502 default:
503 break;
504 }
505 return -1;
506}
507
017ce802 508static int snd_rme32_playback_setrate(struct rme32 * rme32, int rate)
1da177e4
LT		 509{
510 int ds;
511
512 ds = rme32->wcreg & RME32_WCR_DS_BM;
513 switch (rate) {
514 case 32000:
515 rme32->wcreg &= ~RME32_WCR_DS_BM;
516 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
517 ~RME32_WCR_FREQ_1;
518 break;
519 case 44100:
520 rme32->wcreg &= ~RME32_WCR_DS_BM;
521 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
522 ~RME32_WCR_FREQ_0;
523 break;
524 case 48000:
525 rme32->wcreg &= ~RME32_WCR_DS_BM;
526 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
527 RME32_WCR_FREQ_1;
528 break;
529 case 64000:
8b7fc421 530 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
1da177e4
LT		 531 return -EINVAL;
532 rme32->wcreg |= RME32_WCR_DS_BM;
533 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
534 ~RME32_WCR_FREQ_1;
535 break;
536 case 88200:
8b7fc421 537 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
1da177e4
LT		 538 return -EINVAL;
539 rme32->wcreg |= RME32_WCR_DS_BM;
540 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
541 ~RME32_WCR_FREQ_0;
542 break;
543 case 96000:
8b7fc421 544 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
1da177e4
LT		 545 return -EINVAL;
546 rme32->wcreg |= RME32_WCR_DS_BM;
547 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
548 RME32_WCR_FREQ_1;
549 break;
550 default:
551 return -EINVAL;
552 }
553 if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) ||
554 (ds && !(rme32->wcreg & RME32_WCR_DS_BM)))
555 {
556 /* change to/from double-speed: reset the DAC (if available) */
557 snd_rme32_reset_dac(rme32);
558 } else {
559 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
560 }
561 return 0;
562}
563
017ce802 564static int snd_rme32_setclockmode(struct rme32 * rme32, int mode)
1da177e4
LT		 565{
566 switch (mode) {
567 case RME32_CLOCKMODE_SLAVE:
568 /* AutoSync */
569 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) &
570 ~RME32_WCR_FREQ_1;
571 break;
572 case RME32_CLOCKMODE_MASTER_32:
573 /* Internal 32.0kHz */
574 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
575 ~RME32_WCR_FREQ_1;
576 break;
577 case RME32_CLOCKMODE_MASTER_44:
578 /* Internal 44.1kHz */
579 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) |
580 RME32_WCR_FREQ_1;
581 break;
582 case RME32_CLOCKMODE_MASTER_48:
583 /* Internal 48.0kHz */
584 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
585 RME32_WCR_FREQ_1;
586 break;
587 default:
588 return -EINVAL;
589 }
590 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
591 return 0;
592}
593
017ce802 594static int snd_rme32_getclockmode(struct rme32 * rme32)
1da177e4
LT		 595{
596 return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
597 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
598}
599
017ce802 600static int snd_rme32_setinputtype(struct rme32 * rme32, int type)
1da177e4
LT		 601{
602 switch (type) {
603 case RME32_INPUT_OPTICAL:
604 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) &
605 ~RME32_WCR_INP_1;
606 break;
607 case RME32_INPUT_COAXIAL:
608 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) &
609 ~RME32_WCR_INP_1;
610 break;
611 case RME32_INPUT_INTERNAL:
612 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) |
613 RME32_WCR_INP_1;
614 break;
615 case RME32_INPUT_XLR:
616 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) |
617 RME32_WCR_INP_1;
618 break;
619 default:
620 return -EINVAL;
621 }
622 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
623 return 0;
624}
625
017ce802 626static int snd_rme32_getinputtype(struct rme32 * rme32)
1da177e4
LT		 627{
628 return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) +
629 (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1);
630}
631
632static void
017ce802 633snd_rme32_setframelog(struct rme32 * rme32, int n_channels, int is_playback)
1da177e4
LT		 634{
635 int frlog;
636
637 if (n_channels == 2) {
638 frlog = 1;
639 } else {
640 /* assume 8 channels */
641 frlog = 3;
642 }
643 if (is_playback) {
644 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
645 rme32->playback_frlog = frlog;
646 } else {
647 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
648 rme32->capture_frlog = frlog;
649 }
650}
651
017ce802 652static int snd_rme32_setformat(struct rme32 * rme32, int format)
1da177e4
LT		 653{
654 switch (format) {
655 case SNDRV_PCM_FORMAT_S16_LE:
656 rme32->wcreg &= ~RME32_WCR_MODE24;
657 break;
658 case SNDRV_PCM_FORMAT_S32_LE:
659 rme32->wcreg |= RME32_WCR_MODE24;
660 break;
661 default:
662 return -EINVAL;
663 }
664 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
665 return 0;
666}
667
668static int
017ce802
TI		 669snd_rme32_playback_hw_params(struct snd_pcm_substream *substream,
670 struct snd_pcm_hw_params *params)
1da177e4
LT		 671{
672 int err, rate, dummy;
017ce802
TI		 673 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
674 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 675
676 if (rme32->fullduplex_mode) {
677 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
678 if (err < 0)
679 return err;
680 } else {
4d23359b
CL		 681 runtime->dma_area = (void __force *)(rme32->iobase +
682 RME32_IO_DATA_BUFFER);
1da177e4
LT		 683 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
684 runtime->dma_bytes = RME32_BUFFER_SIZE;
685 }
686
687 spin_lock_irq(&rme32->lock);
688 if ((rme32->rcreg & RME32_RCR_KMODE) &&
689 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
690 /* AutoSync */
691 if ((int)params_rate(params) != rate) {
692 spin_unlock_irq(&rme32->lock);
693 return -EIO;
694 }
695 } else if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
696 spin_unlock_irq(&rme32->lock);
697 return err;
698 }
699 if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
700 spin_unlock_irq(&rme32->lock);
701 return err;
702 }
703
704 snd_rme32_setframelog(rme32, params_channels(params), 1);
705 if (rme32->capture_periodsize != 0) {
706 if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) {
707 spin_unlock_irq(&rme32->lock);
708 return -EBUSY;
709 }
710 }
711 rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog;
712 /* S/PDIF setup */
713 if ((rme32->wcreg & RME32_WCR_ADAT) == 0) {
714 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
715 rme32->wcreg |= rme32->wcreg_spdif_stream;
716 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
717 }
718 spin_unlock_irq(&rme32->lock);
719
720 return 0;
721}
722
723static int
017ce802
TI		 724snd_rme32_capture_hw_params(struct snd_pcm_substream *substream,
725 struct snd_pcm_hw_params *params)
1da177e4
LT		 726{
727 int err, isadat, rate;
017ce802
TI		 728 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
729 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 730
731 if (rme32->fullduplex_mode) {
732 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
733 if (err < 0)
734 return err;
735 } else {
4d23359b
CL		 736 runtime->dma_area = (void __force *)rme32->iobase +
737 RME32_IO_DATA_BUFFER;
1da177e4
LT		 738 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
739 runtime->dma_bytes = RME32_BUFFER_SIZE;
740 }
741
742 spin_lock_irq(&rme32->lock);
743 /* enable AutoSync for record-preparing */
744 rme32->wcreg |= RME32_WCR_AUTOSYNC;
745 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
746
747 if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
748 spin_unlock_irq(&rme32->lock);
749 return err;
750 }
751 if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
752 spin_unlock_irq(&rme32->lock);
753 return err;
754 }
755 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
756 if ((int)params_rate(params) != rate) {
757 spin_unlock_irq(&rme32->lock);
758 return -EIO;
759 }
760 if ((isadat && runtime->hw.channels_min == 2) ||
761 (!isadat && runtime->hw.channels_min == 8)) {
762 spin_unlock_irq(&rme32->lock);
763 return -EIO;
764 }
765 }
766 /* AutoSync off for recording */
767 rme32->wcreg &= ~RME32_WCR_AUTOSYNC;
768 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
769
770 snd_rme32_setframelog(rme32, params_channels(params), 0);
771 if (rme32->playback_periodsize != 0) {
772 if (params_period_size(params) << rme32->capture_frlog !=
773 rme32->playback_periodsize) {
774 spin_unlock_irq(&rme32->lock);
775 return -EBUSY;
776 }
777 }
778 rme32->capture_periodsize =
779 params_period_size(params) << rme32->capture_frlog;
780 spin_unlock_irq(&rme32->lock);
781
782 return 0;
783}
784
017ce802 785static int snd_rme32_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4 786{
017ce802 787 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 788 if (! rme32->fullduplex_mode)
789 return 0;
790 return snd_pcm_lib_free_pages(substream);
791}
792
017ce802 793static void snd_rme32_pcm_start(struct rme32 * rme32, int from_pause)
1da177e4
LT		 794{
795 if (!from_pause) {
796 writel(0, rme32->iobase + RME32_IO_RESET_POS);
797 }
798
799 rme32->wcreg |= RME32_WCR_START;
800 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
801}
802
017ce802 803static void snd_rme32_pcm_stop(struct rme32 * rme32, int to_pause)
1da177e4
LT		 804{
805 /*
806 * Check if there is an unconfirmed IRQ, if so confirm it, or else
807 * the hardware will not stop generating interrupts
808 */
809 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
810 if (rme32->rcreg & RME32_RCR_IRQ) {
811 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
812 }
813 rme32->wcreg &= ~RME32_WCR_START;
814 if (rme32->wcreg & RME32_WCR_SEL)
815 rme32->wcreg |= RME32_WCR_MUTE;
816 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
817 if (! to_pause)
818 writel(0, rme32->iobase + RME32_IO_RESET_POS);
819}
820
7d12e780 821static irqreturn_t snd_rme32_interrupt(int irq, void *dev_id)
1da177e4 822{
017ce802 823 struct rme32 *rme32 = (struct rme32 *) dev_id;
1da177e4
LT		 824
825 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
826 if (!(rme32->rcreg & RME32_RCR_IRQ)) {
827 return IRQ_NONE;
828 } else {
829 if (rme32->capture_substream) {
830 snd_pcm_period_elapsed(rme32->capture_substream);
831 }
832 if (rme32->playback_substream) {
833 snd_pcm_period_elapsed(rme32->playback_substream);
834 }
835 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
836 }
837 return IRQ_HANDLED;
838}
839
840static unsigned int period_bytes[] = { RME32_BLOCK_SIZE };
841
842
017ce802 843static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
1da177e4
LT		 844 .count = ARRAY_SIZE(period_bytes),
845 .list = period_bytes,
846 .mask = 0
847};
848
017ce802 849static void snd_rme32_set_buffer_constraint(struct rme32 *rme32, struct snd_pcm_runtime *runtime)
1da177e4
LT		 850{
851 if (! rme32->fullduplex_mode) {
852 snd_pcm_hw_constraint_minmax(runtime,
853 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
854 RME32_BUFFER_SIZE, RME32_BUFFER_SIZE);
855 snd_pcm_hw_constraint_list(runtime, 0,
856 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
857 &hw_constraints_period_bytes);
858 }
859}
860
017ce802 861static int snd_rme32_playback_spdif_open(struct snd_pcm_substream *substream)
1da177e4
LT		 862{
863 int rate, dummy;
017ce802
TI		 864 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
865 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 866
867 snd_pcm_set_sync(substream);
868
869 spin_lock_irq(&rme32->lock);
870 if (rme32->playback_substream != NULL) {
871 spin_unlock_irq(&rme32->lock);
872 return -EBUSY;
873 }
874 rme32->wcreg &= ~RME32_WCR_ADAT;
875 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
876 rme32->playback_substream = substream;
877 spin_unlock_irq(&rme32->lock);
878
879 if (rme32->fullduplex_mode)
880 runtime->hw = snd_rme32_spdif_fd_info;
881 else
882 runtime->hw = snd_rme32_spdif_info;
8b7fc421 883 if (rme32->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO) {
1da177e4
LT		 884 runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
885 runtime->hw.rate_max = 96000;
886 }
887 if ((rme32->rcreg & RME32_RCR_KMODE) &&
888 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
889 /* AutoSync */
890 runtime->hw.rates = snd_rme32_ratecode(rate);
891 runtime->hw.rate_min = rate;
892 runtime->hw.rate_max = rate;
893 }
894
895 snd_rme32_set_buffer_constraint(rme32, runtime);
896
897 rme32->wcreg_spdif_stream = rme32->wcreg_spdif;
898 rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
899 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
900 SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id);
901 return 0;
902}
903
017ce802 904static int snd_rme32_capture_spdif_open(struct snd_pcm_substream *substream)
1da177e4
LT		 905{
906 int isadat, rate;
017ce802
TI		 907 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
908 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 909
910 snd_pcm_set_sync(substream);
911
912 spin_lock_irq(&rme32->lock);
913 if (rme32->capture_substream != NULL) {
914 spin_unlock_irq(&rme32->lock);
915 return -EBUSY;
916 }
917 rme32->capture_substream = substream;
918 spin_unlock_irq(&rme32->lock);
919
920 if (rme32->fullduplex_mode)
921 runtime->hw = snd_rme32_spdif_fd_info;
922 else
923 runtime->hw = snd_rme32_spdif_info;
924 if (RME32_PRO_WITH_8414(rme32)) {
925 runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
926 runtime->hw.rate_max = 96000;
927 }
928 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
929 if (isadat) {
930 return -EIO;
931 }
932 runtime->hw.rates = snd_rme32_ratecode(rate);
933 runtime->hw.rate_min = rate;
934 runtime->hw.rate_max = rate;
935 }
936
937 snd_rme32_set_buffer_constraint(rme32, runtime);
938
939 return 0;
940}
941
942static int
017ce802 943snd_rme32_playback_adat_open(struct snd_pcm_substream *substream)
1da177e4
LT		 944{
945 int rate, dummy;
017ce802
TI		 946 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
947 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 948
949 snd_pcm_set_sync(substream);
950
951 spin_lock_irq(&rme32->lock);
952 if (rme32->playback_substream != NULL) {
953 spin_unlock_irq(&rme32->lock);
954 return -EBUSY;
955 }
956 rme32->wcreg |= RME32_WCR_ADAT;
957 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
958 rme32->playback_substream = substream;
959 spin_unlock_irq(&rme32->lock);
960
961 if (rme32->fullduplex_mode)
962 runtime->hw = snd_rme32_adat_fd_info;
963 else
964 runtime->hw = snd_rme32_adat_info;
965 if ((rme32->rcreg & RME32_RCR_KMODE) &&
966 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
967 /* AutoSync */
968 runtime->hw.rates = snd_rme32_ratecode(rate);
969 runtime->hw.rate_min = rate;
970 runtime->hw.rate_max = rate;
971 }
972
973 snd_rme32_set_buffer_constraint(rme32, runtime);
974 return 0;
975}
976
977static int
017ce802 978snd_rme32_capture_adat_open(struct snd_pcm_substream *substream)
1da177e4
LT		 979{
980 int isadat, rate;
017ce802
TI		 981 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
982 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 983
984 if (rme32->fullduplex_mode)
985 runtime->hw = snd_rme32_adat_fd_info;
986 else
987 runtime->hw = snd_rme32_adat_info;
988 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
989 if (!isadat) {
990 return -EIO;
991 }
992 runtime->hw.rates = snd_rme32_ratecode(rate);
993 runtime->hw.rate_min = rate;
994 runtime->hw.rate_max = rate;
995 }
996
997 snd_pcm_set_sync(substream);
998
999 spin_lock_irq(&rme32->lock);
1000 if (rme32->capture_substream != NULL) {
1001 spin_unlock_irq(&rme32->lock);
1002 return -EBUSY;
1003 }
1004 rme32->capture_substream = substream;
1005 spin_unlock_irq(&rme32->lock);
1006
1007 snd_rme32_set_buffer_constraint(rme32, runtime);
1008 return 0;
1009}
1010
017ce802 1011static int snd_rme32_playback_close(struct snd_pcm_substream *substream)
1da177e4 1012{
017ce802 1013 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1014 int spdif = 0;
1015
1016 spin_lock_irq(&rme32->lock);
1017 rme32->playback_substream = NULL;
1018 rme32->playback_periodsize = 0;
1019 spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0;
1020 spin_unlock_irq(&rme32->lock);
1021 if (spdif) {
1022 rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1023 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
1024 SNDRV_CTL_EVENT_MASK_INFO,
1025 &rme32->spdif_ctl->id);
1026 }
1027 return 0;
1028}
1029
017ce802 1030static int snd_rme32_capture_close(struct snd_pcm_substream *substream)
1da177e4 1031{
017ce802 1032 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1033
1034 spin_lock_irq(&rme32->lock);
1035 rme32->capture_substream = NULL;
1036 rme32->capture_periodsize = 0;
1037 spin_unlock(&rme32->lock);
1038 return 0;
1039}
1040
017ce802 1041static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream)
1da177e4 1042{
017ce802 1043 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1044
1045 spin_lock_irq(&rme32->lock);
1046 if (rme32->fullduplex_mode) {
1047 memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm));
1048 rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1049 rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1050 } else {
1051 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1052 }
1053 if (rme32->wcreg & RME32_WCR_SEL)
1054 rme32->wcreg &= ~RME32_WCR_MUTE;
1055 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1056 spin_unlock_irq(&rme32->lock);
1057 return 0;
1058}
1059
017ce802 1060static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 1061{
017ce802 1062 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1063
1064 spin_lock_irq(&rme32->lock);
1065 if (rme32->fullduplex_mode) {
1066 memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm));
1067 rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1068 rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2;
1069 rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1070 } else {
1071 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1072 }
1073 spin_unlock_irq(&rme32->lock);
1074 return 0;
1075}
1076
1077static int
017ce802 1078snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 1079{
017ce802 1080 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4 1081 struct list_head *pos;
017ce802 1082 struct snd_pcm_substream *s;
1da177e4
LT		 1083
1084 spin_lock(&rme32->lock);
1085 snd_pcm_group_for_each(pos, substream) {
1086 s = snd_pcm_group_substream_entry(pos);
1087 if (s != rme32->playback_substream &&
1088 s != rme32->capture_substream)
1089 continue;
1090 switch (cmd) {
1091 case SNDRV_PCM_TRIGGER_START:
1092 rme32->running |= (1 << s->stream);
1093 if (rme32->fullduplex_mode) {
1094 /* remember the current DMA position */
1095 if (s == rme32->playback_substream) {
1096 rme32->playback_pcm.hw_io =
1097 rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1098 } else {
1099 rme32->capture_pcm.hw_io =
1100 rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1101 }
1102 }
1103 break;
1104 case SNDRV_PCM_TRIGGER_STOP:
1105 rme32->running &= ~(1 << s->stream);
1106 break;
1107 }
1108 snd_pcm_trigger_done(s, substream);
1109 }
1110
1111 /* prefill playback buffer */
1112 if (cmd == SNDRV_PCM_TRIGGER_START && rme32->fullduplex_mode) {
1113 snd_pcm_group_for_each(pos, substream) {
1114 s = snd_pcm_group_substream_entry(pos);
1115 if (s == rme32->playback_substream) {
1116 s->ops->ack(s);
1117 break;
1118 }
1119 }
1120 }
1121
1122 switch (cmd) {
1123 case SNDRV_PCM_TRIGGER_START:
1124 if (rme32->running && ! RME32_ISWORKING(rme32))
1125 snd_rme32_pcm_start(rme32, 0);
1126 break;
1127 case SNDRV_PCM_TRIGGER_STOP:
1128 if (! rme32->running && RME32_ISWORKING(rme32))
1129 snd_rme32_pcm_stop(rme32, 0);
1130 break;
1131 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1132 if (rme32->running && RME32_ISWORKING(rme32))
1133 snd_rme32_pcm_stop(rme32, 1);
1134 break;
1135 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1136 if (rme32->running && ! RME32_ISWORKING(rme32))
1137 snd_rme32_pcm_start(rme32, 1);
1138 break;
1139 }
1140 spin_unlock(&rme32->lock);
1141 return 0;
1142}
1143
1144/* pointer callback for halfduplex mode */
1145static snd_pcm_uframes_t
017ce802 1146snd_rme32_playback_pointer(struct snd_pcm_substream *substream)
1da177e4 1147{
017ce802 1148 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1149 return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog;
1150}
1151
1152static snd_pcm_uframes_t
017ce802 1153snd_rme32_capture_pointer(struct snd_pcm_substream *substream)
1da177e4 1154{
017ce802 1155 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1156 return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog;
1157}
1158
1159
1160/* ack and pointer callbacks for fullduplex mode */
017ce802
TI		 1161static void snd_rme32_pb_trans_copy(struct snd_pcm_substream *substream,
1162 struct snd_pcm_indirect *rec, size_t bytes)
1da177e4 1163{
017ce802 1164 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1165 memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1166 substream->runtime->dma_area + rec->sw_data, bytes);
1167}
1168
017ce802 1169static int snd_rme32_playback_fd_ack(struct snd_pcm_substream *substream)
1da177e4 1170{
017ce802
TI		 1171 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1172 struct snd_pcm_indirect *rec, *cprec;
1da177e4
LT		 1173
1174 rec = &rme32->playback_pcm;
1175 cprec = &rme32->capture_pcm;
1176 spin_lock(&rme32->lock);
1177 rec->hw_queue_size = RME32_BUFFER_SIZE;
1178 if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE))
1179 rec->hw_queue_size -= cprec->hw_ready;
1180 spin_unlock(&rme32->lock);
1181 snd_pcm_indirect_playback_transfer(substream, rec,
1182 snd_rme32_pb_trans_copy);
1183 return 0;
1184}
1185
017ce802
TI		 1186static void snd_rme32_cp_trans_copy(struct snd_pcm_substream *substream,
1187 struct snd_pcm_indirect *rec, size_t bytes)
1da177e4 1188{
017ce802 1189 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1190 memcpy_fromio(substream->runtime->dma_area + rec->sw_data,
1191 rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1192 bytes);
1193}
1194
017ce802 1195static int snd_rme32_capture_fd_ack(struct snd_pcm_substream *substream)
1da177e4 1196{
017ce802 1197 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1198 snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm,
1199 snd_rme32_cp_trans_copy);
1200 return 0;
1201}
1202
1203static snd_pcm_uframes_t
017ce802 1204snd_rme32_playback_fd_pointer(struct snd_pcm_substream *substream)
1da177e4 1205{
017ce802 1206 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1207 return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm,
1208 snd_rme32_pcm_byteptr(rme32));
1209}
1210
1211static snd_pcm_uframes_t
017ce802 1212snd_rme32_capture_fd_pointer(struct snd_pcm_substream *substream)
1da177e4 1213{
017ce802 1214 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1215 return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm,
1216 snd_rme32_pcm_byteptr(rme32));
1217}
1218
1219/* for halfduplex mode */
017ce802 1220static struct snd_pcm_ops snd_rme32_playback_spdif_ops = {
1da177e4
LT		 1221 .open = snd_rme32_playback_spdif_open,
1222 .close = snd_rme32_playback_close,
1223 .ioctl = snd_pcm_lib_ioctl,
1224 .hw_params = snd_rme32_playback_hw_params,
1225 .hw_free = snd_rme32_pcm_hw_free,
1226 .prepare = snd_rme32_playback_prepare,
1227 .trigger = snd_rme32_pcm_trigger,
1228 .pointer = snd_rme32_playback_pointer,
1229 .copy = snd_rme32_playback_copy,
1230 .silence = snd_rme32_playback_silence,
1231 .mmap = snd_pcm_lib_mmap_iomem,
1232};
1233
017ce802 1234static struct snd_pcm_ops snd_rme32_capture_spdif_ops = {
1da177e4
LT		 1235 .open = snd_rme32_capture_spdif_open,
1236 .close = snd_rme32_capture_close,
1237 .ioctl = snd_pcm_lib_ioctl,
1238 .hw_params = snd_rme32_capture_hw_params,
1239 .hw_free = snd_rme32_pcm_hw_free,
1240 .prepare = snd_rme32_capture_prepare,
1241 .trigger = snd_rme32_pcm_trigger,
1242 .pointer = snd_rme32_capture_pointer,
1243 .copy = snd_rme32_capture_copy,
1244 .mmap = snd_pcm_lib_mmap_iomem,
1245};
1246
017ce802 1247static struct snd_pcm_ops snd_rme32_playback_adat_ops = {
1da177e4
LT		 1248 .open = snd_rme32_playback_adat_open,
1249 .close = snd_rme32_playback_close,
1250 .ioctl = snd_pcm_lib_ioctl,
1251 .hw_params = snd_rme32_playback_hw_params,
1252 .prepare = snd_rme32_playback_prepare,
1253 .trigger = snd_rme32_pcm_trigger,
1254 .pointer = snd_rme32_playback_pointer,
1255 .copy = snd_rme32_playback_copy,
1256 .silence = snd_rme32_playback_silence,
1257 .mmap = snd_pcm_lib_mmap_iomem,
1258};
1259
017ce802 1260static struct snd_pcm_ops snd_rme32_capture_adat_ops = {
1da177e4
LT		 1261 .open = snd_rme32_capture_adat_open,
1262 .close = snd_rme32_capture_close,
1263 .ioctl = snd_pcm_lib_ioctl,
1264 .hw_params = snd_rme32_capture_hw_params,
1265 .prepare = snd_rme32_capture_prepare,
1266 .trigger = snd_rme32_pcm_trigger,
1267 .pointer = snd_rme32_capture_pointer,
1268 .copy = snd_rme32_capture_copy,
1269 .mmap = snd_pcm_lib_mmap_iomem,
1270};
1271
1272/* for fullduplex mode */
017ce802 1273static struct snd_pcm_ops snd_rme32_playback_spdif_fd_ops = {
1da177e4
LT		 1274 .open = snd_rme32_playback_spdif_open,
1275 .close = snd_rme32_playback_close,
1276 .ioctl = snd_pcm_lib_ioctl,
1277 .hw_params = snd_rme32_playback_hw_params,
1278 .hw_free = snd_rme32_pcm_hw_free,
1279 .prepare = snd_rme32_playback_prepare,
1280 .trigger = snd_rme32_pcm_trigger,
1281 .pointer = snd_rme32_playback_fd_pointer,
1282 .ack = snd_rme32_playback_fd_ack,
1283};
1284
017ce802 1285static struct snd_pcm_ops snd_rme32_capture_spdif_fd_ops = {
1da177e4
LT		 1286 .open = snd_rme32_capture_spdif_open,
1287 .close = snd_rme32_capture_close,
1288 .ioctl = snd_pcm_lib_ioctl,
1289 .hw_params = snd_rme32_capture_hw_params,
1290 .hw_free = snd_rme32_pcm_hw_free,
1291 .prepare = snd_rme32_capture_prepare,
1292 .trigger = snd_rme32_pcm_trigger,
1293 .pointer = snd_rme32_capture_fd_pointer,
1294 .ack = snd_rme32_capture_fd_ack,
1295};
1296
017ce802 1297static struct snd_pcm_ops snd_rme32_playback_adat_fd_ops = {
1da177e4
LT		 1298 .open = snd_rme32_playback_adat_open,
1299 .close = snd_rme32_playback_close,
1300 .ioctl = snd_pcm_lib_ioctl,
1301 .hw_params = snd_rme32_playback_hw_params,
1302 .prepare = snd_rme32_playback_prepare,
1303 .trigger = snd_rme32_pcm_trigger,
1304 .pointer = snd_rme32_playback_fd_pointer,
1305 .ack = snd_rme32_playback_fd_ack,
1306};
1307
017ce802 1308static struct snd_pcm_ops snd_rme32_capture_adat_fd_ops = {
1da177e4
LT		 1309 .open = snd_rme32_capture_adat_open,
1310 .close = snd_rme32_capture_close,
1311 .ioctl = snd_pcm_lib_ioctl,
1312 .hw_params = snd_rme32_capture_hw_params,
1313 .prepare = snd_rme32_capture_prepare,
1314 .trigger = snd_rme32_pcm_trigger,
1315 .pointer = snd_rme32_capture_fd_pointer,
1316 .ack = snd_rme32_capture_fd_ack,
1317};
1318
1319static void snd_rme32_free(void *private_data)
1320{
017ce802 1321 struct rme32 *rme32 = (struct rme32 *) private_data;
1da177e4
LT		 1322
1323 if (rme32 == NULL) {
1324 return;
1325 }
1326 if (rme32->irq >= 0) {
1327 snd_rme32_pcm_stop(rme32, 0);
1328 free_irq(rme32->irq, (void *) rme32);
1329 rme32->irq = -1;
1330 }
1331 if (rme32->iobase) {
1332 iounmap(rme32->iobase);
1333 rme32->iobase = NULL;
1334 }
1335 if (rme32->port) {
1336 pci_release_regions(rme32->pci);
1337 rme32->port = 0;
1338 }
1339 pci_disable_device(rme32->pci);
1340}
1341
017ce802 1342static void snd_rme32_free_spdif_pcm(struct snd_pcm *pcm)
1da177e4 1343{
017ce802 1344 struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
1da177e4
LT		 1345 rme32->spdif_pcm = NULL;
1346}
1347
1348static void
017ce802 1349snd_rme32_free_adat_pcm(struct snd_pcm *pcm)
1da177e4 1350{
017ce802 1351 struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
1da177e4
LT		 1352 rme32->adat_pcm = NULL;
1353}
1354
017ce802 1355static int __devinit snd_rme32_create(struct rme32 * rme32)
1da177e4
LT		 1356{
1357 struct pci_dev *pci = rme32->pci;
1358 int err;
1359
1360 rme32->irq = -1;
1361 spin_lock_init(&rme32->lock);
1362
1363 if ((err = pci_enable_device(pci)) < 0)
1364 return err;
1365
1366 if ((err = pci_request_regions(pci, "RME32")) < 0)
1367 return err;
1368 rme32->port = pci_resource_start(rme32->pci, 0);
1369
1da177e4 1370 if ((rme32->iobase = ioremap_nocache(rme32->port, RME32_IO_SIZE)) == 0) {
99b359ba 1371 snd_printk(KERN_ERR "unable to remap memory region 0x%lx-0x%lx\n",
1da177e4
LT		 1372 rme32->port, rme32->port + RME32_IO_SIZE - 1);
1373 return -ENOMEM;
1374 }
1375
65ca68b3 1376 if (request_irq(pci->irq, snd_rme32_interrupt, IRQF_DISABLED | IRQF_SHARED, "RME32", (void *) rme32)) {
688956f2
TI		 1377 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1378 return -EBUSY;
1379 }
1380 rme32->irq = pci->irq;
1381
1da177e4
LT		 1382 /* read the card's revision number */
1383 pci_read_config_byte(pci, 8, &rme32->rev);
1384
1385 /* set up ALSA pcm device for S/PDIF */
1386 if ((err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm)) < 0) {
1387 return err;
1388 }
1389 rme32->spdif_pcm->private_data = rme32;
1390 rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm;
1391 strcpy(rme32->spdif_pcm->name, "Digi32 IEC958");
1392 if (rme32->fullduplex_mode) {
1393 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1394 &snd_rme32_playback_spdif_fd_ops);
1395 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1396 &snd_rme32_capture_spdif_fd_ops);
1397 snd_pcm_lib_preallocate_pages_for_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1398 snd_dma_continuous_data(GFP_KERNEL),
1399 0, RME32_MID_BUFFER_SIZE);
1400 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1401 } else {
1402 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1403 &snd_rme32_playback_spdif_ops);
1404 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1405 &snd_rme32_capture_spdif_ops);
1406 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1407 }
1408
1409 /* set up ALSA pcm device for ADAT */
8b7fc421
RD		 1410 if ((pci->device == PCI_DEVICE_ID_RME_DIGI32) ||
1411 (pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO)) {
1da177e4
LT		 1412 /* ADAT is not available on DIGI32 and DIGI32 Pro */
1413 rme32->adat_pcm = NULL;
1414 }
1415 else {
1416 if ((err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1,
1417 1, 1, &rme32->adat_pcm)) < 0)
1418 {
1419 return err;
1420 }
1421 rme32->adat_pcm->private_data = rme32;
1422 rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm;
1423 strcpy(rme32->adat_pcm->name, "Digi32 ADAT");
1424 if (rme32->fullduplex_mode) {
1425 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1426 &snd_rme32_playback_adat_fd_ops);
1427 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
1428 &snd_rme32_capture_adat_fd_ops);
1429 snd_pcm_lib_preallocate_pages_for_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1430 snd_dma_continuous_data(GFP_KERNEL),
1431 0, RME32_MID_BUFFER_SIZE);
1432 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1433 } else {
1434 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1435 &snd_rme32_playback_adat_ops);
1436 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
1437 &snd_rme32_capture_adat_ops);
1438 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1439 }
1440 }
1441
1442
1443 rme32->playback_periodsize = 0;
1444 rme32->capture_periodsize = 0;
1445
1446 /* make sure playback/capture is stopped, if by some reason active */
1447 snd_rme32_pcm_stop(rme32, 0);
1448
1449 /* reset DAC */
1450 snd_rme32_reset_dac(rme32);
1451
1452 /* reset buffer pointer */
1453 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1454
1455 /* set default values in registers */
1456 rme32->wcreg = RME32_WCR_SEL | /* normal playback */
1457 RME32_WCR_INP_0 | /* input select */
1458 RME32_WCR_MUTE; /* muting on */
1459 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1460
1461
1462 /* init switch interface */
1463 if ((err = snd_rme32_create_switches(rme32->card, rme32)) < 0) {
1464 return err;
1465 }
1466
1467 /* init proc interface */
1468 snd_rme32_proc_init(rme32);
1469
1470 rme32->capture_substream = NULL;
1471 rme32->playback_substream = NULL;
1472
1473 return 0;
1474}
1475
1476/*
1477 * proc interface
1478 */
1479
1480static void
017ce802 1481snd_rme32_proc_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer)
1da177e4
LT		 1482{
1483 int n;
017ce802 1484 struct rme32 *rme32 = (struct rme32 *) entry->private_data;
1da177e4
LT		 1485
1486 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
1487
1488 snd_iprintf(buffer, rme32->card->longname);
1489 snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1);
1490
1491 snd_iprintf(buffer, "\nGeneral settings\n");
1492 if (rme32->fullduplex_mode)
1493 snd_iprintf(buffer, " Full-duplex mode\n");
1494 else
1495 snd_iprintf(buffer, " Half-duplex mode\n");
1496 if (RME32_PRO_WITH_8414(rme32)) {
1497 snd_iprintf(buffer, " receiver: CS8414\n");
1498 } else {
1499 snd_iprintf(buffer, " receiver: CS8412\n");
1500 }
1501 if (rme32->wcreg & RME32_WCR_MODE24) {
1502 snd_iprintf(buffer, " format: 24 bit");
1503 } else {
1504 snd_iprintf(buffer, " format: 16 bit");
1505 }
1506 if (rme32->wcreg & RME32_WCR_MONO) {
1507 snd_iprintf(buffer, ", Mono\n");
1508 } else {
1509 snd_iprintf(buffer, ", Stereo\n");
1510 }
1511
1512 snd_iprintf(buffer, "\nInput settings\n");
1513 switch (snd_rme32_getinputtype(rme32)) {
1514 case RME32_INPUT_OPTICAL:
1515 snd_iprintf(buffer, " input: optical");
1516 break;
1517 case RME32_INPUT_COAXIAL:
1518 snd_iprintf(buffer, " input: coaxial");
1519 break;
1520 case RME32_INPUT_INTERNAL:
1521 snd_iprintf(buffer, " input: internal");
1522 break;
1523 case RME32_INPUT_XLR:
1524 snd_iprintf(buffer, " input: XLR");
1525 break;
1526 }
1527 if (snd_rme32_capture_getrate(rme32, &n) < 0) {
1528 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1529 } else {
1530 if (n) {
1531 snd_iprintf(buffer, " (8 channels)\n");
1532 } else {
1533 snd_iprintf(buffer, " (2 channels)\n");
1534 }
1535 snd_iprintf(buffer, " sample rate: %d Hz\n",
1536 snd_rme32_capture_getrate(rme32, &n));
1537 }
1538
1539 snd_iprintf(buffer, "\nOutput settings\n");
1540 if (rme32->wcreg & RME32_WCR_SEL) {
1541 snd_iprintf(buffer, " output signal: normal playback");
1542 } else {
1543 snd_iprintf(buffer, " output signal: same as input");
1544 }
1545 if (rme32->wcreg & RME32_WCR_MUTE) {
1546 snd_iprintf(buffer, " (muted)\n");
1547 } else {
1548 snd_iprintf(buffer, "\n");
1549 }
1550
1551 /* master output frequency */
1552 if (!
1553 ((!(rme32->wcreg & RME32_WCR_FREQ_0))
1554 && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) {
1555 snd_iprintf(buffer, " sample rate: %d Hz\n",
1556 snd_rme32_playback_getrate(rme32));
1557 }
1558 if (rme32->rcreg & RME32_RCR_KMODE) {
1559 snd_iprintf(buffer, " sample clock source: AutoSync\n");
1560 } else {
1561 snd_iprintf(buffer, " sample clock source: Internal\n");
1562 }
1563 if (rme32->wcreg & RME32_WCR_PRO) {
1564 snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1565 } else {
1566 snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1567 }
1568 if (rme32->wcreg & RME32_WCR_EMP) {
1569 snd_iprintf(buffer, " emphasis: on\n");
1570 } else {
1571 snd_iprintf(buffer, " emphasis: off\n");
1572 }
1573}
1574
017ce802 1575static void __devinit snd_rme32_proc_init(struct rme32 * rme32)
1da177e4 1576{
017ce802 1577 struct snd_info_entry *entry;
1da177e4
LT		 1578
1579 if (! snd_card_proc_new(rme32->card, "rme32", &entry))
bf850204 1580 snd_info_set_text_ops(entry, rme32, snd_rme32_proc_read);
1da177e4
LT		 1581}
1582
1583/*
1584 * control interface
1585 */
1586
1587static int
017ce802
TI		 1588snd_rme32_info_loopback_control(struct snd_kcontrol *kcontrol,
1589 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1590{
1591 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1592 uinfo->count = 1;
1593 uinfo->value.integer.min = 0;
1594 uinfo->value.integer.max = 1;
1595 return 0;
1596}
1597static int
017ce802
TI		 1598snd_rme32_get_loopback_control(struct snd_kcontrol *kcontrol,
1599 struct snd_ctl_elem_value *ucontrol)
1da177e4 1600{
017ce802 1601 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1602
1603 spin_lock_irq(&rme32->lock);
1604 ucontrol->value.integer.value[0] =
1605 rme32->wcreg & RME32_WCR_SEL ? 0 : 1;
1606 spin_unlock_irq(&rme32->lock);
1607 return 0;
1608}
1609static int
017ce802
TI		 1610snd_rme32_put_loopback_control(struct snd_kcontrol *kcontrol,
1611 struct snd_ctl_elem_value *ucontrol)
1da177e4 1612{
017ce802 1613 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1614 unsigned int val;
1615 int change;
1616
1617 val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL;
1618 spin_lock_irq(&rme32->lock);
1619 val = (rme32->wcreg & ~RME32_WCR_SEL) | val;
1620 change = val != rme32->wcreg;
1621 if (ucontrol->value.integer.value[0])
1622 val &= ~RME32_WCR_MUTE;
1623 else
1624 val |= RME32_WCR_MUTE;
1625 rme32->wcreg = val;
1626 writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1627 spin_unlock_irq(&rme32->lock);
1628 return change;
1629}
1630
1631static int
017ce802
TI		 1632snd_rme32_info_inputtype_control(struct snd_kcontrol *kcontrol,
1633 struct snd_ctl_elem_info *uinfo)
1da177e4 1634{
017ce802 1635 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1636 static char *texts[4] = { "Optical", "Coaxial", "Internal", "XLR" };
1637
1638 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1639 uinfo->count = 1;
1640 switch (rme32->pci->device) {
8b7fc421
RD		 1641 case PCI_DEVICE_ID_RME_DIGI32:
1642 case PCI_DEVICE_ID_RME_DIGI32_8:
1da177e4
LT		 1643 uinfo->value.enumerated.items = 3;
1644 break;
8b7fc421 1645 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1da177e4
LT		 1646 uinfo->value.enumerated.items = 4;
1647 break;
1648 default:
1649 snd_BUG();
1650 break;
1651 }
1652 if (uinfo->value.enumerated.item >
1653 uinfo->value.enumerated.items - 1) {
1654 uinfo->value.enumerated.item =
1655 uinfo->value.enumerated.items - 1;
1656 }
1657 strcpy(uinfo->value.enumerated.name,
1658 texts[uinfo->value.enumerated.item]);
1659 return 0;
1660}
1661static int
017ce802
TI		 1662snd_rme32_get_inputtype_control(struct snd_kcontrol *kcontrol,
1663 struct snd_ctl_elem_value *ucontrol)
1da177e4 1664{
017ce802 1665 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1666 unsigned int items = 3;
1667
1668 spin_lock_irq(&rme32->lock);
1669 ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32);
1670
1671 switch (rme32->pci->device) {
8b7fc421
RD		 1672 case PCI_DEVICE_ID_RME_DIGI32:
1673 case PCI_DEVICE_ID_RME_DIGI32_8:
1da177e4
LT		 1674 items = 3;
1675 break;
8b7fc421 1676 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1da177e4
LT		 1677 items = 4;
1678 break;
1679 default:
1680 snd_BUG();
1681 break;
1682 }
1683 if (ucontrol->value.enumerated.item[0] >= items) {
1684 ucontrol->value.enumerated.item[0] = items - 1;
1685 }
1686
1687 spin_unlock_irq(&rme32->lock);
1688 return 0;
1689}
1690static int
017ce802
TI		 1691snd_rme32_put_inputtype_control(struct snd_kcontrol *kcontrol,
1692 struct snd_ctl_elem_value *ucontrol)
1da177e4 1693{
017ce802 1694 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1695 unsigned int val;
1696 int change, items = 3;
1697
1698 switch (rme32->pci->device) {
8b7fc421
RD		 1699 case PCI_DEVICE_ID_RME_DIGI32:
1700 case PCI_DEVICE_ID_RME_DIGI32_8:
1da177e4
LT		 1701 items = 3;
1702 break;
8b7fc421 1703 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1da177e4
LT		 1704 items = 4;
1705 break;
1706 default:
1707 snd_BUG();
1708 break;
1709 }
1710 val = ucontrol->value.enumerated.item[0] % items;
1711
1712 spin_lock_irq(&rme32->lock);
1713 change = val != (unsigned int)snd_rme32_getinputtype(rme32);
1714 snd_rme32_setinputtype(rme32, val);
1715 spin_unlock_irq(&rme32->lock);
1716 return change;
1717}
1718
1719static int
017ce802
TI		 1720snd_rme32_info_clockmode_control(struct snd_kcontrol *kcontrol,
1721 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1722{
1723 static char *texts[4] = { "AutoSync",
1724 "Internal 32.0kHz",
1725 "Internal 44.1kHz",
1726 "Internal 48.0kHz" };
1727
1728 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1729 uinfo->count = 1;
1730 uinfo->value.enumerated.items = 4;
1731 if (uinfo->value.enumerated.item > 3) {
1732 uinfo->value.enumerated.item = 3;
1733 }
1734 strcpy(uinfo->value.enumerated.name,
1735 texts[uinfo->value.enumerated.item]);
1736 return 0;
1737}
1738static int
017ce802
TI		 1739snd_rme32_get_clockmode_control(struct snd_kcontrol *kcontrol,
1740 struct snd_ctl_elem_value *ucontrol)
1da177e4 1741{
017ce802 1742 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1743
1744 spin_lock_irq(&rme32->lock);
1745 ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32);
1746 spin_unlock_irq(&rme32->lock);
1747 return 0;
1748}
1749static int
017ce802
TI		 1750snd_rme32_put_clockmode_control(struct snd_kcontrol *kcontrol,
1751 struct snd_ctl_elem_value *ucontrol)
1da177e4 1752{
017ce802 1753 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1754 unsigned int val;
1755 int change;
1756
1757 val = ucontrol->value.enumerated.item[0] % 3;
1758 spin_lock_irq(&rme32->lock);
1759 change = val != (unsigned int)snd_rme32_getclockmode(rme32);
1760 snd_rme32_setclockmode(rme32, val);
1761 spin_unlock_irq(&rme32->lock);
1762 return change;
1763}
1764
017ce802 1765static u32 snd_rme32_convert_from_aes(struct snd_aes_iec958 * aes)
1da177e4
LT		 1766{
1767 u32 val = 0;
1768 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0;
1769 if (val & RME32_WCR_PRO)
1770 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1771 else
1772 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1773 return val;
1774}
1775
017ce802 1776static void snd_rme32_convert_to_aes(struct snd_aes_iec958 * aes, u32 val)
1da177e4
LT		 1777{
1778 aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0);
1779 if (val & RME32_WCR_PRO)
1780 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1781 else
1782 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1783}
1784
017ce802
TI		 1785static int snd_rme32_control_spdif_info(struct snd_kcontrol *kcontrol,
1786 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1787{
1788 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1789 uinfo->count = 1;
1790 return 0;
1791}
1792
017ce802
TI		 1793static int snd_rme32_control_spdif_get(struct snd_kcontrol *kcontrol,
1794 struct snd_ctl_elem_value *ucontrol)
1da177e4 1795{
017ce802 1796 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1797
1798 snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1799 rme32->wcreg_spdif);
1800 return 0;
1801}
1802
017ce802
TI		 1803static int snd_rme32_control_spdif_put(struct snd_kcontrol *kcontrol,
1804 struct snd_ctl_elem_value *ucontrol)
1da177e4 1805{
017ce802 1806 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1807 int change;
1808 u32 val;
1809
1810 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1811 spin_lock_irq(&rme32->lock);
1812 change = val != rme32->wcreg_spdif;
1813 rme32->wcreg_spdif = val;
1814 spin_unlock_irq(&rme32->lock);
1815 return change;
1816}
1817
017ce802
TI		 1818static int snd_rme32_control_spdif_stream_info(struct snd_kcontrol *kcontrol,
1819 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1820{
1821 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1822 uinfo->count = 1;
1823 return 0;
1824}
1825
017ce802
TI		 1826static int snd_rme32_control_spdif_stream_get(struct snd_kcontrol *kcontrol,
1827 struct snd_ctl_elem_value *
1da177e4
LT		 1828 ucontrol)
1829{
017ce802 1830 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1831
1832 snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1833 rme32->wcreg_spdif_stream);
1834 return 0;
1835}
1836
017ce802
TI		 1837static int snd_rme32_control_spdif_stream_put(struct snd_kcontrol *kcontrol,
1838 struct snd_ctl_elem_value *
1da177e4
LT		 1839 ucontrol)
1840{
017ce802 1841 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1842 int change;
1843 u32 val;
1844
1845 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1846 spin_lock_irq(&rme32->lock);
1847 change = val != rme32->wcreg_spdif_stream;
1848 rme32->wcreg_spdif_stream = val;
1849 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
1850 rme32->wcreg |= val;
1851 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1852 spin_unlock_irq(&rme32->lock);
1853 return change;
1854}
1855
017ce802
TI		 1856static int snd_rme32_control_spdif_mask_info(struct snd_kcontrol *kcontrol,
1857 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1858{
1859 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1860 uinfo->count = 1;
1861 return 0;
1862}
1863
017ce802
TI		 1864static int snd_rme32_control_spdif_mask_get(struct snd_kcontrol *kcontrol,
1865 struct snd_ctl_elem_value *
1da177e4
LT		 1866 ucontrol)
1867{
1868 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1869 return 0;
1870}
1871
017ce802 1872static struct snd_kcontrol_new snd_rme32_controls[] = {
1da177e4
LT		 1873 {
1874 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1875 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1876 .info = snd_rme32_control_spdif_info,
1877 .get = snd_rme32_control_spdif_get,
1878 .put = snd_rme32_control_spdif_put
1879 },
1880 {
1881 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1882 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1883 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
1884 .info = snd_rme32_control_spdif_stream_info,
1885 .get = snd_rme32_control_spdif_stream_get,
1886 .put = snd_rme32_control_spdif_stream_put
1887 },
1888 {
1889 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 1890 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 1891 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1892 .info = snd_rme32_control_spdif_mask_info,
1893 .get = snd_rme32_control_spdif_mask_get,
1894 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS
1895 },
1896 {
1897 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 1898 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 1899 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
1900 .info = snd_rme32_control_spdif_mask_info,
1901 .get = snd_rme32_control_spdif_mask_get,
1902 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS
1903 },
1904 {
1905 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1906 .name = "Input Connector",
1907 .info = snd_rme32_info_inputtype_control,
1908 .get = snd_rme32_get_inputtype_control,
1909 .put = snd_rme32_put_inputtype_control
1910 },
1911 {
1912 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1913 .name = "Loopback Input",
1914 .info = snd_rme32_info_loopback_control,
1915 .get = snd_rme32_get_loopback_control,
1916 .put = snd_rme32_put_loopback_control
1917 },
1918 {
1919 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1920 .name = "Sample Clock Source",
1921 .info = snd_rme32_info_clockmode_control,
1922 .get = snd_rme32_get_clockmode_control,
1923 .put = snd_rme32_put_clockmode_control
1924 }
1925};
1926
017ce802 1927static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32)
1da177e4
LT		 1928{
1929 int idx, err;
017ce802 1930 struct snd_kcontrol *kctl;
1da177e4
LT		 1931
1932 for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) {
1933 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32))) < 0)
1934 return err;
1935 if (idx == 1) /* IEC958 (S/PDIF) Stream */
1936 rme32->spdif_ctl = kctl;
1937 }
1938
1939 return 0;
1940}
1941
1942/*
1943 * Card initialisation
1944 */
1945
017ce802 1946static void snd_rme32_card_free(struct snd_card *card)
1da177e4
LT		 1947{
1948 snd_rme32_free(card->private_data);
1949}
1950
1951static int __devinit
1952snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1953{
1954 static int dev;
017ce802
TI		 1955 struct rme32 *rme32;
1956 struct snd_card *card;
1da177e4
LT		 1957 int err;
1958
1959 if (dev >= SNDRV_CARDS) {
1960 return -ENODEV;
1961 }
1962 if (!enable[dev]) {
1963 dev++;
1964 return -ENOENT;
1965 }
1966
1967 if ((card = snd_card_new(index[dev], id[dev], THIS_MODULE,
017ce802 1968 sizeof(struct rme32))) == NULL)
1da177e4
LT		 1969 return -ENOMEM;
1970 card->private_free = snd_rme32_card_free;
017ce802 1971 rme32 = (struct rme32 *) card->private_data;
1da177e4
LT		 1972 rme32->card = card;
1973 rme32->pci = pci;
1974 snd_card_set_dev(card, &pci->dev);
1975 if (fullduplex[dev])
1976 rme32->fullduplex_mode = 1;
1977 if ((err = snd_rme32_create(rme32)) < 0) {
1978 snd_card_free(card);
1979 return err;
1980 }
1981
1982 strcpy(card->driver, "Digi32");
1983 switch (rme32->pci->device) {
8b7fc421 1984 case PCI_DEVICE_ID_RME_DIGI32:
1da177e4
LT		 1985 strcpy(card->shortname, "RME Digi32");
1986 break;
8b7fc421 1987 case PCI_DEVICE_ID_RME_DIGI32_8:
1da177e4
LT		 1988 strcpy(card->shortname, "RME Digi32/8");
1989 break;
8b7fc421 1990 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1da177e4
LT		 1991 strcpy(card->shortname, "RME Digi32 PRO");
1992 break;
1993 }
1994 sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d",
1995 card->shortname, rme32->rev, rme32->port, rme32->irq);
1996
1997 if ((err = snd_card_register(card)) < 0) {
1998 snd_card_free(card);
1999 return err;
2000 }
2001 pci_set_drvdata(pci, card);
2002 dev++;
2003 return 0;
2004}
2005
2006static void __devexit snd_rme32_remove(struct pci_dev *pci)
2007{
2008 snd_card_free(pci_get_drvdata(pci));
2009 pci_set_drvdata(pci, NULL);
2010}
2011
2012static struct pci_driver driver = {
2013 .name = "RME Digi32",
2014 .id_table = snd_rme32_ids,
2015 .probe = snd_rme32_probe,
2016 .remove = __devexit_p(snd_rme32_remove),
2017};
2018
2019static int __init alsa_card_rme32_init(void)
2020{
01d25d46 2021 return pci_register_driver(&driver);
1da177e4
LT		 2022}
2023
2024static void __exit alsa_card_rme32_exit(void)
2025{
2026 pci_unregister_driver(&driver);
2027}
2028
2029module_init(alsa_card_rme32_init)
2030module_exit(alsa_card_rme32_exit)
Linux 6.x block layer and io_uring tree(s)