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Merge tag 'char-misc-4.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh...
[linux-2.6-block.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
5a613584 9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
079d88cc
WF		 10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
84eb01be
TI		 32#include <linux/init.h>
33#include <linux/delay.h>
34#include <linux/slab.h>
65a77217 35#include <linux/module.h>
84eb01be 36#include <sound/core.h>
07acecc1 37#include <sound/jack.h>
433968da 38#include <sound/asoundef.h>
d45e6889 39#include <sound/tlv.h>
25adc137
DH		 40#include <sound/hdaudio.h>
41#include <sound/hda_i915.h>
84eb01be
TI		 42#include "hda_codec.h"
43#include "hda_local.h"
1835a0f9 44#include "hda_jack.h"
84eb01be 45
0ebaa24c
TI		 46static bool static_hdmi_pcm;
47module_param(static_hdmi_pcm, bool, 0644);
48MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
49
7639a06c
TI		 50#define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
51#define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
52#define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
e2656412 53#define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
91815d8a 54#define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
432ac1a2 55#define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
91815d8a
LY		 56 || is_skylake(codec) || is_broxton(codec) \
57 || is_kabylake(codec))
75dcbe4d 58
7639a06c
TI		 59#define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
60#define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
ca2e7224 61#define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
fb87fa3a 62
384a48d7
SW		 63struct hdmi_spec_per_cvt {
64 hda_nid_t cvt_nid;
65 int assigned;
66 unsigned int channels_min;
67 unsigned int channels_max;
68 u32 rates;
69 u64 formats;
70 unsigned int maxbps;
71};
079d88cc 72
4eea3091
TI		 73/* max. connections to a widget */
74#define HDA_MAX_CONNECTIONS 32
75
384a48d7
SW		 76struct hdmi_spec_per_pin {
77 hda_nid_t pin_nid;
78 int num_mux_nids;
79 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
2df6742f 80 int mux_idx;
1df5a06a 81 hda_nid_t cvt_nid;
744626da
WF		 82
83 struct hda_codec *codec;
384a48d7 84 struct hdmi_eld sink_eld;
a4e9a38b 85 struct mutex lock;
744626da 86 struct delayed_work work;
92c69e79 87 struct snd_kcontrol *eld_ctl;
788d441a 88 struct snd_jack *acomp_jack; /* jack via audio component */
c6e8453e 89 int repoll_count;
b054087d
TI		 90 bool setup; /* the stream has been set up by prepare callback */
91 int channels; /* current number of channels */
1a6003b5 92 bool non_pcm;
d45e6889
TI		 93 bool chmap_set; /* channel-map override by ALSA API? */
94 unsigned char chmap[8]; /* ALSA API channel-map */
cd6a6503 95#ifdef CONFIG_SND_PROC_FS
a4e9a38b
TI		 96 struct snd_info_entry *proc_entry;
97#endif
384a48d7 98};
079d88cc 99
307229d2
AH		 100struct cea_channel_speaker_allocation;
101
102/* operations used by generic code that can be overridden by patches */
103struct hdmi_ops {
104 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
105 unsigned char *buf, int *eld_size);
106
107 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
108 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
109 int asp_slot);
110 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
111 int asp_slot, int channel);
112
113 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
114 int ca, int active_channels, int conn_type);
115
116 /* enable/disable HBR (HD passthrough) */
117 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
118
119 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
120 hda_nid_t pin_nid, u32 stream_tag, int format);
121
122 /* Helpers for producing the channel map TLVs. These can be overridden
123 * for devices that have non-standard mapping requirements. */
124 int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
125 int channels);
126 void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
127 unsigned int *chmap, int channels);
128
129 /* check that the user-given chmap is supported */
130 int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
131};
132
384a48d7
SW		 133struct hdmi_spec {
134 int num_cvts;
bce0d2a8
TI		 135 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
136 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 137
384a48d7 138 int num_pins;
bce0d2a8 139 struct snd_array pins; /* struct hdmi_spec_per_pin */
bbbc7e85 140 struct hda_pcm *pcm_rec[16];
d45e6889 141 unsigned int channels_max; /* max over all cvts */
079d88cc 142
4bd038f9 143 struct hdmi_eld temp_eld;
307229d2 144 struct hdmi_ops ops;
75fae117
SW		 145
146 bool dyn_pin_out;
147
079d88cc 148 /*
5a613584 149 * Non-generic VIA/NVIDIA specific
079d88cc
WF		 150 */
151 struct hda_multi_out multiout;
d0b1252d 152 struct hda_pcm_stream pcm_playback;
25adc137
DH		 153
154 /* i915/powerwell (Haswell+/Valleyview+) specific */
155 struct i915_audio_component_audio_ops i915_audio_ops;
55913110 156 bool i915_bound; /* was i915 bound in this driver? */
079d88cc
WF		 157};
158
f4e3040b 159#ifdef CONFIG_SND_HDA_I915
6603249d
TI		 160#define codec_has_acomp(codec) \
161 ((codec)->bus->core.audio_component != NULL)
f4e3040b
TI		 162#else
163#define codec_has_acomp(codec) false
164#endif
079d88cc
WF		 165
166struct hdmi_audio_infoframe {
167 u8 type; /* 0x84 */
168 u8 ver; /* 0x01 */
169 u8 len; /* 0x0a */
170
53d7d69d
WF		 171 u8 checksum;
172
079d88cc
WF		 173 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
174 u8 SS01_SF24;
175 u8 CXT04;
176 u8 CA;
177 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 178};
179
180struct dp_audio_infoframe {
181 u8 type; /* 0x84 */
182 u8 len; /* 0x1b */
183 u8 ver; /* 0x11 << 2 */
184
185 u8 CC02_CT47; /* match with HDMI infoframe from this on */
186 u8 SS01_SF24;
187 u8 CXT04;
188 u8 CA;
189 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 190};
191
2b203dbb
TI		 192union audio_infoframe {
193 struct hdmi_audio_infoframe hdmi;
194 struct dp_audio_infoframe dp;
195 u8 bytes[0];
196};
197
079d88cc
WF		 198/*
199 * CEA speaker placement:
200 *
201 * FLH FCH FRH
202 * FLW FL FLC FC FRC FR FRW
203 *
204 * LFE
205 * TC
206 *
207 * RL RLC RC RRC RR
208 *
209 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
210 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
211 */
212enum cea_speaker_placement {
213 FL = (1 << 0), /* Front Left */
214 FC = (1 << 1), /* Front Center */
215 FR = (1 << 2), /* Front Right */
216 FLC = (1 << 3), /* Front Left Center */
217 FRC = (1 << 4), /* Front Right Center */
218 RL = (1 << 5), /* Rear Left */
219 RC = (1 << 6), /* Rear Center */
220 RR = (1 << 7), /* Rear Right */
221 RLC = (1 << 8), /* Rear Left Center */
222 RRC = (1 << 9), /* Rear Right Center */
223 LFE = (1 << 10), /* Low Frequency Effect */
224 FLW = (1 << 11), /* Front Left Wide */
225 FRW = (1 << 12), /* Front Right Wide */
226 FLH = (1 << 13), /* Front Left High */
227 FCH = (1 << 14), /* Front Center High */
228 FRH = (1 << 15), /* Front Right High */
229 TC = (1 << 16), /* Top Center */
230};
231
232/*
233 * ELD SA bits in the CEA Speaker Allocation data block
234 */
235static int eld_speaker_allocation_bits[] = {
236 [0] = FL | FR,
237 [1] = LFE,
238 [2] = FC,
239 [3] = RL | RR,
240 [4] = RC,
241 [5] = FLC | FRC,
242 [6] = RLC | RRC,
243 /* the following are not defined in ELD yet */
244 [7] = FLW | FRW,
245 [8] = FLH | FRH,
246 [9] = TC,
247 [10] = FCH,
248};
249
250struct cea_channel_speaker_allocation {
251 int ca_index;
252 int speakers[8];
253
254 /* derived values, just for convenience */
255 int channels;
256 int spk_mask;
257};
258
259/*
260 * ALSA sequence is:
261 *
262 * surround40 surround41 surround50 surround51 surround71
263 * ch0 front left = = = =
264 * ch1 front right = = = =
265 * ch2 rear left = = = =
266 * ch3 rear right = = = =
267 * ch4 LFE center center center
268 * ch5 LFE LFE
269 * ch6 side left
270 * ch7 side right
271 *
272 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
273 */
274static int hdmi_channel_mapping[0x32][8] = {
275 /* stereo */
276 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
277 /* 2.1 */
278 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
279 /* Dolby Surround */
280 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
281 /* surround40 */
282 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
283 /* 4ch */
284 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
285 /* surround41 */
9396d317 286 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 287 /* surround50 */
288 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
289 /* surround51 */
290 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
291 /* 7.1 */
292 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
293};
294
295/*
296 * This is an ordered list!
297 *
298 * The preceding ones have better chances to be selected by
53d7d69d 299 * hdmi_channel_allocation().
079d88cc
WF		 300 */
301static struct cea_channel_speaker_allocation channel_allocations[] = {
302/* channel: 7 6 5 4 3 2 1 0 */
303{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
304 /* 2.1 */
305{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
306 /* Dolby Surround */
307{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
308 /* surround40 */
309{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
310 /* surround41 */
311{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
312 /* surround50 */
313{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
314 /* surround51 */
315{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
316 /* 6.1 */
317{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
318 /* surround71 */
319{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
320
321{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
322{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
323{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
324{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
325{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
326{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
327{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
328{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
329{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
330{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
331{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
332{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
333{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
334{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
335{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
336{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
337{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
338{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
339{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
340{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
341{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
342{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
343{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
344{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
345{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
346{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
347{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
348{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
349{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
350{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
351{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
352{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
353{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
354{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
355{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
356{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
357{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
358{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
359{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
360{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
361{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
362};
363
364
365/*
366 * HDMI routines
367 */
368
bce0d2a8
TI		 369#define get_pin(spec, idx) \
370 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
371#define get_cvt(spec, idx) \
372 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
bbbc7e85 373#define get_pcm_rec(spec, idx) ((spec)->pcm_rec[idx])
bce0d2a8 374
4e76a883 375static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 376{
4e76a883 377 struct hdmi_spec *spec = codec->spec;
384a48d7 378 int pin_idx;
079d88cc 379
384a48d7 380 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 381 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
384a48d7 382 return pin_idx;
079d88cc 383
4e76a883 384 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
384a48d7
SW		 385 return -EINVAL;
386}
387
4e76a883 388static int hinfo_to_pin_index(struct hda_codec *codec,
384a48d7
SW		 389 struct hda_pcm_stream *hinfo)
390{
4e76a883 391 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 392 int pin_idx;
393
394 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 395 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
384a48d7
SW		 396 return pin_idx;
397
4e76a883 398 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
384a48d7
SW		 399 return -EINVAL;
400}
401
4e76a883 402static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
384a48d7 403{
4e76a883 404 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 405 int cvt_idx;
406
407 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 408 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 409 return cvt_idx;
410
4e76a883 411 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 412 return -EINVAL;
413}
414
14bc52b8
PLB		 415static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
416 struct snd_ctl_elem_info *uinfo)
417{
418 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 419 struct hdmi_spec *spec = codec->spec;
a4e9a38b 420 struct hdmi_spec_per_pin *per_pin;
68e03de9 421 struct hdmi_eld *eld;
14bc52b8
PLB		 422 int pin_idx;
423
14bc52b8
PLB		 424 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
425
426 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 427 per_pin = get_pin(spec, pin_idx);
428 eld = &per_pin->sink_eld;
68e03de9 429
a4e9a38b 430 mutex_lock(&per_pin->lock);
68e03de9 431 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
a4e9a38b 432 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 433
434 return 0;
435}
436
437static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
438 struct snd_ctl_elem_value *ucontrol)
439{
440 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 441 struct hdmi_spec *spec = codec->spec;
a4e9a38b 442 struct hdmi_spec_per_pin *per_pin;
68e03de9 443 struct hdmi_eld *eld;
14bc52b8
PLB		 444 int pin_idx;
445
14bc52b8 446 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 447 per_pin = get_pin(spec, pin_idx);
448 eld = &per_pin->sink_eld;
68e03de9 449
a4e9a38b 450 mutex_lock(&per_pin->lock);
360a8245
DH		 451 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
452 eld->eld_size > ELD_MAX_SIZE) {
a4e9a38b 453 mutex_unlock(&per_pin->lock);
68e03de9
DH		 454 snd_BUG();
455 return -EINVAL;
456 }
457
458 memset(ucontrol->value.bytes.data, 0,
459 ARRAY_SIZE(ucontrol->value.bytes.data));
460 if (eld->eld_valid)
461 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
462 eld->eld_size);
a4e9a38b 463 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 464
465 return 0;
466}
467
468static struct snd_kcontrol_new eld_bytes_ctl = {
469 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
470 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
471 .name = "ELD",
472 .info = hdmi_eld_ctl_info,
473 .get = hdmi_eld_ctl_get,
474};
475
476static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
477 int device)
478{
479 struct snd_kcontrol *kctl;
480 struct hdmi_spec *spec = codec->spec;
481 int err;
482
483 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
484 if (!kctl)
485 return -ENOMEM;
486 kctl->private_value = pin_idx;
487 kctl->id.device = device;
488
bce0d2a8 489 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
14bc52b8
PLB		 490 if (err < 0)
491 return err;
492
bce0d2a8 493 get_pin(spec, pin_idx)->eld_ctl = kctl;
14bc52b8
PLB		 494 return 0;
495}
496
079d88cc
WF		 497#ifdef BE_PARANOID
498static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
499 int *packet_index, int *byte_index)
500{
501 int val;
502
503 val = snd_hda_codec_read(codec, pin_nid, 0,
504 AC_VERB_GET_HDMI_DIP_INDEX, 0);
505
506 *packet_index = val >> 5;
507 *byte_index = val & 0x1f;
508}
509#endif
510
511static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
512 int packet_index, int byte_index)
513{
514 int val;
515
516 val = (packet_index << 5) | (byte_index & 0x1f);
517
518 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
519}
520
521static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
522 unsigned char val)
523{
524 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
525}
526
384a48d7 527static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 528{
75fae117
SW		 529 struct hdmi_spec *spec = codec->spec;
530 int pin_out;
531
079d88cc
WF		 532 /* Unmute */
533 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
534 snd_hda_codec_write(codec, pin_nid, 0,
535 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
75fae117
SW		 536
537 if (spec->dyn_pin_out)
538 /* Disable pin out until stream is active */
539 pin_out = 0;
540 else
541 /* Enable pin out: some machines with GM965 gets broken output
542 * when the pin is disabled or changed while using with HDMI
543 */
544 pin_out = PIN_OUT;
545
079d88cc 546 snd_hda_codec_write(codec, pin_nid, 0,
75fae117 547 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
079d88cc
WF		 548}
549
384a48d7 550static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 551{
384a48d7 552 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 553 AC_VERB_GET_CVT_CHAN_COUNT, 0);
554}
555
556static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 557 hda_nid_t cvt_nid, int chs)
079d88cc 558{
384a48d7
SW		 559 if (chs != hdmi_get_channel_count(codec, cvt_nid))
560 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 561 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
562}
563
a4e9a38b
TI		 564/*
565 * ELD proc files
566 */
567
cd6a6503 568#ifdef CONFIG_SND_PROC_FS
a4e9a38b
TI		 569static void print_eld_info(struct snd_info_entry *entry,
570 struct snd_info_buffer *buffer)
571{
572 struct hdmi_spec_per_pin *per_pin = entry->private_data;
573
574 mutex_lock(&per_pin->lock);
575 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
576 mutex_unlock(&per_pin->lock);
577}
578
579static void write_eld_info(struct snd_info_entry *entry,
580 struct snd_info_buffer *buffer)
581{
582 struct hdmi_spec_per_pin *per_pin = entry->private_data;
583
584 mutex_lock(&per_pin->lock);
585 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
586 mutex_unlock(&per_pin->lock);
587}
588
589static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
590{
591 char name[32];
592 struct hda_codec *codec = per_pin->codec;
593 struct snd_info_entry *entry;
594 int err;
595
596 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
6efdd851 597 err = snd_card_proc_new(codec->card, name, &entry);
a4e9a38b
TI		 598 if (err < 0)
599 return err;
600
601 snd_info_set_text_ops(entry, per_pin, print_eld_info);
602 entry->c.text.write = write_eld_info;
603 entry->mode |= S_IWUSR;
604 per_pin->proc_entry = entry;
605
606 return 0;
607}
608
609static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
610{
1947a114 611 if (!per_pin->codec->bus->shutdown) {
c560a679 612 snd_info_free_entry(per_pin->proc_entry);
a4e9a38b
TI		 613 per_pin->proc_entry = NULL;
614 }
615}
616#else
b55447a7
TI		 617static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
618 int index)
a4e9a38b
TI		 619{
620 return 0;
621}
b55447a7 622static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
a4e9a38b
TI		 623{
624}
625#endif
079d88cc
WF		 626
627/*
628 * Channel mapping routines
629 */
630
631/*
632 * Compute derived values in channel_allocations[].
633 */
634static void init_channel_allocations(void)
635{
636 int i, j;
637 struct cea_channel_speaker_allocation *p;
638
639 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
640 p = channel_allocations + i;
641 p->channels = 0;
642 p->spk_mask = 0;
643 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
644 if (p->speakers[j]) {
645 p->channels++;
646 p->spk_mask |= p->speakers[j];
647 }
648 }
649}
650
72357c78
WX		 651static int get_channel_allocation_order(int ca)
652{
653 int i;
654
655 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
656 if (channel_allocations[i].ca_index == ca)
657 break;
658 }
659 return i;
660}
661
079d88cc
WF		 662/*
663 * The transformation takes two steps:
664 *
665 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
666 * spk_mask => (channel_allocations[]) => ai->CA
667 *
668 * TODO: it could select the wrong CA from multiple candidates.
669*/
79514d47
TI		 670static int hdmi_channel_allocation(struct hda_codec *codec,
671 struct hdmi_eld *eld, int channels)
079d88cc 672{
079d88cc 673 int i;
53d7d69d 674 int ca = 0;
079d88cc 675 int spk_mask = 0;
079d88cc
WF		 676 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
677
678 /*
679 * CA defaults to 0 for basic stereo audio
680 */
681 if (channels <= 2)
682 return 0;
683
079d88cc
WF		 684 /*
685 * expand ELD's speaker allocation mask
686 *
687 * ELD tells the speaker mask in a compact(paired) form,
688 * expand ELD's notions to match the ones used by Audio InfoFrame.
689 */
690 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
1613d6b4 691 if (eld->info.spk_alloc & (1 << i))
079d88cc
WF		 692 spk_mask |= eld_speaker_allocation_bits[i];
693 }
694
695 /* search for the first working match in the CA table */
696 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
697 if (channels == channel_allocations[i].channels &&
698 (spk_mask & channel_allocations[i].spk_mask) ==
699 channel_allocations[i].spk_mask) {
53d7d69d 700 ca = channel_allocations[i].ca_index;
079d88cc
WF		 701 break;
702 }
703 }
704
18e39186
AH		 705 if (!ca) {
706 /* if there was no match, select the regular ALSA channel
707 * allocation with the matching number of channels */
708 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
709 if (channels == channel_allocations[i].channels) {
710 ca = channel_allocations[i].ca_index;
711 break;
712 }
713 }
714 }
715
1613d6b4 716 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
79514d47 717 codec_dbg(codec, "HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 718 ca, channels, buf);
079d88cc 719
53d7d69d 720 return ca;
079d88cc
WF		 721}
722
723static void hdmi_debug_channel_mapping(struct hda_codec *codec,
724 hda_nid_t pin_nid)
725{
726#ifdef CONFIG_SND_DEBUG_VERBOSE
307229d2 727 struct hdmi_spec *spec = codec->spec;
079d88cc 728 int i;
307229d2 729 int channel;
079d88cc
WF		 730
731 for (i = 0; i < 8; i++) {
307229d2 732 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
4e76a883 733 codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n",
307229d2 734 channel, i);
079d88cc
WF		 735 }
736#endif
737}
738
d45e6889 739static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 740 hda_nid_t pin_nid,
433968da 741 bool non_pcm,
53d7d69d 742 int ca)
079d88cc 743{
307229d2 744 struct hdmi_spec *spec = codec->spec;
90f28002 745 struct cea_channel_speaker_allocation *ch_alloc;
079d88cc 746 int i;
079d88cc 747 int err;
72357c78 748 int order;
433968da 749 int non_pcm_mapping[8];
079d88cc 750
72357c78 751 order = get_channel_allocation_order(ca);
90f28002 752 ch_alloc = &channel_allocations[order];
433968da 753
079d88cc 754 if (hdmi_channel_mapping[ca][1] == 0) {
90f28002
AH		 755 int hdmi_slot = 0;
756 /* fill actual channel mappings in ALSA channel (i) order */
757 for (i = 0; i < ch_alloc->channels; i++) {
758 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
759 hdmi_slot++; /* skip zero slots */
760
761 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
762 }
763 /* fill the rest of the slots with ALSA channel 0xf */
764 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
765 if (!ch_alloc->speakers[7 - hdmi_slot])
766 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
079d88cc
WF		 767 }
768
433968da 769 if (non_pcm) {
90f28002 770 for (i = 0; i < ch_alloc->channels; i++)
11f7c52d 771 non_pcm_mapping[i] = (i << 4) | i;
433968da 772 for (; i < 8; i++)
11f7c52d 773 non_pcm_mapping[i] = (0xf << 4) | i;
433968da
WX		 774 }
775
079d88cc 776 for (i = 0; i < 8; i++) {
307229d2
AH		 777 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
778 int hdmi_slot = slotsetup & 0x0f;
779 int channel = (slotsetup & 0xf0) >> 4;
780 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
079d88cc 781 if (err) {
4e76a883 782 codec_dbg(codec, "HDMI: channel mapping failed\n");
079d88cc
WF		 783 break;
784 }
785 }
079d88cc
WF		 786}
787
d45e6889
TI		 788struct channel_map_table {
789 unsigned char map; /* ALSA API channel map position */
d45e6889
TI		 790 int spk_mask; /* speaker position bit mask */
791};
792
793static struct channel_map_table map_tables[] = {
a5b7d510
AH		 794 { SNDRV_CHMAP_FL, FL },
795 { SNDRV_CHMAP_FR, FR },
796 { SNDRV_CHMAP_RL, RL },
797 { SNDRV_CHMAP_RR, RR },
798 { SNDRV_CHMAP_LFE, LFE },
799 { SNDRV_CHMAP_FC, FC },
800 { SNDRV_CHMAP_RLC, RLC },
801 { SNDRV_CHMAP_RRC, RRC },
802 { SNDRV_CHMAP_RC, RC },
803 { SNDRV_CHMAP_FLC, FLC },
804 { SNDRV_CHMAP_FRC, FRC },
94908a39
AH		 805 { SNDRV_CHMAP_TFL, FLH },
806 { SNDRV_CHMAP_TFR, FRH },
a5b7d510
AH		 807 { SNDRV_CHMAP_FLW, FLW },
808 { SNDRV_CHMAP_FRW, FRW },
809 { SNDRV_CHMAP_TC, TC },
94908a39 810 { SNDRV_CHMAP_TFC, FCH },
d45e6889
TI		 811 {} /* terminator */
812};
813
814/* from ALSA API channel position to speaker bit mask */
815static int to_spk_mask(unsigned char c)
816{
817 struct channel_map_table *t = map_tables;
818 for (; t->map; t++) {
819 if (t->map == c)
820 return t->spk_mask;
821 }
822 return 0;
823}
824
825/* from ALSA API channel position to CEA slot */
a5b7d510 826static int to_cea_slot(int ordered_ca, unsigned char pos)
d45e6889 827{
a5b7d510
AH		 828 int mask = to_spk_mask(pos);
829 int i;
d45e6889 830
a5b7d510
AH		 831 if (mask) {
832 for (i = 0; i < 8; i++) {
833 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
834 return i;
835 }
d45e6889 836 }
a5b7d510
AH		 837
838 return -1;
d45e6889
TI		 839}
840
841/* from speaker bit mask to ALSA API channel position */
842static int spk_to_chmap(int spk)
843{
844 struct channel_map_table *t = map_tables;
845 for (; t->map; t++) {
846 if (t->spk_mask == spk)
847 return t->map;
848 }
849 return 0;
850}
851
a5b7d510
AH		 852/* from CEA slot to ALSA API channel position */
853static int from_cea_slot(int ordered_ca, unsigned char slot)
854{
855 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
856
857 return spk_to_chmap(mask);
858}
859
d45e6889
TI		 860/* get the CA index corresponding to the given ALSA API channel map */
861static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
862{
863 int i, spks = 0, spk_mask = 0;
864
865 for (i = 0; i < chs; i++) {
866 int mask = to_spk_mask(map[i]);
867 if (mask) {
868 spk_mask |= mask;
869 spks++;
870 }
871 }
872
873 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
874 if ((chs == channel_allocations[i].channels ||
875 spks == channel_allocations[i].channels) &&
876 (spk_mask & channel_allocations[i].spk_mask) ==
877 channel_allocations[i].spk_mask)
878 return channel_allocations[i].ca_index;
879 }
880 return -1;
881}
882
883/* set up the channel slots for the given ALSA API channel map */
884static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
885 hda_nid_t pin_nid,
a5b7d510
AH		 886 int chs, unsigned char *map,
887 int ca)
d45e6889 888{
307229d2 889 struct hdmi_spec *spec = codec->spec;
a5b7d510 890 int ordered_ca = get_channel_allocation_order(ca);
11f7c52d
AH		 891 int alsa_pos, hdmi_slot;
892 int assignments[8] = {[0 ... 7] = 0xf};
893
894 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
895
a5b7d510 896 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
11f7c52d
AH		 897
898 if (hdmi_slot < 0)
899 continue; /* unassigned channel */
900
901 assignments[hdmi_slot] = alsa_pos;
902 }
903
904 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
307229d2 905 int err;
11f7c52d 906
307229d2
AH		 907 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
908 assignments[hdmi_slot]);
d45e6889
TI		 909 if (err)
910 return -EINVAL;
911 }
912 return 0;
913}
914
915/* store ALSA API channel map from the current default map */
916static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
917{
918 int i;
56cac413 919 int ordered_ca = get_channel_allocation_order(ca);
d45e6889 920 for (i = 0; i < 8; i++) {
56cac413 921 if (i < channel_allocations[ordered_ca].channels)
a5b7d510 922 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
d45e6889
TI		 923 else
924 map[i] = 0;
925 }
926}
927
928static void hdmi_setup_channel_mapping(struct hda_codec *codec,
929 hda_nid_t pin_nid, bool non_pcm, int ca,
20608731
AH		 930 int channels, unsigned char *map,
931 bool chmap_set)
d45e6889 932{
20608731 933 if (!non_pcm && chmap_set) {
d45e6889 934 hdmi_manual_setup_channel_mapping(codec, pin_nid,
a5b7d510 935 channels, map, ca);
d45e6889
TI		 936 } else {
937 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
938 hdmi_setup_fake_chmap(map, ca);
939 }
980b2495
AH		 940
941 hdmi_debug_channel_mapping(codec, pin_nid);
d45e6889 942}
079d88cc 943
307229d2
AH		 944static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
945 int asp_slot, int channel)
946{
947 return snd_hda_codec_write(codec, pin_nid, 0,
948 AC_VERB_SET_HDMI_CHAN_SLOT,
949 (channel << 4) | asp_slot);
950}
951
952static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
953 int asp_slot)
954{
955 return (snd_hda_codec_read(codec, pin_nid, 0,
956 AC_VERB_GET_HDMI_CHAN_SLOT,
957 asp_slot) & 0xf0) >> 4;
958}
959
079d88cc
WF		 960/*
961 * Audio InfoFrame routines
962 */
963
964/*
965 * Enable Audio InfoFrame Transmission
966 */
967static void hdmi_start_infoframe_trans(struct hda_codec *codec,
968 hda_nid_t pin_nid)
969{
970 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
971 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
972 AC_DIPXMIT_BEST);
973}
974
975/*
976 * Disable Audio InfoFrame Transmission
977 */
978static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
979 hda_nid_t pin_nid)
980{
981 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
982 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
983 AC_DIPXMIT_DISABLE);
984}
985
986static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
987{
988#ifdef CONFIG_SND_DEBUG_VERBOSE
989 int i;
990 int size;
991
992 size = snd_hdmi_get_eld_size(codec, pin_nid);
4e76a883 993 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
079d88cc
WF		 994
995 for (i = 0; i < 8; i++) {
996 size = snd_hda_codec_read(codec, pin_nid, 0,
997 AC_VERB_GET_HDMI_DIP_SIZE, i);
4e76a883 998 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
079d88cc
WF		 999 }
1000#endif
1001}
1002
1003static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
1004{
1005#ifdef BE_PARANOID
1006 int i, j;
1007 int size;
1008 int pi, bi;
1009 for (i = 0; i < 8; i++) {
1010 size = snd_hda_codec_read(codec, pin_nid, 0,
1011 AC_VERB_GET_HDMI_DIP_SIZE, i);
1012 if (size == 0)
1013 continue;
1014
1015 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
1016 for (j = 1; j < 1000; j++) {
1017 hdmi_write_dip_byte(codec, pin_nid, 0x0);
1018 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
1019 if (pi != i)
4e76a883 1020 codec_dbg(codec, "dip index %d: %d != %d\n",
079d88cc
WF		 1021 bi, pi, i);
1022 if (bi == 0) /* byte index wrapped around */
1023 break;
1024 }
4e76a883 1025 codec_dbg(codec,
079d88cc
WF		 1026 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
1027 i, size, j);
1028 }
1029#endif
1030}
1031
53d7d69d 1032static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 1033{
53d7d69d 1034 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 1035 u8 sum = 0;
1036 int i;
1037
53d7d69d 1038 hdmi_ai->checksum = 0;
079d88cc 1039
53d7d69d 1040 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 1041 sum += bytes[i];
1042
53d7d69d 1043 hdmi_ai->checksum = -sum;
079d88cc
WF		 1044}
1045
1046static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1047 hda_nid_t pin_nid,
53d7d69d 1048 u8 *dip, int size)
079d88cc 1049{
079d88cc
WF		 1050 int i;
1051
1052 hdmi_debug_dip_size(codec, pin_nid);
1053 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1054
079d88cc 1055 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 1056 for (i = 0; i < size; i++)
1057 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 1058}
1059
1060static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 1061 u8 *dip, int size)
079d88cc 1062{
079d88cc
WF		 1063 u8 val;
1064 int i;
1065
1066 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1067 != AC_DIPXMIT_BEST)
1068 return false;
1069
1070 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 1071 for (i = 0; i < size; i++) {
079d88cc
WF		 1072 val = snd_hda_codec_read(codec, pin_nid, 0,
1073 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 1074 if (val != dip[i])
079d88cc
WF		 1075 return false;
1076 }
1077
1078 return true;
1079}
1080
307229d2
AH		 1081static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1082 hda_nid_t pin_nid,
1083 int ca, int active_channels,
1084 int conn_type)
1085{
1086 union audio_infoframe ai;
1087
caaf5ef9 1088 memset(&ai, 0, sizeof(ai));
307229d2
AH		 1089 if (conn_type == 0) { /* HDMI */
1090 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1091
1092 hdmi_ai->type = 0x84;
1093 hdmi_ai->ver = 0x01;
1094 hdmi_ai->len = 0x0a;
1095 hdmi_ai->CC02_CT47 = active_channels - 1;
1096 hdmi_ai->CA = ca;
1097 hdmi_checksum_audio_infoframe(hdmi_ai);
1098 } else if (conn_type == 1) { /* DisplayPort */
1099 struct dp_audio_infoframe *dp_ai = &ai.dp;
1100
1101 dp_ai->type = 0x84;
1102 dp_ai->len = 0x1b;
1103 dp_ai->ver = 0x11 << 2;
1104 dp_ai->CC02_CT47 = active_channels - 1;
1105 dp_ai->CA = ca;
1106 } else {
4e76a883 1107 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
307229d2
AH		 1108 pin_nid);
1109 return;
1110 }
1111
1112 /*
1113 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1114 * sizeof(*dp_ai) to avoid partial match/update problems when
1115 * the user switches between HDMI/DP monitors.
1116 */
1117 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1118 sizeof(ai))) {
4e76a883
TI		 1119 codec_dbg(codec,
1120 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
307229d2
AH		 1121 pin_nid,
1122 active_channels, ca);
1123 hdmi_stop_infoframe_trans(codec, pin_nid);
1124 hdmi_fill_audio_infoframe(codec, pin_nid,
1125 ai.bytes, sizeof(ai));
1126 hdmi_start_infoframe_trans(codec, pin_nid);
1127 }
1128}
1129
b054087d
TI		 1130static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1131 struct hdmi_spec_per_pin *per_pin,
1132 bool non_pcm)
079d88cc 1133{
307229d2 1134 struct hdmi_spec *spec = codec->spec;
384a48d7 1135 hda_nid_t pin_nid = per_pin->pin_nid;
b054087d 1136 int channels = per_pin->channels;
1df5a06a 1137 int active_channels;
384a48d7 1138 struct hdmi_eld *eld;
1df5a06a 1139 int ca, ordered_ca;
079d88cc 1140
b054087d
TI		 1141 if (!channels)
1142 return;
1143
75dcbe4d 1144 if (is_haswell_plus(codec))
58f7d28d
ML		 1145 snd_hda_codec_write(codec, pin_nid, 0,
1146 AC_VERB_SET_AMP_GAIN_MUTE,
1147 AMP_OUT_UNMUTE);
1148
bce0d2a8 1149 eld = &per_pin->sink_eld;
079d88cc 1150
d45e6889
TI		 1151 if (!non_pcm && per_pin->chmap_set)
1152 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1153 else
79514d47 1154 ca = hdmi_channel_allocation(codec, eld, channels);
d45e6889
TI		 1155 if (ca < 0)
1156 ca = 0;
384a48d7 1157
1df5a06a
AH		 1158 ordered_ca = get_channel_allocation_order(ca);
1159 active_channels = channel_allocations[ordered_ca].channels;
1160
1161 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1162
39edac70
AH		 1163 /*
1164 * always configure channel mapping, it may have been changed by the
1165 * user in the meantime
1166 */
1167 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1168 channels, per_pin->chmap,
1169 per_pin->chmap_set);
1170
307229d2
AH		 1171 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1172 eld->info.conn_type);
433968da 1173
1a6003b5 1174 per_pin->non_pcm = non_pcm;
079d88cc
WF		 1175}
1176
079d88cc
WF		 1177/*
1178 * Unsolicited events
1179 */
1180
efe47108 1181static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 1182
1a4f69d5 1183static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
079d88cc
WF		 1184{
1185 struct hdmi_spec *spec = codec->spec;
1a4f69d5
TI		 1186 int pin_idx = pin_nid_to_pin_index(codec, nid);
1187
20ce9029
DH		 1188 if (pin_idx < 0)
1189 return;
20ce9029
DH		 1190 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1191 snd_hda_jack_report_sync(codec);
1192}
1193
1a4f69d5
TI		 1194static void jack_callback(struct hda_codec *codec,
1195 struct hda_jack_callback *jack)
1196{
2ebab40e 1197 check_presence_and_report(codec, jack->nid);
1a4f69d5
TI		 1198}
1199
20ce9029
DH		 1200static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1201{
3a93897e 1202 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
3a93897e 1203 struct hda_jack_tbl *jack;
2e59e5ab 1204 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
3a93897e
TI		 1205
1206 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1207 if (!jack)
1208 return;
3a93897e 1209 jack->jack_dirty = 1;
079d88cc 1210
4e76a883 1211 codec_dbg(codec,
2e59e5ab 1212 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
20ce9029 1213 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
fae3d88a 1214 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 1215
1a4f69d5 1216 check_presence_and_report(codec, jack->nid);
079d88cc
WF		 1217}
1218
1219static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1220{
1221 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1222 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1223 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1224 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1225
4e76a883 1226 codec_info(codec,
e9ea8e8f 1227 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 1228 codec->addr,
079d88cc
WF		 1229 tag,
1230 subtag,
1231 cp_state,
1232 cp_ready);
1233
1234 /* TODO */
1235 if (cp_state)
1236 ;
1237 if (cp_ready)
1238 ;
1239}
1240
1241
1242static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1243{
079d88cc
WF		 1244 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1245 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1246
3a93897e 1247 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
4e76a883 1248 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
079d88cc
WF		 1249 return;
1250 }
1251
1252 if (subtag == 0)
1253 hdmi_intrinsic_event(codec, res);
1254 else
1255 hdmi_non_intrinsic_event(codec, res);
1256}
1257
58f7d28d 1258static void haswell_verify_D0(struct hda_codec *codec,
53b434f0 1259 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2 1260{
58f7d28d 1261 int pwr;
83f26ad2 1262
53b434f0
WX		 1263 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1264 * thus pins could only choose converter 0 for use. Make sure the
1265 * converters are in correct power state */
fd678cac 1266 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 1267 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1268
fd678cac 1269 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 1270 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1271 AC_PWRST_D0);
1272 msleep(40);
1273 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1274 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
4e76a883 1275 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
83f26ad2 1276 }
83f26ad2
DH		 1277}
1278
079d88cc
WF		 1279/*
1280 * Callbacks
1281 */
1282
92f10b3f
TI		 1283/* HBR should be Non-PCM, 8 channels */
1284#define is_hbr_format(format) \
1285 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1286
307229d2
AH		 1287static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1288 bool hbr)
079d88cc 1289{
307229d2 1290 int pinctl, new_pinctl;
83f26ad2 1291
384a48d7
SW		 1292 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1293 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1294 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1295
13122e6e
AH		 1296 if (pinctl < 0)
1297 return hbr ? -EINVAL : 0;
1298
ea87d1c4 1299 new_pinctl = pinctl & ~AC_PINCTL_EPT;
307229d2 1300 if (hbr)
ea87d1c4
AH		 1301 new_pinctl |= AC_PINCTL_EPT_HBR;
1302 else
1303 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1304
4e76a883
TI		 1305 codec_dbg(codec,
1306 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
384a48d7 1307 pin_nid,
ea87d1c4
AH		 1308 pinctl == new_pinctl ? "" : "new-",
1309 new_pinctl);
1310
1311 if (pinctl != new_pinctl)
384a48d7 1312 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1313 AC_VERB_SET_PIN_WIDGET_CONTROL,
1314 new_pinctl);
307229d2
AH		 1315 } else if (hbr)
1316 return -EINVAL;
ea87d1c4 1317
307229d2
AH		 1318 return 0;
1319}
1320
1321static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1322 hda_nid_t pin_nid, u32 stream_tag, int format)
1323{
1324 struct hdmi_spec *spec = codec->spec;
1325 int err;
1326
75dcbe4d 1327 if (is_haswell_plus(codec))
307229d2
AH		 1328 haswell_verify_D0(codec, cvt_nid, pin_nid);
1329
1330 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1331
1332 if (err) {
4e76a883 1333 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
307229d2 1334 return err;
ea87d1c4 1335 }
079d88cc 1336
384a48d7 1337 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1338 return 0;
079d88cc
WF		 1339}
1340
7ef166b8
WX		 1341static int hdmi_choose_cvt(struct hda_codec *codec,
1342 int pin_idx, int *cvt_id, int *mux_id)
bbbe3390
TI		 1343{
1344 struct hdmi_spec *spec = codec->spec;
384a48d7 1345 struct hdmi_spec_per_pin *per_pin;
384a48d7 1346 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 1347 int cvt_idx, mux_idx = 0;
bbbe3390 1348
bce0d2a8 1349 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 1350
1351 /* Dynamically assign converter to stream */
1352 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 1353 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 1354
384a48d7
SW		 1355 /* Must not already be assigned */
1356 if (per_cvt->assigned)
1357 continue;
1358 /* Must be in pin's mux's list of converters */
1359 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1360 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1361 break;
1362 /* Not in mux list */
1363 if (mux_idx == per_pin->num_mux_nids)
1364 continue;
1365 break;
1366 }
7ef166b8 1367
384a48d7
SW		 1368 /* No free converters */
1369 if (cvt_idx == spec->num_cvts)
1370 return -ENODEV;
1371
2df6742f
ML		 1372 per_pin->mux_idx = mux_idx;
1373
7ef166b8
WX		 1374 if (cvt_id)
1375 *cvt_id = cvt_idx;
1376 if (mux_id)
1377 *mux_id = mux_idx;
1378
1379 return 0;
1380}
1381
2df6742f
ML		 1382/* Assure the pin select the right convetor */
1383static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1384 struct hdmi_spec_per_pin *per_pin)
1385{
1386 hda_nid_t pin_nid = per_pin->pin_nid;
1387 int mux_idx, curr;
1388
1389 mux_idx = per_pin->mux_idx;
1390 curr = snd_hda_codec_read(codec, pin_nid, 0,
1391 AC_VERB_GET_CONNECT_SEL, 0);
1392 if (curr != mux_idx)
1393 snd_hda_codec_write_cache(codec, pin_nid, 0,
1394 AC_VERB_SET_CONNECT_SEL,
1395 mux_idx);
1396}
1397
300016b9
ML		 1398/* Intel HDMI workaround to fix audio routing issue:
1399 * For some Intel display codecs, pins share the same connection list.
1400 * So a conveter can be selected by multiple pins and playback on any of these
1401 * pins will generate sound on the external display, because audio flows from
1402 * the same converter to the display pipeline. Also muting one pin may make
1403 * other pins have no sound output.
1404 * So this function assures that an assigned converter for a pin is not selected
1405 * by any other pins.
1406 */
1407static void intel_not_share_assigned_cvt(struct hda_codec *codec,
f82d7d16 1408 hda_nid_t pin_nid, int mux_idx)
7ef166b8
WX		 1409{
1410 struct hdmi_spec *spec = codec->spec;
7639a06c 1411 hda_nid_t nid;
f82d7d16
ML		 1412 int cvt_idx, curr;
1413 struct hdmi_spec_per_cvt *per_cvt;
7ef166b8 1414
f82d7d16 1415 /* configure all pins, including "no physical connection" ones */
7639a06c 1416 for_each_hda_codec_node(nid, codec) {
f82d7d16
ML		 1417 unsigned int wid_caps = get_wcaps(codec, nid);
1418 unsigned int wid_type = get_wcaps_type(wid_caps);
1419
1420 if (wid_type != AC_WID_PIN)
1421 continue;
7ef166b8 1422
f82d7d16 1423 if (nid == pin_nid)
7ef166b8
WX		 1424 continue;
1425
f82d7d16 1426 curr = snd_hda_codec_read(codec, nid, 0,
7ef166b8 1427 AC_VERB_GET_CONNECT_SEL, 0);
f82d7d16
ML		 1428 if (curr != mux_idx)
1429 continue;
7ef166b8 1430
f82d7d16
ML		 1431 /* choose an unassigned converter. The conveters in the
1432 * connection list are in the same order as in the codec.
1433 */
1434 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1435 per_cvt = get_cvt(spec, cvt_idx);
1436 if (!per_cvt->assigned) {
4e76a883
TI		 1437 codec_dbg(codec,
1438 "choose cvt %d for pin nid %d\n",
f82d7d16
ML		 1439 cvt_idx, nid);
1440 snd_hda_codec_write_cache(codec, nid, 0,
7ef166b8 1441 AC_VERB_SET_CONNECT_SEL,
f82d7d16
ML		 1442 cvt_idx);
1443 break;
1444 }
7ef166b8
WX		 1445 }
1446 }
1447}
1448
1449/*
1450 * HDA PCM callbacks
1451 */
1452static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1453 struct hda_codec *codec,
1454 struct snd_pcm_substream *substream)
1455{
1456 struct hdmi_spec *spec = codec->spec;
1457 struct snd_pcm_runtime *runtime = substream->runtime;
1458 int pin_idx, cvt_idx, mux_idx = 0;
1459 struct hdmi_spec_per_pin *per_pin;
1460 struct hdmi_eld *eld;
1461 struct hdmi_spec_per_cvt *per_cvt = NULL;
1462 int err;
1463
1464 /* Validate hinfo */
4e76a883 1465 pin_idx = hinfo_to_pin_index(codec, hinfo);
7ef166b8
WX		 1466 if (snd_BUG_ON(pin_idx < 0))
1467 return -EINVAL;
1468 per_pin = get_pin(spec, pin_idx);
1469 eld = &per_pin->sink_eld;
1470
1471 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1472 if (err < 0)
1473 return err;
1474
1475 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1476 /* Claim converter */
1477 per_cvt->assigned = 1;
1df5a06a 1478 per_pin->cvt_nid = per_cvt->cvt_nid;
384a48d7
SW		 1479 hinfo->nid = per_cvt->cvt_nid;
1480
bddee96b 1481 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7
SW		 1482 AC_VERB_SET_CONNECT_SEL,
1483 mux_idx);
7ef166b8
WX		 1484
1485 /* configure unused pins to choose other converters */
ca2e7224 1486 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
300016b9 1487 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
7ef166b8 1488
384a48d7 1489 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 1490
2def8172 1491 /* Initially set the converter's capabilities */
384a48d7
SW		 1492 hinfo->channels_min = per_cvt->channels_min;
1493 hinfo->channels_max = per_cvt->channels_max;
1494 hinfo->rates = per_cvt->rates;
1495 hinfo->formats = per_cvt->formats;
1496 hinfo->maxbps = per_cvt->maxbps;
2def8172 1497
384a48d7 1498 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1499 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1500 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1501 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1502 !hinfo->rates || !hinfo->formats) {
1503 per_cvt->assigned = 0;
1504 hinfo->nid = 0;
1505 snd_hda_spdif_ctls_unassign(codec, pin_idx);
bbbe3390 1506 return -ENODEV;
2ad779b7 1507 }
bbbe3390 1508 }
2def8172
SW		 1509
1510 /* Store the updated parameters */
639cef0e
TI		 1511 runtime->hw.channels_min = hinfo->channels_min;
1512 runtime->hw.channels_max = hinfo->channels_max;
1513 runtime->hw.formats = hinfo->formats;
1514 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1515
1516 snd_pcm_hw_constraint_step(substream->runtime, 0,
1517 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1518 return 0;
1519}
1520
079d88cc
WF		 1521/*
1522 * HDA/HDMI auto parsing
1523 */
384a48d7 1524static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1525{
1526 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1527 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1528 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1529
1530 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
4e76a883
TI		 1531 codec_warn(codec,
1532 "HDMI: pin %d wcaps %#x does not support connection list\n",
079d88cc
WF		 1533 pin_nid, get_wcaps(codec, pin_nid));
1534 return -EINVAL;
1535 }
1536
384a48d7
SW		 1537 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1538 per_pin->mux_nids,
1539 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1540
1541 return 0;
1542}
1543
e90247f9
TI		 1544/* update per_pin ELD from the given new ELD;
1545 * setup info frame and notification accordingly
1546 */
1547static void update_eld(struct hda_codec *codec,
1548 struct hdmi_spec_per_pin *per_pin,
1549 struct hdmi_eld *eld)
1550{
1551 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1552 bool old_eld_valid = pin_eld->eld_valid;
1553 bool eld_changed;
1554
1555 if (eld->eld_valid)
1556 snd_hdmi_show_eld(codec, &eld->info);
1557
1558 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1559 if (eld->eld_valid && pin_eld->eld_valid)
1560 if (pin_eld->eld_size != eld->eld_size ||
1561 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1562 eld->eld_size) != 0)
1563 eld_changed = true;
1564
1565 pin_eld->eld_valid = eld->eld_valid;
1566 pin_eld->eld_size = eld->eld_size;
1567 if (eld->eld_valid)
1568 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1569 pin_eld->info = eld->info;
1570
1571 /*
1572 * Re-setup pin and infoframe. This is needed e.g. when
1573 * - sink is first plugged-in
1574 * - transcoder can change during stream playback on Haswell
1575 * and this can make HW reset converter selection on a pin.
1576 */
1577 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1578 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1579 intel_verify_pin_cvt_connect(codec, per_pin);
1580 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
1581 per_pin->mux_idx);
1582 }
1583
1584 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1585 }
1586
1587 if (eld_changed)
1588 snd_ctl_notify(codec->card,
1589 SNDRV_CTL_EVENT_MASK_VALUE |
1590 SNDRV_CTL_EVENT_MASK_INFO,
1591 &per_pin->eld_ctl->id);
1592}
1593
788d441a
TI		 1594/* update ELD and jack state via HD-audio verbs */
1595static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1596 int repoll)
079d88cc 1597{
464837a7 1598 struct hda_jack_tbl *jack;
744626da 1599 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1600 struct hdmi_spec *spec = codec->spec;
1601 struct hdmi_eld *eld = &spec->temp_eld;
1602 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
744626da 1603 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1604 /*
1605 * Always execute a GetPinSense verb here, even when called from
1606 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1607 * response's PD bit is not the real PD value, but indicates that
1608 * the real PD value changed. An older version of the HD-audio
1609 * specification worked this way. Hence, we just ignore the data in
1610 * the unsolicited response to avoid custom WARs.
1611 */
da4a7a39 1612 int present;
efe47108 1613 bool ret;
9a5e5234 1614 bool do_repoll = false;
079d88cc 1615
664c7155 1616 snd_hda_power_up_pm(codec);
da4a7a39
DH		 1617 present = snd_hda_pin_sense(codec, pin_nid);
1618
a4e9a38b 1619 mutex_lock(&per_pin->lock);
4bd038f9
DH		 1620 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1621 if (pin_eld->monitor_present)
1622 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1623 else
1624 eld->eld_valid = false;
079d88cc 1625
4e76a883 1626 codec_dbg(codec,
384a48d7 1627 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
10250911 1628 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
5d44f927 1629
4bd038f9 1630 if (eld->eld_valid) {
307229d2 1631 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1613d6b4 1632 &eld->eld_size) < 0)
4bd038f9 1633 eld->eld_valid = false;
1613d6b4 1634 else {
79514d47 1635 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1613d6b4 1636 eld->eld_size) < 0)
4bd038f9 1637 eld->eld_valid = false;
1613d6b4 1638 }
9a5e5234
TI		 1639 if (!eld->eld_valid && repoll)
1640 do_repoll = true;
744626da 1641 }
4bd038f9 1642
9a5e5234 1643 if (do_repoll)
e90247f9
TI		 1644 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1645 else
1646 update_eld(codec, per_pin, eld);
92c69e79 1647
aff747eb 1648 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
464837a7
DH		 1649
1650 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1651 if (jack)
1652 jack->block_report = !ret;
1653
a4e9a38b 1654 mutex_unlock(&per_pin->lock);
664c7155 1655 snd_hda_power_down_pm(codec);
efe47108 1656 return ret;
079d88cc
WF		 1657}
1658
788d441a
TI		 1659/* update ELD and jack state via audio component */
1660static void sync_eld_via_acomp(struct hda_codec *codec,
1661 struct hdmi_spec_per_pin *per_pin)
1662{
788d441a
TI		 1663 struct hdmi_spec *spec = codec->spec;
1664 struct hdmi_eld *eld = &spec->temp_eld;
1665 int size;
1666
e2dc7d7d
TI		 1667 mutex_lock(&per_pin->lock);
1668 size = snd_hdac_acomp_get_eld(&codec->bus->core, per_pin->pin_nid,
1669 &eld->monitor_present, eld->eld_buffer,
1670 ELD_MAX_SIZE);
1671 if (size < 0)
1672 goto unlock;
1673 if (size > 0) {
1674 size = min(size, ELD_MAX_SIZE);
1675 if (snd_hdmi_parse_eld(codec, &eld->info,
1676 eld->eld_buffer, size) < 0)
1677 size = -EINVAL;
1678 }
788d441a 1679
e2dc7d7d
TI		 1680 if (size > 0) {
1681 eld->eld_valid = true;
1682 eld->eld_size = size;
1683 } else {
1684 eld->eld_valid = false;
1685 eld->eld_size = 0;
788d441a 1686 }
e2dc7d7d
TI		 1687
1688 update_eld(codec, per_pin, eld);
1689 snd_jack_report(per_pin->acomp_jack,
1690 eld->monitor_present ? SND_JACK_AVOUT : 0);
1691 unlock:
1692 mutex_unlock(&per_pin->lock);
788d441a
TI		 1693}
1694
1695static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1696{
1697 struct hda_codec *codec = per_pin->codec;
1698
1699 if (codec_has_acomp(codec)) {
1700 sync_eld_via_acomp(codec, per_pin);
1701 return false; /* don't call snd_hda_jack_report_sync() */
1702 } else {
1703 return hdmi_present_sense_via_verbs(per_pin, repoll);
1704 }
1705}
1706
744626da
WF		 1707static void hdmi_repoll_eld(struct work_struct *work)
1708{
1709 struct hdmi_spec_per_pin *per_pin =
1710 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1711
c6e8453e
WF		 1712 if (per_pin->repoll_count++ > 6)
1713 per_pin->repoll_count = 0;
1714
efe47108
TI		 1715 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1716 snd_hda_jack_report_sync(per_pin->codec);
744626da
WF		 1717}
1718
c88d4e84
TI		 1719static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1720 hda_nid_t nid);
1721
079d88cc
WF		 1722static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1723{
1724 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1725 unsigned int caps, config;
1726 int pin_idx;
1727 struct hdmi_spec_per_pin *per_pin;
07acecc1 1728 int err;
079d88cc 1729
efc2f8de 1730 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1731 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1732 return 0;
1733
efc2f8de 1734 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1735 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1736 return 0;
1737
75dcbe4d 1738 if (is_haswell_plus(codec))
c88d4e84
TI		 1739 intel_haswell_fixup_connect_list(codec, pin_nid);
1740
384a48d7 1741 pin_idx = spec->num_pins;
bce0d2a8
TI		 1742 per_pin = snd_array_new(&spec->pins);
1743 if (!per_pin)
1744 return -ENOMEM;
384a48d7
SW		 1745
1746 per_pin->pin_nid = pin_nid;
1a6003b5 1747 per_pin->non_pcm = false;
079d88cc 1748
384a48d7
SW		 1749 err = hdmi_read_pin_conn(codec, pin_idx);
1750 if (err < 0)
1751 return err;
079d88cc 1752
079d88cc
WF		 1753 spec->num_pins++;
1754
384a48d7 1755 return 0;
079d88cc
WF		 1756}
1757
384a48d7 1758static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1759{
1760 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1761 struct hdmi_spec_per_cvt *per_cvt;
1762 unsigned int chans;
1763 int err;
079d88cc 1764
384a48d7
SW		 1765 chans = get_wcaps(codec, cvt_nid);
1766 chans = get_wcaps_channels(chans);
1767
bce0d2a8
TI		 1768 per_cvt = snd_array_new(&spec->cvts);
1769 if (!per_cvt)
1770 return -ENOMEM;
384a48d7
SW		 1771
1772 per_cvt->cvt_nid = cvt_nid;
1773 per_cvt->channels_min = 2;
d45e6889 1774 if (chans <= 16) {
384a48d7 1775 per_cvt->channels_max = chans;
d45e6889
TI		 1776 if (chans > spec->channels_max)
1777 spec->channels_max = chans;
1778 }
384a48d7
SW		 1779
1780 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1781 &per_cvt->rates,
1782 &per_cvt->formats,
1783 &per_cvt->maxbps);
1784 if (err < 0)
1785 return err;
1786
bce0d2a8
TI		 1787 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1788 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1789 spec->num_cvts++;
079d88cc
WF		 1790
1791 return 0;
1792}
1793
1794static int hdmi_parse_codec(struct hda_codec *codec)
1795{
1796 hda_nid_t nid;
1797 int i, nodes;
1798
7639a06c 1799 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
079d88cc 1800 if (!nid || nodes < 0) {
4e76a883 1801 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
079d88cc
WF		 1802 return -EINVAL;
1803 }
1804
1805 for (i = 0; i < nodes; i++, nid++) {
1806 unsigned int caps;
1807 unsigned int type;
1808
efc2f8de 1809 caps = get_wcaps(codec, nid);
079d88cc
WF		 1810 type = get_wcaps_type(caps);
1811
1812 if (!(caps & AC_WCAP_DIGITAL))
1813 continue;
1814
1815 switch (type) {
1816 case AC_WID_AUD_OUT:
384a48d7 1817 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1818 break;
1819 case AC_WID_PIN:
3eaead57 1820 hdmi_add_pin(codec, nid);
079d88cc
WF		 1821 break;
1822 }
1823 }
1824
079d88cc
WF		 1825 return 0;
1826}
1827
84eb01be
TI		 1828/*
1829 */
1a6003b5
TI		 1830static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1831{
1832 struct hda_spdif_out *spdif;
1833 bool non_pcm;
1834
1835 mutex_lock(&codec->spdif_mutex);
1836 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1837 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1838 mutex_unlock(&codec->spdif_mutex);
1839 return non_pcm;
1840}
1841
84eb01be
TI		 1842/*
1843 * HDMI callbacks
1844 */
1845
1846static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1847 struct hda_codec *codec,
1848 unsigned int stream_tag,
1849 unsigned int format,
1850 struct snd_pcm_substream *substream)
1851{
384a48d7
SW		 1852 hda_nid_t cvt_nid = hinfo->nid;
1853 struct hdmi_spec *spec = codec->spec;
4e76a883 1854 int pin_idx = hinfo_to_pin_index(codec, hinfo);
b054087d
TI		 1855 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1856 hda_nid_t pin_nid = per_pin->pin_nid;
ddd621fb 1857 struct snd_pcm_runtime *runtime = substream->runtime;
1a6003b5 1858 bool non_pcm;
75fae117 1859 int pinctl;
1a6003b5 1860
ca2e7224 1861 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
2df6742f
ML		 1862 /* Verify pin:cvt selections to avoid silent audio after S3.
1863 * After S3, the audio driver restores pin:cvt selections
1864 * but this can happen before gfx is ready and such selection
1865 * is overlooked by HW. Thus multiple pins can share a same
1866 * default convertor and mute control will affect each other,
1867 * which can cause a resumed audio playback become silent
1868 * after S3.
1869 */
1870 intel_verify_pin_cvt_connect(codec, per_pin);
1871 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
1872 }
1873
ddd621fb
LY		 1874 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1875 /* Todo: add DP1.2 MST audio support later */
e2dc7d7d 1876 snd_hdac_sync_audio_rate(&codec->bus->core, pin_nid, runtime->rate);
ddd621fb 1877
1a6003b5 1878 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
a4e9a38b 1879 mutex_lock(&per_pin->lock);
b054087d
TI		 1880 per_pin->channels = substream->runtime->channels;
1881 per_pin->setup = true;
384a48d7 1882
b054087d 1883 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
a4e9a38b 1884 mutex_unlock(&per_pin->lock);
84eb01be 1885
75fae117
SW		 1886 if (spec->dyn_pin_out) {
1887 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1888 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1889 snd_hda_codec_write(codec, pin_nid, 0,
1890 AC_VERB_SET_PIN_WIDGET_CONTROL,
1891 pinctl | PIN_OUT);
1892 }
1893
307229d2 1894 return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1895}
1896
8dfaa573
TI		 1897static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1898 struct hda_codec *codec,
1899 struct snd_pcm_substream *substream)
1900{
1901 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1902 return 0;
1903}
1904
f2ad24fa
TI		 1905static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1906 struct hda_codec *codec,
1907 struct snd_pcm_substream *substream)
384a48d7
SW		 1908{
1909 struct hdmi_spec *spec = codec->spec;
1910 int cvt_idx, pin_idx;
1911 struct hdmi_spec_per_cvt *per_cvt;
1912 struct hdmi_spec_per_pin *per_pin;
75fae117 1913 int pinctl;
384a48d7 1914
384a48d7 1915 if (hinfo->nid) {
4e76a883 1916 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
384a48d7
SW		 1917 if (snd_BUG_ON(cvt_idx < 0))
1918 return -EINVAL;
bce0d2a8 1919 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1920
1921 snd_BUG_ON(!per_cvt->assigned);
1922 per_cvt->assigned = 0;
1923 hinfo->nid = 0;
1924
4e76a883 1925 pin_idx = hinfo_to_pin_index(codec, hinfo);
384a48d7
SW		 1926 if (snd_BUG_ON(pin_idx < 0))
1927 return -EINVAL;
bce0d2a8 1928 per_pin = get_pin(spec, pin_idx);
384a48d7 1929
75fae117
SW		 1930 if (spec->dyn_pin_out) {
1931 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1932 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1933 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1934 AC_VERB_SET_PIN_WIDGET_CONTROL,
1935 pinctl & ~PIN_OUT);
1936 }
1937
384a48d7 1938 snd_hda_spdif_ctls_unassign(codec, pin_idx);
cbbaa603 1939
a4e9a38b 1940 mutex_lock(&per_pin->lock);
d45e6889
TI		 1941 per_pin->chmap_set = false;
1942 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
b054087d
TI		 1943
1944 per_pin->setup = false;
1945 per_pin->channels = 0;
a4e9a38b 1946 mutex_unlock(&per_pin->lock);
384a48d7 1947 }
d45e6889 1948
384a48d7
SW		 1949 return 0;
1950}
1951
1952static const struct hda_pcm_ops generic_ops = {
1953 .open = hdmi_pcm_open,
f2ad24fa 1954 .close = hdmi_pcm_close,
384a48d7 1955 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 1956 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1957};
1958
d45e6889
TI		 1959/*
1960 * ALSA API channel-map control callbacks
1961 */
1962static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1963 struct snd_ctl_elem_info *uinfo)
1964{
1965 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1966 struct hda_codec *codec = info->private_data;
1967 struct hdmi_spec *spec = codec->spec;
1968 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1969 uinfo->count = spec->channels_max;
1970 uinfo->value.integer.min = 0;
1971 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1972 return 0;
1973}
1974
307229d2
AH		 1975static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
1976 int channels)
1977{
1978 /* If the speaker allocation matches the channel count, it is OK.*/
1979 if (cap->channels != channels)
1980 return -1;
1981
1982 /* all channels are remappable freely */
1983 return SNDRV_CTL_TLVT_CHMAP_VAR;
1984}
1985
1986static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
1987 unsigned int *chmap, int channels)
1988{
1989 int count = 0;
1990 int c;
1991
1992 for (c = 7; c >= 0; c--) {
1993 int spk = cap->speakers[c];
1994 if (!spk)
1995 continue;
1996
1997 chmap[count++] = spk_to_chmap(spk);
1998 }
1999
2000 WARN_ON(count != channels);
2001}
2002
d45e6889
TI		 2003static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
2004 unsigned int size, unsigned int __user *tlv)
2005{
2006 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2007 struct hda_codec *codec = info->private_data;
2008 struct hdmi_spec *spec = codec->spec;
d45e6889
TI		 2009 unsigned int __user *dst;
2010 int chs, count = 0;
2011
2012 if (size < 8)
2013 return -ENOMEM;
2014 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
2015 return -EFAULT;
2016 size -= 8;
2017 dst = tlv + 2;
498dab3a 2018 for (chs = 2; chs <= spec->channels_max; chs++) {
307229d2 2019 int i;
d45e6889
TI		 2020 struct cea_channel_speaker_allocation *cap;
2021 cap = channel_allocations;
2022 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
2023 int chs_bytes = chs * 4;
307229d2
AH		 2024 int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
2025 unsigned int tlv_chmap[8];
2026
2027 if (type < 0)
d45e6889 2028 continue;
d45e6889
TI		 2029 if (size < 8)
2030 return -ENOMEM;
307229d2 2031 if (put_user(type, dst) ||
d45e6889
TI		 2032 put_user(chs_bytes, dst + 1))
2033 return -EFAULT;
2034 dst += 2;
2035 size -= 8;
2036 count += 8;
2037 if (size < chs_bytes)
2038 return -ENOMEM;
2039 size -= chs_bytes;
2040 count += chs_bytes;
307229d2
AH		 2041 spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
2042 if (copy_to_user(dst, tlv_chmap, chs_bytes))
2043 return -EFAULT;
2044 dst += chs;
d45e6889
TI		 2045 }
2046 }
2047 if (put_user(count, tlv + 1))
2048 return -EFAULT;
2049 return 0;
2050}
2051
2052static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
2053 struct snd_ctl_elem_value *ucontrol)
2054{
2055 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2056 struct hda_codec *codec = info->private_data;
2057 struct hdmi_spec *spec = codec->spec;
2058 int pin_idx = kcontrol->private_value;
bce0d2a8 2059 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 2060 int i;
2061
2062 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
2063 ucontrol->value.integer.value[i] = per_pin->chmap[i];
2064 return 0;
2065}
2066
2067static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
2068 struct snd_ctl_elem_value *ucontrol)
2069{
2070 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2071 struct hda_codec *codec = info->private_data;
2072 struct hdmi_spec *spec = codec->spec;
2073 int pin_idx = kcontrol->private_value;
bce0d2a8 2074 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 2075 unsigned int ctl_idx;
2076 struct snd_pcm_substream *substream;
2077 unsigned char chmap[8];
307229d2 2078 int i, err, ca, prepared = 0;
d45e6889
TI		 2079
2080 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2081 substream = snd_pcm_chmap_substream(info, ctl_idx);
2082 if (!substream || !substream->runtime)
6f54c361 2083 return 0; /* just for avoiding error from alsactl restore */
d45e6889
TI		 2084 switch (substream->runtime->status->state) {
2085 case SNDRV_PCM_STATE_OPEN:
2086 case SNDRV_PCM_STATE_SETUP:
2087 break;
2088 case SNDRV_PCM_STATE_PREPARED:
2089 prepared = 1;
2090 break;
2091 default:
2092 return -EBUSY;
2093 }
2094 memset(chmap, 0, sizeof(chmap));
2095 for (i = 0; i < ARRAY_SIZE(chmap); i++)
2096 chmap[i] = ucontrol->value.integer.value[i];
2097 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
2098 return 0;
2099 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
2100 if (ca < 0)
2101 return -EINVAL;
307229d2
AH		 2102 if (spec->ops.chmap_validate) {
2103 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
2104 if (err)
2105 return err;
2106 }
a4e9a38b 2107 mutex_lock(&per_pin->lock);
d45e6889
TI		 2108 per_pin->chmap_set = true;
2109 memcpy(per_pin->chmap, chmap, sizeof(chmap));
2110 if (prepared)
b054087d 2111 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
a4e9a38b 2112 mutex_unlock(&per_pin->lock);
d45e6889
TI		 2113
2114 return 0;
2115}
2116
84eb01be
TI		 2117static int generic_hdmi_build_pcms(struct hda_codec *codec)
2118{
2119 struct hdmi_spec *spec = codec->spec;
384a48d7 2120 int pin_idx;
84eb01be 2121
384a48d7
SW		 2122 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2123 struct hda_pcm *info;
84eb01be 2124 struct hda_pcm_stream *pstr;
bce0d2a8 2125
bbbc7e85 2126 info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
bce0d2a8
TI		 2127 if (!info)
2128 return -ENOMEM;
bbbc7e85 2129 spec->pcm_rec[pin_idx] = info;
84eb01be 2130 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 2131 info->own_chmap = true;
384a48d7 2132
84eb01be 2133 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 2134 pstr->substreams = 1;
2135 pstr->ops = generic_ops;
2136 /* other pstr fields are set in open */
84eb01be
TI		 2137 }
2138
2139 return 0;
2140}
2141
788d441a
TI		 2142static void free_acomp_jack_priv(struct snd_jack *jack)
2143{
2144 struct hdmi_spec_per_pin *per_pin = jack->private_data;
2145
2146 per_pin->acomp_jack = NULL;
2147}
2148
2149static int add_acomp_jack_kctl(struct hda_codec *codec,
2150 struct hdmi_spec_per_pin *per_pin,
2151 const char *name)
2152{
2153 struct snd_jack *jack;
2154 int err;
2155
2156 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
2157 true, false);
2158 if (err < 0)
2159 return err;
2160 per_pin->acomp_jack = jack;
2161 jack->private_data = per_pin;
2162 jack->private_free = free_acomp_jack_priv;
2163 return 0;
2164}
2165
0b6c49b5
DH		 2166static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
2167{
31ef2257 2168 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 2169 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2170 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2171 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
909cadc6 2172 bool phantom_jack;
0b6c49b5 2173
31ef2257
TI		 2174 if (pcmdev > 0)
2175 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
788d441a
TI		 2176 if (codec_has_acomp(codec))
2177 return add_acomp_jack_kctl(codec, per_pin, hdmi_str);
909cadc6
TI		 2178 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2179 if (phantom_jack)
30efd8de
DH		 2180 strncat(hdmi_str, " Phantom",
2181 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
0b6c49b5 2182
909cadc6
TI		 2183 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
2184 phantom_jack);
0b6c49b5
DH		 2185}
2186
84eb01be
TI		 2187static int generic_hdmi_build_controls(struct hda_codec *codec)
2188{
2189 struct hdmi_spec *spec = codec->spec;
2190 int err;
384a48d7 2191 int pin_idx;
84eb01be 2192
384a48d7 2193 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2194 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
0b6c49b5
DH		 2195
2196 err = generic_hdmi_build_jack(codec, pin_idx);
2197 if (err < 0)
2198 return err;
2199
dcda5806
TI		 2200 err = snd_hda_create_dig_out_ctls(codec,
2201 per_pin->pin_nid,
2202 per_pin->mux_nids[0],
2203 HDA_PCM_TYPE_HDMI);
84eb01be
TI		 2204 if (err < 0)
2205 return err;
384a48d7 2206 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 2207
2208 /* add control for ELD Bytes */
bce0d2a8
TI		 2209 err = hdmi_create_eld_ctl(codec, pin_idx,
2210 get_pcm_rec(spec, pin_idx)->device);
14bc52b8
PLB		 2211
2212 if (err < 0)
2213 return err;
31ef2257 2214
82b1d73f 2215 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 2216 }
2217
d45e6889
TI		 2218 /* add channel maps */
2219 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bbbc7e85 2220 struct hda_pcm *pcm;
d45e6889
TI		 2221 struct snd_pcm_chmap *chmap;
2222 struct snd_kcontrol *kctl;
2223 int i;
2ca320e2 2224
bbbc7e85
TI		 2225 pcm = spec->pcm_rec[pin_idx];
2226 if (!pcm || !pcm->pcm)
2ca320e2 2227 break;
bbbc7e85 2228 err = snd_pcm_add_chmap_ctls(pcm->pcm,
d45e6889
TI		 2229 SNDRV_PCM_STREAM_PLAYBACK,
2230 NULL, 0, pin_idx, &chmap);
2231 if (err < 0)
2232 return err;
2233 /* override handlers */
2234 chmap->private_data = codec;
2235 kctl = chmap->kctl;
2236 for (i = 0; i < kctl->count; i++)
2237 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2238 kctl->info = hdmi_chmap_ctl_info;
2239 kctl->get = hdmi_chmap_ctl_get;
2240 kctl->put = hdmi_chmap_ctl_put;
2241 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2242 }
2243
84eb01be
TI		 2244 return 0;
2245}
2246
8b8d654b 2247static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 2248{
2249 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2250 int pin_idx;
2251
2252 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2253 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2254
744626da 2255 per_pin->codec = codec;
a4e9a38b 2256 mutex_init(&per_pin->lock);
744626da 2257 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
a4e9a38b 2258 eld_proc_new(per_pin, pin_idx);
84eb01be 2259 }
8b8d654b
TI		 2260 return 0;
2261}
2262
2263static int generic_hdmi_init(struct hda_codec *codec)
2264{
2265 struct hdmi_spec *spec = codec->spec;
2266 int pin_idx;
2267
2268 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2269 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b
TI		 2270 hda_nid_t pin_nid = per_pin->pin_nid;
2271
2272 hdmi_init_pin(codec, pin_nid);
788d441a
TI		 2273 if (!codec_has_acomp(codec))
2274 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2275 codec->jackpoll_interval > 0 ?
2276 jack_callback : NULL);
8b8d654b 2277 }
84eb01be
TI		 2278 return 0;
2279}
2280
bce0d2a8
TI		 2281static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2282{
2283 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2284 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
bce0d2a8
TI		 2285}
2286
2287static void hdmi_array_free(struct hdmi_spec *spec)
2288{
2289 snd_array_free(&spec->pins);
2290 snd_array_free(&spec->cvts);
bce0d2a8
TI		 2291}
2292
84eb01be
TI		 2293static void generic_hdmi_free(struct hda_codec *codec)
2294{
2295 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2296 int pin_idx;
2297
6603249d 2298 if (codec_has_acomp(codec))
25adc137
DH		 2299 snd_hdac_i915_register_notifier(NULL);
2300
384a48d7 2301 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2302 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2303
2f35c630 2304 cancel_delayed_work_sync(&per_pin->work);
a4e9a38b 2305 eld_proc_free(per_pin);
788d441a
TI		 2306 if (per_pin->acomp_jack)
2307 snd_device_free(codec->card, per_pin->acomp_jack);
384a48d7 2308 }
84eb01be 2309
55913110
TI		 2310 if (spec->i915_bound)
2311 snd_hdac_i915_exit(&codec->bus->core);
bce0d2a8 2312 hdmi_array_free(spec);
84eb01be
TI		 2313 kfree(spec);
2314}
2315
28cb72e5
WX		 2316#ifdef CONFIG_PM
2317static int generic_hdmi_resume(struct hda_codec *codec)
2318{
2319 struct hdmi_spec *spec = codec->spec;
2320 int pin_idx;
2321
a2833683 2322 codec->patch_ops.init(codec);
eeecd9d1 2323 regcache_sync(codec->core.regmap);
28cb72e5
WX		 2324
2325 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2326 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2327 hdmi_present_sense(per_pin, 1);
2328 }
2329 return 0;
2330}
2331#endif
2332
fb79e1e0 2333static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 2334 .init = generic_hdmi_init,
2335 .free = generic_hdmi_free,
2336 .build_pcms = generic_hdmi_build_pcms,
2337 .build_controls = generic_hdmi_build_controls,
2338 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 2339#ifdef CONFIG_PM
2340 .resume = generic_hdmi_resume,
2341#endif
84eb01be
TI		 2342};
2343
307229d2
AH		 2344static const struct hdmi_ops generic_standard_hdmi_ops = {
2345 .pin_get_eld = snd_hdmi_get_eld,
2346 .pin_get_slot_channel = hdmi_pin_get_slot_channel,
2347 .pin_set_slot_channel = hdmi_pin_set_slot_channel,
2348 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2349 .pin_hbr_setup = hdmi_pin_hbr_setup,
2350 .setup_stream = hdmi_setup_stream,
2351 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
2352 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
2353};
2354
6ffe168f 2355
c88d4e84
TI		 2356static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2357 hda_nid_t nid)
2358{
2359 struct hdmi_spec *spec = codec->spec;
2360 hda_nid_t conns[4];
2361 int nconns;
6ffe168f 2362
c88d4e84
TI		 2363 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2364 if (nconns == spec->num_cvts &&
2365 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 2366 return;
2367
c88d4e84 2368 /* override pins connection list */
4e76a883 2369 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
c88d4e84 2370 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 2371}
2372
1611a9c9
ML		 2373#define INTEL_VENDOR_NID 0x08
2374#define INTEL_GET_VENDOR_VERB 0xf81
2375#define INTEL_SET_VENDOR_VERB 0x781
2376#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2377#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2378
2379static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 2380 bool update_tree)
1611a9c9
ML		 2381{
2382 unsigned int vendor_param;
2383
1611a9c9
ML		 2384 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2385 INTEL_GET_VENDOR_VERB, 0);
2386 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2387 return;
2388
2389 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2390 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2391 INTEL_SET_VENDOR_VERB, vendor_param);
2392 if (vendor_param == -1)
2393 return;
2394
17df3f55
TI		 2395 if (update_tree)
2396 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 2397}
2398
c88d4e84
TI		 2399static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2400{
2401 unsigned int vendor_param;
2402
2403 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2404 INTEL_GET_VENDOR_VERB, 0);
2405 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2406 return;
2407
2408 /* enable DP1.2 mode */
2409 vendor_param |= INTEL_EN_DP12;
a551d914 2410 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
c88d4e84
TI		 2411 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2412 INTEL_SET_VENDOR_VERB, vendor_param);
2413}
2414
17df3f55
TI		 2415/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2416 * Otherwise you may get severe h/w communication errors.
2417 */
2418static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2419 unsigned int power_state)
2420{
2421 if (power_state == AC_PWRST_D0) {
2422 intel_haswell_enable_all_pins(codec, false);
2423 intel_haswell_fixup_enable_dp12(codec);
2424 }
c88d4e84 2425
17df3f55
TI		 2426 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2427 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2428}
6ffe168f 2429
f0675d4a 2430static void intel_pin_eld_notify(void *audio_ptr, int port)
25adc137
DH		 2431{
2432 struct hda_codec *codec = audio_ptr;
2433 int pin_nid = port + 0x04;
2434
8ae743e8
TI		 2435 /* skip notification during system suspend (but not in runtime PM);
2436 * the state will be updated at resume
2437 */
2438 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2439 return;
eb399d3c
TI		 2440 /* ditto during suspend/resume process itself */
2441 if (atomic_read(&(codec)->core.in_pm))
2442 return;
8ae743e8 2443
25adc137
DH		 2444 check_presence_and_report(codec, pin_nid);
2445}
2446
84eb01be
TI		 2447static int patch_generic_hdmi(struct hda_codec *codec)
2448{
2449 struct hdmi_spec *spec;
84eb01be
TI		 2450
2451 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2452 if (spec == NULL)
2453 return -ENOMEM;
2454
307229d2 2455 spec->ops = generic_standard_hdmi_ops;
84eb01be 2456 codec->spec = spec;
bce0d2a8 2457 hdmi_array_init(spec, 4);
6ffe168f 2458
55913110
TI		 2459 /* Try to bind with i915 for any Intel codecs (if not done yet) */
2460 if (!codec_has_acomp(codec) &&
2461 (codec->core.vendor_id >> 16) == 0x8086)
2462 if (!snd_hdac_i915_init(&codec->bus->core))
2463 spec->i915_bound = true;
2464
75dcbe4d 2465 if (is_haswell_plus(codec)) {
17df3f55 2466 intel_haswell_enable_all_pins(codec, true);
c88d4e84 2467 intel_haswell_fixup_enable_dp12(codec);
17df3f55 2468 }
6ffe168f 2469
2bd1f73f
ML		 2470 /* For Valleyview/Cherryview, only the display codec is in the display
2471 * power well and can use link_power ops to request/release the power.
2472 * For Haswell/Broadwell, the controller is also in the power well and
2473 * can cover the codec power request, and so need not set this flag.
2474 * For previous platforms, there is no such power well feature.
2475 */
ff9d8859
LH		 2476 if (is_valleyview_plus(codec) || is_skylake(codec) ||
2477 is_broxton(codec))
2bd1f73f
ML		 2478 codec->core.link_power_control = 1;
2479
84eb01be 2480 if (hdmi_parse_codec(codec) < 0) {
55913110
TI		 2481 if (spec->i915_bound)
2482 snd_hdac_i915_exit(&codec->bus->core);
84eb01be
TI		 2483 codec->spec = NULL;
2484 kfree(spec);
2485 return -EINVAL;
2486 }
2487 codec->patch_ops = generic_hdmi_patch_ops;
75dcbe4d 2488 if (is_haswell_plus(codec)) {
17df3f55 2489 codec->patch_ops.set_power_state = haswell_set_power_state;
5dc989bd
ML		 2490 codec->dp_mst = true;
2491 }
17df3f55 2492
2377c3c3
LH		 2493 /* Enable runtime pm for HDMI audio codec of HSW/BDW/SKL/BYT/BSW */
2494 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2495 codec->auto_runtime_pm = 1;
2496
8b8d654b 2497 generic_hdmi_init_per_pins(codec);
84eb01be 2498
84eb01be
TI		 2499 init_channel_allocations();
2500
790b415c
LY		 2501 if (codec_has_acomp(codec)) {
2502 codec->depop_delay = 0;
2503 spec->i915_audio_ops.audio_ptr = codec;
2504 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2505 * will call pin_eld_notify with using audio_ptr pointer
2506 * We need make sure audio_ptr is really setup
2507 */
2508 wmb();
2509 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2510 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2511 }
2512
84eb01be
TI		 2513 return 0;
2514}
2515
3aaf8980
SW		 2516/*
2517 * Shared non-generic implementations
2518 */
2519
2520static int simple_playback_build_pcms(struct hda_codec *codec)
2521{
2522 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2523 struct hda_pcm *info;
8ceb332d
TI		 2524 unsigned int chans;
2525 struct hda_pcm_stream *pstr;
bce0d2a8 2526 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2527
bce0d2a8
TI		 2528 per_cvt = get_cvt(spec, 0);
2529 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2530 chans = get_wcaps_channels(chans);
3aaf8980 2531
bbbc7e85 2532 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
bce0d2a8
TI		 2533 if (!info)
2534 return -ENOMEM;
bbbc7e85 2535 spec->pcm_rec[0] = info;
8ceb332d
TI		 2536 info->pcm_type = HDA_PCM_TYPE_HDMI;
2537 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2538 *pstr = spec->pcm_playback;
bce0d2a8 2539 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2540 if (pstr->channels_max <= 2 && chans && chans <= 16)
2541 pstr->channels_max = chans;
3aaf8980
SW		 2542
2543 return 0;
2544}
2545
4b6ace9e
TI		 2546/* unsolicited event for jack sensing */
2547static void simple_hdmi_unsol_event(struct hda_codec *codec,
2548 unsigned int res)
2549{
9dd8cf12 2550 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2551 snd_hda_jack_report_sync(codec);
2552}
2553
2554/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2555 * as long as spec->pins[] is set correctly
2556 */
2557#define simple_hdmi_build_jack generic_hdmi_build_jack
2558
3aaf8980
SW		 2559static int simple_playback_build_controls(struct hda_codec *codec)
2560{
2561 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2562 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2563 int err;
3aaf8980 2564
bce0d2a8 2565 per_cvt = get_cvt(spec, 0);
c9a6338a
AH		 2566 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2567 per_cvt->cvt_nid,
2568 HDA_PCM_TYPE_HDMI);
8ceb332d
TI		 2569 if (err < 0)
2570 return err;
2571 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 2572}
2573
4f0110ce
TI		 2574static int simple_playback_init(struct hda_codec *codec)
2575{
2576 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2577 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2578 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 2579
2580 snd_hda_codec_write(codec, pin, 0,
2581 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2582 /* some codecs require to unmute the pin */
2583 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2584 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2585 AMP_OUT_UNMUTE);
62f949bf 2586 snd_hda_jack_detect_enable(codec, pin);
4f0110ce
TI		 2587 return 0;
2588}
2589
3aaf8980
SW		 2590static void simple_playback_free(struct hda_codec *codec)
2591{
2592 struct hdmi_spec *spec = codec->spec;
2593
bce0d2a8 2594 hdmi_array_free(spec);
3aaf8980
SW		 2595 kfree(spec);
2596}
2597
84eb01be
TI		 2598/*
2599 * Nvidia specific implementations
2600 */
2601
2602#define Nv_VERB_SET_Channel_Allocation 0xF79
2603#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2604#define Nv_VERB_SET_Audio_Protection_On 0xF98
2605#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2606
2607#define nvhdmi_master_con_nid_7x 0x04
2608#define nvhdmi_master_pin_nid_7x 0x05
2609
fb79e1e0 2610static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2611 /*front, rear, clfe, rear_surr */
2612 0x6, 0x8, 0xa, 0xc,
2613};
2614
ceaa86ba
TI		 2615static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2616 /* set audio protect on */
2617 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2618 /* enable digital output on pin widget */
2619 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2620 {} /* terminator */
2621};
2622
2623static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 2624 /* set audio protect on */
2625 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2626 /* enable digital output on pin widget */
2627 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2628 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2629 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2630 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2631 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2632 {} /* terminator */
2633};
2634
2635#ifdef LIMITED_RATE_FMT_SUPPORT
2636/* support only the safe format and rate */
2637#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2638#define SUPPORTED_MAXBPS 16
2639#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2640#else
2641/* support all rates and formats */
2642#define SUPPORTED_RATES \
2643 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2644 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2645 SNDRV_PCM_RATE_192000)
2646#define SUPPORTED_MAXBPS 24
2647#define SUPPORTED_FORMATS \
2648 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2649#endif
2650
ceaa86ba
TI		 2651static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2652{
2653 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2654 return 0;
2655}
2656
2657static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 2658{
ceaa86ba 2659 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 2660 return 0;
2661}
2662
393004b2
ND		 2663static unsigned int channels_2_6_8[] = {
2664 2, 6, 8
2665};
2666
2667static unsigned int channels_2_8[] = {
2668 2, 8
2669};
2670
2671static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2672 .count = ARRAY_SIZE(channels_2_6_8),
2673 .list = channels_2_6_8,
2674 .mask = 0,
2675};
2676
2677static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2678 .count = ARRAY_SIZE(channels_2_8),
2679 .list = channels_2_8,
2680 .mask = 0,
2681};
2682
84eb01be
TI		 2683static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2684 struct hda_codec *codec,
2685 struct snd_pcm_substream *substream)
2686{
2687 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 2688 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2689
b9a94a9c 2690 switch (codec->preset->vendor_id) {
393004b2
ND		 2691 case 0x10de0002:
2692 case 0x10de0003:
2693 case 0x10de0005:
2694 case 0x10de0006:
2695 hw_constraints_channels = &hw_constraints_2_8_channels;
2696 break;
2697 case 0x10de0007:
2698 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2699 break;
2700 default:
2701 break;
2702 }
2703
2704 if (hw_constraints_channels != NULL) {
2705 snd_pcm_hw_constraint_list(substream->runtime, 0,
2706 SNDRV_PCM_HW_PARAM_CHANNELS,
2707 hw_constraints_channels);
ad09fc9d
TI		 2708 } else {
2709 snd_pcm_hw_constraint_step(substream->runtime, 0,
2710 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 2711 }
2712
84eb01be
TI		 2713 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2714}
2715
2716static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2717 struct hda_codec *codec,
2718 struct snd_pcm_substream *substream)
2719{
2720 struct hdmi_spec *spec = codec->spec;
2721 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2722}
2723
2724static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2725 struct hda_codec *codec,
2726 unsigned int stream_tag,
2727 unsigned int format,
2728 struct snd_pcm_substream *substream)
2729{
2730 struct hdmi_spec *spec = codec->spec;
2731 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2732 stream_tag, format, substream);
2733}
2734
d0b1252d
TI		 2735static const struct hda_pcm_stream simple_pcm_playback = {
2736 .substreams = 1,
2737 .channels_min = 2,
2738 .channels_max = 2,
2739 .ops = {
2740 .open = simple_playback_pcm_open,
2741 .close = simple_playback_pcm_close,
2742 .prepare = simple_playback_pcm_prepare
2743 },
2744};
2745
2746static const struct hda_codec_ops simple_hdmi_patch_ops = {
2747 .build_controls = simple_playback_build_controls,
2748 .build_pcms = simple_playback_build_pcms,
2749 .init = simple_playback_init,
2750 .free = simple_playback_free,
250e41ac 2751 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 2752};
2753
2754static int patch_simple_hdmi(struct hda_codec *codec,
2755 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2756{
2757 struct hdmi_spec *spec;
bce0d2a8
TI		 2758 struct hdmi_spec_per_cvt *per_cvt;
2759 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 2760
2761 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2762 if (!spec)
2763 return -ENOMEM;
2764
2765 codec->spec = spec;
bce0d2a8 2766 hdmi_array_init(spec, 1);
d0b1252d
TI		 2767
2768 spec->multiout.num_dacs = 0; /* no analog */
2769 spec->multiout.max_channels = 2;
2770 spec->multiout.dig_out_nid = cvt_nid;
2771 spec->num_cvts = 1;
2772 spec->num_pins = 1;
bce0d2a8
TI		 2773 per_pin = snd_array_new(&spec->pins);
2774 per_cvt = snd_array_new(&spec->cvts);
2775 if (!per_pin || !per_cvt) {
2776 simple_playback_free(codec);
2777 return -ENOMEM;
2778 }
2779 per_cvt->cvt_nid = cvt_nid;
2780 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 2781 spec->pcm_playback = simple_pcm_playback;
2782
2783 codec->patch_ops = simple_hdmi_patch_ops;
2784
2785 return 0;
2786}
2787
1f348522
AP		 2788static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2789 int channels)
2790{
2791 unsigned int chanmask;
2792 int chan = channels ? (channels - 1) : 1;
2793
2794 switch (channels) {
2795 default:
2796 case 0:
2797 case 2:
2798 chanmask = 0x00;
2799 break;
2800 case 4:
2801 chanmask = 0x08;
2802 break;
2803 case 6:
2804 chanmask = 0x0b;
2805 break;
2806 case 8:
2807 chanmask = 0x13;
2808 break;
2809 }
2810
2811 /* Set the audio infoframe channel allocation and checksum fields. The
2812 * channel count is computed implicitly by the hardware. */
2813 snd_hda_codec_write(codec, 0x1, 0,
2814 Nv_VERB_SET_Channel_Allocation, chanmask);
2815
2816 snd_hda_codec_write(codec, 0x1, 0,
2817 Nv_VERB_SET_Info_Frame_Checksum,
2818 (0x71 - chan - chanmask));
2819}
2820
84eb01be
TI		 2821static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2822 struct hda_codec *codec,
2823 struct snd_pcm_substream *substream)
2824{
2825 struct hdmi_spec *spec = codec->spec;
2826 int i;
2827
2828 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2829 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2830 for (i = 0; i < 4; i++) {
2831 /* set the stream id */
2832 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2833 AC_VERB_SET_CHANNEL_STREAMID, 0);
2834 /* set the stream format */
2835 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2836 AC_VERB_SET_STREAM_FORMAT, 0);
2837 }
2838
1f348522
AP		 2839 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2840 * streams are disabled. */
2841 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2842
84eb01be
TI		 2843 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2844}
2845
2846static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2847 struct hda_codec *codec,
2848 unsigned int stream_tag,
2849 unsigned int format,
2850 struct snd_pcm_substream *substream)
2851{
2852 int chs;
112daa7a 2853 unsigned int dataDCC2, channel_id;
84eb01be 2854 int i;
7c935976 2855 struct hdmi_spec *spec = codec->spec;
e3245cdd 2856 struct hda_spdif_out *spdif;
bce0d2a8 2857 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 2858
2859 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 2860 per_cvt = get_cvt(spec, 0);
2861 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 2862
2863 chs = substream->runtime->channels;
84eb01be 2864
84eb01be
TI		 2865 dataDCC2 = 0x2;
2866
84eb01be 2867 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 2868 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2869 snd_hda_codec_write(codec,
2870 nvhdmi_master_con_nid_7x,
2871 0,
2872 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2873 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2874
2875 /* set the stream id */
2876 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2877 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2878
2879 /* set the stream format */
2880 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2881 AC_VERB_SET_STREAM_FORMAT, format);
2882
2883 /* turn on again (if needed) */
2884 /* enable and set the channel status audio/data flag */
7c935976 2885 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2886 snd_hda_codec_write(codec,
2887 nvhdmi_master_con_nid_7x,
2888 0,
2889 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2890 spdif->ctls & 0xff);
84eb01be
TI		 2891 snd_hda_codec_write(codec,
2892 nvhdmi_master_con_nid_7x,
2893 0,
2894 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2895 }
2896
2897 for (i = 0; i < 4; i++) {
2898 if (chs == 2)
2899 channel_id = 0;
2900 else
2901 channel_id = i * 2;
2902
2903 /* turn off SPDIF once;
2904 *otherwise the IEC958 bits won't be updated
2905 */
2906 if (codec->spdif_status_reset &&
7c935976 2907 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2908 snd_hda_codec_write(codec,
2909 nvhdmi_con_nids_7x[i],
2910 0,
2911 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2912 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2913 /* set the stream id */
2914 snd_hda_codec_write(codec,
2915 nvhdmi_con_nids_7x[i],
2916 0,
2917 AC_VERB_SET_CHANNEL_STREAMID,
2918 (stream_tag << 4) | channel_id);
2919 /* set the stream format */
2920 snd_hda_codec_write(codec,
2921 nvhdmi_con_nids_7x[i],
2922 0,
2923 AC_VERB_SET_STREAM_FORMAT,
2924 format);
2925 /* turn on again (if needed) */
2926 /* enable and set the channel status audio/data flag */
2927 if (codec->spdif_status_reset &&
7c935976 2928 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2929 snd_hda_codec_write(codec,
2930 nvhdmi_con_nids_7x[i],
2931 0,
2932 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2933 spdif->ctls & 0xff);
84eb01be
TI		 2934 snd_hda_codec_write(codec,
2935 nvhdmi_con_nids_7x[i],
2936 0,
2937 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2938 }
2939 }
2940
1f348522 2941 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 2942
2943 mutex_unlock(&codec->spdif_mutex);
2944 return 0;
2945}
2946
fb79e1e0 2947static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 2948 .substreams = 1,
2949 .channels_min = 2,
2950 .channels_max = 8,
2951 .nid = nvhdmi_master_con_nid_7x,
2952 .rates = SUPPORTED_RATES,
2953 .maxbps = SUPPORTED_MAXBPS,
2954 .formats = SUPPORTED_FORMATS,
2955 .ops = {
2956 .open = simple_playback_pcm_open,
2957 .close = nvhdmi_8ch_7x_pcm_close,
2958 .prepare = nvhdmi_8ch_7x_pcm_prepare
2959 },
2960};
2961
84eb01be
TI		 2962static int patch_nvhdmi_2ch(struct hda_codec *codec)
2963{
2964 struct hdmi_spec *spec;
d0b1252d
TI		 2965 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2966 nvhdmi_master_pin_nid_7x);
2967 if (err < 0)
2968 return err;
84eb01be 2969
ceaa86ba 2970 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 2971 /* override the PCM rates, etc, as the codec doesn't give full list */
2972 spec = codec->spec;
2973 spec->pcm_playback.rates = SUPPORTED_RATES;
2974 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2975 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 2976 return 0;
2977}
2978
53775b0d
TI		 2979static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2980{
2981 struct hdmi_spec *spec = codec->spec;
2982 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 2983 if (!err) {
2984 struct hda_pcm *info = get_pcm_rec(spec, 0);
2985 info->own_chmap = true;
2986 }
53775b0d
TI		 2987 return err;
2988}
2989
2990static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2991{
2992 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2993 struct hda_pcm *info;
53775b0d
TI		 2994 struct snd_pcm_chmap *chmap;
2995 int err;
2996
2997 err = simple_playback_build_controls(codec);
2998 if (err < 0)
2999 return err;
3000
3001 /* add channel maps */
bce0d2a8
TI		 3002 info = get_pcm_rec(spec, 0);
3003 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 3004 SNDRV_PCM_STREAM_PLAYBACK,
3005 snd_pcm_alt_chmaps, 8, 0, &chmap);
3006 if (err < 0)
3007 return err;
b9a94a9c 3008 switch (codec->preset->vendor_id) {
53775b0d
TI		 3009 case 0x10de0002:
3010 case 0x10de0003:
3011 case 0x10de0005:
3012 case 0x10de0006:
3013 chmap->channel_mask = (1U << 2) | (1U << 8);
3014 break;
3015 case 0x10de0007:
3016 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3017 }
3018 return 0;
3019}
3020
84eb01be
TI		 3021static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3022{
3023 struct hdmi_spec *spec;
3024 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 3025 if (err < 0)
3026 return err;
3027 spec = codec->spec;
3028 spec->multiout.max_channels = 8;
d0b1252d 3029 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 3030 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 3031 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3032 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 3033
3034 /* Initialize the audio infoframe channel mask and checksum to something
3035 * valid */
3036 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3037
84eb01be
TI		 3038 return 0;
3039}
3040
611885bc
AH		 3041/*
3042 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3043 * - 0x10de0015
3044 * - 0x10de0040
3045 */
3046static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3047 int channels)
3048{
3049 if (cap->ca_index == 0x00 && channels == 2)
3050 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3051
3052 return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
3053}
3054
3055static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
3056{
3057 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3058 return -EINVAL;
3059
3060 return 0;
3061}
3062
3063static int patch_nvhdmi(struct hda_codec *codec)
3064{
3065 struct hdmi_spec *spec;
3066 int err;
3067
3068 err = patch_generic_hdmi(codec);
3069 if (err)
3070 return err;
3071
3072 spec = codec->spec;
75fae117 3073 spec->dyn_pin_out = true;
611885bc
AH		 3074
3075 spec->ops.chmap_cea_alloc_validate_get_type =
3076 nvhdmi_chmap_cea_alloc_validate_get_type;
3077 spec->ops.chmap_validate = nvhdmi_chmap_validate;
3078
3079 return 0;
3080}
3081
26e9a960
TR		 3082/*
3083 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3084 * accessed using vendor-defined verbs. These registers can be used for
3085 * interoperability between the HDA and HDMI drivers.
3086 */
3087
3088/* Audio Function Group node */
3089#define NVIDIA_AFG_NID 0x01
3090
3091/*
3092 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3093 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3094 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3095 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3096 * additional bit (at position 30) to signal the validity of the format.
3097 *
3098 * | 31 | 30 | 29 16 | 15 0 |
3099 * +---------+-------+--------+--------+
3100 * | TRIGGER | VALID | UNUSED | FORMAT |
3101 * +-----------------------------------|
3102 *
3103 * Note that for the trigger bit to take effect it needs to change value
3104 * (i.e. it needs to be toggled).
3105 */
3106#define NVIDIA_GET_SCRATCH0 0xfa6
3107#define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3108#define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3109#define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3110#define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3111#define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3112#define NVIDIA_SCRATCH_VALID (1 << 6)
3113
3114#define NVIDIA_GET_SCRATCH1 0xfab
3115#define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3116#define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3117#define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3118#define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3119
3120/*
3121 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3122 * the format is invalidated so that the HDMI codec can be disabled.
3123 */
3124static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3125{
3126 unsigned int value;
3127
3128 /* bits [31:30] contain the trigger and valid bits */
3129 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3130 NVIDIA_GET_SCRATCH0, 0);
3131 value = (value >> 24) & 0xff;
3132
3133 /* bits [15:0] are used to store the HDA format */
3134 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3135 NVIDIA_SET_SCRATCH0_BYTE0,
3136 (format >> 0) & 0xff);
3137 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3138 NVIDIA_SET_SCRATCH0_BYTE1,
3139 (format >> 8) & 0xff);
3140
3141 /* bits [16:24] are unused */
3142 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3143 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3144
3145 /*
3146 * Bit 30 signals that the data is valid and hence that HDMI audio can
3147 * be enabled.
3148 */
3149 if (format == 0)
3150 value &= ~NVIDIA_SCRATCH_VALID;
3151 else
3152 value |= NVIDIA_SCRATCH_VALID;
3153
3154 /*
3155 * Whenever the trigger bit is toggled, an interrupt is raised in the
3156 * HDMI codec. The HDMI driver will use that as trigger to update its
3157 * configuration.
3158 */
3159 value ^= NVIDIA_SCRATCH_TRIGGER;
3160
3161 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3162 NVIDIA_SET_SCRATCH0_BYTE3, value);
3163}
3164
3165static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3166 struct hda_codec *codec,
3167 unsigned int stream_tag,
3168 unsigned int format,
3169 struct snd_pcm_substream *substream)
3170{
3171 int err;
3172
3173 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3174 format, substream);
3175 if (err < 0)
3176 return err;
3177
3178 /* notify the HDMI codec of the format change */
3179 tegra_hdmi_set_format(codec, format);
3180
3181 return 0;
3182}
3183
3184static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3185 struct hda_codec *codec,
3186 struct snd_pcm_substream *substream)
3187{
3188 /* invalidate the format in the HDMI codec */
3189 tegra_hdmi_set_format(codec, 0);
3190
3191 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3192}
3193
3194static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3195{
3196 struct hdmi_spec *spec = codec->spec;
3197 unsigned int i;
3198
3199 for (i = 0; i < spec->num_pins; i++) {
3200 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3201
3202 if (pcm->pcm_type == type)
3203 return pcm;
3204 }
3205
3206 return NULL;
3207}
3208
3209static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3210{
3211 struct hda_pcm_stream *stream;
3212 struct hda_pcm *pcm;
3213 int err;
3214
3215 err = generic_hdmi_build_pcms(codec);
3216 if (err < 0)
3217 return err;
3218
3219 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3220 if (!pcm)
3221 return -ENODEV;
3222
3223 /*
3224 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3225 * codec about format changes.
3226 */
3227 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3228 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3229 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3230
3231 return 0;
3232}
3233
3234static int patch_tegra_hdmi(struct hda_codec *codec)
3235{
3236 int err;
3237
3238 err = patch_generic_hdmi(codec);
3239 if (err)
3240 return err;
3241
3242 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3243
3244 return 0;
3245}
3246
84eb01be 3247/*
5a613584 3248 * ATI/AMD-specific implementations
84eb01be
TI		 3249 */
3250
5a613584 3251#define is_amdhdmi_rev3_or_later(codec) \
7639a06c
TI		 3252 ((codec)->core.vendor_id == 0x1002aa01 && \
3253 ((codec)->core.revision_id & 0xff00) >= 0x0300)
5a613584
AH		 3254#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3255
3256/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3257#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3258#define ATI_VERB_SET_DOWNMIX_INFO 0x772
3259#define ATI_VERB_SET_MULTICHANNEL_01 0x777
3260#define ATI_VERB_SET_MULTICHANNEL_23 0x778
3261#define ATI_VERB_SET_MULTICHANNEL_45 0x779
3262#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
461cf6b3 3263#define ATI_VERB_SET_HBR_CONTROL 0x77c
5a613584
AH		 3264#define ATI_VERB_SET_MULTICHANNEL_1 0x785
3265#define ATI_VERB_SET_MULTICHANNEL_3 0x786
3266#define ATI_VERB_SET_MULTICHANNEL_5 0x787
3267#define ATI_VERB_SET_MULTICHANNEL_7 0x788
3268#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3269#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3270#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3271#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3272#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3273#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3274#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
461cf6b3 3275#define ATI_VERB_GET_HBR_CONTROL 0xf7c
5a613584
AH		 3276#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3277#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3278#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3279#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3280#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3281
84d69e79
AH		 3282/* AMD specific HDA cvt verbs */
3283#define ATI_VERB_SET_RAMP_RATE 0x770
3284#define ATI_VERB_GET_RAMP_RATE 0xf70
3285
5a613584
AH		 3286#define ATI_OUT_ENABLE 0x1
3287
3288#define ATI_MULTICHANNEL_MODE_PAIRED 0
3289#define ATI_MULTICHANNEL_MODE_SINGLE 1
3290
461cf6b3
AH		 3291#define ATI_HBR_CAPABLE 0x01
3292#define ATI_HBR_ENABLE 0x10
3293
89250f84
AH		 3294static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3295 unsigned char *buf, int *eld_size)
3296{
3297 /* call hda_eld.c ATI/AMD-specific function */
3298 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3299 is_amdhdmi_rev3_or_later(codec));
3300}
3301
5a613584
AH		 3302static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3303 int active_channels, int conn_type)
3304{
3305 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3306}
3307
3308static int atihdmi_paired_swap_fc_lfe(int pos)
3309{
3310 /*
3311 * ATI/AMD have automatic FC/LFE swap built-in
3312 * when in pairwise mapping mode.
3313 */
3314
3315 switch (pos) {
3316 /* see channel_allocations[].speakers[] */
3317 case 2: return 3;
3318 case 3: return 2;
3319 default: break;
3320 }
3321
3322 return pos;
3323}
3324
3325static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
3326{
3327 struct cea_channel_speaker_allocation *cap;
3328 int i, j;
3329
3330 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3331
3332 cap = &channel_allocations[get_channel_allocation_order(ca)];
3333 for (i = 0; i < chs; ++i) {
3334 int mask = to_spk_mask(map[i]);
3335 bool ok = false;
3336 bool companion_ok = false;
3337
3338 if (!mask)
3339 continue;
3340
3341 for (j = 0 + i % 2; j < 8; j += 2) {
3342 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3343 if (cap->speakers[chan_idx] == mask) {
3344 /* channel is in a supported position */
3345 ok = true;
3346
3347 if (i % 2 == 0 && i + 1 < chs) {
3348 /* even channel, check the odd companion */
3349 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3350 int comp_mask_req = to_spk_mask(map[i+1]);
3351 int comp_mask_act = cap->speakers[comp_chan_idx];
3352
3353 if (comp_mask_req == comp_mask_act)
3354 companion_ok = true;
3355 else
3356 return -EINVAL;
3357 }
3358 break;
3359 }
3360 }
3361
3362 if (!ok)
3363 return -EINVAL;
3364
3365 if (companion_ok)
3366 i++; /* companion channel already checked */
3367 }
3368
3369 return 0;
3370}
3371
3372static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3373 int hdmi_slot, int stream_channel)
3374{
3375 int verb;
3376 int ati_channel_setup = 0;
3377
3378 if (hdmi_slot > 7)
3379 return -EINVAL;
3380
3381 if (!has_amd_full_remap_support(codec)) {
3382 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3383
3384 /* In case this is an odd slot but without stream channel, do not
3385 * disable the slot since the corresponding even slot could have a
3386 * channel. In case neither have a channel, the slot pair will be
3387 * disabled when this function is called for the even slot. */
3388 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3389 return 0;
3390
3391 hdmi_slot -= hdmi_slot % 2;
3392
3393 if (stream_channel != 0xf)
3394 stream_channel -= stream_channel % 2;
3395 }
3396
3397 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3398
3399 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3400
3401 if (stream_channel != 0xf)
3402 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3403
3404 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3405}
3406
3407static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3408 int asp_slot)
3409{
3410 bool was_odd = false;
3411 int ati_asp_slot = asp_slot;
3412 int verb;
3413 int ati_channel_setup;
3414
3415 if (asp_slot > 7)
3416 return -EINVAL;
3417
3418 if (!has_amd_full_remap_support(codec)) {
3419 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3420 if (ati_asp_slot % 2 != 0) {
3421 ati_asp_slot -= 1;
3422 was_odd = true;
3423 }
3424 }
3425
3426 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3427
3428 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3429
3430 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3431 return 0xf;
3432
3433 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3434}
84eb01be 3435
5a613584
AH		 3436static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3437 int channels)
3438{
3439 int c;
3440
3441 /*
3442 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3443 * we need to take that into account (a single channel may take 2
3444 * channel slots if we need to carry a silent channel next to it).
3445 * On Rev3+ AMD codecs this function is not used.
3446 */
3447 int chanpairs = 0;
3448
3449 /* We only produce even-numbered channel count TLVs */
3450 if ((channels % 2) != 0)
3451 return -1;
3452
3453 for (c = 0; c < 7; c += 2) {
3454 if (cap->speakers[c] || cap->speakers[c+1])
3455 chanpairs++;
3456 }
3457
3458 if (chanpairs * 2 != channels)
3459 return -1;
3460
3461 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3462}
3463
3464static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3465 unsigned int *chmap, int channels)
3466{
3467 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3468 int count = 0;
3469 int c;
3470
3471 for (c = 7; c >= 0; c--) {
3472 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3473 int spk = cap->speakers[chan];
3474 if (!spk) {
3475 /* add N/A channel if the companion channel is occupied */
3476 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3477 chmap[count++] = SNDRV_CHMAP_NA;
3478
3479 continue;
3480 }
3481
3482 chmap[count++] = spk_to_chmap(spk);
3483 }
3484
3485 WARN_ON(count != channels);
3486}
3487
461cf6b3
AH		 3488static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3489 bool hbr)
3490{
3491 int hbr_ctl, hbr_ctl_new;
3492
3493 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
13122e6e 3494 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
461cf6b3
AH		 3495 if (hbr)
3496 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3497 else
3498 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3499
4e76a883
TI		 3500 codec_dbg(codec,
3501 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
461cf6b3
AH		 3502 pin_nid,
3503 hbr_ctl == hbr_ctl_new ? "" : "new-",
3504 hbr_ctl_new);
3505
3506 if (hbr_ctl != hbr_ctl_new)
3507 snd_hda_codec_write(codec, pin_nid, 0,
3508 ATI_VERB_SET_HBR_CONTROL,
3509 hbr_ctl_new);
3510
3511 } else if (hbr)
3512 return -EINVAL;
3513
3514 return 0;
3515}
3516
84d69e79
AH		 3517static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3518 hda_nid_t pin_nid, u32 stream_tag, int format)
3519{
3520
3521 if (is_amdhdmi_rev3_or_later(codec)) {
3522 int ramp_rate = 180; /* default as per AMD spec */
3523 /* disable ramp-up/down for non-pcm as per AMD spec */
3524 if (format & AC_FMT_TYPE_NON_PCM)
3525 ramp_rate = 0;
3526
3527 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3528 }
3529
3530 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3531}
3532
3533
5a613584 3534static int atihdmi_init(struct hda_codec *codec)
84eb01be
TI		 3535{
3536 struct hdmi_spec *spec = codec->spec;
5a613584 3537 int pin_idx, err;
84eb01be 3538
5a613584
AH		 3539 err = generic_hdmi_init(codec);
3540
3541 if (err)
84eb01be 3542 return err;
5a613584
AH		 3543
3544 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3545 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3546
3547 /* make sure downmix information in infoframe is zero */
3548 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3549
3550 /* enable channel-wise remap mode if supported */
3551 if (has_amd_full_remap_support(codec))
3552 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3553 ATI_VERB_SET_MULTICHANNEL_MODE,
3554 ATI_MULTICHANNEL_MODE_SINGLE);
84eb01be 3555 }
5a613584 3556
84eb01be
TI		 3557 return 0;
3558}
3559
84eb01be
TI		 3560static int patch_atihdmi(struct hda_codec *codec)
3561{
3562 struct hdmi_spec *spec;
5a613584
AH		 3563 struct hdmi_spec_per_cvt *per_cvt;
3564 int err, cvt_idx;
3565
3566 err = patch_generic_hdmi(codec);
3567
3568 if (err)
d0b1252d 3569 return err;
5a613584
AH		 3570
3571 codec->patch_ops.init = atihdmi_init;
3572
d0b1252d 3573 spec = codec->spec;
5a613584 3574
89250f84 3575 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
5a613584
AH		 3576 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3577 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3578 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
461cf6b3 3579 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
84d69e79 3580 spec->ops.setup_stream = atihdmi_setup_stream;
5a613584
AH		 3581
3582 if (!has_amd_full_remap_support(codec)) {
3583 /* override to ATI/AMD-specific versions with pairwise mapping */
3584 spec->ops.chmap_cea_alloc_validate_get_type =
3585 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3586 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3587 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3588 }
3589
3590 /* ATI/AMD converters do not advertise all of their capabilities */
3591 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3592 per_cvt = get_cvt(spec, cvt_idx);
3593 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3594 per_cvt->rates |= SUPPORTED_RATES;
3595 per_cvt->formats |= SUPPORTED_FORMATS;
3596 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3597 }
3598
3599 spec->channels_max = max(spec->channels_max, 8u);
3600
84eb01be
TI		 3601 return 0;
3602}
3603
3de5ff88
AL		 3604/* VIA HDMI Implementation */
3605#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3606#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3607
3de5ff88
AL		 3608static int patch_via_hdmi(struct hda_codec *codec)
3609{
250e41ac 3610 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 3611}
84eb01be
TI		 3612
3613/*
3614 * patch entries
3615 */
b9a94a9c
TI		 3616static const struct hda_device_id snd_hda_id_hdmi[] = {
3617HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
3618HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
3619HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
3620HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
3621HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
3622HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
3623HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
3624HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3625HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3626HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3627HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3628HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
3629HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
3630HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
3631HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
3632HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
3633HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
3634HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
3635HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
3636HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
3637HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
3638HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
3639HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
c8900a0f 3640/* 17 is known to be absent */
b9a94a9c
TI		 3641HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
3642HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
3643HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
3644HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
3645HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
3646HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
3647HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
3648HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
3649HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3650HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
3651HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
3652HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
3653HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
3654HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
3655HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
3656HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
3657HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
3658HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
3659HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
3660HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
3661HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
3ec622f4 3662HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
b9a94a9c
TI		 3663HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
3664HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
3665HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
3666HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
3667HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
3668HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_generic_hdmi),
3669HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
3670HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
3671HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
3672HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_generic_hdmi),
3673HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_generic_hdmi),
3674HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_generic_hdmi),
3675HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_generic_hdmi),
3676HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_generic_hdmi),
3677HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_generic_hdmi),
3678HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_generic_hdmi),
91815d8a 3679HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_generic_hdmi),
b9a94a9c
TI		 3680HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
3681HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_generic_hdmi),
3682HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_generic_hdmi),
3683HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
d8a766a1 3684/* special ID for generic HDMI */
b9a94a9c 3685HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
84eb01be
TI		 3686{} /* terminator */
3687};
b9a94a9c 3688MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
84eb01be
TI		 3689
3690MODULE_LICENSE("GPL");
3691MODULE_DESCRIPTION("HDMI HD-audio codec");
3692MODULE_ALIAS("snd-hda-codec-intelhdmi");
3693MODULE_ALIAS("snd-hda-codec-nvhdmi");
3694MODULE_ALIAS("snd-hda-codec-atihdmi");
3695
d8a766a1 3696static struct hda_codec_driver hdmi_driver = {
b9a94a9c 3697 .id = snd_hda_id_hdmi,
84eb01be
TI		 3698};
3699
d8a766a1 3700module_hda_codec_driver(hdmi_driver);
Linux 6.x block layer and io_uring tree(s)