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ALSA: hda/ca0132 - Fix possible workqueue stall
[linux-2.6-block.git] / sound / pci / hda / patch_ca0132.c
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d0fa1179 1// SPDX-License-Identifier: GPL-2.0-or-later
95c6e9cb
IM		 2/*
3 * HD audio interface patch for Creative CA0132 chip
4 *
5 * Copyright (c) 2011, Creative Technology Ltd.
6 *
7 * Based on patch_ca0110.c
8 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
95c6e9cb
IM		 9 */
10
11#include <linux/init.h>
12#include <linux/delay.h>
13#include <linux/slab.h>
95c6e9cb 14#include <linux/mutex.h>
da155d5b 15#include <linux/module.h>
4aa3bb0c 16#include <linux/firmware.h>
a9291f46 17#include <linux/kernel.h>
aa31704f
CM		 18#include <linux/types.h>
19#include <linux/io.h>
20#include <linux/pci.h>
d9b84a15 21#include <asm/io.h>
95c6e9cb 22#include <sound/core.h>
be57bfff 23#include <sound/hda_codec.h>
95c6e9cb 24#include "hda_local.h"
128bc4ba 25#include "hda_auto_parser.h"
5aaca44d 26#include "hda_jack.h"
95c6e9cb 27
bcd109c0
IM		 28#include "ca0132_regs.h"
29
ef6b2ead
IM		 30/* Enable this to see controls for tuning purpose. */
31/*#define ENABLE_TUNING_CONTROLS*/
32
8e142e9e
TS		 33#ifdef ENABLE_TUNING_CONTROLS
34#include <sound/tlv.h>
35#endif
36
ef6b2ead
IM		 37#define FLOAT_ZERO 0x00000000
38#define FLOAT_ONE 0x3f800000
39#define FLOAT_TWO 0x40000000
38ba69ff 40#define FLOAT_THREE 0x40400000
7cb9d94c 41#define FLOAT_EIGHT 0x41000000
ef6b2ead
IM		 42#define FLOAT_MINUS_5 0xc0a00000
43
ef6b2ead
IM		 44#define UNSOL_TAG_DSP 0x16
45
4aa3bb0c
IM		 46#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
47#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
48
49#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
50#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
51#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
52
53#define MASTERCONTROL 0x80
ef6b2ead
IM		 54#define MASTERCONTROL_ALLOC_DMA_CHAN 10
55#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
4aa3bb0c 56
95c6e9cb
IM		 57#define WIDGET_CHIP_CTRL 0x15
58#define WIDGET_DSP_CTRL 0x16
59
4aa3bb0c
IM		 60#define MEM_CONNID_MICIN1 3
61#define MEM_CONNID_MICIN2 5
62#define MEM_CONNID_MICOUT1 12
63#define MEM_CONNID_MICOUT2 14
64#define MEM_CONNID_WUH 10
65#define MEM_CONNID_DSP 16
66#define MEM_CONNID_DMIC 100
67
68#define SCP_SET 0
69#define SCP_GET 1
70
01ef7dbf 71#define EFX_FILE "ctefx.bin"
7a928186 72#define DESKTOP_EFX_FILE "ctefx-desktop.bin"
8a19bcee 73#define R3DI_EFX_FILE "ctefx-r3di.bin"
01ef7dbf 74
24f3cede 75#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf 76MODULE_FIRMWARE(EFX_FILE);
7a928186 77MODULE_FIRMWARE(DESKTOP_EFX_FILE);
8a19bcee 78MODULE_FIRMWARE(R3DI_EFX_FILE);
7a527ede 79#endif
01ef7dbf 80
3a03f83b 81static const char *const dirstr[2] = { "Playback", "Capture" };
ef6b2ead 82
7cb9d94c 83#define NUM_OF_OUTPUTS 3
ef6b2ead
IM		 84enum {
85 SPEAKER_OUT,
7cb9d94c
CM		 86 HEADPHONE_OUT,
87 SURROUND_OUT
ef6b2ead
IM		 88};
89
90enum {
91 DIGITAL_MIC,
92 LINE_MIC_IN
93};
94
7cb9d94c 95/* Strings for Input Source Enum Control */
3a03f83b 96static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" };
7cb9d94c
CM		 97#define IN_SRC_NUM_OF_INPUTS 3
98enum {
99 REAR_MIC,
100 REAR_LINE_IN,
101 FRONT_MIC,
102};
103
ef6b2ead
IM		 104enum {
105#define VNODE_START_NID 0x80
106 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
107 VNID_MIC,
108 VNID_HP_SEL,
109 VNID_AMIC1_SEL,
110 VNID_HP_ASEL,
111 VNID_AMIC1_ASEL,
112 VNODE_END_NID,
113#define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
114
115#define EFFECT_START_NID 0x90
116#define OUT_EFFECT_START_NID EFFECT_START_NID
117 SURROUND = OUT_EFFECT_START_NID,
118 CRYSTALIZER,
119 DIALOG_PLUS,
120 SMART_VOLUME,
121 X_BASS,
122 EQUALIZER,
123 OUT_EFFECT_END_NID,
124#define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
125
126#define IN_EFFECT_START_NID OUT_EFFECT_END_NID
127 ECHO_CANCELLATION = IN_EFFECT_START_NID,
128 VOICE_FOCUS,
129 MIC_SVM,
130 NOISE_REDUCTION,
131 IN_EFFECT_END_NID,
132#define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
133
134 VOICEFX = IN_EFFECT_END_NID,
135 PLAY_ENHANCEMENT,
136 CRYSTAL_VOICE,
7cb9d94c
CM		 137 EFFECT_END_NID,
138 OUTPUT_SOURCE_ENUM,
47cdf76e
CM		 139 INPUT_SOURCE_ENUM,
140 XBASS_XOVER,
141 EQ_PRESET_ENUM,
142 SMART_VOLUME_ENUM,
212de2e7
CM		 143 MIC_BOOST_ENUM,
144 AE5_HEADPHONE_GAIN_ENUM,
d51434d4
CM		 145 AE5_SOUND_FILTER_ENUM,
146 ZXR_HEADPHONE_GAIN
ef6b2ead
IM		 147#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
148};
149
150/* Effects values size*/
151#define EFFECT_VALS_MAX_COUNT 12
152
47cdf76e
CM		 153/*
154 * Default values for the effect slider controls, they are in order of their
155 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
156 * X-bass.
157 */
158static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
159/* Amount of effect level sliders for ca0132_alt controls. */
160#define EFFECT_LEVEL_SLIDERS 5
161
e8412ca4
DR		 162/* Latency introduced by DSP blocks in milliseconds. */
163#define DSP_CAPTURE_INIT_LATENCY 0
164#define DSP_CRYSTAL_VOICE_LATENCY 124
165#define DSP_PLAYBACK_INIT_LATENCY 13
166#define DSP_PLAY_ENHANCEMENT_LATENCY 30
167#define DSP_SPEAKER_OUT_LATENCY 7
168
ef6b2ead 169struct ct_effect {
975cc02a 170 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 171 hda_nid_t nid;
172 int mid; /*effect module ID*/
173 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
174 int direct; /* 0:output; 1:input*/
175 int params; /* number of default non-on/off params */
176 /*effect default values, 1st is on/off. */
177 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
178};
179
180#define EFX_DIR_OUT 0
181#define EFX_DIR_IN 1
182
862154bb 183static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
ef6b2ead
IM		 184 { .name = "Surround",
185 .nid = SURROUND,
186 .mid = 0x96,
187 .reqs = {0, 1},
188 .direct = EFX_DIR_OUT,
189 .params = 1,
190 .def_vals = {0x3F800000, 0x3F2B851F}
191 },
192 { .name = "Crystalizer",
193 .nid = CRYSTALIZER,
194 .mid = 0x96,
195 .reqs = {7, 8},
196 .direct = EFX_DIR_OUT,
197 .params = 1,
198 .def_vals = {0x3F800000, 0x3F266666}
199 },
200 { .name = "Dialog Plus",
201 .nid = DIALOG_PLUS,
202 .mid = 0x96,
203 .reqs = {2, 3},
204 .direct = EFX_DIR_OUT,
205 .params = 1,
206 .def_vals = {0x00000000, 0x3F000000}
207 },
208 { .name = "Smart Volume",
209 .nid = SMART_VOLUME,
210 .mid = 0x96,
211 .reqs = {4, 5, 6},
212 .direct = EFX_DIR_OUT,
213 .params = 2,
214 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
215 },
216 { .name = "X-Bass",
217 .nid = X_BASS,
218 .mid = 0x96,
219 .reqs = {24, 23, 25},
220 .direct = EFX_DIR_OUT,
221 .params = 2,
222 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
223 },
224 { .name = "Equalizer",
225 .nid = EQUALIZER,
226 .mid = 0x96,
227 .reqs = {9, 10, 11, 12, 13, 14,
228 15, 16, 17, 18, 19, 20},
229 .direct = EFX_DIR_OUT,
230 .params = 11,
231 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
232 0x00000000, 0x00000000, 0x00000000, 0x00000000,
233 0x00000000, 0x00000000, 0x00000000, 0x00000000}
234 },
235 { .name = "Echo Cancellation",
236 .nid = ECHO_CANCELLATION,
237 .mid = 0x95,
238 .reqs = {0, 1, 2, 3},
239 .direct = EFX_DIR_IN,
240 .params = 3,
241 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
242 },
243 { .name = "Voice Focus",
244 .nid = VOICE_FOCUS,
245 .mid = 0x95,
246 .reqs = {6, 7, 8, 9},
247 .direct = EFX_DIR_IN,
248 .params = 3,
249 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
250 },
251 { .name = "Mic SVM",
252 .nid = MIC_SVM,
253 .mid = 0x95,
254 .reqs = {44, 45},
255 .direct = EFX_DIR_IN,
256 .params = 1,
257 .def_vals = {0x00000000, 0x3F3D70A4}
258 },
259 { .name = "Noise Reduction",
260 .nid = NOISE_REDUCTION,
261 .mid = 0x95,
262 .reqs = {4, 5},
263 .direct = EFX_DIR_IN,
264 .params = 1,
265 .def_vals = {0x3F800000, 0x3F000000}
266 },
267 { .name = "VoiceFX",
268 .nid = VOICEFX,
269 .mid = 0x95,
270 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
271 .direct = EFX_DIR_IN,
272 .params = 8,
273 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
274 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
275 0x00000000}
276 }
277};
278
279/* Tuning controls */
280#ifdef ENABLE_TUNING_CONTROLS
281
282enum {
283#define TUNING_CTL_START_NID 0xC0
284 WEDGE_ANGLE = TUNING_CTL_START_NID,
285 SVM_LEVEL,
286 EQUALIZER_BAND_0,
287 EQUALIZER_BAND_1,
288 EQUALIZER_BAND_2,
289 EQUALIZER_BAND_3,
290 EQUALIZER_BAND_4,
291 EQUALIZER_BAND_5,
292 EQUALIZER_BAND_6,
293 EQUALIZER_BAND_7,
294 EQUALIZER_BAND_8,
295 EQUALIZER_BAND_9,
296 TUNING_CTL_END_NID
297#define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
298};
299
300struct ct_tuning_ctl {
975cc02a 301 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 302 hda_nid_t parent_nid;
303 hda_nid_t nid;
304 int mid; /*effect module ID*/
305 int req; /*effect module request*/
306 int direct; /* 0:output; 1:input*/
307 unsigned int def_val;/*effect default values*/
308};
309
862154bb 310static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
ef6b2ead
IM		 311 { .name = "Wedge Angle",
312 .parent_nid = VOICE_FOCUS,
313 .nid = WEDGE_ANGLE,
314 .mid = 0x95,
315 .req = 8,
316 .direct = EFX_DIR_IN,
317 .def_val = 0x41F00000
318 },
319 { .name = "SVM Level",
320 .parent_nid = MIC_SVM,
321 .nid = SVM_LEVEL,
322 .mid = 0x95,
323 .req = 45,
324 .direct = EFX_DIR_IN,
325 .def_val = 0x3F3D70A4
326 },
327 { .name = "EQ Band0",
328 .parent_nid = EQUALIZER,
329 .nid = EQUALIZER_BAND_0,
330 .mid = 0x96,
331 .req = 11,
332 .direct = EFX_DIR_OUT,
333 .def_val = 0x00000000
334 },
335 { .name = "EQ Band1",
336 .parent_nid = EQUALIZER,
337 .nid = EQUALIZER_BAND_1,
338 .mid = 0x96,
339 .req = 12,
340 .direct = EFX_DIR_OUT,
341 .def_val = 0x00000000
342 },
343 { .name = "EQ Band2",
344 .parent_nid = EQUALIZER,
345 .nid = EQUALIZER_BAND_2,
346 .mid = 0x96,
347 .req = 13,
348 .direct = EFX_DIR_OUT,
349 .def_val = 0x00000000
350 },
351 { .name = "EQ Band3",
352 .parent_nid = EQUALIZER,
353 .nid = EQUALIZER_BAND_3,
354 .mid = 0x96,
355 .req = 14,
356 .direct = EFX_DIR_OUT,
357 .def_val = 0x00000000
358 },
359 { .name = "EQ Band4",
360 .parent_nid = EQUALIZER,
361 .nid = EQUALIZER_BAND_4,
362 .mid = 0x96,
363 .req = 15,
364 .direct = EFX_DIR_OUT,
365 .def_val = 0x00000000
366 },
367 { .name = "EQ Band5",
368 .parent_nid = EQUALIZER,
369 .nid = EQUALIZER_BAND_5,
370 .mid = 0x96,
371 .req = 16,
372 .direct = EFX_DIR_OUT,
373 .def_val = 0x00000000
374 },
375 { .name = "EQ Band6",
376 .parent_nid = EQUALIZER,
377 .nid = EQUALIZER_BAND_6,
378 .mid = 0x96,
379 .req = 17,
380 .direct = EFX_DIR_OUT,
381 .def_val = 0x00000000
382 },
383 { .name = "EQ Band7",
384 .parent_nid = EQUALIZER,
385 .nid = EQUALIZER_BAND_7,
386 .mid = 0x96,
387 .req = 18,
388 .direct = EFX_DIR_OUT,
389 .def_val = 0x00000000
390 },
391 { .name = "EQ Band8",
392 .parent_nid = EQUALIZER,
393 .nid = EQUALIZER_BAND_8,
394 .mid = 0x96,
395 .req = 19,
396 .direct = EFX_DIR_OUT,
397 .def_val = 0x00000000
398 },
399 { .name = "EQ Band9",
400 .parent_nid = EQUALIZER,
401 .nid = EQUALIZER_BAND_9,
402 .mid = 0x96,
403 .req = 20,
404 .direct = EFX_DIR_OUT,
405 .def_val = 0x00000000
406 }
407};
408#endif
409
410/* Voice FX Presets */
411#define VOICEFX_MAX_PARAM_COUNT 9
412
413struct ct_voicefx {
414 char *name;
415 hda_nid_t nid;
416 int mid;
417 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
418};
419
420struct ct_voicefx_preset {
421 char *name; /*preset name*/
422 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
423};
424
862154bb 425static const struct ct_voicefx ca0132_voicefx = {
ef6b2ead
IM		 426 .name = "VoiceFX Capture Switch",
427 .nid = VOICEFX,
428 .mid = 0x95,
429 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
430};
431
862154bb 432static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
ef6b2ead
IM		 433 { .name = "Neutral",
434 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
435 0x44FA0000, 0x3F800000, 0x3F800000,
436 0x3F800000, 0x00000000, 0x00000000 }
437 },
438 { .name = "Female2Male",
439 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
440 0x44FA0000, 0x3F19999A, 0x3F866666,
441 0x3F800000, 0x00000000, 0x00000000 }
442 },
443 { .name = "Male2Female",
444 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
445 0x450AC000, 0x4017AE14, 0x3F6B851F,
446 0x3F800000, 0x00000000, 0x00000000 }
447 },
448 { .name = "ScrappyKid",
449 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
450 0x44FA0000, 0x40400000, 0x3F28F5C3,
451 0x3F800000, 0x00000000, 0x00000000 }
452 },
453 { .name = "Elderly",
454 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
455 0x44E10000, 0x3FB33333, 0x3FB9999A,
456 0x3F800000, 0x3E3A2E43, 0x00000000 }
457 },
458 { .name = "Orc",
459 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
460 0x45098000, 0x3F266666, 0x3FC00000,
461 0x3F800000, 0x00000000, 0x00000000 }
462 },
463 { .name = "Elf",
464 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
465 0x45193000, 0x3F8E147B, 0x3F75C28F,
466 0x3F800000, 0x00000000, 0x00000000 }
467 },
468 { .name = "Dwarf",
469 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
470 0x45007000, 0x3F451EB8, 0x3F7851EC,
471 0x3F800000, 0x00000000, 0x00000000 }
472 },
473 { .name = "AlienBrute",
474 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
475 0x451F6000, 0x3F266666, 0x3FA7D945,
476 0x3F800000, 0x3CF5C28F, 0x00000000 }
477 },
478 { .name = "Robot",
479 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
480 0x44FA0000, 0x3FB2718B, 0x3F800000,
481 0xBC07010E, 0x00000000, 0x00000000 }
482 },
483 { .name = "Marine",
484 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
485 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
486 0x3F0A3D71, 0x00000000, 0x00000000 }
487 },
488 { .name = "Emo",
489 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
490 0x44FA0000, 0x3F800000, 0x3F800000,
491 0x3E4CCCCD, 0x00000000, 0x00000000 }
492 },
493 { .name = "DeepVoice",
494 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
495 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
496 0x3F800000, 0x00000000, 0x00000000 }
497 },
498 { .name = "Munchkin",
499 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
500 0x44FA0000, 0x3F800000, 0x3F1A043C,
501 0x3F800000, 0x00000000, 0x00000000 }
502 }
503};
504
47cdf76e
CM		 505/* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
506
507#define EQ_PRESET_MAX_PARAM_COUNT 11
508
509struct ct_eq {
510 char *name;
511 hda_nid_t nid;
512 int mid;
513 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
514};
515
516struct ct_eq_preset {
517 char *name; /*preset name*/
518 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
519};
520
862154bb 521static const struct ct_eq ca0132_alt_eq_enum = {
47cdf76e
CM		 522 .name = "FX: Equalizer Preset Switch",
523 .nid = EQ_PRESET_ENUM,
524 .mid = 0x96,
525 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
526};
527
528
862154bb 529static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
47cdf76e
CM		 530 { .name = "Flat",
531 .vals = { 0x00000000, 0x00000000, 0x00000000,
532 0x00000000, 0x00000000, 0x00000000,
533 0x00000000, 0x00000000, 0x00000000,
534 0x00000000, 0x00000000 }
535 },
536 { .name = "Acoustic",
537 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
538 0x40000000, 0x00000000, 0x00000000,
539 0x00000000, 0x00000000, 0x40000000,
540 0x40000000, 0x40000000 }
541 },
542 { .name = "Classical",
543 .vals = { 0x00000000, 0x00000000, 0x40C00000,
544 0x40C00000, 0x40466666, 0x00000000,
545 0x00000000, 0x00000000, 0x00000000,
546 0x40466666, 0x40466666 }
547 },
548 { .name = "Country",
549 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
550 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
551 0x00000000, 0x00000000, 0x40000000,
552 0x40466666, 0x40800000 }
553 },
554 { .name = "Dance",
555 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
556 0x40466666, 0x40866666, 0xBF99999A,
557 0xBF99999A, 0x00000000, 0x00000000,
558 0x40800000, 0x40800000 }
559 },
560 { .name = "Jazz",
561 .vals = { 0x00000000, 0x00000000, 0x00000000,
562 0x3F8CCCCD, 0x40800000, 0x40800000,
563 0x40800000, 0x00000000, 0x3F8CCCCD,
564 0x40466666, 0x40466666 }
565 },
566 { .name = "New Age",
567 .vals = { 0x00000000, 0x00000000, 0x40000000,
568 0x40000000, 0x00000000, 0x00000000,
569 0x00000000, 0x3F8CCCCD, 0x40000000,
570 0x40000000, 0x40000000 }
571 },
572 { .name = "Pop",
573 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
574 0x40000000, 0x40000000, 0x00000000,
575 0xBF99999A, 0xBF99999A, 0x00000000,
576 0x40466666, 0x40C00000 }
577 },
578 { .name = "Rock",
579 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
580 0x3F8CCCCD, 0x40000000, 0xBF99999A,
581 0xBF99999A, 0x00000000, 0x00000000,
582 0x40800000, 0x40800000 }
583 },
584 { .name = "Vocal",
585 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
586 0xBF99999A, 0x00000000, 0x40466666,
587 0x40800000, 0x40466666, 0x00000000,
588 0x00000000, 0x3F8CCCCD }
589 }
590};
591
7cb9d94c
CM		 592/* DSP command sequences for ca0132_alt_select_out */
593#define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */
594struct ca0132_alt_out_set {
595 char *name; /*preset name*/
596 unsigned char commands;
597 unsigned int mids[ALT_OUT_SET_MAX_COMMANDS];
598 unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS];
599 unsigned int vals[ALT_OUT_SET_MAX_COMMANDS];
600};
601
602static const struct ca0132_alt_out_set alt_out_presets[] = {
603 { .name = "Line Out",
604 .commands = 7,
605 .mids = { 0x96, 0x96, 0x96, 0x8F,
606 0x96, 0x96, 0x96 },
607 .reqs = { 0x19, 0x17, 0x18, 0x01,
608 0x1F, 0x15, 0x3A },
609 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
610 0x00000000, 0x00000000, 0x00000000,
611 0x00000000 }
612 },
613 { .name = "Headphone",
614 .commands = 7,
615 .mids = { 0x96, 0x96, 0x96, 0x8F,
616 0x96, 0x96, 0x96 },
617 .reqs = { 0x19, 0x17, 0x18, 0x01,
618 0x1F, 0x15, 0x3A },
619 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
620 0x00000000, 0x00000000, 0x00000000,
621 0x00000000 }
622 },
623 { .name = "Surround",
624 .commands = 8,
625 .mids = { 0x96, 0x8F, 0x96, 0x96,
626 0x96, 0x96, 0x96, 0x96 },
627 .reqs = { 0x18, 0x01, 0x1F, 0x15,
628 0x3A, 0x1A, 0x1B, 0x1C },
629 .vals = { 0x00000000, 0x00000000, 0x00000000,
630 0x00000000, 0x00000000, 0x00000000,
631 0x00000000, 0x00000000 }
632 }
633};
634
017310fb
CM		 635/*
636 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
637 * and I don't know what the third req is, but it's always zero. I assume it's
638 * some sort of update or set command to tell the DSP there's new volume info.
639 */
640#define DSP_VOL_OUT 0
641#define DSP_VOL_IN 1
642
643struct ct_dsp_volume_ctl {
644 hda_nid_t vnid;
645 int mid; /* module ID*/
646 unsigned int reqs[3]; /* scp req ID */
647};
648
862154bb 649static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
017310fb
CM		 650 { .vnid = VNID_SPK,
651 .mid = 0x32,
652 .reqs = {3, 4, 2}
653 },
654 { .vnid = VNID_MIC,
655 .mid = 0x37,
656 .reqs = {2, 3, 1}
657 }
658};
659
2283c85b
CM		 660/* Values for ca0113_mmio_command_set for selecting output. */
661#define AE5_CA0113_OUT_SET_COMMANDS 6
662struct ae5_ca0113_output_set {
663 unsigned int group[AE5_CA0113_OUT_SET_COMMANDS];
664 unsigned int target[AE5_CA0113_OUT_SET_COMMANDS];
665 unsigned int vals[AE5_CA0113_OUT_SET_COMMANDS];
666};
667
668static const struct ae5_ca0113_output_set ae5_ca0113_output_presets[] = {
669 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
670 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
671 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }
672 },
673 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
674 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
675 .vals = { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 }
676 },
677 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
678 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
679 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }
680 }
681};
682
212de2e7
CM		 683/* ae5 ca0113 command sequences to set headphone gain levels. */
684#define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4
685struct ae5_headphone_gain_set {
686 char *name;
687 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS];
688};
689
690static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = {
691 { .name = "Low (16-31",
692 .vals = { 0xff, 0x2c, 0xf5, 0x32 }
693 },
694 { .name = "Medium (32-149",
695 .vals = { 0x38, 0xa8, 0x3e, 0x4c }
696 },
697 { .name = "High (150-600",
698 .vals = { 0xff, 0xff, 0xff, 0x7f }
699 }
700};
701
702struct ae5_filter_set {
703 char *name;
704 unsigned int val;
705};
706
707static const struct ae5_filter_set ae5_filter_presets[] = {
708 { .name = "Slow Roll Off",
709 .val = 0xa0
710 },
711 { .name = "Minimum Phase",
712 .val = 0xc0
713 },
714 { .name = "Fast Roll Off",
715 .val = 0x80
716 }
717};
718
95c6e9cb
IM		 719enum hda_cmd_vendor_io {
720 /* for DspIO node */
721 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
722 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
723
724 VENDOR_DSPIO_STATUS = 0xF01,
725 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
726 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
727 VENDOR_DSPIO_DSP_INIT = 0x703,
728 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
729 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
730
731 /* for ChipIO node */
732 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
733 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
734 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
735 VENDOR_CHIPIO_DATA_LOW = 0x300,
736 VENDOR_CHIPIO_DATA_HIGH = 0x400,
737
bf85a91c
CM		 738 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500,
739 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00,
740
95c6e9cb
IM		 741 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
742 VENDOR_CHIPIO_STATUS = 0xF01,
743 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
744 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
745
4aa3bb0c
IM		 746 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
747 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
bf85a91c
CM		 748 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08,
749 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709,
750 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09,
4aa3bb0c 751
95c6e9cb 752 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
4aa3bb0c 753 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
95c6e9cb
IM		 754
755 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
756 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
757 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
758 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
759 VENDOR_CHIPIO_FLAG_SET = 0x70F,
760 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
4aa3bb0c
IM		 761 VENDOR_CHIPIO_PARAM_SET = 0x710,
762 VENDOR_CHIPIO_PARAM_GET = 0xF10,
95c6e9cb
IM		 763
764 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
765 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
766 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
767 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
768
4aa3bb0c
IM		 769 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
770 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
771 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
772 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
773
774 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
775 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
776 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
777 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
778 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
779 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
780
781 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
95c6e9cb
IM		 782};
783
784/*
785 * Control flag IDs
786 */
787enum control_flag_id {
788 /* Connection manager stream setup is bypassed/enabled */
789 CONTROL_FLAG_C_MGR = 0,
790 /* DSP DMA is bypassed/enabled */
791 CONTROL_FLAG_DMA = 1,
792 /* 8051 'idle' mode is disabled/enabled */
793 CONTROL_FLAG_IDLE_ENABLE = 2,
794 /* Tracker for the SPDIF-in path is bypassed/enabled */
795 CONTROL_FLAG_TRACKER = 3,
796 /* DigitalOut to Spdif2Out connection is disabled/enabled */
797 CONTROL_FLAG_SPDIF2OUT = 4,
798 /* Digital Microphone is disabled/enabled */
799 CONTROL_FLAG_DMIC = 5,
800 /* ADC_B rate is 48 kHz/96 kHz */
801 CONTROL_FLAG_ADC_B_96KHZ = 6,
802 /* ADC_C rate is 48 kHz/96 kHz */
803 CONTROL_FLAG_ADC_C_96KHZ = 7,
804 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
805 CONTROL_FLAG_DAC_96KHZ = 8,
806 /* DSP rate is 48 kHz/96 kHz */
807 CONTROL_FLAG_DSP_96KHZ = 9,
808 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
809 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
810 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
811 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
812 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
813 CONTROL_FLAG_DECODE_LOOP = 12,
814 /* De-emphasis filter on DAC-1 disabled/enabled */
815 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
816 /* De-emphasis filter on DAC-2 disabled/enabled */
817 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
818 /* De-emphasis filter on DAC-3 disabled/enabled */
819 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
820 /* High-pass filter on ADC_B disabled/enabled */
821 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
822 /* High-pass filter on ADC_C disabled/enabled */
823 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
824 /* Common mode on Port_A disabled/enabled */
825 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
826 /* Common mode on Port_D disabled/enabled */
827 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
828 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
829 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
830 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
4aa3bb0c 831 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
95c6e9cb
IM		 832 /* ASI rate is 48kHz/96kHz */
833 CONTROL_FLAG_ASI_96KHZ = 22,
834 /* DAC power settings able to control attached ports no/yes */
835 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
836 /* Clock Stop OK reporting is disabled/enabled */
837 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
838 /* Number of control flags */
839 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
840};
841
842/*
843 * Control parameter IDs
844 */
4aa3bb0c 845enum control_param_id {
ef6b2ead
IM		 846 /* 0: None, 1: Mic1In*/
847 CONTROL_PARAM_VIP_SOURCE = 1,
95c6e9cb
IM		 848 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
849 CONTROL_PARAM_SPDIF1_SOURCE = 2,
ef6b2ead
IM		 850 /* Port A output stage gain setting to use when 16 Ohm output
851 * impedance is selected*/
852 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
853 /* Port D output stage gain setting to use when 16 Ohm output
854 * impedance is selected*/
855 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
95c6e9cb 856
bf85a91c
CM		 857 /*
858 * This control param name was found in the 8051 memory, and makes
859 * sense given the fact the AE-5 uses it and has the ASI flag set.
860 */
861 CONTROL_PARAM_ASI = 23,
862
95c6e9cb
IM		 863 /* Stream Control */
864
865 /* Select stream with the given ID */
866 CONTROL_PARAM_STREAM_ID = 24,
867 /* Source connection point for the selected stream */
868 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
869 /* Destination connection point for the selected stream */
870 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
871 /* Number of audio channels in the selected stream */
872 CONTROL_PARAM_STREAMS_CHANNELS = 27,
873 /*Enable control for the selected stream */
874 CONTROL_PARAM_STREAM_CONTROL = 28,
875
876 /* Connection Point Control */
877
878 /* Select connection point with the given ID */
879 CONTROL_PARAM_CONN_POINT_ID = 29,
880 /* Connection point sample rate */
881 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
882
883 /* Node Control */
884
885 /* Select HDA node with the given ID */
886 CONTROL_PARAM_NODE_ID = 31
887};
888
889/*
890 * Dsp Io Status codes
891 */
892enum hda_vendor_status_dspio {
893 /* Success */
894 VENDOR_STATUS_DSPIO_OK = 0x00,
895 /* Busy, unable to accept new command, the host must retry */
896 VENDOR_STATUS_DSPIO_BUSY = 0x01,
897 /* SCP command queue is full */
898 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
899 /* SCP response queue is empty */
900 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
901};
902
903/*
904 * Chip Io Status codes
905 */
906enum hda_vendor_status_chipio {
907 /* Success */
908 VENDOR_STATUS_CHIPIO_OK = 0x00,
909 /* Busy, unable to accept new command, the host must retry */
910 VENDOR_STATUS_CHIPIO_BUSY = 0x01
911};
912
913/*
914 * CA0132 sample rate
915 */
916enum ca0132_sample_rate {
917 SR_6_000 = 0x00,
918 SR_8_000 = 0x01,
919 SR_9_600 = 0x02,
920 SR_11_025 = 0x03,
921 SR_16_000 = 0x04,
922 SR_22_050 = 0x05,
923 SR_24_000 = 0x06,
924 SR_32_000 = 0x07,
925 SR_44_100 = 0x08,
926 SR_48_000 = 0x09,
927 SR_88_200 = 0x0A,
928 SR_96_000 = 0x0B,
929 SR_144_000 = 0x0C,
930 SR_176_400 = 0x0D,
931 SR_192_000 = 0x0E,
932 SR_384_000 = 0x0F,
933
934 SR_COUNT = 0x10,
935
936 SR_RATE_UNKNOWN = 0x1F
937};
938
01ef7dbf
IM		 939enum dsp_download_state {
940 DSP_DOWNLOAD_FAILED = -1,
941 DSP_DOWNLOAD_INIT = 0,
942 DSP_DOWNLOADING = 1,
943 DSP_DOWNLOADED = 2
944};
945
01ef7dbf
IM		 946/* retrieve parameters from hda format */
947#define get_hdafmt_chs(fmt) (fmt & 0xf)
948#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
949#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
950#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
951
952/*
953 * CA0132 specific
954 */
955
956struct ca0132_spec {
b0eaa072 957 const struct snd_kcontrol_new *mixers[5];
a7e76271 958 unsigned int num_mixers;
5aaca44d
IM		 959 const struct hda_verb *base_init_verbs;
960 const struct hda_verb *base_exit_verbs;
d5c016b5 961 const struct hda_verb *chip_init_verbs;
e42c7c73 962 const struct hda_verb *desktop_init_verbs;
d5c016b5 963 struct hda_verb *spec_init_verbs;
01ef7dbf 964 struct auto_pin_cfg autocfg;
5aaca44d
IM		 965
966 /* Nodes configurations */
01ef7dbf
IM		 967 struct hda_multi_out multiout;
968 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
969 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
5aaca44d 970 unsigned int num_outputs;
01ef7dbf
IM		 971 hda_nid_t input_pins[AUTO_PIN_LAST];
972 hda_nid_t adcs[AUTO_PIN_LAST];
973 hda_nid_t dig_out;
974 hda_nid_t dig_in;
975 unsigned int num_inputs;
a7e76271
IM		 976 hda_nid_t shared_mic_nid;
977 hda_nid_t shared_out_nid;
d5c016b5 978 hda_nid_t unsol_tag_hp;
63177afc 979 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
d5c016b5 980 hda_nid_t unsol_tag_amic1;
01ef7dbf
IM		 981
982 /* chip access */
983 struct mutex chipio_mutex; /* chip access mutex */
984 u32 curr_chip_addx;
985
986 /* DSP download related */
987 enum dsp_download_state dsp_state;
988 unsigned int dsp_stream_id;
989 unsigned int wait_scp;
990 unsigned int wait_scp_header;
991 unsigned int wait_num_data;
992 unsigned int scp_resp_header;
993 unsigned int scp_resp_data[4];
994 unsigned int scp_resp_count;
38ba69ff 995 bool startup_check_entered;
e93ac30a 996 bool dsp_reload;
5aaca44d
IM		 997
998 /* mixer and effects related */
999 unsigned char dmic_ctl;
1000 int cur_out_type;
1001 int cur_mic_type;
1002 long vnode_lvol[VNODES_COUNT];
1003 long vnode_rvol[VNODES_COUNT];
1004 long vnode_lswitch[VNODES_COUNT];
1005 long vnode_rswitch[VNODES_COUNT];
1006 long effects_switch[EFFECTS_COUNT];
1007 long voicefx_val;
1008 long cur_mic_boost;
7cb9d94c
CM		 1009 /* ca0132_alt control related values */
1010 unsigned char in_enum_val;
1011 unsigned char out_enum_val;
47cdf76e
CM		 1012 unsigned char mic_boost_enum_val;
1013 unsigned char smart_volume_setting;
1014 long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
1015 long xbass_xover_freq;
1016 long eq_preset_val;
1017 unsigned int tlv[4];
1018 struct hda_vmaster_mute_hook vmaster_mute;
212de2e7
CM		 1019 /* AE-5 Control values */
1020 unsigned char ae5_headphone_gain_val;
1021 unsigned char ae5_filter_val;
d51434d4
CM		 1022 /* ZxR Control Values */
1023 unsigned char zxr_gain_set;
44f0c978 1024
993884f6
CCC		 1025 struct hda_codec *codec;
1026 struct delayed_work unsol_hp_work;
d5c016b5 1027 int quirk;
993884f6 1028
44f0c978
IM		 1029#ifdef ENABLE_TUNING_CONTROLS
1030 long cur_ctl_vals[TUNING_CTLS_COUNT];
1031#endif
aa31704f 1032 /*
08eca6b1
CM		 1033 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
1034 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
1035 * things.
aa31704f 1036 */
08eca6b1 1037 bool use_pci_mmio;
aa31704f 1038 void __iomem *mem_base;
009b8f97
CM		 1039
1040 /*
1041 * Whether or not to use the alt functions like alt_select_out,
1042 * alt_select_in, etc. Only used on desktop codecs for now, because of
1043 * surround sound support.
1044 */
1045 bool use_alt_functions;
47cdf76e
CM		 1046
1047 /*
1048 * Whether or not to use alt controls: volume effect sliders, EQ
1049 * presets, smart volume presets, and new control names with FX prefix.
1050 * Renames PlayEnhancement and CrystalVoice too.
1051 */
1052 bool use_alt_controls;
01ef7dbf
IM		 1053};
1054
d5c016b5
GM		 1055/*
1056 * CA0132 quirks table
1057 */
1058enum {
1059 QUIRK_NONE,
1060 QUIRK_ALIENWARE,
a57a46b9 1061 QUIRK_ALIENWARE_M17XR4,
8a19bcee 1062 QUIRK_SBZ,
b29733db
CM		 1063 QUIRK_ZXR,
1064 QUIRK_ZXR_DBPRO,
8a19bcee 1065 QUIRK_R3DI,
8f8c523c 1066 QUIRK_R3D,
f6276463 1067 QUIRK_AE5,
d5c016b5
GM		 1068};
1069
6da8f446
TI		 1070#ifdef CONFIG_PCI
1071#define ca0132_quirk(spec) ((spec)->quirk)
1072#define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio)
1073#define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions)
1074#define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls)
1075#else
1076#define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; })
1077#define ca0132_use_alt_functions(spec) ({ (void)(spec); false; })
1078#define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; })
1079#define ca0132_use_alt_controls(spec) ({ (void)(spec); false; })
1080#endif
1081
fe14f39e
TI		 1082static const struct hda_pintbl alienware_pincfgs[] = {
1083 { 0x0b, 0x90170110 }, /* Builtin Speaker */
1084 { 0x0c, 0x411111f0 }, /* N/A */
1085 { 0x0d, 0x411111f0 }, /* N/A */
1086 { 0x0e, 0x411111f0 }, /* N/A */
1087 { 0x0f, 0x0321101f }, /* HP */
1088 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
1089 { 0x11, 0x03a11021 }, /* Mic */
1090 { 0x12, 0xd5a30140 }, /* Builtin Mic */
1091 { 0x13, 0x411111f0 }, /* N/A */
1092 { 0x18, 0x411111f0 }, /* N/A */
1093 {}
1094};
1095
63177afc
CM		 1096/* Sound Blaster Z pin configs taken from Windows Driver */
1097static const struct hda_pintbl sbz_pincfgs[] = {
1098 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1099 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1100 { 0x0d, 0x014510f0 }, /* Digital Out */
1101 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1102 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1103 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1104 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1105 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1106 { 0x13, 0x908700f0 }, /* What U Hear In*/
1107 { 0x18, 0x50d000f0 }, /* N/A */
1108 {}
1109};
1110
6dcd7244
CM		 1111/* Sound Blaster ZxR pin configs taken from Windows Driver */
1112static const struct hda_pintbl zxr_pincfgs[] = {
1113 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */
1114 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/
1115 { 0x0d, 0x014510f0 }, /* Digital Out */
1116 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/
1117 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */
1118 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */
1119 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */
1120 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */
1121 { 0x13, 0x908700f0 }, /* What U Hear In*/
1122 { 0x18, 0x50d000f0 }, /* N/A */
1123 {}
1124};
1125
7f73df95
CM		 1126/* Recon3D pin configs taken from Windows Driver */
1127static const struct hda_pintbl r3d_pincfgs[] = {
1128 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1129 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1130 { 0x0d, 0x014510f0 }, /* Digital Out */
1131 { 0x0e, 0x01c520f0 }, /* SPDIF In */
1132 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1133 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1134 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1135 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1136 { 0x13, 0x908700f0 }, /* What U Hear In*/
1137 { 0x18, 0x50d000f0 }, /* N/A */
1138 {}
1139};
1140
d06feaf0
CM		 1141/* Sound Blaster AE-5 pin configs taken from Windows Driver */
1142static const struct hda_pintbl ae5_pincfgs[] = {
1143 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1144 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1145 { 0x0d, 0x014510f0 }, /* Digital Out */
1146 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1147 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1148 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1149 { 0x11, 0x01a170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1150 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1151 { 0x13, 0x908700f0 }, /* What U Hear In*/
1152 { 0x18, 0x50d000f0 }, /* N/A */
1153 {}
1154};
1155
63177afc
CM		 1156/* Recon3D integrated pin configs taken from Windows Driver */
1157static const struct hda_pintbl r3di_pincfgs[] = {
1158 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1159 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1160 { 0x0d, 0x014510f0 }, /* Digital Out */
1161 { 0x0e, 0x41c520f0 }, /* SPDIF In */
1162 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1163 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1164 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1165 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1166 { 0x13, 0x908700f0 }, /* What U Hear In*/
1167 { 0x18, 0x500000f0 }, /* N/A */
1168 {}
1169};
1170
d5c016b5 1171static const struct snd_pci_quirk ca0132_quirks[] = {
a57a46b9 1172 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
5328e1ea
GM		 1173 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1174 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
b5337cfe 1175 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
8a19bcee
CM		 1176 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1177 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
2ca371d8 1178 SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ),
cce99729 1179 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ),
8a19bcee 1180 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
dad59262 1181 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
c5a59d24 1182 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
8f8c523c 1183 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
f6276463 1184 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
d5c016b5
GM		 1185 {}
1186};
1187
01ef7dbf
IM		 1188/*
1189 * CA0132 codec access
1190 */
399ae725 1191static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
01ef7dbf
IM		 1192 unsigned int verb, unsigned int parm, unsigned int *res)
1193{
1194 unsigned int response;
1195 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1196 *res = response;
1197
1198 return ((response == -1) ? -1 : 0);
1199}
1200
1201static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1202 unsigned short converter_format, unsigned int *res)
1203{
1204 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1205 converter_format & 0xffff, res);
1206}
1207
1208static int codec_set_converter_stream_channel(struct hda_codec *codec,
1209 hda_nid_t nid, unsigned char stream,
1210 unsigned char channel, unsigned int *res)
1211{
1212 unsigned char converter_stream_channel = 0;
1213
1214 converter_stream_channel = (stream << 4) | (channel & 0x0f);
1215 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1216 converter_stream_channel, res);
1217}
1218
1219/* Chip access helper function */
1220static int chipio_send(struct hda_codec *codec,
1221 unsigned int reg,
1222 unsigned int data)
1223{
1224 unsigned int res;
6d67530e 1225 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1226
1227 /* send bits of data specified by reg */
1228 do {
1229 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1230 reg, data);
1231 if (res == VENDOR_STATUS_CHIPIO_OK)
1232 return 0;
6d67530e
IM		 1233 msleep(20);
1234 } while (time_before(jiffies, timeout));
1235
01ef7dbf
IM		 1236 return -EIO;
1237}
1238
1239/*
1240 * Write chip address through the vendor widget -- NOT protected by the Mutex!
1241 */
1242static int chipio_write_address(struct hda_codec *codec,
1243 unsigned int chip_addx)
1244{
4861af80 1245 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1246 int res;
1247
4861af80
IM		 1248 if (spec->curr_chip_addx == chip_addx)
1249 return 0;
1250
01ef7dbf
IM		 1251 /* send low 16 bits of the address */
1252 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1253 chip_addx & 0xffff);
1254
1255 if (res != -EIO) {
1256 /* send high 16 bits of the address */
1257 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1258 chip_addx >> 16);
1259 }
1260
d1600401 1261 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
01ef7dbf 1262
4861af80 1263 return res;
01ef7dbf
IM		 1264}
1265
1266/*
1267 * Write data through the vendor widget -- NOT protected by the Mutex!
1268 */
01ef7dbf
IM		 1269static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1270{
5aaca44d 1271 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1272 int res;
1273
1274 /* send low 16 bits of the data */
1275 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1276
1277 if (res != -EIO) {
1278 /* send high 16 bits of the data */
1279 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1280 data >> 16);
1281 }
1282
5aaca44d
IM		 1283 /*If no error encountered, automatically increment the address
1284 as per chip behaviour*/
1285 spec->curr_chip_addx = (res != -EIO) ?
d1600401 1286 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 1287 return res;
1288}
1289
d5c21b88
IM		 1290/*
1291 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1292 */
01ef7dbf
IM		 1293static int chipio_write_data_multiple(struct hda_codec *codec,
1294 const u32 *data,
1295 unsigned int count)
1296{
1297 int status = 0;
1298
1299 if (data == NULL) {
4e76a883 1300 codec_dbg(codec, "chipio_write_data null ptr\n");
01ef7dbf
IM		 1301 return -EINVAL;
1302 }
1303
1304 while ((count-- != 0) && (status == 0))
1305 status = chipio_write_data(codec, *data++);
1306
1307 return status;
1308}
1309
1310
1311/*
1312 * Read data through the vendor widget -- NOT protected by the Mutex!
1313 */
1314static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1315{
5aaca44d 1316 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1317 int res;
1318
1319 /* post read */
1320 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1321
1322 if (res != -EIO) {
1323 /* read status */
1324 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1325 }
1326
1327 if (res != -EIO) {
1328 /* read data */
1329 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1330 VENDOR_CHIPIO_HIC_READ_DATA,
1331 0);
1332 }
1333
5aaca44d
IM		 1334 /*If no error encountered, automatically increment the address
1335 as per chip behaviour*/
1336 spec->curr_chip_addx = (res != -EIO) ?
d1600401 1337 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 1338 return res;
1339}
1340
1341/*
1342 * Write given value to the given address through the chip I/O widget.
1343 * protected by the Mutex
1344 */
1345static int chipio_write(struct hda_codec *codec,
1346 unsigned int chip_addx, const unsigned int data)
1347{
1348 struct ca0132_spec *spec = codec->spec;
1349 int err;
1350
1351 mutex_lock(&spec->chipio_mutex);
1352
1353 /* write the address, and if successful proceed to write data */
1354 err = chipio_write_address(codec, chip_addx);
1355 if (err < 0)
1356 goto exit;
1357
1358 err = chipio_write_data(codec, data);
1359 if (err < 0)
1360 goto exit;
1361
1362exit:
1363 mutex_unlock(&spec->chipio_mutex);
1364 return err;
1365}
1366
38ba69ff
CM		 1367/*
1368 * Write given value to the given address through the chip I/O widget.
1369 * not protected by the Mutex
1370 */
1371static int chipio_write_no_mutex(struct hda_codec *codec,
1372 unsigned int chip_addx, const unsigned int data)
1373{
1374 int err;
1375
1376
1377 /* write the address, and if successful proceed to write data */
1378 err = chipio_write_address(codec, chip_addx);
1379 if (err < 0)
1380 goto exit;
1381
1382 err = chipio_write_data(codec, data);
1383 if (err < 0)
1384 goto exit;
1385
1386exit:
1387 return err;
1388}
1389
d5c21b88
IM		 1390/*
1391 * Write multiple values to the given address through the chip I/O widget.
1392 * protected by the Mutex
1393 */
01ef7dbf
IM		 1394static int chipio_write_multiple(struct hda_codec *codec,
1395 u32 chip_addx,
1396 const u32 *data,
1397 unsigned int count)
1398{
1399 struct ca0132_spec *spec = codec->spec;
1400 int status;
1401
1402 mutex_lock(&spec->chipio_mutex);
4861af80 1403 status = chipio_write_address(codec, chip_addx);
01ef7dbf
IM		 1404 if (status < 0)
1405 goto error;
1406
1407 status = chipio_write_data_multiple(codec, data, count);
1408error:
1409 mutex_unlock(&spec->chipio_mutex);
1410
1411 return status;
1412}
1413
1414/*
1415 * Read the given address through the chip I/O widget
1416 * protected by the Mutex
1417 */
1418static int chipio_read(struct hda_codec *codec,
1419 unsigned int chip_addx, unsigned int *data)
1420{
1421 struct ca0132_spec *spec = codec->spec;
1422 int err;
1423
1424 mutex_lock(&spec->chipio_mutex);
1425
1426 /* write the address, and if successful proceed to write data */
1427 err = chipio_write_address(codec, chip_addx);
1428 if (err < 0)
1429 goto exit;
1430
1431 err = chipio_read_data(codec, data);
1432 if (err < 0)
1433 goto exit;
1434
1435exit:
1436 mutex_unlock(&spec->chipio_mutex);
1437 return err;
1438}
1439
d5c21b88
IM		 1440/*
1441 * Set chip control flags through the chip I/O widget.
1442 */
01ef7dbf
IM		 1443static void chipio_set_control_flag(struct hda_codec *codec,
1444 enum control_flag_id flag_id,
1445 bool flag_state)
1446{
1447 unsigned int val;
1448 unsigned int flag_bit;
1449
1450 flag_bit = (flag_state ? 1 : 0);
1451 val = (flag_bit << 7) | (flag_id);
1452 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1453 VENDOR_CHIPIO_FLAG_SET, val);
1454}
1455
d5c21b88
IM		 1456/*
1457 * Set chip parameters through the chip I/O widget.
1458 */
01ef7dbf
IM		 1459static void chipio_set_control_param(struct hda_codec *codec,
1460 enum control_param_id param_id, int param_val)
1461{
1462 struct ca0132_spec *spec = codec->spec;
1463 int val;
1464
1465 if ((param_id < 32) && (param_val < 8)) {
1466 val = (param_val << 5) | (param_id);
1467 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1468 VENDOR_CHIPIO_PARAM_SET, val);
1469 } else {
1470 mutex_lock(&spec->chipio_mutex);
1471 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1472 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1473 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1474 param_id);
1475 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1476 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1477 param_val);
1478 }
1479 mutex_unlock(&spec->chipio_mutex);
1480 }
1481}
1482
009b8f97
CM		 1483/*
1484 * Set chip parameters through the chip I/O widget. NO MUTEX.
1485 */
1486static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1487 enum control_param_id param_id, int param_val)
1488{
1489 int val;
1490
1491 if ((param_id < 32) && (param_val < 8)) {
1492 val = (param_val << 5) | (param_id);
1493 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1494 VENDOR_CHIPIO_PARAM_SET, val);
1495 } else {
1496 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1497 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1498 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1499 param_id);
1500 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1501 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1502 param_val);
1503 }
1504 }
1505}
38ba69ff
CM		 1506/*
1507 * Connect stream to a source point, and then connect
1508 * that source point to a destination point.
1509 */
1510static void chipio_set_stream_source_dest(struct hda_codec *codec,
1511 int streamid, int source_point, int dest_point)
1512{
1513 chipio_set_control_param_no_mutex(codec,
1514 CONTROL_PARAM_STREAM_ID, streamid);
1515 chipio_set_control_param_no_mutex(codec,
1516 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1517 chipio_set_control_param_no_mutex(codec,
1518 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1519}
1520
1521/*
1522 * Set number of channels in the selected stream.
1523 */
1524static void chipio_set_stream_channels(struct hda_codec *codec,
1525 int streamid, unsigned int channels)
1526{
1527 chipio_set_control_param_no_mutex(codec,
1528 CONTROL_PARAM_STREAM_ID, streamid);
1529 chipio_set_control_param_no_mutex(codec,
1530 CONTROL_PARAM_STREAMS_CHANNELS, channels);
1531}
009b8f97
CM		 1532
1533/*
1534 * Enable/Disable audio stream.
1535 */
1536static void chipio_set_stream_control(struct hda_codec *codec,
1537 int streamid, int enable)
1538{
1539 chipio_set_control_param_no_mutex(codec,
1540 CONTROL_PARAM_STREAM_ID, streamid);
1541 chipio_set_control_param_no_mutex(codec,
1542 CONTROL_PARAM_STREAM_CONTROL, enable);
1543}
1544
38ba69ff
CM		 1545
1546/*
1547 * Set sampling rate of the connection point. NO MUTEX.
1548 */
1549static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1550 int connid, enum ca0132_sample_rate rate)
1551{
1552 chipio_set_control_param_no_mutex(codec,
1553 CONTROL_PARAM_CONN_POINT_ID, connid);
1554 chipio_set_control_param_no_mutex(codec,
1555 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1556}
1557
d5c21b88
IM		 1558/*
1559 * Set sampling rate of the connection point.
1560 */
01ef7dbf
IM		 1561static void chipio_set_conn_rate(struct hda_codec *codec,
1562 int connid, enum ca0132_sample_rate rate)
1563{
1564 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1565 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1566 rate);
1567}
1568
b9b41345
CM		 1569/*
1570 * Writes to the 8051's internal address space directly instead of indirectly,
1571 * giving access to the special function registers located at addresses
1572 * 0x80-0xFF.
1573 */
1574static void chipio_8051_write_direct(struct hda_codec *codec,
1575 unsigned int addr, unsigned int data)
1576{
1577 unsigned int verb;
1578
1579 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data;
1580 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1581}
1582
d5c21b88
IM		 1583/*
1584 * Enable clocks.
1585 */
01ef7dbf
IM		 1586static void chipio_enable_clocks(struct hda_codec *codec)
1587{
1588 struct ca0132_spec *spec = codec->spec;
1589
1590 mutex_lock(&spec->chipio_mutex);
1591 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1592 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1593 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1594 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1595 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1596 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1597 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1598 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1599 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1600 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1601 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1602 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1603 mutex_unlock(&spec->chipio_mutex);
1604}
1605
1606/*
1607 * CA0132 DSP IO stuffs
1608 */
1609static int dspio_send(struct hda_codec *codec, unsigned int reg,
1610 unsigned int data)
1611{
b645d796 1612 int res;
6d67530e 1613 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1614
1615 /* send bits of data specified by reg to dsp */
1616 do {
1617 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1618 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1619 return res;
6d67530e
IM		 1620 msleep(20);
1621 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1622
1623 return -EIO;
1624}
1625
d5c21b88
IM		 1626/*
1627 * Wait for DSP to be ready for commands
1628 */
01ef7dbf
IM		 1629static void dspio_write_wait(struct hda_codec *codec)
1630{
4861af80
IM		 1631 int status;
1632 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1633
01ef7dbf 1634 do {
4861af80
IM		 1635 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1636 VENDOR_DSPIO_STATUS, 0);
1637 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1638 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1639 break;
1640 msleep(1);
1641 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1642}
1643
d5c21b88
IM		 1644/*
1645 * Write SCP data to DSP
1646 */
01ef7dbf
IM		 1647static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1648{
1649 struct ca0132_spec *spec = codec->spec;
1650 int status;
1651
1652 dspio_write_wait(codec);
1653
1654 mutex_lock(&spec->chipio_mutex);
1655 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1656 scp_data & 0xffff);
1657 if (status < 0)
1658 goto error;
1659
1660 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1661 scp_data >> 16);
1662 if (status < 0)
1663 goto error;
1664
1665 /* OK, now check if the write itself has executed*/
1666 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1667 VENDOR_DSPIO_STATUS, 0);
1668error:
1669 mutex_unlock(&spec->chipio_mutex);
1670
1671 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1672 -EIO : 0;
1673}
1674
d5c21b88
IM		 1675/*
1676 * Write multiple SCP data to DSP
1677 */
01ef7dbf
IM		 1678static int dspio_write_multiple(struct hda_codec *codec,
1679 unsigned int *buffer, unsigned int size)
1680{
1681 int status = 0;
1682 unsigned int count;
1683
a16fbb85 1684 if (buffer == NULL)
01ef7dbf
IM		 1685 return -EINVAL;
1686
1687 count = 0;
1688 while (count < size) {
1689 status = dspio_write(codec, *buffer++);
1690 if (status != 0)
1691 break;
1692 count++;
1693 }
1694
1695 return status;
1696}
1697
a73d511c
IM		 1698static int dspio_read(struct hda_codec *codec, unsigned int *data)
1699{
1700 int status;
1701
1702 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1703 if (status == -EIO)
1704 return status;
1705
1706 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1707 if (status == -EIO ||
1708 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1709 return -EIO;
1710
1711 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1712 VENDOR_DSPIO_SCP_READ_DATA, 0);
1713
1714 return 0;
1715}
1716
1717static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1718 unsigned int *buf_size, unsigned int size_count)
1719{
1720 int status = 0;
1721 unsigned int size = *buf_size;
1722 unsigned int count;
1723 unsigned int skip_count;
1724 unsigned int dummy;
1725
a16fbb85 1726 if (buffer == NULL)
a73d511c
IM		 1727 return -1;
1728
1729 count = 0;
1730 while (count < size && count < size_count) {
1731 status = dspio_read(codec, buffer++);
1732 if (status != 0)
1733 break;
1734 count++;
1735 }
1736
1737 skip_count = count;
1738 if (status == 0) {
1739 while (skip_count < size) {
1740 status = dspio_read(codec, &dummy);
1741 if (status != 0)
1742 break;
1743 skip_count++;
1744 }
1745 }
1746 *buf_size = count;
1747
1748 return status;
1749}
1750
d5c21b88
IM		 1751/*
1752 * Construct the SCP header using corresponding fields
1753 */
01ef7dbf
IM		 1754static inline unsigned int
1755make_scp_header(unsigned int target_id, unsigned int source_id,
1756 unsigned int get_flag, unsigned int req,
1757 unsigned int device_flag, unsigned int resp_flag,
1758 unsigned int error_flag, unsigned int data_size)
1759{
1760 unsigned int header = 0;
1761
1762 header = (data_size & 0x1f) << 27;
1763 header |= (error_flag & 0x01) << 26;
1764 header |= (resp_flag & 0x01) << 25;
1765 header |= (device_flag & 0x01) << 24;
1766 header |= (req & 0x7f) << 17;
1767 header |= (get_flag & 0x01) << 16;
1768 header |= (source_id & 0xff) << 8;
1769 header |= target_id & 0xff;
1770
1771 return header;
1772}
1773
d5c21b88
IM		 1774/*
1775 * Extract corresponding fields from SCP header
1776 */
01ef7dbf
IM		 1777static inline void
1778extract_scp_header(unsigned int header,
1779 unsigned int *target_id, unsigned int *source_id,
1780 unsigned int *get_flag, unsigned int *req,
1781 unsigned int *device_flag, unsigned int *resp_flag,
1782 unsigned int *error_flag, unsigned int *data_size)
1783{
1784 if (data_size)
1785 *data_size = (header >> 27) & 0x1f;
1786 if (error_flag)
1787 *error_flag = (header >> 26) & 0x01;
1788 if (resp_flag)
1789 *resp_flag = (header >> 25) & 0x01;
1790 if (device_flag)
1791 *device_flag = (header >> 24) & 0x01;
1792 if (req)
1793 *req = (header >> 17) & 0x7f;
1794 if (get_flag)
1795 *get_flag = (header >> 16) & 0x01;
1796 if (source_id)
1797 *source_id = (header >> 8) & 0xff;
1798 if (target_id)
1799 *target_id = header & 0xff;
1800}
1801
1802#define SCP_MAX_DATA_WORDS (16)
1803
1804/* Structure to contain any SCP message */
1805struct scp_msg {
1806 unsigned int hdr;
1807 unsigned int data[SCP_MAX_DATA_WORDS];
1808};
1809
a73d511c
IM		 1810static void dspio_clear_response_queue(struct hda_codec *codec)
1811{
1812 unsigned int dummy = 0;
1813 int status = -1;
1814
1815 /* clear all from the response queue */
1816 do {
1817 status = dspio_read(codec, &dummy);
1818 } while (status == 0);
1819}
1820
1821static int dspio_get_response_data(struct hda_codec *codec)
1822{
1823 struct ca0132_spec *spec = codec->spec;
1824 unsigned int data = 0;
1825 unsigned int count;
1826
1827 if (dspio_read(codec, &data) < 0)
1828 return -EIO;
1829
1830 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1831 spec->scp_resp_header = data;
1832 spec->scp_resp_count = data >> 27;
1833 count = spec->wait_num_data;
1834 dspio_read_multiple(codec, spec->scp_resp_data,
1835 &spec->scp_resp_count, count);
1836 return 0;
1837 }
1838
1839 return -EIO;
1840}
1841
d5c21b88
IM		 1842/*
1843 * Send SCP message to DSP
1844 */
01ef7dbf
IM		 1845static int dspio_send_scp_message(struct hda_codec *codec,
1846 unsigned char *send_buf,
1847 unsigned int send_buf_size,
1848 unsigned char *return_buf,
1849 unsigned int return_buf_size,
1850 unsigned int *bytes_returned)
1851{
1852 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1853 int status = -1;
1854 unsigned int scp_send_size = 0;
1855 unsigned int total_size;
1856 bool waiting_for_resp = false;
1857 unsigned int header;
1858 struct scp_msg *ret_msg;
1859 unsigned int resp_src_id, resp_target_id;
1860 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1861
1862 if (bytes_returned)
1863 *bytes_returned = 0;
1864
1865 /* get scp header from buffer */
1866 header = *((unsigned int *)send_buf);
1867 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1868 &device_flag, NULL, NULL, &data_size);
1869 scp_send_size = data_size + 1;
1870 total_size = (scp_send_size * 4);
1871
1872 if (send_buf_size < total_size)
1873 return -EINVAL;
1874
1875 if (get_flag || device_flag) {
1876 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1877 return -EINVAL;
1878
1879 spec->wait_scp_header = *((unsigned int *)send_buf);
1880
1881 /* swap source id with target id */
1882 resp_target_id = src_id;
1883 resp_src_id = target_id;
1884 spec->wait_scp_header &= 0xffff0000;
1885 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1886 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1887 spec->wait_scp = 1;
1888 waiting_for_resp = true;
1889 }
1890
1891 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1892 scp_send_size);
1893 if (status < 0) {
1894 spec->wait_scp = 0;
1895 return status;
1896 }
1897
1898 if (waiting_for_resp) {
6d67530e 1899 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1900 memset(return_buf, 0, return_buf_size);
01ef7dbf
IM		 1901 do {
1902 msleep(20);
6d67530e 1903 } while (spec->wait_scp && time_before(jiffies, timeout));
01ef7dbf 1904 waiting_for_resp = false;
6d67530e 1905 if (!spec->wait_scp) {
01ef7dbf
IM		 1906 ret_msg = (struct scp_msg *)return_buf;
1907 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1908 memcpy(&ret_msg->data, spec->scp_resp_data,
1909 spec->wait_num_data);
1910 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1911 status = 0;
1912 } else {
1913 status = -EIO;
1914 }
1915 spec->wait_scp = 0;
1916 }
1917
1918 return status;
1919}
1920
d5c21b88
IM		 1921/**
1922 * Prepare and send the SCP message to DSP
1923 * @codec: the HDA codec
1924 * @mod_id: ID of the DSP module to send the command
1925 * @req: ID of request to send to the DSP module
1926 * @dir: SET or GET
1927 * @data: pointer to the data to send with the request, request specific
1928 * @len: length of the data, in bytes
1929 * @reply: point to the buffer to hold data returned for a reply
1930 * @reply_len: length of the reply buffer returned from GET
1931 *
1932 * Returns zero or a negative error code.
1933 */
01ef7dbf 1934static int dspio_scp(struct hda_codec *codec,
447fd8e9
CM		 1935 int mod_id, int src_id, int req, int dir, const void *data,
1936 unsigned int len, void *reply, unsigned int *reply_len)
01ef7dbf
IM		 1937{
1938 int status = 0;
1939 struct scp_msg scp_send, scp_reply;
1940 unsigned int ret_bytes, send_size, ret_size;
1941 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1942 unsigned int reply_data_size;
1943
1944 memset(&scp_send, 0, sizeof(scp_send));
1945 memset(&scp_reply, 0, sizeof(scp_reply));
1946
1947 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1948 return -EINVAL;
1949
1950 if (dir == SCP_GET && reply == NULL) {
4e76a883 1951 codec_dbg(codec, "dspio_scp get but has no buffer\n");
01ef7dbf
IM		 1952 return -EINVAL;
1953 }
1954
1955 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
4e76a883 1956 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
01ef7dbf
IM		 1957 return -EINVAL;
1958 }
1959
447fd8e9 1960 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
01ef7dbf
IM		 1961 0, 0, 0, len/sizeof(unsigned int));
1962 if (data != NULL && len > 0) {
1963 len = min((unsigned int)(sizeof(scp_send.data)), len);
1964 memcpy(scp_send.data, data, len);
1965 }
1966
1967 ret_bytes = 0;
1968 send_size = sizeof(unsigned int) + len;
1969 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1970 send_size, (unsigned char *)&scp_reply,
1971 sizeof(scp_reply), &ret_bytes);
1972
1973 if (status < 0) {
4e76a883 1974 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
01ef7dbf
IM		 1975 return status;
1976 }
1977
1978 /* extract send and reply headers members */
1979 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1980 NULL, NULL, NULL, NULL, NULL);
1981 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1982 &reply_resp_flag, &reply_error_flag,
1983 &reply_data_size);
1984
1985 if (!send_get_flag)
1986 return 0;
1987
1988 if (reply_resp_flag && !reply_error_flag) {
1989 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1990 / sizeof(unsigned int);
1991
1992 if (*reply_len < ret_size*sizeof(unsigned int)) {
4e76a883 1993 codec_dbg(codec, "reply too long for buf\n");
01ef7dbf
IM		 1994 return -EINVAL;
1995 } else if (ret_size != reply_data_size) {
4e76a883 1996 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
01ef7dbf 1997 return -EINVAL;
46a049da
AB		 1998 } else if (!reply) {
1999 codec_dbg(codec, "NULL reply\n");
2000 return -EINVAL;
01ef7dbf
IM		 2001 } else {
2002 *reply_len = ret_size*sizeof(unsigned int);
2003 memcpy(reply, scp_reply.data, *reply_len);
2004 }
2005 } else {
4e76a883 2006 codec_dbg(codec, "reply ill-formed or errflag set\n");
01ef7dbf
IM		 2007 return -EIO;
2008 }
2009
2010 return status;
2011}
2012
5aaca44d
IM		 2013/*
2014 * Set DSP parameters
2015 */
2016static int dspio_set_param(struct hda_codec *codec, int mod_id,
447fd8e9 2017 int src_id, int req, const void *data, unsigned int len)
5aaca44d 2018{
447fd8e9
CM		 2019 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
2020 NULL);
5aaca44d
IM		 2021}
2022
2023static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
447fd8e9 2024 int req, const unsigned int data)
5aaca44d 2025{
447fd8e9
CM		 2026 return dspio_set_param(codec, mod_id, 0x20, req, &data,
2027 sizeof(unsigned int));
2028}
2029
2030static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
2031 int req, const unsigned int data)
2032{
2033 return dspio_set_param(codec, mod_id, 0x00, req, &data,
2034 sizeof(unsigned int));
5aaca44d
IM		 2035}
2036
d5c21b88
IM		 2037/*
2038 * Allocate a DSP DMA channel via an SCP message
2039 */
01ef7dbf
IM		 2040static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
2041{
2042 int status = 0;
2043 unsigned int size = sizeof(dma_chan);
2044
4e76a883 2045 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
447fd8e9
CM		 2046 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2047 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
2048 dma_chan, &size);
01ef7dbf
IM		 2049
2050 if (status < 0) {
4e76a883 2051 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
01ef7dbf
IM		 2052 return status;
2053 }
2054
2055 if ((*dma_chan + 1) == 0) {
4e76a883 2056 codec_dbg(codec, "no free dma channels to allocate\n");
01ef7dbf
IM		 2057 return -EBUSY;
2058 }
2059
4e76a883
TI		 2060 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
2061 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
01ef7dbf
IM		 2062
2063 return status;
2064}
2065
d5c21b88
IM		 2066/*
2067 * Free a DSP DMA via an SCP message
2068 */
01ef7dbf
IM		 2069static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
2070{
2071 int status = 0;
2072 unsigned int dummy = 0;
2073
4e76a883
TI		 2074 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
2075 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
01ef7dbf 2076
447fd8e9
CM		 2077 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2078 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
2079 sizeof(dma_chan), NULL, &dummy);
01ef7dbf
IM		 2080
2081 if (status < 0) {
4e76a883 2082 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
01ef7dbf
IM		 2083 return status;
2084 }
2085
4e76a883 2086 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
01ef7dbf
IM		 2087
2088 return status;
2089}
2090
2091/*
d5c21b88 2092 * (Re)start the DSP
01ef7dbf
IM		 2093 */
2094static int dsp_set_run_state(struct hda_codec *codec)
2095{
2096 unsigned int dbg_ctrl_reg;
2097 unsigned int halt_state;
2098 int err;
2099
2100 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
2101 if (err < 0)
2102 return err;
2103
2104 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
2105 DSP_DBGCNTL_STATE_LOBIT;
2106
2107 if (halt_state != 0) {
2108 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
2109 DSP_DBGCNTL_SS_MASK);
2110 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2111 dbg_ctrl_reg);
2112 if (err < 0)
2113 return err;
2114
2115 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
2116 DSP_DBGCNTL_EXEC_MASK;
2117 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2118 dbg_ctrl_reg);
2119 if (err < 0)
2120 return err;
2121 }
2122
2123 return 0;
2124}
2125
d5c21b88
IM		 2126/*
2127 * Reset the DSP
2128 */
01ef7dbf
IM		 2129static int dsp_reset(struct hda_codec *codec)
2130{
2131 unsigned int res;
2132 int retry = 20;
2133
4e76a883 2134 codec_dbg(codec, "dsp_reset\n");
01ef7dbf
IM		 2135 do {
2136 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2137 retry--;
2138 } while (res == -EIO && retry);
2139
2140 if (!retry) {
4e76a883 2141 codec_dbg(codec, "dsp_reset timeout\n");
01ef7dbf
IM		 2142 return -EIO;
2143 }
2144
2145 return 0;
2146}
2147
d5c21b88
IM		 2148/*
2149 * Convert chip address to DSP address
2150 */
01ef7dbf
IM		 2151static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2152 bool *code, bool *yram)
2153{
2154 *code = *yram = false;
2155
2156 if (UC_RANGE(chip_addx, 1)) {
2157 *code = true;
2158 return UC_OFF(chip_addx);
2159 } else if (X_RANGE_ALL(chip_addx, 1)) {
2160 return X_OFF(chip_addx);
2161 } else if (Y_RANGE_ALL(chip_addx, 1)) {
2162 *yram = true;
2163 return Y_OFF(chip_addx);
2164 }
2165
4a8b89f9 2166 return INVALID_CHIP_ADDRESS;
01ef7dbf
IM		 2167}
2168
d5c21b88
IM		 2169/*
2170 * Check if the DSP DMA is active
2171 */
01ef7dbf
IM		 2172static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2173{
2174 unsigned int dma_chnlstart_reg;
2175
2176 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2177
2178 return ((dma_chnlstart_reg & (1 <<
2179 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2180}
2181
2182static int dsp_dma_setup_common(struct hda_codec *codec,
2183 unsigned int chip_addx,
2184 unsigned int dma_chan,
2185 unsigned int port_map_mask,
2186 bool ovly)
2187{
2188 int status = 0;
2189 unsigned int chnl_prop;
2190 unsigned int dsp_addx;
2191 unsigned int active;
2192 bool code, yram;
2193
4e76a883 2194 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
01ef7dbf
IM		 2195
2196 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
4e76a883 2197 codec_dbg(codec, "dma chan num invalid\n");
01ef7dbf
IM		 2198 return -EINVAL;
2199 }
2200
2201 if (dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2202 codec_dbg(codec, "dma already active\n");
01ef7dbf
IM		 2203 return -EBUSY;
2204 }
2205
2206 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2207
2208 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 2209 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 2210 return -ENXIO;
2211 }
2212
2213 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2214 active = 0;
2215
4e76a883 2216 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
01ef7dbf
IM		 2217
2218 if (ovly) {
2219 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2220 &chnl_prop);
2221
2222 if (status < 0) {
4e76a883 2223 codec_dbg(codec, "read CHNLPROP Reg fail\n");
01ef7dbf
IM		 2224 return status;
2225 }
4e76a883 2226 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
01ef7dbf
IM		 2227 }
2228
2229 if (!code)
2230 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2231 else
2232 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2233
2234 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2235
2236 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2237 if (status < 0) {
4e76a883 2238 codec_dbg(codec, "write CHNLPROP Reg fail\n");
01ef7dbf
IM		 2239 return status;
2240 }
4e76a883 2241 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
01ef7dbf
IM		 2242
2243 if (ovly) {
2244 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2245 &active);
2246
2247 if (status < 0) {
4e76a883 2248 codec_dbg(codec, "read ACTIVE Reg fail\n");
01ef7dbf
IM		 2249 return status;
2250 }
4e76a883 2251 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
01ef7dbf
IM		 2252 }
2253
2254 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2255 DSPDMAC_ACTIVE_AAR_MASK;
2256
2257 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2258 if (status < 0) {
4e76a883 2259 codec_dbg(codec, "write ACTIVE Reg fail\n");
01ef7dbf
IM		 2260 return status;
2261 }
2262
4e76a883 2263 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
01ef7dbf
IM		 2264
2265 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2266 port_map_mask);
2267 if (status < 0) {
4e76a883 2268 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
01ef7dbf
IM		 2269 return status;
2270 }
4e76a883 2271 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
01ef7dbf
IM		 2272
2273 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2274 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2275 if (status < 0) {
4e76a883 2276 codec_dbg(codec, "write IRQCNT Reg fail\n");
01ef7dbf
IM		 2277 return status;
2278 }
4e76a883 2279 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
01ef7dbf 2280
4e76a883 2281 codec_dbg(codec,
01ef7dbf
IM		 2282 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2283 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2284 chip_addx, dsp_addx, dma_chan,
2285 port_map_mask, chnl_prop, active);
2286
4e76a883 2287 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
01ef7dbf
IM		 2288
2289 return 0;
2290}
2291
d5c21b88
IM		 2292/*
2293 * Setup the DSP DMA per-transfer-specific registers
2294 */
01ef7dbf
IM		 2295static int dsp_dma_setup(struct hda_codec *codec,
2296 unsigned int chip_addx,
2297 unsigned int count,
2298 unsigned int dma_chan)
2299{
2300 int status = 0;
2301 bool code, yram;
2302 unsigned int dsp_addx;
2303 unsigned int addr_field;
2304 unsigned int incr_field;
2305 unsigned int base_cnt;
2306 unsigned int cur_cnt;
2307 unsigned int dma_cfg = 0;
2308 unsigned int adr_ofs = 0;
2309 unsigned int xfr_cnt = 0;
2310 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2311 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2312
4e76a883 2313 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
01ef7dbf
IM		 2314
2315 if (count > max_dma_count) {
4e76a883 2316 codec_dbg(codec, "count too big\n");
01ef7dbf
IM		 2317 return -EINVAL;
2318 }
2319
2320 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2321 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 2322 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 2323 return -ENXIO;
2324 }
2325
4e76a883 2326 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
01ef7dbf
IM		 2327
2328 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2329 incr_field = 0;
2330
2331 if (!code) {
2332 addr_field <<= 1;
2333 if (yram)
2334 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2335
2336 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2337 }
2338
2339 dma_cfg = addr_field + incr_field;
2340 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2341 dma_cfg);
2342 if (status < 0) {
4e76a883 2343 codec_dbg(codec, "write DMACFG Reg fail\n");
01ef7dbf
IM		 2344 return status;
2345 }
4e76a883 2346 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
01ef7dbf
IM		 2347
2348 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2349 (code ? 0 : 1));
2350
2351 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2352 adr_ofs);
2353 if (status < 0) {
4e76a883 2354 codec_dbg(codec, "write DSPADROFS Reg fail\n");
01ef7dbf
IM		 2355 return status;
2356 }
4e76a883 2357 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
01ef7dbf
IM		 2358
2359 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2360
2361 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2362
2363 xfr_cnt = base_cnt | cur_cnt;
2364
2365 status = chipio_write(codec,
2366 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2367 if (status < 0) {
4e76a883 2368 codec_dbg(codec, "write XFRCNT Reg fail\n");
01ef7dbf
IM		 2369 return status;
2370 }
4e76a883 2371 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
01ef7dbf 2372
4e76a883 2373 codec_dbg(codec,
01ef7dbf
IM		 2374 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2375 "ADROFS=0x%x, XFRCNT=0x%x\n",
2376 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2377
4e76a883 2378 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
01ef7dbf
IM		 2379
2380 return 0;
2381}
2382
d5c21b88
IM		 2383/*
2384 * Start the DSP DMA
2385 */
01ef7dbf
IM		 2386static int dsp_dma_start(struct hda_codec *codec,
2387 unsigned int dma_chan, bool ovly)
2388{
2389 unsigned int reg = 0;
2390 int status = 0;
2391
4e76a883 2392 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
01ef7dbf
IM		 2393
2394 if (ovly) {
2395 status = chipio_read(codec,
2396 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2397
2398 if (status < 0) {
4e76a883 2399 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 2400 return status;
2401 }
4e76a883 2402 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
01ef7dbf
IM		 2403
2404 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2405 DSPDMAC_CHNLSTART_DIS_MASK);
2406 }
2407
2408 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2409 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2410 if (status < 0) {
4e76a883 2411 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 2412 return status;
2413 }
4e76a883 2414 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
01ef7dbf
IM		 2415
2416 return status;
2417}
2418
d5c21b88
IM		 2419/*
2420 * Stop the DSP DMA
2421 */
01ef7dbf
IM		 2422static int dsp_dma_stop(struct hda_codec *codec,
2423 unsigned int dma_chan, bool ovly)
2424{
2425 unsigned int reg = 0;
2426 int status = 0;
2427
4e76a883 2428 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
01ef7dbf
IM		 2429
2430 if (ovly) {
2431 status = chipio_read(codec,
2432 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2433
2434 if (status < 0) {
4e76a883 2435 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 2436 return status;
2437 }
4e76a883 2438 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
01ef7dbf
IM		 2439 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2440 DSPDMAC_CHNLSTART_DIS_MASK);
2441 }
2442
2443 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2444 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2445 if (status < 0) {
4e76a883 2446 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 2447 return status;
2448 }
4e76a883 2449 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
01ef7dbf
IM		 2450
2451 return status;
2452}
2453
d5c21b88
IM		 2454/**
2455 * Allocate router ports
2456 *
2457 * @codec: the HDA codec
2458 * @num_chans: number of channels in the stream
2459 * @ports_per_channel: number of ports per channel
2460 * @start_device: start device
2461 * @port_map: pointer to the port list to hold the allocated ports
2462 *
2463 * Returns zero or a negative error code.
2464 */
01ef7dbf
IM		 2465static int dsp_allocate_router_ports(struct hda_codec *codec,
2466 unsigned int num_chans,
2467 unsigned int ports_per_channel,
2468 unsigned int start_device,
2469 unsigned int *port_map)
2470{
2471 int status = 0;
2472 int res;
2473 u8 val;
2474
2475 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2476 if (status < 0)
2477 return status;
2478
2479 val = start_device << 6;
2480 val |= (ports_per_channel - 1) << 4;
2481 val |= num_chans - 1;
2482
2483 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2484 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2485 val);
2486
2487 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2488 VENDOR_CHIPIO_PORT_ALLOC_SET,
2489 MEM_CONNID_DSP);
2490
2491 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2492 if (status < 0)
2493 return status;
2494
2495 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2496 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2497
2498 *port_map = res;
2499
2500 return (res < 0) ? res : 0;
2501}
2502
d5c21b88
IM		 2503/*
2504 * Free router ports
2505 */
01ef7dbf
IM		 2506static int dsp_free_router_ports(struct hda_codec *codec)
2507{
2508 int status = 0;
2509
2510 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2511 if (status < 0)
2512 return status;
2513
2514 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2515 VENDOR_CHIPIO_PORT_FREE_SET,
2516 MEM_CONNID_DSP);
2517
2518 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2519
2520 return status;
2521}
2522
d5c21b88
IM		 2523/*
2524 * Allocate DSP ports for the download stream
2525 */
01ef7dbf
IM		 2526static int dsp_allocate_ports(struct hda_codec *codec,
2527 unsigned int num_chans,
2528 unsigned int rate_multi, unsigned int *port_map)
2529{
2530 int status;
2531
4e76a883 2532 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
01ef7dbf
IM		 2533
2534 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2535 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2536 return -EINVAL;
2537 }
2538
2539 status = dsp_allocate_router_ports(codec, num_chans,
2540 rate_multi, 0, port_map);
2541
4e76a883 2542 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
01ef7dbf
IM		 2543
2544 return status;
2545}
2546
01ef7dbf
IM		 2547static int dsp_allocate_ports_format(struct hda_codec *codec,
2548 const unsigned short fmt,
2549 unsigned int *port_map)
2550{
2551 int status;
2552 unsigned int num_chans;
2553
2554 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2555 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2556 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2557
2558 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2559 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2560 return -EINVAL;
2561 }
2562
2563 num_chans = get_hdafmt_chs(fmt) + 1;
2564
2565 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2566
2567 return status;
2568}
2569
d5c21b88
IM		 2570/*
2571 * free DSP ports
2572 */
2573static int dsp_free_ports(struct hda_codec *codec)
2574{
2575 int status;
2576
4e76a883 2577 codec_dbg(codec, " dsp_free_ports() -- begin\n");
d5c21b88
IM		 2578
2579 status = dsp_free_router_ports(codec);
2580 if (status < 0) {
4e76a883 2581 codec_dbg(codec, "free router ports fail\n");
d5c21b88
IM		 2582 return status;
2583 }
4e76a883 2584 codec_dbg(codec, " dsp_free_ports() -- complete\n");
d5c21b88
IM		 2585
2586 return status;
2587}
2588
01ef7dbf
IM		 2589/*
2590 * HDA DMA engine stuffs for DSP code download
2591 */
2592struct dma_engine {
2593 struct hda_codec *codec;
2594 unsigned short m_converter_format;
2595 struct snd_dma_buffer *dmab;
2596 unsigned int buf_size;
2597};
2598
2599
2600enum dma_state {
2601 DMA_STATE_STOP = 0,
2602 DMA_STATE_RUN = 1
2603};
2604
6194b99d 2605static int dma_convert_to_hda_format(struct hda_codec *codec,
e97249dd
IM		 2606 unsigned int sample_rate,
2607 unsigned short channels,
01ef7dbf
IM		 2608 unsigned short *hda_format)
2609{
2610 unsigned int format_val;
2611
b7d023e1
TI		 2612 format_val = snd_hdac_calc_stream_format(sample_rate,
2613 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
01ef7dbf
IM		 2614
2615 if (hda_format)
2616 *hda_format = (unsigned short)format_val;
2617
2618 return 0;
2619}
2620
d5c21b88
IM		 2621/*
2622 * Reset DMA for DSP download
2623 */
01ef7dbf
IM		 2624static int dma_reset(struct dma_engine *dma)
2625{
2626 struct hda_codec *codec = dma->codec;
2627 struct ca0132_spec *spec = codec->spec;
2628 int status;
2629
b3667bd7 2630 if (dma->dmab->area)
01ef7dbf
IM		 2631 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2632
2633 status = snd_hda_codec_load_dsp_prepare(codec,
2634 dma->m_converter_format,
2635 dma->buf_size,
2636 dma->dmab);
2637 if (status < 0)
2638 return status;
2639 spec->dsp_stream_id = status;
2640 return 0;
2641}
2642
2643static int dma_set_state(struct dma_engine *dma, enum dma_state state)
95c6e9cb 2644{
01ef7dbf
IM		 2645 bool cmd;
2646
01ef7dbf
IM		 2647 switch (state) {
2648 case DMA_STATE_STOP:
2649 cmd = false;
2650 break;
2651 case DMA_STATE_RUN:
2652 cmd = true;
2653 break;
2654 default:
c41999a2
DH		 2655 return 0;
2656 }
01ef7dbf
IM		 2657
2658 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2659 return 0;
95c6e9cb
IM		 2660}
2661
01ef7dbf
IM		 2662static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2663{
2664 return dma->dmab->bytes;
2665}
95c6e9cb 2666
01ef7dbf
IM		 2667static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2668{
2669 return dma->dmab->area;
2670}
95c6e9cb 2671
01ef7dbf
IM		 2672static int dma_xfer(struct dma_engine *dma,
2673 const unsigned int *data,
2674 unsigned int count)
2675{
2676 memcpy(dma->dmab->area, data, count);
2677 return 0;
2678}
95c6e9cb 2679
01ef7dbf
IM		 2680static void dma_get_converter_format(
2681 struct dma_engine *dma,
2682 unsigned short *format)
2683{
2684 if (format)
2685 *format = dma->m_converter_format;
2686}
95c6e9cb 2687
01ef7dbf 2688static unsigned int dma_get_stream_id(struct dma_engine *dma)
95c6e9cb 2689{
01ef7dbf 2690 struct ca0132_spec *spec = dma->codec->spec;
95c6e9cb 2691
01ef7dbf 2692 return spec->dsp_stream_id;
95c6e9cb
IM		 2693}
2694
01ef7dbf
IM		 2695struct dsp_image_seg {
2696 u32 magic;
2697 u32 chip_addr;
2698 u32 count;
2699 u32 data[0];
2700};
2701
2702static const u32 g_magic_value = 0x4c46584d;
2703static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2704
2705static bool is_valid(const struct dsp_image_seg *p)
95c6e9cb 2706{
01ef7dbf
IM		 2707 return p->magic == g_magic_value;
2708}
95c6e9cb 2709
01ef7dbf
IM		 2710static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2711{
2712 return g_chip_addr_magic_value == p->chip_addr;
2713}
95c6e9cb 2714
01ef7dbf
IM		 2715static bool is_last(const struct dsp_image_seg *p)
2716{
2717 return p->count == 0;
2718}
95c6e9cb 2719
01ef7dbf
IM		 2720static size_t dsp_sizeof(const struct dsp_image_seg *p)
2721{
e046b64b 2722 return struct_size(p, data, p->count);
01ef7dbf
IM		 2723}
2724
2725static const struct dsp_image_seg *get_next_seg_ptr(
2726 const struct dsp_image_seg *p)
2727{
2728 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
95c6e9cb
IM		 2729}
2730
2731/*
01ef7dbf 2732 * CA0132 chip DSP transfer stuffs. For DSP download.
95c6e9cb 2733 */
8ae3124b 2734#define INVALID_DMA_CHANNEL (~0U)
95c6e9cb 2735
d5c21b88
IM		 2736/*
2737 * Program a list of address/data pairs via the ChipIO widget.
2738 * The segment data is in the format of successive pairs of words.
2739 * These are repeated as indicated by the segment's count field.
2740 */
01ef7dbf
IM		 2741static int dspxfr_hci_write(struct hda_codec *codec,
2742 const struct dsp_image_seg *fls)
95c6e9cb 2743{
01ef7dbf
IM		 2744 int status;
2745 const u32 *data;
2746 unsigned int count;
95c6e9cb 2747
01ef7dbf 2748 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
4e76a883 2749 codec_dbg(codec, "hci_write invalid params\n");
01ef7dbf 2750 return -EINVAL;
95c6e9cb
IM		 2751 }
2752
01ef7dbf
IM		 2753 count = fls->count;
2754 data = (u32 *)(fls->data);
2755 while (count >= 2) {
2756 status = chipio_write(codec, data[0], data[1]);
2757 if (status < 0) {
4e76a883 2758 codec_dbg(codec, "hci_write chipio failed\n");
01ef7dbf
IM		 2759 return status;
2760 }
2761 count -= 2;
2762 data += 2;
2763 }
2764 return 0;
95c6e9cb
IM		 2765}
2766
d5c21b88
IM		 2767/**
2768 * Write a block of data into DSP code or data RAM using pre-allocated
2769 * DMA engine.
2770 *
2771 * @codec: the HDA codec
2772 * @fls: pointer to a fast load image
2773 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2774 * no relocation
2775 * @dma_engine: pointer to DMA engine to be used for DSP download
2776 * @dma_chan: The number of DMA channels used for DSP download
2777 * @port_map_mask: port mapping
2778 * @ovly: TRUE if overlay format is required
2779 *
2780 * Returns zero or a negative error code.
2781 */
01ef7dbf
IM		 2782static int dspxfr_one_seg(struct hda_codec *codec,
2783 const struct dsp_image_seg *fls,
2784 unsigned int reloc,
2785 struct dma_engine *dma_engine,
2786 unsigned int dma_chan,
2787 unsigned int port_map_mask,
2788 bool ovly)
95c6e9cb 2789{
406261ce 2790 int status = 0;
01ef7dbf
IM		 2791 bool comm_dma_setup_done = false;
2792 const unsigned int *data;
2793 unsigned int chip_addx;
2794 unsigned int words_to_write;
2795 unsigned int buffer_size_words;
2796 unsigned char *buffer_addx;
2797 unsigned short hda_format;
2798 unsigned int sample_rate_div;
2799 unsigned int sample_rate_mul;
2800 unsigned int num_chans;
2801 unsigned int hda_frame_size_words;
2802 unsigned int remainder_words;
2803 const u32 *data_remainder;
2804 u32 chip_addx_remainder;
2805 unsigned int run_size_words;
2806 const struct dsp_image_seg *hci_write = NULL;
6d67530e
IM		 2807 unsigned long timeout;
2808 bool dma_active;
01ef7dbf
IM		 2809
2810 if (fls == NULL)
2811 return -EINVAL;
2812 if (is_hci_prog_list_seg(fls)) {
2813 hci_write = fls;
2814 fls = get_next_seg_ptr(fls);
2815 }
95c6e9cb 2816
01ef7dbf 2817 if (hci_write && (!fls || is_last(fls))) {
4e76a883 2818 codec_dbg(codec, "hci_write\n");
01ef7dbf
IM		 2819 return dspxfr_hci_write(codec, hci_write);
2820 }
95c6e9cb 2821
01ef7dbf 2822 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
4e76a883 2823 codec_dbg(codec, "Invalid Params\n");
01ef7dbf 2824 return -EINVAL;
95c6e9cb
IM		 2825 }
2826
01ef7dbf
IM		 2827 data = fls->data;
2828 chip_addx = fls->chip_addr,
2829 words_to_write = fls->count;
2830
2831 if (!words_to_write)
2832 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2833 if (reloc)
2834 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2835
2836 if (!UC_RANGE(chip_addx, words_to_write) &&
2837 !X_RANGE_ALL(chip_addx, words_to_write) &&
2838 !Y_RANGE_ALL(chip_addx, words_to_write)) {
4e76a883 2839 codec_dbg(codec, "Invalid chip_addx Params\n");
01ef7dbf 2840 return -EINVAL;
95c6e9cb
IM		 2841 }
2842
01ef7dbf
IM		 2843 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2844 sizeof(u32);
2845
2846 buffer_addx = dma_get_buffer_addr(dma_engine);
2847
2848 if (buffer_addx == NULL) {
4e76a883 2849 codec_dbg(codec, "dma_engine buffer NULL\n");
01ef7dbf
IM		 2850 return -EINVAL;
2851 }
2852
2853 dma_get_converter_format(dma_engine, &hda_format);
2854 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2855 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2856 num_chans = get_hdafmt_chs(hda_format) + 1;
2857
2858 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2859 (num_chans * sample_rate_mul / sample_rate_div));
2860
3bc085a1 2861 if (hda_frame_size_words == 0) {
4e76a883 2862 codec_dbg(codec, "frmsz zero\n");
3bc085a1
XW		 2863 return -EINVAL;
2864 }
2865
01ef7dbf
IM		 2866 buffer_size_words = min(buffer_size_words,
2867 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2868 65536 : 32768));
2869 buffer_size_words -= buffer_size_words % hda_frame_size_words;
4e76a883 2870 codec_dbg(codec,
01ef7dbf
IM		 2871 "chpadr=0x%08x frmsz=%u nchan=%u "
2872 "rate_mul=%u div=%u bufsz=%u\n",
2873 chip_addx, hda_frame_size_words, num_chans,
2874 sample_rate_mul, sample_rate_div, buffer_size_words);
2875
3bc085a1 2876 if (buffer_size_words < hda_frame_size_words) {
4e76a883 2877 codec_dbg(codec, "dspxfr_one_seg:failed\n");
01ef7dbf
IM		 2878 return -EINVAL;
2879 }
2880
2881 remainder_words = words_to_write % hda_frame_size_words;
2882 data_remainder = data;
2883 chip_addx_remainder = chip_addx;
2884
2885 data += remainder_words;
2886 chip_addx += remainder_words*sizeof(u32);
2887 words_to_write -= remainder_words;
2888
2889 while (words_to_write != 0) {
2890 run_size_words = min(buffer_size_words, words_to_write);
4e76a883 2891 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
01ef7dbf
IM		 2892 words_to_write, run_size_words, remainder_words);
2893 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2894 if (!comm_dma_setup_done) {
2895 status = dsp_dma_stop(codec, dma_chan, ovly);
2896 if (status < 0)
425a7880 2897 return status;
01ef7dbf
IM		 2898 status = dsp_dma_setup_common(codec, chip_addx,
2899 dma_chan, port_map_mask, ovly);
2900 if (status < 0)
2901 return status;
2902 comm_dma_setup_done = true;
2903 }
2904
2905 status = dsp_dma_setup(codec, chip_addx,
2906 run_size_words, dma_chan);
2907 if (status < 0)
2908 return status;
2909 status = dsp_dma_start(codec, dma_chan, ovly);
2910 if (status < 0)
2911 return status;
2912 if (!dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2913 codec_dbg(codec, "dspxfr:DMA did not start\n");
01ef7dbf
IM		 2914 return -EIO;
2915 }
2916 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2917 if (status < 0)
2918 return status;
2919 if (remainder_words != 0) {
2920 status = chipio_write_multiple(codec,
2921 chip_addx_remainder,
2922 data_remainder,
2923 remainder_words);
b3667bd7
TI		 2924 if (status < 0)
2925 return status;
01ef7dbf
IM		 2926 remainder_words = 0;
2927 }
2928 if (hci_write) {
2929 status = dspxfr_hci_write(codec, hci_write);
b3667bd7
TI		 2930 if (status < 0)
2931 return status;
01ef7dbf
IM		 2932 hci_write = NULL;
2933 }
6d67530e
IM		 2934
2935 timeout = jiffies + msecs_to_jiffies(2000);
2936 do {
2937 dma_active = dsp_is_dma_active(codec, dma_chan);
2938 if (!dma_active)
01ef7dbf 2939 break;
6d67530e
IM		 2940 msleep(20);
2941 } while (time_before(jiffies, timeout));
2942 if (dma_active)
2943 break;
2944
4e76a883 2945 codec_dbg(codec, "+++++ DMA complete\n");
01ef7dbf 2946 dma_set_state(dma_engine, DMA_STATE_STOP);
b3667bd7 2947 status = dma_reset(dma_engine);
01ef7dbf
IM		 2948
2949 if (status < 0)
2950 return status;
2951
2952 data += run_size_words;
2953 chip_addx += run_size_words*sizeof(u32);
2954 words_to_write -= run_size_words;
2955 }
2956
2957 if (remainder_words != 0) {
2958 status = chipio_write_multiple(codec, chip_addx_remainder,
2959 data_remainder, remainder_words);
2960 }
2961
2962 return status;
95c6e9cb
IM		 2963}
2964
d5c21b88
IM		 2965/**
2966 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2967 *
2968 * @codec: the HDA codec
2969 * @fls_data: pointer to a fast load image
2970 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2971 * no relocation
e97249dd 2972 * @sample_rate: sampling rate of the stream used for DSP download
e60b2c7f 2973 * @channels: channels of the stream used for DSP download
d5c21b88
IM		 2974 * @ovly: TRUE if overlay format is required
2975 *
2976 * Returns zero or a negative error code.
2977 */
01ef7dbf
IM		 2978static int dspxfr_image(struct hda_codec *codec,
2979 const struct dsp_image_seg *fls_data,
e97249dd
IM		 2980 unsigned int reloc,
2981 unsigned int sample_rate,
2982 unsigned short channels,
01ef7dbf 2983 bool ovly)
95c6e9cb
IM		 2984{
2985 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 2986 int status;
2987 unsigned short hda_format = 0;
2988 unsigned int response;
2989 unsigned char stream_id = 0;
2990 struct dma_engine *dma_engine;
2991 unsigned int dma_chan;
2992 unsigned int port_map_mask;
2993
2994 if (fls_data == NULL)
2995 return -EINVAL;
2996
2997 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
549e8292
TI		 2998 if (!dma_engine)
2999 return -ENOMEM;
95c6e9cb 3000
01ef7dbf
IM		 3001 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
3002 if (!dma_engine->dmab) {
549e8292
TI		 3003 kfree(dma_engine);
3004 return -ENOMEM;
01ef7dbf 3005 }
95c6e9cb 3006
01ef7dbf 3007 dma_engine->codec = codec;
6194b99d 3008 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
01ef7dbf
IM		 3009 dma_engine->m_converter_format = hda_format;
3010 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
3011 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
3012
8ae3124b 3013 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
01ef7dbf
IM		 3014
3015 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
3016 hda_format, &response);
3017
3018 if (status < 0) {
4e76a883 3019 codec_dbg(codec, "set converter format fail\n");
01ef7dbf
IM		 3020 goto exit;
3021 }
3022
3023 status = snd_hda_codec_load_dsp_prepare(codec,
3024 dma_engine->m_converter_format,
3025 dma_engine->buf_size,
3026 dma_engine->dmab);
3027 if (status < 0)
95c6e9cb 3028 goto exit;
01ef7dbf
IM		 3029 spec->dsp_stream_id = status;
3030
3031 if (ovly) {
3032 status = dspio_alloc_dma_chan(codec, &dma_chan);
3033 if (status < 0) {
4e76a883 3034 codec_dbg(codec, "alloc dmachan fail\n");
8ae3124b 3035 dma_chan = INVALID_DMA_CHANNEL;
01ef7dbf
IM		 3036 goto exit;
3037 }
3038 }
95c6e9cb 3039
01ef7dbf
IM		 3040 port_map_mask = 0;
3041 status = dsp_allocate_ports_format(codec, hda_format,
3042 &port_map_mask);
3043 if (status < 0) {
4e76a883 3044 codec_dbg(codec, "alloc ports fail\n");
01ef7dbf
IM		 3045 goto exit;
3046 }
3047
3048 stream_id = dma_get_stream_id(dma_engine);
3049 status = codec_set_converter_stream_channel(codec,
3050 WIDGET_CHIP_CTRL, stream_id, 0, &response);
3051 if (status < 0) {
4e76a883 3052 codec_dbg(codec, "set stream chan fail\n");
01ef7dbf
IM		 3053 goto exit;
3054 }
3055
3056 while ((fls_data != NULL) && !is_last(fls_data)) {
3057 if (!is_valid(fls_data)) {
4e76a883 3058 codec_dbg(codec, "FLS check fail\n");
01ef7dbf
IM		 3059 status = -EINVAL;
3060 goto exit;
3061 }
3062 status = dspxfr_one_seg(codec, fls_data, reloc,
3063 dma_engine, dma_chan,
3064 port_map_mask, ovly);
3065 if (status < 0)
3066 break;
3067
3068 if (is_hci_prog_list_seg(fls_data))
3069 fls_data = get_next_seg_ptr(fls_data);
3070
3071 if ((fls_data != NULL) && !is_last(fls_data))
3072 fls_data = get_next_seg_ptr(fls_data);
3073 }
3074
3075 if (port_map_mask != 0)
3076 status = dsp_free_ports(codec);
3077
3078 if (status < 0)
95c6e9cb
IM		 3079 goto exit;
3080
01ef7dbf
IM		 3081 status = codec_set_converter_stream_channel(codec,
3082 WIDGET_CHIP_CTRL, 0, 0, &response);
3083
95c6e9cb 3084exit:
01ef7dbf
IM		 3085 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
3086 dspio_free_dma_chan(codec, dma_chan);
3087
b3667bd7 3088 if (dma_engine->dmab->area)
01ef7dbf
IM		 3089 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
3090 kfree(dma_engine->dmab);
3091 kfree(dma_engine);
3092
3093 return status;
95c6e9cb
IM		 3094}
3095
3096/*
01ef7dbf 3097 * CA0132 DSP download stuffs.
95c6e9cb 3098 */
01ef7dbf 3099static void dspload_post_setup(struct hda_codec *codec)
95c6e9cb 3100{
009b8f97 3101 struct ca0132_spec *spec = codec->spec;
4e76a883 3102 codec_dbg(codec, "---- dspload_post_setup ------\n");
6da8f446 3103 if (!ca0132_use_alt_functions(spec)) {
009b8f97
CM		 3104 /*set DSP speaker to 2.0 configuration*/
3105 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3106 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
95c6e9cb 3107
009b8f97
CM		 3108 /*update write pointer*/
3109 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3110 }
01ef7dbf 3111}
95c6e9cb 3112
d5c21b88 3113/**
e60b2c7f 3114 * dspload_image - Download DSP from a DSP Image Fast Load structure.
d5c21b88
IM		 3115 *
3116 * @codec: the HDA codec
3117 * @fls: pointer to a fast load image
3118 * @ovly: TRUE if overlay format is required
3119 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3120 * no relocation
3121 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
3122 * @router_chans: number of audio router channels to be allocated (0 means use
3123 * internal defaults; max is 32)
3124 *
e60b2c7f
TI		 3125 * Download DSP from a DSP Image Fast Load structure. This structure is a
3126 * linear, non-constant sized element array of structures, each of which
3127 * contain the count of the data to be loaded, the data itself, and the
3128 * corresponding starting chip address of the starting data location.
d5c21b88
IM		 3129 * Returns zero or a negative error code.
3130 */
01ef7dbf
IM		 3131static int dspload_image(struct hda_codec *codec,
3132 const struct dsp_image_seg *fls,
3133 bool ovly,
3134 unsigned int reloc,
3135 bool autostart,
3136 int router_chans)
3137{
3138 int status = 0;
e97249dd
IM		 3139 unsigned int sample_rate;
3140 unsigned short channels;
01ef7dbf 3141
4e76a883 3142 codec_dbg(codec, "---- dspload_image begin ------\n");
01ef7dbf
IM		 3143 if (router_chans == 0) {
3144 if (!ovly)
3145 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3146 else
3147 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3148 }
95c6e9cb 3149
e97249dd
IM		 3150 sample_rate = 48000;
3151 channels = (unsigned short)router_chans;
01ef7dbf 3152
e97249dd
IM		 3153 while (channels > 16) {
3154 sample_rate *= 2;
3155 channels /= 2;
01ef7dbf
IM		 3156 }
3157
01ef7dbf 3158 do {
4e76a883 3159 codec_dbg(codec, "Ready to program DMA\n");
01ef7dbf
IM		 3160 if (!ovly)
3161 status = dsp_reset(codec);
3162
3163 if (status < 0)
3164 break;
3165
4e76a883 3166 codec_dbg(codec, "dsp_reset() complete\n");
e97249dd
IM		 3167 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3168 ovly);
01ef7dbf
IM		 3169
3170 if (status < 0)
3171 break;
3172
4e76a883 3173 codec_dbg(codec, "dspxfr_image() complete\n");
01ef7dbf
IM		 3174 if (autostart && !ovly) {
3175 dspload_post_setup(codec);
3176 status = dsp_set_run_state(codec);
3177 }
3178
4e76a883 3179 codec_dbg(codec, "LOAD FINISHED\n");
01ef7dbf
IM		 3180 } while (0);
3181
3182 return status;
3183}
3184
f664417e 3185#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf
IM		 3186static bool dspload_is_loaded(struct hda_codec *codec)
3187{
3188 unsigned int data = 0;
3189 int status = 0;
3190
3191 status = chipio_read(codec, 0x40004, &data);
3192 if ((status < 0) || (data != 1))
3193 return false;
3194
3195 return true;
3196}
f664417e
TI		 3197#else
3198#define dspload_is_loaded(codec) false
3199#endif
01ef7dbf
IM		 3200
3201static bool dspload_wait_loaded(struct hda_codec *codec)
3202{
6d67530e 3203 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
01ef7dbf
IM		 3204
3205 do {
01ef7dbf 3206 if (dspload_is_loaded(codec)) {
d9684bb5 3207 codec_info(codec, "ca0132 DSP downloaded and running\n");
01ef7dbf
IM		 3208 return true;
3209 }
6d67530e
IM		 3210 msleep(20);
3211 } while (time_before(jiffies, timeout));
01ef7dbf 3212
d9684bb5 3213 codec_err(codec, "ca0132 failed to download DSP\n");
01ef7dbf 3214 return false;
95c6e9cb
IM		 3215}
3216
e93ac30a 3217/*
b9b41345
CM		 3218 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
3219 * based cards, and has a second mmio region, region2, that's used for special
3220 * commands.
e93ac30a
CM		 3221 */
3222
a62e4739
CM		 3223/*
3224 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3225 * the mmio address 0x320 is used to set GPIO pins. The format for the data
3226 * The first eight bits are just the number of the pin. So far, I've only seen
3227 * this number go to 7.
b9b41345
CM		 3228 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
3229 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
3230 * then off to send that bit.
a62e4739 3231 */
b9b41345 3232static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
a62e4739
CM		 3233 bool enable)
3234{
3235 struct ca0132_spec *spec = codec->spec;
3236 unsigned short gpio_data;
3237
3238 gpio_data = gpio_pin & 0xF;
3239 gpio_data |= ((enable << 8) & 0x100);
3240
3241 writew(gpio_data, spec->mem_base + 0x320);
3242}
3243
b9b41345
CM		 3244/*
3245 * Special pci region2 commands that are only used by the AE-5. They follow
3246 * a set format, and require reads at certain points to seemingly 'clear'
3247 * the response data. My first tests didn't do these reads, and would cause
3248 * the card to get locked up until the memory was read. These commands
3249 * seem to work with three distinct values that I've taken to calling group,
3250 * target-id, and value.
3251 */
3252static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
3253 unsigned int target, unsigned int value)
3254{
3255 struct ca0132_spec *spec = codec->spec;
3256 unsigned int write_val;
3257
3258 writel(0x0000007e, spec->mem_base + 0x210);
3259 readl(spec->mem_base + 0x210);
3260 writel(0x0000005a, spec->mem_base + 0x210);
3261 readl(spec->mem_base + 0x210);
3262 readl(spec->mem_base + 0x210);
3263
3264 writel(0x00800005, spec->mem_base + 0x20c);
3265 writel(group, spec->mem_base + 0x804);
3266
3267 writel(0x00800005, spec->mem_base + 0x20c);
3268 write_val = (target & 0xff);
3269 write_val |= (value << 8);
3270
3271
3272 writel(write_val, spec->mem_base + 0x204);
3273 /*
3274 * Need delay here or else it goes too fast and works inconsistently.
3275 */
3276 msleep(20);
3277
3278 readl(spec->mem_base + 0x860);
3279 readl(spec->mem_base + 0x854);
3280 readl(spec->mem_base + 0x840);
3281
3282 writel(0x00800004, spec->mem_base + 0x20c);
3283 writel(0x00000000, spec->mem_base + 0x210);
3284 readl(spec->mem_base + 0x210);
3285 readl(spec->mem_base + 0x210);
3286}
3287
212de2e7
CM		 3288/*
3289 * This second type of command is used for setting the sound filter type.
3290 */
3291static void ca0113_mmio_command_set_type2(struct hda_codec *codec,
3292 unsigned int group, unsigned int target, unsigned int value)
3293{
3294 struct ca0132_spec *spec = codec->spec;
3295 unsigned int write_val;
3296
3297 writel(0x0000007e, spec->mem_base + 0x210);
3298 readl(spec->mem_base + 0x210);
3299 writel(0x0000005a, spec->mem_base + 0x210);
3300 readl(spec->mem_base + 0x210);
3301 readl(spec->mem_base + 0x210);
3302
3303 writel(0x00800003, spec->mem_base + 0x20c);
3304 writel(group, spec->mem_base + 0x804);
3305
3306 writel(0x00800005, spec->mem_base + 0x20c);
3307 write_val = (target & 0xff);
3308 write_val |= (value << 8);
3309
3310
3311 writel(write_val, spec->mem_base + 0x204);
3312 msleep(20);
3313 readl(spec->mem_base + 0x860);
3314 readl(spec->mem_base + 0x854);
3315 readl(spec->mem_base + 0x840);
3316
3317 writel(0x00800004, spec->mem_base + 0x20c);
3318 writel(0x00000000, spec->mem_base + 0x210);
3319 readl(spec->mem_base + 0x210);
3320 readl(spec->mem_base + 0x210);
3321}
3322
b9b41345
CM		 3323/*
3324 * Setup GPIO for the other variants of Core3D.
3325 */
3326
e93ac30a
CM		 3327/*
3328 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3329 * the card shows as having no GPIO pins.
3330 */
3331static void ca0132_gpio_init(struct hda_codec *codec)
3332{
3333 struct ca0132_spec *spec = codec->spec;
3334
6da8f446 3335 switch (ca0132_quirk(spec)) {
e93ac30a 3336 case QUIRK_SBZ:
03c9b6b1 3337 case QUIRK_AE5:
e93ac30a
CM		 3338 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3339 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3340 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3341 break;
3342 case QUIRK_R3DI:
3343 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3344 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3345 break;
6da8f446
TI		 3346 default:
3347 break;
e93ac30a
CM		 3348 }
3349
3350}
3351
3352/* Sets the GPIO for audio output. */
3353static void ca0132_gpio_setup(struct hda_codec *codec)
3354{
3355 struct ca0132_spec *spec = codec->spec;
3356
6da8f446 3357 switch (ca0132_quirk(spec)) {
e93ac30a
CM		 3358 case QUIRK_SBZ:
3359 snd_hda_codec_write(codec, 0x01, 0,
3360 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3361 snd_hda_codec_write(codec, 0x01, 0,
3362 AC_VERB_SET_GPIO_MASK, 0x07);
3363 snd_hda_codec_write(codec, 0x01, 0,
3364 AC_VERB_SET_GPIO_DATA, 0x04);
3365 snd_hda_codec_write(codec, 0x01, 0,
3366 AC_VERB_SET_GPIO_DATA, 0x06);
3367 break;
3368 case QUIRK_R3DI:
3369 snd_hda_codec_write(codec, 0x01, 0,
3370 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3371 snd_hda_codec_write(codec, 0x01, 0,
3372 AC_VERB_SET_GPIO_MASK, 0x1F);
3373 snd_hda_codec_write(codec, 0x01, 0,
3374 AC_VERB_SET_GPIO_DATA, 0x0C);
3375 break;
6da8f446
TI		 3376 default:
3377 break;
e93ac30a
CM		 3378 }
3379}
3380
7e6ed62e
CM		 3381/*
3382 * GPIO control functions for the Recon3D integrated.
3383 */
3384
3385enum r3di_gpio_bit {
3386 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3387 R3DI_MIC_SELECT_BIT = 1,
3388 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3389 R3DI_OUT_SELECT_BIT = 2,
3390 /*
3391 * I dunno what this actually does, but it stays on until the dsp
3392 * is downloaded.
3393 */
3394 R3DI_GPIO_DSP_DOWNLOADING = 3,
3395 /*
3396 * Same as above, no clue what it does, but it comes on after the dsp
3397 * is downloaded.
3398 */
3399 R3DI_GPIO_DSP_DOWNLOADED = 4
3400};
3401
3402enum r3di_mic_select {
3403 /* Set GPIO bit 1 to 0 for rear mic */
3404 R3DI_REAR_MIC = 0,
3405 /* Set GPIO bit 1 to 1 for front microphone*/
3406 R3DI_FRONT_MIC = 1
3407};
3408
3409enum r3di_out_select {
3410 /* Set GPIO bit 2 to 0 for headphone */
3411 R3DI_HEADPHONE_OUT = 0,
3412 /* Set GPIO bit 2 to 1 for speaker */
3413 R3DI_LINE_OUT = 1
3414};
3415enum r3di_dsp_status {
3416 /* Set GPIO bit 3 to 1 until DSP is downloaded */
3417 R3DI_DSP_DOWNLOADING = 0,
3418 /* Set GPIO bit 4 to 1 once DSP is downloaded */
3419 R3DI_DSP_DOWNLOADED = 1
3420};
3421
7cb9d94c
CM		 3422
3423static void r3di_gpio_mic_set(struct hda_codec *codec,
3424 enum r3di_mic_select cur_mic)
3425{
3426 unsigned int cur_gpio;
3427
3428 /* Get the current GPIO Data setup */
3429 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3430
3431 switch (cur_mic) {
3432 case R3DI_REAR_MIC:
3433 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3434 break;
3435 case R3DI_FRONT_MIC:
3436 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3437 break;
3438 }
3439 snd_hda_codec_write(codec, codec->core.afg, 0,
3440 AC_VERB_SET_GPIO_DATA, cur_gpio);
3441}
3442
3443static void r3di_gpio_out_set(struct hda_codec *codec,
3444 enum r3di_out_select cur_out)
3445{
3446 unsigned int cur_gpio;
3447
3448 /* Get the current GPIO Data setup */
3449 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3450
3451 switch (cur_out) {
3452 case R3DI_HEADPHONE_OUT:
3453 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT);
3454 break;
3455 case R3DI_LINE_OUT:
3456 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT);
3457 break;
3458 }
3459 snd_hda_codec_write(codec, codec->core.afg, 0,
3460 AC_VERB_SET_GPIO_DATA, cur_gpio);
3461}
3462
7e6ed62e
CM		 3463static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3464 enum r3di_dsp_status dsp_status)
3465{
3466 unsigned int cur_gpio;
3467
3468 /* Get the current GPIO Data setup */
3469 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3470
3471 switch (dsp_status) {
3472 case R3DI_DSP_DOWNLOADING:
3473 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3474 snd_hda_codec_write(codec, codec->core.afg, 0,
3475 AC_VERB_SET_GPIO_DATA, cur_gpio);
3476 break;
3477 case R3DI_DSP_DOWNLOADED:
3478 /* Set DOWNLOADING bit to 0. */
3479 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3480
3481 snd_hda_codec_write(codec, codec->core.afg, 0,
3482 AC_VERB_SET_GPIO_DATA, cur_gpio);
3483
3484 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3485 break;
3486 }
3487
3488 snd_hda_codec_write(codec, codec->core.afg, 0,
3489 AC_VERB_SET_GPIO_DATA, cur_gpio);
3490}
3491
825315bc
IM		 3492/*
3493 * PCM callbacks
3494 */
95c6e9cb
IM		 3495static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3496 struct hda_codec *codec,
3497 unsigned int stream_tag,
3498 unsigned int format,
3499 struct snd_pcm_substream *substream)
3500{
3501 struct ca0132_spec *spec = codec->spec;
825315bc 3502
28fba950 3503 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
825315bc
IM		 3504
3505 return 0;
95c6e9cb
IM		 3506}
3507
3508static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3509 struct hda_codec *codec,
3510 struct snd_pcm_substream *substream)
3511{
3512 struct ca0132_spec *spec = codec->spec;
825315bc
IM		 3513
3514 if (spec->dsp_state == DSP_DOWNLOADING)
3515 return 0;
3516
3517 /*If Playback effects are on, allow stream some time to flush
3518 *effects tail*/
3519 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3520 msleep(50);
3521
28fba950 3522 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
825315bc
IM		 3523
3524 return 0;
95c6e9cb
IM		 3525}
3526
e8412ca4
DR		 3527static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3528 struct hda_codec *codec,
3529 struct snd_pcm_substream *substream)
3530{
3531 struct ca0132_spec *spec = codec->spec;
3532 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3533 struct snd_pcm_runtime *runtime = substream->runtime;
3534
3535 if (spec->dsp_state != DSP_DOWNLOADED)
3536 return 0;
3537
3538 /* Add latency if playback enhancement and either effect is enabled. */
3539 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3540 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3541 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3542 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3543 }
3544
3545 /* Applying Speaker EQ adds latency as well. */
3546 if (spec->cur_out_type == SPEAKER_OUT)
3547 latency += DSP_SPEAKER_OUT_LATENCY;
3548
3549 return (latency * runtime->rate) / 1000;
3550}
3551
95c6e9cb
IM		 3552/*
3553 * Digital out
3554 */
27ebeb0b
TI		 3555static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3556 struct hda_codec *codec,
3557 struct snd_pcm_substream *substream)
95c6e9cb
IM		 3558{
3559 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3560 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95c6e9cb
IM		 3561}
3562
27ebeb0b 3563static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
95c6e9cb
IM		 3564 struct hda_codec *codec,
3565 unsigned int stream_tag,
3566 unsigned int format,
3567 struct snd_pcm_substream *substream)
3568{
3569 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 3570 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3571 stream_tag, format, substream);
95c6e9cb
IM		 3572}
3573
27ebeb0b 3574static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
95c6e9cb 3575 struct hda_codec *codec,
95c6e9cb
IM		 3576 struct snd_pcm_substream *substream)
3577{
3578 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3579 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 3580}
3581
27ebeb0b
TI		 3582static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3583 struct hda_codec *codec,
3584 struct snd_pcm_substream *substream)
95c6e9cb
IM		 3585{
3586 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3587 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
95c6e9cb
IM		 3588}
3589
825315bc
IM		 3590/*
3591 * Analog capture
3592 */
3593static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3594 struct hda_codec *codec,
3595 unsigned int stream_tag,
3596 unsigned int format,
3597 struct snd_pcm_substream *substream)
3598{
13c12dbe 3599 snd_hda_codec_setup_stream(codec, hinfo->nid,
28fba950 3600 stream_tag, 0, format);
825315bc
IM		 3601
3602 return 0;
3603}
3604
3605static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3606 struct hda_codec *codec,
3607 struct snd_pcm_substream *substream)
3608{
3609 struct ca0132_spec *spec = codec->spec;
3610
3611 if (spec->dsp_state == DSP_DOWNLOADING)
3612 return 0;
3613
28fba950 3614 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
825315bc
IM		 3615 return 0;
3616}
3617
e8412ca4
DR		 3618static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3619 struct hda_codec *codec,
3620 struct snd_pcm_substream *substream)
3621{
3622 struct ca0132_spec *spec = codec->spec;
3623 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
3624 struct snd_pcm_runtime *runtime = substream->runtime;
3625
3626 if (spec->dsp_state != DSP_DOWNLOADED)
3627 return 0;
3628
3629 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3630 latency += DSP_CRYSTAL_VOICE_LATENCY;
3631
3632 return (latency * runtime->rate) / 1000;
3633}
3634
e90f29e4
IM		 3635/*
3636 * Controls stuffs.
3637 */
3638
3639/*
3640 * Mixer controls helpers.
3641 */
3642#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
3643 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3644 .name = xname, \
3645 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3646 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3647 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3648 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3649 .info = ca0132_volume_info, \
3650 .get = ca0132_volume_get, \
3651 .put = ca0132_volume_put, \
3652 .tlv = { .c = ca0132_volume_tlv }, \
3653 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3654
017310fb
CM		 3655/*
3656 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
3657 * volume put, which is used for setting the DSP volume. This was done because
3658 * the ca0132 functions were taking too much time and causing lag.
3659 */
3660#define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
3661 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3662 .name = xname, \
3663 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3664 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3665 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3666 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3667 .info = snd_hda_mixer_amp_volume_info, \
3668 .get = snd_hda_mixer_amp_volume_get, \
3669 .put = ca0132_alt_volume_put, \
3670 .tlv = { .c = snd_hda_mixer_amp_tlv }, \
3671 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3672
e90f29e4
IM		 3673#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
3674 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3675 .name = xname, \
3676 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3677 .info = snd_hda_mixer_amp_switch_info, \
3678 .get = ca0132_switch_get, \
3679 .put = ca0132_switch_put, \
3680 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3681
3682/* stereo */
3683#define CA0132_CODEC_VOL(xname, nid, dir) \
3684 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
017310fb
CM		 3685#define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
3686 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
e90f29e4
IM		 3687#define CA0132_CODEC_MUTE(xname, nid, dir) \
3688 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
3689
017310fb
CM		 3690/* lookup tables */
3691/*
3692 * Lookup table with decibel values for the DSP. When volume is changed in
3693 * Windows, the DSP is also sent the dB value in floating point. In Windows,
3694 * these values have decimal points, probably because the Windows driver
3695 * actually uses floating point. We can't here, so I made a lookup table of
3696 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
3697 * DAC's, and 9 is the maximum.
3698 */
3699static const unsigned int float_vol_db_lookup[] = {
37000xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
37010xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
37020xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
37030xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
37040xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
37050xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
37060xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
37070xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
37080xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
37090xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
37100xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
37110xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
37120xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
37130xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
37140xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
37150x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
37160x40C00000, 0x40E00000, 0x41000000, 0x41100000
3717};
3718
47cdf76e
CM		 3719/*
3720 * This table counts from float 0 to 1 in increments of .01, which is
3721 * useful for a few different sliders.
3722 */
3723static const unsigned int float_zero_to_one_lookup[] = {
37240x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
37250x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
37260x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
37270x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
37280x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
37290x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
37300x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
37310x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
37320x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
37330x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
37340x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
37350x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
37360x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
37370x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
37380x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
37390x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
37400x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3741};
3742
3743/*
3744 * This table counts from float 10 to 1000, which is the range of the x-bass
3745 * crossover slider in Windows.
3746 */
3747static const unsigned int float_xbass_xover_lookup[] = {
37480x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
37490x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
37500x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
37510x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
37520x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
37530x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
37540x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
37550x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
37560x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
37570x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
37580x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
37590x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
37600x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
37610x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
37620x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
37630x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
37640x44728000, 0x44750000, 0x44778000, 0x447A0000
3765};
3766
4091fb95 3767/* The following are for tuning of products */
44f0c978
IM		 3768#ifdef ENABLE_TUNING_CONTROLS
3769
3770static unsigned int voice_focus_vals_lookup[] = {
37710x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
37720x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
37730x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
37740x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
37750x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
37760x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
37770x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
37780x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
37790x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
37800x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
37810x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
37820x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
37830x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
37840x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
37850x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
37860x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
37870x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
37880x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
37890x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
37900x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
37910x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
37920x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
37930x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
37940x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
37950x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
37960x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
37970x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
3798};
3799
3800static unsigned int mic_svm_vals_lookup[] = {
38010x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
38020x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
38030x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
38040x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
38050x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
38060x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
38070x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
38080x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
38090x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
38100x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
38110x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
38120x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
38130x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
38140x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
38150x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
38160x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
38170x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3818};
3819
3820static unsigned int equalizer_vals_lookup[] = {
38210xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
38220xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
38230xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
38240xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
38250x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
38260x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
38270x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
38280x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
38290x41C00000
3830};
3831
3832static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
3833 unsigned int *lookup, int idx)
3834{
3835 int i = 0;
3836
3837 for (i = 0; i < TUNING_CTLS_COUNT; i++)
3838 if (nid == ca0132_tuning_ctls[i].nid)
3839 break;
3840
3841 snd_hda_power_up(codec);
447fd8e9 3842 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
44f0c978
IM		 3843 ca0132_tuning_ctls[i].req,
3844 &(lookup[idx]), sizeof(unsigned int));
3845 snd_hda_power_down(codec);
3846
3847 return 1;
3848}
3849
3850static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
3851 struct snd_ctl_elem_value *ucontrol)
3852{
3853 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3854 struct ca0132_spec *spec = codec->spec;
3855 hda_nid_t nid = get_amp_nid(kcontrol);
3856 long *valp = ucontrol->value.integer.value;
3857 int idx = nid - TUNING_CTL_START_NID;
3858
3859 *valp = spec->cur_ctl_vals[idx];
3860 return 0;
3861}
3862
3863static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
3864 struct snd_ctl_elem_info *uinfo)
3865{
3866 int chs = get_amp_channels(kcontrol);
3867 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3868 uinfo->count = chs == 3 ? 2 : 1;
3869 uinfo->value.integer.min = 20;
3870 uinfo->value.integer.max = 180;
3871 uinfo->value.integer.step = 1;
3872
3873 return 0;
3874}
3875
3876static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
3877 struct snd_ctl_elem_value *ucontrol)
3878{
3879 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3880 struct ca0132_spec *spec = codec->spec;
3881 hda_nid_t nid = get_amp_nid(kcontrol);
3882 long *valp = ucontrol->value.integer.value;
3883 int idx;
3884
3885 idx = nid - TUNING_CTL_START_NID;
3886 /* any change? */
3887 if (spec->cur_ctl_vals[idx] == *valp)
3888 return 0;
3889
3890 spec->cur_ctl_vals[idx] = *valp;
3891
3892 idx = *valp - 20;
3893 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3894
3895 return 1;
3896}
3897
3898static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3899 struct snd_ctl_elem_info *uinfo)
3900{
3901 int chs = get_amp_channels(kcontrol);
3902 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3903 uinfo->count = chs == 3 ? 2 : 1;
3904 uinfo->value.integer.min = 0;
3905 uinfo->value.integer.max = 100;
3906 uinfo->value.integer.step = 1;
3907
3908 return 0;
3909}
3910
3911static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3912 struct snd_ctl_elem_value *ucontrol)
3913{
3914 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3915 struct ca0132_spec *spec = codec->spec;
3916 hda_nid_t nid = get_amp_nid(kcontrol);
3917 long *valp = ucontrol->value.integer.value;
3918 int idx;
3919
3920 idx = nid - TUNING_CTL_START_NID;
3921 /* any change? */
3922 if (spec->cur_ctl_vals[idx] == *valp)
3923 return 0;
3924
3925 spec->cur_ctl_vals[idx] = *valp;
3926
3927 idx = *valp;
3928 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3929
3930 return 0;
3931}
3932
3933static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3934 struct snd_ctl_elem_info *uinfo)
3935{
3936 int chs = get_amp_channels(kcontrol);
3937 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3938 uinfo->count = chs == 3 ? 2 : 1;
3939 uinfo->value.integer.min = 0;
3940 uinfo->value.integer.max = 48;
3941 uinfo->value.integer.step = 1;
3942
3943 return 0;
3944}
3945
3946static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3947 struct snd_ctl_elem_value *ucontrol)
3948{
3949 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3950 struct ca0132_spec *spec = codec->spec;
3951 hda_nid_t nid = get_amp_nid(kcontrol);
3952 long *valp = ucontrol->value.integer.value;
3953 int idx;
3954
3955 idx = nid - TUNING_CTL_START_NID;
3956 /* any change? */
3957 if (spec->cur_ctl_vals[idx] == *valp)
3958 return 0;
3959
3960 spec->cur_ctl_vals[idx] = *valp;
3961
3962 idx = *valp;
3963 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3964
3965 return 1;
3966}
3967
8e142e9e
TS		 3968static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3969static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
44f0c978
IM		 3970
3971static int add_tuning_control(struct hda_codec *codec,
3972 hda_nid_t pnid, hda_nid_t nid,
3973 const char *name, int dir)
3974{
975cc02a 3975 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
44f0c978
IM		 3976 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3977 struct snd_kcontrol_new knew =
3978 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3979
3980 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3981 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3982 knew.tlv.c = 0;
3983 knew.tlv.p = 0;
3984 switch (pnid) {
3985 case VOICE_FOCUS:
3986 knew.info = voice_focus_ctl_info;
3987 knew.get = tuning_ctl_get;
3988 knew.put = voice_focus_ctl_put;
3989 knew.tlv.p = voice_focus_db_scale;
3990 break;
3991 case MIC_SVM:
3992 knew.info = mic_svm_ctl_info;
3993 knew.get = tuning_ctl_get;
3994 knew.put = mic_svm_ctl_put;
3995 break;
3996 case EQUALIZER:
3997 knew.info = equalizer_ctl_info;
3998 knew.get = tuning_ctl_get;
3999 knew.put = equalizer_ctl_put;
4000 knew.tlv.p = eq_db_scale;
4001 break;
4002 default:
4003 return 0;
4004 }
4005 knew.private_value =
4006 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
4007 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
4008 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
4009}
4010
4011static int add_tuning_ctls(struct hda_codec *codec)
4012{
4013 int i;
4014 int err;
4015
4016 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
4017 err = add_tuning_control(codec,
4018 ca0132_tuning_ctls[i].parent_nid,
4019 ca0132_tuning_ctls[i].nid,
4020 ca0132_tuning_ctls[i].name,
4021 ca0132_tuning_ctls[i].direct);
4022 if (err < 0)
4023 return err;
4024 }
4025
4026 return 0;
4027}
4028
4029static void ca0132_init_tuning_defaults(struct hda_codec *codec)
4030{
4031 struct ca0132_spec *spec = codec->spec;
4032 int i;
4033
4034 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
4035 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
4036 /* SVM level defaults to 0.74. */
4037 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
4038
4039 /* EQ defaults to 0dB. */
4040 for (i = 2; i < TUNING_CTLS_COUNT; i++)
4041 spec->cur_ctl_vals[i] = 24;
4042}
4043#endif /*ENABLE_TUNING_CONTROLS*/
4044
5aaca44d
IM		 4045/*
4046 * Select the active output.
4047 * If autodetect is enabled, output will be selected based on jack detection.
4048 * If jack inserted, headphone will be selected, else built-in speakers
4049 * If autodetect is disabled, output will be selected based on selection.
4050 */
4051static int ca0132_select_out(struct hda_codec *codec)
4052{
4053 struct ca0132_spec *spec = codec->spec;
4054 unsigned int pin_ctl;
4055 int jack_present;
4056 int auto_jack;
4057 unsigned int tmp;
4058 int err;
4059
4e76a883 4060 codec_dbg(codec, "ca0132_select_out\n");
5aaca44d 4061
664c7155 4062 snd_hda_power_up_pm(codec);
5aaca44d
IM		 4063
4064 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4065
4066 if (auto_jack)
fe14f39e 4067 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
5aaca44d
IM		 4068 else
4069 jack_present =
4070 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
4071
4072 if (jack_present)
4073 spec->cur_out_type = HEADPHONE_OUT;
4074 else
4075 spec->cur_out_type = SPEAKER_OUT;
4076
4077 if (spec->cur_out_type == SPEAKER_OUT) {
4e76a883 4078 codec_dbg(codec, "ca0132_select_out speaker\n");
5aaca44d
IM		 4079 /*speaker out config*/
4080 tmp = FLOAT_ONE;
4081 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4082 if (err < 0)
4083 goto exit;
4084 /*enable speaker EQ*/
4085 tmp = FLOAT_ONE;
4086 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4087 if (err < 0)
4088 goto exit;
4089
4090 /* Setup EAPD */
4091 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4092 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4093 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4094 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4095 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4096 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4097 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4098 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4099
4100 /* disable headphone node */
4101 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4102 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4103 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4104 pin_ctl & ~PIN_HP);
5aaca44d
IM		 4105 /* enable speaker node */
4106 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
8a19bcee 4107 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4108 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4109 pin_ctl | PIN_OUT);
5aaca44d 4110 } else {
4e76a883 4111 codec_dbg(codec, "ca0132_select_out hp\n");
5aaca44d
IM		 4112 /*headphone out config*/
4113 tmp = FLOAT_ZERO;
4114 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4115 if (err < 0)
4116 goto exit;
4117 /*disable speaker EQ*/
4118 tmp = FLOAT_ZERO;
4119 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4120 if (err < 0)
4121 goto exit;
4122
4123 /* Setup EAPD */
4124 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4125 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4126 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4127 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4128 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4129 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4130 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4131 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4132
4133 /* disable speaker*/
4134 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4135 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4136 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4137 pin_ctl & ~PIN_HP);
5aaca44d
IM		 4138 /* enable headphone*/
4139 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4140 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4141 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4142 pin_ctl | PIN_HP);
5aaca44d
IM		 4143 }
4144
4145exit:
664c7155 4146 snd_hda_power_down_pm(codec);
5aaca44d
IM		 4147
4148 return err < 0 ? err : 0;
4149}
4150
212de2e7 4151static int ae5_headphone_gain_set(struct hda_codec *codec, long val);
d51434d4 4152static int zxr_headphone_gain_set(struct hda_codec *codec, long val);
8e6bc6b3 4153static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
212de2e7 4154
2283c85b
CM		 4155static void ae5_mmio_select_out(struct hda_codec *codec)
4156{
4157 struct ca0132_spec *spec = codec->spec;
4158 unsigned int i;
4159
4160 for (i = 0; i < AE5_CA0113_OUT_SET_COMMANDS; i++)
4161 ca0113_mmio_command_set(codec,
4162 ae5_ca0113_output_presets[spec->cur_out_type].group[i],
4163 ae5_ca0113_output_presets[spec->cur_out_type].target[i],
4164 ae5_ca0113_output_presets[spec->cur_out_type].vals[i]);
4165}
4166
746fc9de
CM		 4167/*
4168 * These are the commands needed to setup output on each of the different card
4169 * types.
4170 */
4171static void ca0132_alt_select_out_quirk_handler(struct hda_codec *codec)
4172{
4173 struct ca0132_spec *spec = codec->spec;
2283c85b 4174 unsigned int tmp;
746fc9de
CM		 4175
4176 switch (spec->cur_out_type) {
4177 case SPEAKER_OUT:
6da8f446 4178 switch (ca0132_quirk(spec)) {
746fc9de
CM		 4179 case QUIRK_SBZ:
4180 ca0113_mmio_gpio_set(codec, 7, false);
4181 ca0113_mmio_gpio_set(codec, 4, true);
4182 ca0113_mmio_gpio_set(codec, 1, true);
2283c85b 4183 chipio_set_control_param(codec, 0x0d, 0x18);
746fc9de 4184 break;
55845949
CM		 4185 case QUIRK_ZXR:
4186 ca0113_mmio_gpio_set(codec, 2, true);
4187 ca0113_mmio_gpio_set(codec, 3, true);
4188 ca0113_mmio_gpio_set(codec, 5, false);
d51434d4 4189 zxr_headphone_gain_set(codec, 0);
55845949
CM		 4190 chipio_set_control_param(codec, 0x0d, 0x24);
4191 break;
746fc9de 4192 case QUIRK_R3DI:
2283c85b 4193 chipio_set_control_param(codec, 0x0d, 0x24);
746fc9de
CM		 4194 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4195 break;
4196 case QUIRK_R3D:
2283c85b 4197 chipio_set_control_param(codec, 0x0d, 0x24);
746fc9de
CM		 4198 ca0113_mmio_gpio_set(codec, 1, true);
4199 break;
2283c85b
CM		 4200 case QUIRK_AE5:
4201 ae5_mmio_select_out(codec);
212de2e7 4202 ae5_headphone_gain_set(codec, 2);
2283c85b
CM		 4203 tmp = FLOAT_ZERO;
4204 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4205 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4206 chipio_set_control_param(codec, 0x0d, 0xa4);
4207 chipio_write(codec, 0x18b03c, 0x00000012);
4208 break;
6da8f446
TI		 4209 default:
4210 break;
746fc9de
CM		 4211 }
4212 break;
4213 case HEADPHONE_OUT:
6da8f446 4214 switch (ca0132_quirk(spec)) {
746fc9de
CM		 4215 case QUIRK_SBZ:
4216 ca0113_mmio_gpio_set(codec, 7, true);
4217 ca0113_mmio_gpio_set(codec, 4, true);
4218 ca0113_mmio_gpio_set(codec, 1, false);
2283c85b 4219 chipio_set_control_param(codec, 0x0d, 0x12);
746fc9de 4220 break;
55845949
CM		 4221 case QUIRK_ZXR:
4222 ca0113_mmio_gpio_set(codec, 2, false);
4223 ca0113_mmio_gpio_set(codec, 3, false);
4224 ca0113_mmio_gpio_set(codec, 5, true);
d51434d4 4225 zxr_headphone_gain_set(codec, spec->zxr_gain_set);
55845949
CM		 4226 chipio_set_control_param(codec, 0x0d, 0x21);
4227 break;
746fc9de 4228 case QUIRK_R3DI:
2283c85b 4229 chipio_set_control_param(codec, 0x0d, 0x21);
746fc9de
CM		 4230 r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT);
4231 break;
4232 case QUIRK_R3D:
2283c85b 4233 chipio_set_control_param(codec, 0x0d, 0x21);
746fc9de
CM		 4234 ca0113_mmio_gpio_set(codec, 0x1, false);
4235 break;
2283c85b
CM		 4236 case QUIRK_AE5:
4237 ae5_mmio_select_out(codec);
212de2e7
CM		 4238 ae5_headphone_gain_set(codec,
4239 spec->ae5_headphone_gain_val);
2283c85b
CM		 4240 tmp = FLOAT_ONE;
4241 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4242 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4243 chipio_set_control_param(codec, 0x0d, 0xa1);
4244 chipio_write(codec, 0x18b03c, 0x00000012);
4245 break;
6da8f446
TI		 4246 default:
4247 break;
746fc9de
CM		 4248 }
4249 break;
4250 case SURROUND_OUT:
6da8f446 4251 switch (ca0132_quirk(spec)) {
746fc9de
CM		 4252 case QUIRK_SBZ:
4253 ca0113_mmio_gpio_set(codec, 7, false);
4254 ca0113_mmio_gpio_set(codec, 4, true);
4255 ca0113_mmio_gpio_set(codec, 1, true);
2283c85b 4256 chipio_set_control_param(codec, 0x0d, 0x18);
746fc9de 4257 break;
55845949
CM		 4258 case QUIRK_ZXR:
4259 ca0113_mmio_gpio_set(codec, 2, true);
4260 ca0113_mmio_gpio_set(codec, 3, true);
4261 ca0113_mmio_gpio_set(codec, 5, false);
d51434d4 4262 zxr_headphone_gain_set(codec, 0);
55845949
CM		 4263 chipio_set_control_param(codec, 0x0d, 0x24);
4264 break;
746fc9de 4265 case QUIRK_R3DI:
2283c85b 4266 chipio_set_control_param(codec, 0x0d, 0x24);
746fc9de
CM		 4267 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4268 break;
4269 case QUIRK_R3D:
4270 ca0113_mmio_gpio_set(codec, 1, true);
2283c85b
CM		 4271 chipio_set_control_param(codec, 0x0d, 0x24);
4272 break;
4273 case QUIRK_AE5:
4274 ae5_mmio_select_out(codec);
212de2e7 4275 ae5_headphone_gain_set(codec, 2);
2283c85b
CM		 4276 tmp = FLOAT_ZERO;
4277 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4278 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4279 chipio_set_control_param(codec, 0x0d, 0xa4);
4280 chipio_write(codec, 0x18b03c, 0x00000012);
746fc9de 4281 break;
6da8f446
TI		 4282 default:
4283 break;
746fc9de
CM		 4284 }
4285 break;
4286 }
4287}
4288
7cb9d94c
CM		 4289/*
4290 * This function behaves similarly to the ca0132_select_out funciton above,
4291 * except with a few differences. It adds the ability to select the current
4292 * output with an enumerated control "output source" if the auto detect
4293 * mute switch is set to off. If the auto detect mute switch is enabled, it
4294 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
4295 * It also adds the ability to auto-detect the front headphone port. The only
4296 * way to select surround is to disable auto detect, and set Surround with the
4297 * enumerated control.
4298 */
4299static int ca0132_alt_select_out(struct hda_codec *codec)
4300{
4301 struct ca0132_spec *spec = codec->spec;
4302 unsigned int pin_ctl;
4303 int jack_present;
4304 int auto_jack;
4305 unsigned int i;
4306 unsigned int tmp;
4307 int err;
4308 /* Default Headphone is rear headphone */
4309 hda_nid_t headphone_nid = spec->out_pins[1];
4310
4311 codec_dbg(codec, "%s\n", __func__);
4312
4313 snd_hda_power_up_pm(codec);
4314
4315 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4316
4317 /*
4318 * If headphone rear or front is plugged in, set to headphone.
4319 * If neither is plugged in, set to rear line out. Only if
4320 * hp/speaker auto detect is enabled.
4321 */
4322 if (auto_jack) {
4323 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
4324 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
4325
4326 if (jack_present)
4327 spec->cur_out_type = HEADPHONE_OUT;
4328 else
4329 spec->cur_out_type = SPEAKER_OUT;
4330 } else
4331 spec->cur_out_type = spec->out_enum_val;
4332
4333 /* Begin DSP output switch */
4334 tmp = FLOAT_ONE;
4335 err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp);
4336 if (err < 0)
4337 goto exit;
4338
746fc9de
CM		 4339 ca0132_alt_select_out_quirk_handler(codec);
4340
7cb9d94c
CM		 4341 switch (spec->cur_out_type) {
4342 case SPEAKER_OUT:
4343 codec_dbg(codec, "%s speaker\n", __func__);
7cb9d94c
CM		 4344
4345 /* disable headphone node */
4346 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4347 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4348 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4349 pin_ctl & ~PIN_HP);
4350 /* enable line-out node */
4351 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4352 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4353 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4354 pin_ctl | PIN_OUT);
4355 /* Enable EAPD */
4356 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4357 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4358
4359 /* If PlayEnhancement is enabled, set different source */
4360 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4361 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4362 else
4363 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4364 break;
4365 case HEADPHONE_OUT:
4366 codec_dbg(codec, "%s hp\n", __func__);
7cb9d94c
CM		 4367
4368 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4369 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4370
4371 /* disable speaker*/
4372 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4373 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4374 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4375 pin_ctl & ~PIN_HP);
4376
4377 /* enable headphone, either front or rear */
4378
4379 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4380 headphone_nid = spec->out_pins[2];
4381 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4382 headphone_nid = spec->out_pins[1];
4383
4384 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0,
4385 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4386 snd_hda_set_pin_ctl(codec, headphone_nid,
4387 pin_ctl | PIN_HP);
4388
4389 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4390 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4391 else
4392 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4393 break;
4394 case SURROUND_OUT:
4395 codec_dbg(codec, "%s surround\n", __func__);
746fc9de 4396
7cb9d94c
CM		 4397 /* enable line out node */
4398 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4399 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4400 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4401 pin_ctl | PIN_OUT);
4402 /* Disable headphone out */
4403 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4404 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4405 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4406 pin_ctl & ~PIN_HP);
4407 /* Enable EAPD on line out */
4408 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4409 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4410 /* enable center/lfe out node */
4411 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0,
4412 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4413 snd_hda_set_pin_ctl(codec, spec->out_pins[2],
4414 pin_ctl | PIN_OUT);
4415 /* Now set rear surround node as out. */
4416 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0,
4417 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4418 snd_hda_set_pin_ctl(codec, spec->out_pins[3],
4419 pin_ctl | PIN_OUT);
4420
8e6bc6b3 4421 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
7cb9d94c
CM		 4422 break;
4423 }
8e6bc6b3
CM		 4424 /*
4425 * Surround always sets it's scp command to req 0x04 to FLOAT_EIGHT.
4426 * With this set though, X_BASS cannot be enabled. So, if we have OutFX
4427 * enabled, we need to make sure X_BASS is off, otherwise everything
4428 * sounds all muffled. Running ca0132_effects_set with X_BASS as the
4429 * effect should sort this out.
4430 */
4431 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4432 ca0132_effects_set(codec, X_BASS,
4433 spec->effects_switch[X_BASS - EFFECT_START_NID]);
7cb9d94c 4434
2283c85b 4435 /* run through the output dsp commands for the selected output. */
7cb9d94c
CM		 4436 for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) {
4437 err = dspio_set_uint_param(codec,
4438 alt_out_presets[spec->cur_out_type].mids[i],
4439 alt_out_presets[spec->cur_out_type].reqs[i],
4440 alt_out_presets[spec->cur_out_type].vals[i]);
4441
4442 if (err < 0)
4443 goto exit;
4444 }
4445
4446exit:
4447 snd_hda_power_down_pm(codec);
4448
4449 return err < 0 ? err : 0;
4450}
4451
993884f6
CCC		 4452static void ca0132_unsol_hp_delayed(struct work_struct *work)
4453{
4454 struct ca0132_spec *spec = container_of(
4455 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
f8fb1170
TI		 4456 struct hda_jack_tbl *jack;
4457
6da8f446 4458 if (ca0132_use_alt_functions(spec))
7cb9d94c
CM		 4459 ca0132_alt_select_out(spec->codec);
4460 else
4461 ca0132_select_out(spec->codec);
4462
d5c016b5 4463 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
f8fb1170
TI		 4464 if (jack) {
4465 jack->block_report = 0;
4466 snd_hda_jack_report_sync(spec->codec);
4467 }
993884f6
CCC		 4468}
4469
5aaca44d
IM		 4470static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4471static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
e0026d03
CM		 4472static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4473static int stop_mic1(struct hda_codec *codec);
4474static int ca0132_cvoice_switch_set(struct hda_codec *codec);
47cdf76e 4475static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
5aaca44d
IM		 4476
4477/*
4478 * Select the active VIP source
4479 */
4480static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4481{
4482 struct ca0132_spec *spec = codec->spec;
4483 unsigned int tmp;
4484
e8f1bd5d 4485 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 4486 return 0;
4487
4488 /* if CrystalVoice if off, vipsource should be 0 */
4489 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4490 (val == 0)) {
4491 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4492 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4493 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4494 if (spec->cur_mic_type == DIGITAL_MIC)
4495 tmp = FLOAT_TWO;
4496 else
4497 tmp = FLOAT_ONE;
4498 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4499 tmp = FLOAT_ZERO;
4500 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4501 } else {
4502 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4503 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4504 if (spec->cur_mic_type == DIGITAL_MIC)
4505 tmp = FLOAT_TWO;
4506 else
4507 tmp = FLOAT_ONE;
4508 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4509 tmp = FLOAT_ONE;
4510 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4511 msleep(20);
4512 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4513 }
4514
4515 return 1;
4516}
4517
e0026d03
CM		 4518static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4519{
4520 struct ca0132_spec *spec = codec->spec;
4521 unsigned int tmp;
4522
4523 if (spec->dsp_state != DSP_DOWNLOADED)
4524 return 0;
4525
4526 codec_dbg(codec, "%s\n", __func__);
4527
4528 chipio_set_stream_control(codec, 0x03, 0);
4529 chipio_set_stream_control(codec, 0x04, 0);
4530
4531 /* if CrystalVoice is off, vipsource should be 0 */
4532 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4533 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4534 codec_dbg(codec, "%s: off.", __func__);
4535 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4536
4537 tmp = FLOAT_ZERO;
4538 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4539
4540 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4541 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6da8f446 4542 if (ca0132_quirk(spec) == QUIRK_R3DI)
e0026d03
CM		 4543 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4544
4545
4546 if (spec->in_enum_val == REAR_LINE_IN)
4547 tmp = FLOAT_ZERO;
4548 else {
6da8f446 4549 if (ca0132_quirk(spec) == QUIRK_SBZ)
e0026d03
CM		 4550 tmp = FLOAT_THREE;
4551 else
4552 tmp = FLOAT_ONE;
4553 }
4554
4555 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4556
4557 } else {
4558 codec_dbg(codec, "%s: on.", __func__);
4559 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4560 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
6da8f446 4561 if (ca0132_quirk(spec) == QUIRK_R3DI)
e0026d03
CM		 4562 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4563
4564 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
4565 tmp = FLOAT_TWO;
4566 else
4567 tmp = FLOAT_ONE;
4568 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4569
4570 tmp = FLOAT_ONE;
4571 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4572
4573 msleep(20);
4574 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4575 }
4576
4577 chipio_set_stream_control(codec, 0x03, 1);
4578 chipio_set_stream_control(codec, 0x04, 1);
4579
4580 return 1;
4581}
4582
5aaca44d
IM		 4583/*
4584 * Select the active microphone.
4585 * If autodetect is enabled, mic will be selected based on jack detection.
4586 * If jack inserted, ext.mic will be selected, else built-in mic
4587 * If autodetect is disabled, mic will be selected based on selection.
4588 */
4589static int ca0132_select_mic(struct hda_codec *codec)
4590{
4591 struct ca0132_spec *spec = codec->spec;
4592 int jack_present;
4593 int auto_jack;
4594
4e76a883 4595 codec_dbg(codec, "ca0132_select_mic\n");
5aaca44d 4596
664c7155 4597 snd_hda_power_up_pm(codec);
5aaca44d
IM		 4598
4599 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4600
4601 if (auto_jack)
fe14f39e 4602 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5aaca44d
IM		 4603 else
4604 jack_present =
4605 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
4606
4607 if (jack_present)
4608 spec->cur_mic_type = LINE_MIC_IN;
4609 else
4610 spec->cur_mic_type = DIGITAL_MIC;
4611
4612 if (spec->cur_mic_type == DIGITAL_MIC) {
4613 /* enable digital Mic */
4614 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
4615 ca0132_set_dmic(codec, 1);
4616 ca0132_mic_boost_set(codec, 0);
4617 /* set voice focus */
4618 ca0132_effects_set(codec, VOICE_FOCUS,
4619 spec->effects_switch
4620 [VOICE_FOCUS - EFFECT_START_NID]);
4621 } else {
4622 /* disable digital Mic */
4623 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
4624 ca0132_set_dmic(codec, 0);
4625 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
4626 /* disable voice focus */
4627 ca0132_effects_set(codec, VOICE_FOCUS, 0);
4628 }
4629
664c7155 4630 snd_hda_power_down_pm(codec);
5aaca44d
IM		 4631
4632 return 0;
4633}
4634
7cb9d94c
CM		 4635/*
4636 * Select the active input.
4637 * Mic detection isn't used, because it's kind of pointless on the SBZ.
4638 * The front mic has no jack-detection, so the only way to switch to it
4639 * is to do it manually in alsamixer.
4640 */
4641static int ca0132_alt_select_in(struct hda_codec *codec)
4642{
4643 struct ca0132_spec *spec = codec->spec;
4644 unsigned int tmp;
4645
4646 codec_dbg(codec, "%s\n", __func__);
4647
4648 snd_hda_power_up_pm(codec);
4649
4650 chipio_set_stream_control(codec, 0x03, 0);
4651 chipio_set_stream_control(codec, 0x04, 0);
4652
4653 spec->cur_mic_type = spec->in_enum_val;
4654
4655 switch (spec->cur_mic_type) {
4656 case REAR_MIC:
6da8f446 4657 switch (ca0132_quirk(spec)) {
7cb9d94c 4658 case QUIRK_SBZ:
42aa3a16 4659 case QUIRK_R3D:
b9b41345 4660 ca0113_mmio_gpio_set(codec, 0, false);
7cb9d94c
CM		 4661 tmp = FLOAT_THREE;
4662 break;
55845949
CM		 4663 case QUIRK_ZXR:
4664 tmp = FLOAT_THREE;
4665 break;
7cb9d94c
CM		 4666 case QUIRK_R3DI:
4667 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4668 tmp = FLOAT_ONE;
4669 break;
f231daaf
CM		 4670 case QUIRK_AE5:
4671 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x00);
4672 tmp = FLOAT_THREE;
4673 break;
7cb9d94c
CM		 4674 default:
4675 tmp = FLOAT_ONE;
4676 break;
4677 }
4678
4679 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4680 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6da8f446 4681 if (ca0132_quirk(spec) == QUIRK_R3DI)
7cb9d94c
CM		 4682 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4683
4684 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4685
4686 chipio_set_stream_control(codec, 0x03, 1);
4687 chipio_set_stream_control(codec, 0x04, 1);
6da8f446 4688 switch (ca0132_quirk(spec)) {
f231daaf 4689 case QUIRK_SBZ:
7cb9d94c
CM		 4690 chipio_write(codec, 0x18B098, 0x0000000C);
4691 chipio_write(codec, 0x18B09C, 0x0000000C);
f231daaf 4692 break;
55845949
CM		 4693 case QUIRK_ZXR:
4694 chipio_write(codec, 0x18B098, 0x0000000C);
4695 chipio_write(codec, 0x18B09C, 0x000000CC);
4696 break;
f231daaf
CM		 4697 case QUIRK_AE5:
4698 chipio_write(codec, 0x18B098, 0x0000000C);
4699 chipio_write(codec, 0x18B09C, 0x0000004C);
4700 break;
6da8f446
TI		 4701 default:
4702 break;
7cb9d94c 4703 }
47cdf76e 4704 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
7cb9d94c
CM		 4705 break;
4706 case REAR_LINE_IN:
4707 ca0132_mic_boost_set(codec, 0);
6da8f446 4708 switch (ca0132_quirk(spec)) {
7cb9d94c 4709 case QUIRK_SBZ:
42aa3a16 4710 case QUIRK_R3D:
b9b41345 4711 ca0113_mmio_gpio_set(codec, 0, false);
7cb9d94c
CM		 4712 break;
4713 case QUIRK_R3DI:
4714 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4715 break;
f231daaf
CM		 4716 case QUIRK_AE5:
4717 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x00);
4718 break;
6da8f446
TI		 4719 default:
4720 break;
7cb9d94c
CM		 4721 }
4722
4723 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4724 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6da8f446 4725 if (ca0132_quirk(spec) == QUIRK_R3DI)
7cb9d94c
CM		 4726 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4727
4728 tmp = FLOAT_ZERO;
4729 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4730
6da8f446 4731 switch (ca0132_quirk(spec)) {
f231daaf
CM		 4732 case QUIRK_SBZ:
4733 case QUIRK_AE5:
7cb9d94c
CM		 4734 chipio_write(codec, 0x18B098, 0x00000000);
4735 chipio_write(codec, 0x18B09C, 0x00000000);
f231daaf 4736 break;
6da8f446
TI		 4737 default:
4738 break;
7cb9d94c 4739 }
7cb9d94c
CM		 4740 chipio_set_stream_control(codec, 0x03, 1);
4741 chipio_set_stream_control(codec, 0x04, 1);
4742 break;
4743 case FRONT_MIC:
6da8f446 4744 switch (ca0132_quirk(spec)) {
7cb9d94c 4745 case QUIRK_SBZ:
42aa3a16 4746 case QUIRK_R3D:
b9b41345
CM		 4747 ca0113_mmio_gpio_set(codec, 0, true);
4748 ca0113_mmio_gpio_set(codec, 5, false);
7cb9d94c
CM		 4749 tmp = FLOAT_THREE;
4750 break;
4751 case QUIRK_R3DI:
4752 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
4753 tmp = FLOAT_ONE;
4754 break;
f231daaf
CM		 4755 case QUIRK_AE5:
4756 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x3f);
4757 tmp = FLOAT_THREE;
4758 break;
7cb9d94c
CM		 4759 default:
4760 tmp = FLOAT_ONE;
4761 break;
4762 }
4763
4764 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4765 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6da8f446 4766 if (ca0132_quirk(spec) == QUIRK_R3DI)
7cb9d94c
CM		 4767 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4768
4769 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4770
4771 chipio_set_stream_control(codec, 0x03, 1);
4772 chipio_set_stream_control(codec, 0x04, 1);
4773
6da8f446 4774 switch (ca0132_quirk(spec)) {
f231daaf 4775 case QUIRK_SBZ:
7cb9d94c
CM		 4776 chipio_write(codec, 0x18B098, 0x0000000C);
4777 chipio_write(codec, 0x18B09C, 0x000000CC);
f231daaf
CM		 4778 break;
4779 case QUIRK_AE5:
4780 chipio_write(codec, 0x18B098, 0x0000000C);
4781 chipio_write(codec, 0x18B09C, 0x0000004C);
4782 break;
6da8f446
TI		 4783 default:
4784 break;
7cb9d94c 4785 }
47cdf76e 4786 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
7cb9d94c
CM		 4787 break;
4788 }
e0026d03 4789 ca0132_cvoice_switch_set(codec);
7cb9d94c
CM		 4790
4791 snd_hda_power_down_pm(codec);
4792 return 0;
7cb9d94c
CM		 4793}
4794
a7e76271
IM		 4795/*
4796 * Check if VNODE settings take effect immediately.
4797 */
4798static bool ca0132_is_vnode_effective(struct hda_codec *codec,
4799 hda_nid_t vnid,
4800 hda_nid_t *shared_nid)
4801{
4802 struct ca0132_spec *spec = codec->spec;
4803 hda_nid_t nid;
a7e76271
IM		 4804
4805 switch (vnid) {
4806 case VNID_SPK:
4807 nid = spec->shared_out_nid;
a7e76271
IM		 4808 break;
4809 case VNID_MIC:
4810 nid = spec->shared_mic_nid;
a7e76271
IM		 4811 break;
4812 default:
9a0869f4 4813 return false;
a7e76271
IM		 4814 }
4815
9a0869f4 4816 if (shared_nid)
a7e76271
IM		 4817 *shared_nid = nid;
4818
9a0869f4 4819 return true;
a7e76271
IM		 4820}
4821
4822/*
4823* The following functions are control change helpers.
4824* They return 0 if no changed. Return 1 if changed.
4825*/
4826static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
4827{
4828 struct ca0132_spec *spec = codec->spec;
4829 unsigned int tmp;
4830
4831 /* based on CrystalVoice state to enable VoiceFX. */
4832 if (enable) {
4833 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
4834 FLOAT_ONE : FLOAT_ZERO;
4835 } else {
4836 tmp = FLOAT_ZERO;
4837 }
4838
4839 dspio_set_uint_param(codec, ca0132_voicefx.mid,
4840 ca0132_voicefx.reqs[0], tmp);
4841
4842 return 1;
4843}
4844
5aaca44d
IM		 4845/*
4846 * Set the effects parameters
4847 */
4848static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
4849{
4850 struct ca0132_spec *spec = codec->spec;
009b8f97 4851 unsigned int on, tmp;
5aaca44d
IM		 4852 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4853 int err = 0;
4854 int idx = nid - EFFECT_START_NID;
4855
4856 if ((idx < 0) || (idx >= num_fx))
4857 return 0; /* no changed */
4858
4859 /* for out effect, qualify with PE */
4860 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
4861 /* if PE if off, turn off out effects. */
4862 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4863 val = 0;
8e6bc6b3
CM		 4864 if (spec->cur_out_type == SURROUND_OUT && nid == X_BASS)
4865 val = 0;
5aaca44d
IM		 4866 }
4867
4868 /* for in effect, qualify with CrystalVoice */
4869 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
4870 /* if CrystalVoice if off, turn off in effects. */
4871 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4872 val = 0;
4873
4874 /* Voice Focus applies to 2-ch Mic, Digital Mic */
4875 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
4876 val = 0;
009b8f97
CM		 4877
4878 /* If Voice Focus on SBZ, set to two channel. */
6da8f446 4879 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec)
7cb9d94c 4880 && (spec->cur_mic_type != REAR_LINE_IN)) {
009b8f97
CM		 4881 if (spec->effects_switch[CRYSTAL_VOICE -
4882 EFFECT_START_NID]) {
4883
4884 if (spec->effects_switch[VOICE_FOCUS -
4885 EFFECT_START_NID]) {
4886 tmp = FLOAT_TWO;
4887 val = 1;
4888 } else
4889 tmp = FLOAT_ONE;
4890
4891 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4892 }
4893 }
4894 /*
4895 * For SBZ noise reduction, there's an extra command
4896 * to module ID 0x47. No clue why.
4897 */
6da8f446 4898 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec)
7cb9d94c 4899 && (spec->cur_mic_type != REAR_LINE_IN)) {
009b8f97
CM		 4900 if (spec->effects_switch[CRYSTAL_VOICE -
4901 EFFECT_START_NID]) {
4902 if (spec->effects_switch[NOISE_REDUCTION -
4903 EFFECT_START_NID])
4904 tmp = FLOAT_ONE;
4905 else
4906 tmp = FLOAT_ZERO;
4907 } else
4908 tmp = FLOAT_ZERO;
4909
4910 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
4911 }
7cb9d94c
CM		 4912
4913 /* If rear line in disable effects. */
6da8f446 4914 if (ca0132_use_alt_functions(spec) &&
7cb9d94c
CM		 4915 spec->in_enum_val == REAR_LINE_IN)
4916 val = 0;
5aaca44d
IM		 4917 }
4918
4e76a883 4919 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5aaca44d
IM		 4920 nid, val);
4921
4922 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
4923 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4924 ca0132_effects[idx].reqs[0], on);
4925
4926 if (err < 0)
4927 return 0; /* no changed */
4928
4929 return 1;
4930}
4931
a7e76271
IM		 4932/*
4933 * Turn on/off Playback Enhancements
4934 */
4935static int ca0132_pe_switch_set(struct hda_codec *codec)
4936{
4937 struct ca0132_spec *spec = codec->spec;
4938 hda_nid_t nid;
4939 int i, ret = 0;
4940
4e76a883 4941 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
a7e76271
IM		 4942 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
4943
6da8f446 4944 if (ca0132_use_alt_functions(spec))
7cb9d94c
CM		 4945 ca0132_alt_select_out(codec);
4946
a7e76271
IM		 4947 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
4948 nid = OUT_EFFECT_START_NID;
4949 /* PE affects all out effects */
4950 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
4951 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4952
4953 return ret;
4954}
4955
5aaca44d
IM		 4956/* Check if Mic1 is streaming, if so, stop streaming */
4957static int stop_mic1(struct hda_codec *codec)
4958{
4959 struct ca0132_spec *spec = codec->spec;
4960 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
4961 AC_VERB_GET_CONV, 0);
4962 if (oldval != 0)
4963 snd_hda_codec_write(codec, spec->adcs[0], 0,
4964 AC_VERB_SET_CHANNEL_STREAMID,
4965 0);
4966 return oldval;
4967}
4968
4969/* Resume Mic1 streaming if it was stopped. */
4970static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
4971{
4972 struct ca0132_spec *spec = codec->spec;
4973 /* Restore the previous stream and channel */
4974 if (oldval != 0)
4975 snd_hda_codec_write(codec, spec->adcs[0], 0,
4976 AC_VERB_SET_CHANNEL_STREAMID,
4977 oldval);
4978}
4979
4980/*
a7e76271 4981 * Turn on/off CrystalVoice
5aaca44d 4982 */
a7e76271
IM		 4983static int ca0132_cvoice_switch_set(struct hda_codec *codec)
4984{
4985 struct ca0132_spec *spec = codec->spec;
4986 hda_nid_t nid;
4987 int i, ret = 0;
4988 unsigned int oldval;
4989
4e76a883 4990 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
a7e76271
IM		 4991 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
4992
4993 i = IN_EFFECT_START_NID - EFFECT_START_NID;
4994 nid = IN_EFFECT_START_NID;
4995 /* CrystalVoice affects all in effects */
4996 for (; nid < IN_EFFECT_END_NID; nid++, i++)
4997 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4998
4999 /* including VoiceFX */
5000 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
5001
5002 /* set correct vipsource */
5003 oldval = stop_mic1(codec);
6da8f446 5004 if (ca0132_use_alt_functions(spec))
e0026d03
CM		 5005 ret |= ca0132_alt_set_vipsource(codec, 1);
5006 else
5007 ret |= ca0132_set_vipsource(codec, 1);
a7e76271
IM		 5008 resume_mic1(codec, oldval);
5009 return ret;
5010}
5011
5aaca44d
IM		 5012static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
5013{
5014 struct ca0132_spec *spec = codec->spec;
5015 int ret = 0;
5016
5017 if (val) /* on */
5018 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5019 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
5020 else /* off */
5021 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5022 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
5023
5024 return ret;
5025}
5026
47cdf76e
CM		 5027static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
5028{
5029 struct ca0132_spec *spec = codec->spec;
5030 int ret = 0;
5031
5032 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5033 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
5034 return ret;
5035}
5036
212de2e7
CM		 5037static int ae5_headphone_gain_set(struct hda_codec *codec, long val)
5038{
5039 unsigned int i;
5040
5041 for (i = 0; i < 4; i++)
5042 ca0113_mmio_command_set(codec, 0x48, 0x11 + i,
5043 ae5_headphone_gain_presets[val].vals[i]);
5044 return 0;
5045}
5046
d51434d4
CM		 5047/*
5048 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone
5049 * amplifier to handle a 600 ohm load.
5050 */
5051static int zxr_headphone_gain_set(struct hda_codec *codec, long val)
5052{
5053 ca0113_mmio_gpio_set(codec, 1, val);
5054
5055 return 0;
5056}
5057
a7e76271
IM		 5058static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
5059 struct snd_ctl_elem_value *ucontrol)
95c6e9cb 5060{
a7e76271
IM		 5061 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5062 hda_nid_t nid = get_amp_nid(kcontrol);
5063 hda_nid_t shared_nid = 0;
5064 bool effective;
5065 int ret = 0;
95c6e9cb 5066 struct ca0132_spec *spec = codec->spec;
a7e76271 5067 int auto_jack;
95c6e9cb 5068
a7e76271
IM		 5069 if (nid == VNID_HP_SEL) {
5070 auto_jack =
5071 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
7cb9d94c 5072 if (!auto_jack) {
6da8f446 5073 if (ca0132_use_alt_functions(spec))
7cb9d94c
CM		 5074 ca0132_alt_select_out(codec);
5075 else
5076 ca0132_select_out(codec);
5077 }
a7e76271
IM		 5078 return 1;
5079 }
95c6e9cb 5080
a7e76271
IM		 5081 if (nid == VNID_AMIC1_SEL) {
5082 auto_jack =
5083 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5084 if (!auto_jack)
5085 ca0132_select_mic(codec);
5086 return 1;
5087 }
95c6e9cb 5088
a7e76271 5089 if (nid == VNID_HP_ASEL) {
6da8f446 5090 if (ca0132_use_alt_functions(spec))
7cb9d94c
CM		 5091 ca0132_alt_select_out(codec);
5092 else
5093 ca0132_select_out(codec);
a7e76271
IM		 5094 return 1;
5095 }
95c6e9cb 5096
a7e76271
IM		 5097 if (nid == VNID_AMIC1_ASEL) {
5098 ca0132_select_mic(codec);
5099 return 1;
95c6e9cb 5100 }
a7e76271
IM		 5101
5102 /* if effective conditions, then update hw immediately. */
5103 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5104 if (effective) {
5105 int dir = get_amp_direction(kcontrol);
5106 int ch = get_amp_channels(kcontrol);
5107 unsigned long pval;
5108
5109 mutex_lock(&codec->control_mutex);
5110 pval = kcontrol->private_value;
5111 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5112 0, dir);
5113 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
5114 kcontrol->private_value = pval;
5115 mutex_unlock(&codec->control_mutex);
95c6e9cb 5116 }
95c6e9cb 5117
a7e76271 5118 return ret;
95c6e9cb 5119}
a7e76271 5120/* End of control change helpers. */
47cdf76e
CM		 5121/*
5122 * Below I've added controls to mess with the effect levels, I've only enabled
5123 * them on the Sound Blaster Z, but they would probably also work on the
5124 * Chromebook. I figured they were probably tuned specifically for it, and left
5125 * out for a reason.
5126 */
5127
5128/* Sets DSP effect level from the sliders above the controls */
5129static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
5130 const unsigned int *lookup, int idx)
5131{
5132 int i = 0;
5133 unsigned int y;
5134 /*
5135 * For X_BASS, req 2 is actually crossover freq instead of
5136 * effect level
5137 */
5138 if (nid == X_BASS)
5139 y = 2;
5140 else
5141 y = 1;
5142
5143 snd_hda_power_up(codec);
5144 if (nid == XBASS_XOVER) {
5145 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5146 if (ca0132_effects[i].nid == X_BASS)
5147 break;
5148
5149 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5150 ca0132_effects[i].reqs[1],
5151 &(lookup[idx - 1]), sizeof(unsigned int));
5152 } else {
5153 /* Find the actual effect structure */
5154 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5155 if (nid == ca0132_effects[i].nid)
5156 break;
5157
5158 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5159 ca0132_effects[i].reqs[y],
5160 &(lookup[idx]), sizeof(unsigned int));
5161 }
5162
5163 snd_hda_power_down(codec);
5164
5165 return 0;
5166}
5167
5168static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
5169 struct snd_ctl_elem_value *ucontrol)
5170{
5171 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5172 struct ca0132_spec *spec = codec->spec;
5173 long *valp = ucontrol->value.integer.value;
5174
5175 *valp = spec->xbass_xover_freq;
5176 return 0;
5177}
5178
5179static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
5180 struct snd_ctl_elem_value *ucontrol)
5181{
5182 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5183 struct ca0132_spec *spec = codec->spec;
5184 hda_nid_t nid = get_amp_nid(kcontrol);
5185 long *valp = ucontrol->value.integer.value;
5186 int idx = nid - OUT_EFFECT_START_NID;
5187
5188 *valp = spec->fx_ctl_val[idx];
5189 return 0;
5190}
5191
5192/*
5193 * The X-bass crossover starts at 10hz, so the min is 1. The
5194 * frequency is set in multiples of 10.
5195 */
5196static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
5197 struct snd_ctl_elem_info *uinfo)
5198{
5199 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5200 uinfo->count = 1;
5201 uinfo->value.integer.min = 1;
5202 uinfo->value.integer.max = 100;
5203 uinfo->value.integer.step = 1;
5204
5205 return 0;
5206}
5207
5208static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
5209 struct snd_ctl_elem_info *uinfo)
5210{
5211 int chs = get_amp_channels(kcontrol);
5212
5213 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5214 uinfo->count = chs == 3 ? 2 : 1;
5215 uinfo->value.integer.min = 0;
5216 uinfo->value.integer.max = 100;
5217 uinfo->value.integer.step = 1;
5218
5219 return 0;
5220}
5221
5222static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
5223 struct snd_ctl_elem_value *ucontrol)
5224{
5225 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5226 struct ca0132_spec *spec = codec->spec;
5227 hda_nid_t nid = get_amp_nid(kcontrol);
5228 long *valp = ucontrol->value.integer.value;
5229 int idx;
5230
5231 /* any change? */
5232 if (spec->xbass_xover_freq == *valp)
5233 return 0;
5234
5235 spec->xbass_xover_freq = *valp;
5236
5237 idx = *valp;
5238 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
5239
5240 return 0;
5241}
5242
5243static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
5244 struct snd_ctl_elem_value *ucontrol)
5245{
5246 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5247 struct ca0132_spec *spec = codec->spec;
5248 hda_nid_t nid = get_amp_nid(kcontrol);
5249 long *valp = ucontrol->value.integer.value;
5250 int idx;
5251
5252 idx = nid - EFFECT_START_NID;
5253 /* any change? */
5254 if (spec->fx_ctl_val[idx] == *valp)
5255 return 0;
5256
5257 spec->fx_ctl_val[idx] = *valp;
5258
5259 idx = *valp;
5260 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
5261
5262 return 0;
5263}
5264
5265
5266/*
5267 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
5268 * only has off or full 30 dB, and didn't like making a volume slider that has
5269 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
5270 */
5271#define MIC_BOOST_NUM_OF_STEPS 4
5272#define MIC_BOOST_ENUM_MAX_STRLEN 10
5273
5274static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
5275 struct snd_ctl_elem_info *uinfo)
5276{
5277 char *sfx = "dB";
5278 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5279
5280 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5281 uinfo->count = 1;
5282 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
5283 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
5284 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
5285 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
5286 strcpy(uinfo->value.enumerated.name, namestr);
5287 return 0;
5288}
5289
5290static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
5291 struct snd_ctl_elem_value *ucontrol)
5292{
5293 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5294 struct ca0132_spec *spec = codec->spec;
5295
5296 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5297 return 0;
5298}
5299
5300static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
5301 struct snd_ctl_elem_value *ucontrol)
5302{
5303 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5304 struct ca0132_spec *spec = codec->spec;
5305 int sel = ucontrol->value.enumerated.item[0];
5306 unsigned int items = MIC_BOOST_NUM_OF_STEPS;
5307
5308 if (sel >= items)
5309 return 0;
5310
5311 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
5312 sel);
5313
5314 spec->mic_boost_enum_val = sel;
5315
5316 if (spec->in_enum_val != REAR_LINE_IN)
5317 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5318
5319 return 1;
5320}
5321
212de2e7
CM		 5322/*
5323 * Sound BlasterX AE-5 Headphone Gain Controls.
5324 */
5325#define AE5_HEADPHONE_GAIN_MAX 3
5326static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol,
5327 struct snd_ctl_elem_info *uinfo)
5328{
5329 char *sfx = " Ohms)";
5330 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5331
5332 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5333 uinfo->count = 1;
5334 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX;
5335 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX)
5336 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1;
5337 sprintf(namestr, "%s %s",
5338 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name,
5339 sfx);
5340 strcpy(uinfo->value.enumerated.name, namestr);
5341 return 0;
5342}
5343
5344static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol,
5345 struct snd_ctl_elem_value *ucontrol)
5346{
5347 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5348 struct ca0132_spec *spec = codec->spec;
5349
5350 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val;
5351 return 0;
5352}
5353
5354static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol,
5355 struct snd_ctl_elem_value *ucontrol)
5356{
5357 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5358 struct ca0132_spec *spec = codec->spec;
5359 int sel = ucontrol->value.enumerated.item[0];
5360 unsigned int items = AE5_HEADPHONE_GAIN_MAX;
5361
5362 if (sel >= items)
5363 return 0;
5364
5365 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n",
5366 sel);
5367
5368 spec->ae5_headphone_gain_val = sel;
5369
5370 if (spec->out_enum_val == HEADPHONE_OUT)
5371 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val);
5372
5373 return 1;
5374}
5375
5376/*
5377 * Sound BlasterX AE-5 sound filter enumerated control.
5378 */
5379#define AE5_SOUND_FILTER_MAX 3
5380
5381static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol,
5382 struct snd_ctl_elem_info *uinfo)
5383{
5384 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5385
5386 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5387 uinfo->count = 1;
5388 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX;
5389 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX)
5390 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1;
5391 sprintf(namestr, "%s",
5392 ae5_filter_presets[uinfo->value.enumerated.item].name);
5393 strcpy(uinfo->value.enumerated.name, namestr);
5394 return 0;
5395}
5396
5397static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol,
5398 struct snd_ctl_elem_value *ucontrol)
5399{
5400 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5401 struct ca0132_spec *spec = codec->spec;
5402
5403 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val;
5404 return 0;
5405}
5406
5407static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol,
5408 struct snd_ctl_elem_value *ucontrol)
5409{
5410 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5411 struct ca0132_spec *spec = codec->spec;
5412 int sel = ucontrol->value.enumerated.item[0];
5413 unsigned int items = AE5_SOUND_FILTER_MAX;
5414
5415 if (sel >= items)
5416 return 0;
5417
5418 codec_dbg(codec, "ae5_sound_filter: %s\n",
5419 ae5_filter_presets[sel].name);
5420
5421 spec->ae5_filter_val = sel;
5422
5423 ca0113_mmio_command_set_type2(codec, 0x48, 0x07,
5424 ae5_filter_presets[sel].val);
5425
5426 return 1;
5427}
95c6e9cb 5428
7cb9d94c
CM		 5429/*
5430 * Input Select Control for alternative ca0132 codecs. This exists because
5431 * front microphone has no auto-detect, and we need a way to set the rear
5432 * as line-in
5433 */
5434static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
5435 struct snd_ctl_elem_info *uinfo)
5436{
5437 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5438 uinfo->count = 1;
5439 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
5440 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
5441 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
5442 strcpy(uinfo->value.enumerated.name,
5443 in_src_str[uinfo->value.enumerated.item]);
5444 return 0;
5445}
5446
5447static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
5448 struct snd_ctl_elem_value *ucontrol)
5449{
5450 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5451 struct ca0132_spec *spec = codec->spec;
5452
5453 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5454 return 0;
5455}
5456
5457static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
5458 struct snd_ctl_elem_value *ucontrol)
5459{
5460 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5461 struct ca0132_spec *spec = codec->spec;
5462 int sel = ucontrol->value.enumerated.item[0];
5463 unsigned int items = IN_SRC_NUM_OF_INPUTS;
5464
5465 if (sel >= items)
5466 return 0;
5467
5468 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
5469 sel, in_src_str[sel]);
5470
5471 spec->in_enum_val = sel;
5472
5473 ca0132_alt_select_in(codec);
5474
5475 return 1;
5476}
5477
5478/* Sound Blaster Z Output Select Control */
5479static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
5480 struct snd_ctl_elem_info *uinfo)
5481{
5482 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5483 uinfo->count = 1;
5484 uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5485 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5486 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5487 strcpy(uinfo->value.enumerated.name,
5488 alt_out_presets[uinfo->value.enumerated.item].name);
5489 return 0;
5490}
5491
5492static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
5493 struct snd_ctl_elem_value *ucontrol)
5494{
5495 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5496 struct ca0132_spec *spec = codec->spec;
5497
5498 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
5499 return 0;
5500}
5501
5502static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
5503 struct snd_ctl_elem_value *ucontrol)
5504{
5505 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5506 struct ca0132_spec *spec = codec->spec;
5507 int sel = ucontrol->value.enumerated.item[0];
5508 unsigned int items = NUM_OF_OUTPUTS;
5509 unsigned int auto_jack;
5510
5511 if (sel >= items)
5512 return 0;
5513
5514 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
5515 sel, alt_out_presets[sel].name);
5516
5517 spec->out_enum_val = sel;
5518
5519 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5520
5521 if (!auto_jack)
5522 ca0132_alt_select_out(codec);
5523
5524 return 1;
5525}
5526
47cdf76e
CM		 5527/*
5528 * Smart Volume output setting control. Three different settings, Normal,
5529 * which takes the value from the smart volume slider. The two others, loud
5530 * and night, disregard the slider value and have uneditable values.
5531 */
5532#define NUM_OF_SVM_SETTINGS 3
3a03f83b 5533static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
47cdf76e
CM		 5534
5535static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
5536 struct snd_ctl_elem_info *uinfo)
5537{
5538 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5539 uinfo->count = 1;
5540 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
5541 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
5542 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
5543 strcpy(uinfo->value.enumerated.name,
5544 out_svm_set_enum_str[uinfo->value.enumerated.item]);
5545 return 0;
5546}
5547
5548static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
5549 struct snd_ctl_elem_value *ucontrol)
5550{
5551 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5552 struct ca0132_spec *spec = codec->spec;
5553
5554 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
5555 return 0;
5556}
5557
5558static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
5559 struct snd_ctl_elem_value *ucontrol)
5560{
5561 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5562 struct ca0132_spec *spec = codec->spec;
5563 int sel = ucontrol->value.enumerated.item[0];
5564 unsigned int items = NUM_OF_SVM_SETTINGS;
5565 unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
5566 unsigned int tmp;
5567
5568 if (sel >= items)
5569 return 0;
5570
5571 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
5572 sel, out_svm_set_enum_str[sel]);
5573
5574 spec->smart_volume_setting = sel;
5575
5576 switch (sel) {
5577 case 0:
5578 tmp = FLOAT_ZERO;
5579 break;
5580 case 1:
5581 tmp = FLOAT_ONE;
5582 break;
5583 case 2:
5584 tmp = FLOAT_TWO;
5585 break;
5586 default:
5587 tmp = FLOAT_ZERO;
5588 break;
5589 }
5590 /* Req 2 is the Smart Volume Setting req. */
5591 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5592 ca0132_effects[idx].reqs[2], tmp);
5593 return 1;
5594}
5595
5596/* Sound Blaster Z EQ preset controls */
5597static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
5598 struct snd_ctl_elem_info *uinfo)
5599{
c5f13d75 5600 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
47cdf76e
CM		 5601
5602 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5603 uinfo->count = 1;
5604 uinfo->value.enumerated.items = items;
5605 if (uinfo->value.enumerated.item >= items)
5606 uinfo->value.enumerated.item = items - 1;
5607 strcpy(uinfo->value.enumerated.name,
5608 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
5609 return 0;
5610}
5611
5612static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
5613 struct snd_ctl_elem_value *ucontrol)
5614{
5615 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5616 struct ca0132_spec *spec = codec->spec;
5617
5618 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
5619 return 0;
5620}
5621
5622static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
5623 struct snd_ctl_elem_value *ucontrol)
5624{
5625 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5626 struct ca0132_spec *spec = codec->spec;
5627 int i, err = 0;
5628 int sel = ucontrol->value.enumerated.item[0];
c5f13d75 5629 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
47cdf76e
CM		 5630
5631 if (sel >= items)
5632 return 0;
5633
5634 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
5635 ca0132_alt_eq_presets[sel].name);
5636 /*
5637 * Idx 0 is default.
5638 * Default needs to qualify with CrystalVoice state.
5639 */
5640 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
5641 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
5642 ca0132_alt_eq_enum.reqs[i],
5643 ca0132_alt_eq_presets[sel].vals[i]);
5644 if (err < 0)
5645 break;
5646 }
5647
5648 if (err >= 0)
5649 spec->eq_preset_val = sel;
5650
5651 return 1;
5652}
5653
a7e76271
IM		 5654static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
5655 struct snd_ctl_elem_info *uinfo)
5656{
a9291f46 5657 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
a7e76271
IM		 5658
5659 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5660 uinfo->count = 1;
5661 uinfo->value.enumerated.items = items;
5662 if (uinfo->value.enumerated.item >= items)
5663 uinfo->value.enumerated.item = items - 1;
5664 strcpy(uinfo->value.enumerated.name,
5665 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
5666 return 0;
5667}
95c6e9cb 5668
a7e76271 5669static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5670 struct snd_ctl_elem_value *ucontrol)
5671{
5672 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5673 struct ca0132_spec *spec = codec->spec;
95c6e9cb 5674
a7e76271 5675 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
95c6e9cb
IM		 5676 return 0;
5677}
5678
a7e76271 5679static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5680 struct snd_ctl_elem_value *ucontrol)
5681{
5682 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5683 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5684 int i, err = 0;
5685 int sel = ucontrol->value.enumerated.item[0];
95c6e9cb 5686
a9291f46 5687 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
95c6e9cb
IM		 5688 return 0;
5689
4e76a883 5690 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
a7e76271 5691 sel, ca0132_voicefx_presets[sel].name);
95c6e9cb 5692
a7e76271
IM		 5693 /*
5694 * Idx 0 is default.
5695 * Default needs to qualify with CrystalVoice state.
5696 */
5697 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
5698 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
5699 ca0132_voicefx.reqs[i],
5700 ca0132_voicefx_presets[sel].vals[i]);
5701 if (err < 0)
5702 break;
5703 }
95c6e9cb 5704
a7e76271
IM		 5705 if (err >= 0) {
5706 spec->voicefx_val = sel;
5707 /* enable voice fx */
5708 ca0132_voicefx_set(codec, (sel ? 1 : 0));
5709 }
95c6e9cb 5710
a7e76271 5711 return 1;
95c6e9cb
IM		 5712}
5713
a7e76271
IM		 5714static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
5715 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 5716{
5717 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5718 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5719 hda_nid_t nid = get_amp_nid(kcontrol);
5720 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 5721 long *valp = ucontrol->value.integer.value;
5722
a7e76271
IM		 5723 /* vnode */
5724 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5725 if (ch & 1) {
5726 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
5727 valp++;
5728 }
5729 if (ch & 2) {
5730 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
5731 valp++;
5732 }
5733 return 0;
5734 }
5735
5736 /* effects, include PE and CrystalVoice */
5737 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
5738 *valp = spec->effects_switch[nid - EFFECT_START_NID];
5739 return 0;
5740 }
5741
5742 /* mic boost */
5743 if (nid == spec->input_pins[0]) {
5744 *valp = spec->cur_mic_boost;
5745 return 0;
5746 }
5747
95c6e9cb
IM		 5748 return 0;
5749}
5750
a7e76271
IM		 5751static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
5752 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 5753{
5754 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5755 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5756 hda_nid_t nid = get_amp_nid(kcontrol);
5757 int ch = get_amp_channels(kcontrol);
95c6e9cb 5758 long *valp = ucontrol->value.integer.value;
a7e76271 5759 int changed = 1;
95c6e9cb 5760
4e76a883 5761 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
a7e76271 5762 nid, *valp);
95c6e9cb
IM		 5763
5764 snd_hda_power_up(codec);
a7e76271
IM		 5765 /* vnode */
5766 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5767 if (ch & 1) {
5768 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
5769 valp++;
5770 }
5771 if (ch & 2) {
5772 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
5773 valp++;
5774 }
5775 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
5776 goto exit;
5777 }
95c6e9cb 5778
a7e76271
IM		 5779 /* PE */
5780 if (nid == PLAY_ENHANCEMENT) {
5781 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5782 changed = ca0132_pe_switch_set(codec);
b97f6bfd 5783 goto exit;
a7e76271 5784 }
95c6e9cb 5785
a7e76271
IM		 5786 /* CrystalVoice */
5787 if (nid == CRYSTAL_VOICE) {
5788 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5789 changed = ca0132_cvoice_switch_set(codec);
b97f6bfd 5790 goto exit;
a7e76271 5791 }
95c6e9cb 5792
a7e76271
IM		 5793 /* out and in effects */
5794 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
5795 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
5796 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5797 changed = ca0132_effects_set(codec, nid, *valp);
5798 goto exit;
5799 }
5800
5801 /* mic boost */
5802 if (nid == spec->input_pins[0]) {
5803 spec->cur_mic_boost = *valp;
6da8f446 5804 if (ca0132_use_alt_functions(spec)) {
7cb9d94c
CM		 5805 if (spec->in_enum_val != REAR_LINE_IN)
5806 changed = ca0132_mic_boost_set(codec, *valp);
5807 } else {
5808 /* Mic boost does not apply to Digital Mic */
5809 if (spec->cur_mic_type != DIGITAL_MIC)
5810 changed = ca0132_mic_boost_set(codec, *valp);
5811 }
a7e76271 5812
a7e76271
IM		 5813 goto exit;
5814 }
95c6e9cb 5815
d51434d4
CM		 5816 if (nid == ZXR_HEADPHONE_GAIN) {
5817 spec->zxr_gain_set = *valp;
5818 if (spec->cur_out_type == HEADPHONE_OUT)
5819 changed = zxr_headphone_gain_set(codec, *valp);
5820 else
5821 changed = 0;
5822
5823 goto exit;
5824 }
5825
a7e76271 5826exit:
95c6e9cb 5827 snd_hda_power_down(codec);
a7e76271 5828 return changed;
95c6e9cb
IM		 5829}
5830
a7e76271
IM		 5831/*
5832 * Volume related
5833 */
017310fb
CM		 5834/*
5835 * Sets the internal DSP decibel level to match the DAC for output, and the
5836 * ADC for input. Currently only the SBZ sets dsp capture volume level, and
5837 * all alternative codecs set DSP playback volume.
5838 */
5839static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
5840{
5841 struct ca0132_spec *spec = codec->spec;
5842 unsigned int dsp_dir;
5843 unsigned int lookup_val;
5844
5845 if (nid == VNID_SPK)
5846 dsp_dir = DSP_VOL_OUT;
5847 else
5848 dsp_dir = DSP_VOL_IN;
5849
5850 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
5851
5852 dspio_set_uint_param(codec,
5853 ca0132_alt_vol_ctls[dsp_dir].mid,
5854 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
5855 float_vol_db_lookup[lookup_val]);
5856
5857 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
5858
5859 dspio_set_uint_param(codec,
5860 ca0132_alt_vol_ctls[dsp_dir].mid,
5861 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
5862 float_vol_db_lookup[lookup_val]);
5863
5864 dspio_set_uint_param(codec,
5865 ca0132_alt_vol_ctls[dsp_dir].mid,
5866 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
5867}
5868
a7e76271
IM		 5869static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
5870 struct snd_ctl_elem_info *uinfo)
5871{
5872 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5873 struct ca0132_spec *spec = codec->spec;
5874 hda_nid_t nid = get_amp_nid(kcontrol);
5875 int ch = get_amp_channels(kcontrol);
5876 int dir = get_amp_direction(kcontrol);
5877 unsigned long pval;
5878 int err;
5879
5880 switch (nid) {
5881 case VNID_SPK:
5882 /* follow shared_out info */
5883 nid = spec->shared_out_nid;
5884 mutex_lock(&codec->control_mutex);
5885 pval = kcontrol->private_value;
5886 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5887 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5888 kcontrol->private_value = pval;
5889 mutex_unlock(&codec->control_mutex);
5890 break;
5891 case VNID_MIC:
5892 /* follow shared_mic info */
5893 nid = spec->shared_mic_nid;
5894 mutex_lock(&codec->control_mutex);
5895 pval = kcontrol->private_value;
5896 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5897 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5898 kcontrol->private_value = pval;
5899 mutex_unlock(&codec->control_mutex);
5900 break;
5901 default:
5902 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5903 }
5904 return err;
5905}
5906
5907static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5908 struct snd_ctl_elem_value *ucontrol)
5909{
5910 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5911 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5912 hda_nid_t nid = get_amp_nid(kcontrol);
5913 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 5914 long *valp = ucontrol->value.integer.value;
5915
a7e76271
IM		 5916 /* store the left and right volume */
5917 if (ch & 1) {
5918 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
5919 valp++;
5920 }
5921 if (ch & 2) {
5922 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
5923 valp++;
5924 }
95c6e9cb
IM		 5925 return 0;
5926}
5927
a7e76271 5928static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5929 struct snd_ctl_elem_value *ucontrol)
5930{
5931 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5932 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5933 hda_nid_t nid = get_amp_nid(kcontrol);
5934 int ch = get_amp_channels(kcontrol);
95c6e9cb 5935 long *valp = ucontrol->value.integer.value;
a7e76271
IM		 5936 hda_nid_t shared_nid = 0;
5937 bool effective;
5938 int changed = 1;
5939
5940 /* store the left and right volume */
5941 if (ch & 1) {
5942 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
5943 valp++;
5944 }
5945 if (ch & 2) {
5946 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
5947 valp++;
5948 }
95c6e9cb 5949
a7e76271
IM		 5950 /* if effective conditions, then update hw immediately. */
5951 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5952 if (effective) {
5953 int dir = get_amp_direction(kcontrol);
5954 unsigned long pval;
5955
5956 snd_hda_power_up(codec);
5957 mutex_lock(&codec->control_mutex);
5958 pval = kcontrol->private_value;
5959 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5960 0, dir);
5961 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5962 kcontrol->private_value = pval;
5963 mutex_unlock(&codec->control_mutex);
5964 snd_hda_power_down(codec);
5965 }
95c6e9cb 5966
a7e76271 5967 return changed;
95c6e9cb
IM		 5968}
5969
017310fb
CM		 5970/*
5971 * This function is the same as the one above, because using an if statement
5972 * inside of the above volume control for the DSP volume would cause too much
5973 * lag. This is a lot more smooth.
5974 */
5975static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
5976 struct snd_ctl_elem_value *ucontrol)
5977{
5978 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5979 struct ca0132_spec *spec = codec->spec;
5980 hda_nid_t nid = get_amp_nid(kcontrol);
5981 int ch = get_amp_channels(kcontrol);
5982 long *valp = ucontrol->value.integer.value;
5983 hda_nid_t vnid = 0;
33539936 5984 int changed;
017310fb
CM		 5985
5986 switch (nid) {
5987 case 0x02:
5988 vnid = VNID_SPK;
5989 break;
5990 case 0x07:
5991 vnid = VNID_MIC;
5992 break;
5993 }
5994
5995 /* store the left and right volume */
5996 if (ch & 1) {
5997 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
5998 valp++;
5999 }
6000 if (ch & 2) {
6001 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
6002 valp++;
6003 }
6004
6005 snd_hda_power_up(codec);
6006 ca0132_alt_dsp_volume_put(codec, vnid);
6007 mutex_lock(&codec->control_mutex);
6008 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
6009 mutex_unlock(&codec->control_mutex);
6010 snd_hda_power_down(codec);
6011
6012 return changed;
6013}
6014
a7e76271
IM		 6015static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
6016 unsigned int size, unsigned int __user *tlv)
95c6e9cb 6017{
a7e76271
IM		 6018 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6019 struct ca0132_spec *spec = codec->spec;
6020 hda_nid_t nid = get_amp_nid(kcontrol);
6021 int ch = get_amp_channels(kcontrol);
6022 int dir = get_amp_direction(kcontrol);
6023 unsigned long pval;
6024 int err;
6025
6026 switch (nid) {
6027 case VNID_SPK:
6028 /* follow shared_out tlv */
6029 nid = spec->shared_out_nid;
6030 mutex_lock(&codec->control_mutex);
6031 pval = kcontrol->private_value;
6032 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6033 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6034 kcontrol->private_value = pval;
6035 mutex_unlock(&codec->control_mutex);
6036 break;
6037 case VNID_MIC:
6038 /* follow shared_mic tlv */
6039 nid = spec->shared_mic_nid;
6040 mutex_lock(&codec->control_mutex);
6041 pval = kcontrol->private_value;
6042 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6043 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6044 kcontrol->private_value = pval;
6045 mutex_unlock(&codec->control_mutex);
6046 break;
6047 default:
6048 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6049 }
6050 return err;
95c6e9cb
IM		 6051}
6052
47cdf76e
CM		 6053/* Add volume slider control for effect level */
6054static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
6055 const char *pfx, int dir)
6056{
47cdf76e
CM		 6057 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6058 int type = dir ? HDA_INPUT : HDA_OUTPUT;
6059 struct snd_kcontrol_new knew =
6060 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
6061
0cc1aa71 6062 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
47cdf76e 6063
bb86124c 6064 knew.tlv.c = NULL;
47cdf76e
CM		 6065
6066 switch (nid) {
6067 case XBASS_XOVER:
6068 knew.info = ca0132_alt_xbass_xover_slider_info;
6069 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6070 knew.put = ca0132_alt_xbass_xover_slider_put;
6071 break;
6072 default:
6073 knew.info = ca0132_alt_effect_slider_info;
6074 knew.get = ca0132_alt_slider_ctl_get;
6075 knew.put = ca0132_alt_effect_slider_put;
6076 knew.private_value =
6077 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
6078 break;
6079 }
6080
6081 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6082}
6083
6084/*
6085 * Added FX: prefix for the alternative codecs, because otherwise the surround
6086 * effect would conflict with the Surround sound volume control. Also seems more
6087 * clear as to what the switches do. Left alone for others.
6088 */
a7e76271
IM		 6089static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
6090 const char *pfx, int dir)
95c6e9cb 6091{
47cdf76e 6092 struct ca0132_spec *spec = codec->spec;
975cc02a 6093 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
a7e76271 6094 int type = dir ? HDA_INPUT : HDA_OUTPUT;
95c6e9cb 6095 struct snd_kcontrol_new knew =
a7e76271 6096 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
47cdf76e
CM		 6097 /* If using alt_controls, add FX: prefix. But, don't add FX:
6098 * prefix to OutFX or InFX enable controls.
6099 */
6da8f446 6100 if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID))
0cc1aa71 6101 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
47cdf76e
CM		 6102 else
6103 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
6104
95c6e9cb
IM		 6105 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6106}
6107
a7e76271 6108static int add_voicefx(struct hda_codec *codec)
95c6e9cb
IM		 6109{
6110 struct snd_kcontrol_new knew =
a7e76271
IM		 6111 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
6112 VOICEFX, 1, 0, HDA_INPUT);
6113 knew.info = ca0132_voicefx_info;
6114 knew.get = ca0132_voicefx_get;
6115 knew.put = ca0132_voicefx_put;
6116 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
95c6e9cb
IM		 6117}
6118
47cdf76e
CM		 6119/* Create the EQ Preset control */
6120static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
6121{
6122 struct snd_kcontrol_new knew =
6123 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
6124 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
6125 knew.info = ca0132_alt_eq_preset_info;
6126 knew.get = ca0132_alt_eq_preset_get;
6127 knew.put = ca0132_alt_eq_preset_put;
6128 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
6129 snd_ctl_new1(&knew, codec));
6130}
6131
6132/*
6133 * Add enumerated control for the three different settings of the smart volume
6134 * output effect. Normal just uses the slider value, and loud and night are
6135 * their own things that ignore that value.
6136 */
6137static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
6138{
6139 struct snd_kcontrol_new knew =
6140 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
6141 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
6142 knew.info = ca0132_alt_svm_setting_info;
6143 knew.get = ca0132_alt_svm_setting_get;
6144 knew.put = ca0132_alt_svm_setting_put;
6145 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
6146 snd_ctl_new1(&knew, codec));
6147
6148}
6149
7cb9d94c
CM		 6150/*
6151 * Create an Output Select enumerated control for codecs with surround
6152 * out capabilities.
6153 */
6154static int ca0132_alt_add_output_enum(struct hda_codec *codec)
6155{
6156 struct snd_kcontrol_new knew =
6157 HDA_CODEC_MUTE_MONO("Output Select",
6158 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
6159 knew.info = ca0132_alt_output_select_get_info;
6160 knew.get = ca0132_alt_output_select_get;
6161 knew.put = ca0132_alt_output_select_put;
6162 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
6163 snd_ctl_new1(&knew, codec));
6164}
6165
6166/*
6167 * Create an Input Source enumerated control for the alternate ca0132 codecs
6168 * because the front microphone has no auto-detect, and Line-in has to be set
6169 * somehow.
6170 */
6171static int ca0132_alt_add_input_enum(struct hda_codec *codec)
6172{
6173 struct snd_kcontrol_new knew =
6174 HDA_CODEC_MUTE_MONO("Input Source",
6175 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
6176 knew.info = ca0132_alt_input_source_info;
6177 knew.get = ca0132_alt_input_source_get;
6178 knew.put = ca0132_alt_input_source_put;
6179 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
6180 snd_ctl_new1(&knew, codec));
6181}
6182
47cdf76e
CM		 6183/*
6184 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
6185 * more control than the original mic boost, which is either full 30dB or off.
6186 */
6187static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
6188{
6189 struct snd_kcontrol_new knew =
6190 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
6191 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
6192 knew.info = ca0132_alt_mic_boost_info;
6193 knew.get = ca0132_alt_mic_boost_get;
6194 knew.put = ca0132_alt_mic_boost_put;
6195 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
6196 snd_ctl_new1(&knew, codec));
6197
6198}
6199
212de2e7
CM		 6200/*
6201 * Add headphone gain enumerated control for the AE-5. This switches between
6202 * three modes, low, medium, and high. When non-headphone outputs are selected,
6203 * it is automatically set to high. This is the same behavior as Windows.
6204 */
6205static int ae5_add_headphone_gain_enum(struct hda_codec *codec)
6206{
6207 struct snd_kcontrol_new knew =
6208 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain",
4b432ad4 6209 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT);
212de2e7
CM		 6210 knew.info = ae5_headphone_gain_info;
6211 knew.get = ae5_headphone_gain_get;
6212 knew.put = ae5_headphone_gain_put;
6213 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM,
6214 snd_ctl_new1(&knew, codec));
6215}
6216
6217/*
6218 * Add sound filter enumerated control for the AE-5. This adds three different
6219 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've
6220 * read into it, it changes the DAC's interpolation filter.
6221 */
6222static int ae5_add_sound_filter_enum(struct hda_codec *codec)
6223{
6224 struct snd_kcontrol_new knew =
6225 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter",
4b432ad4 6226 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT);
212de2e7
CM		 6227 knew.info = ae5_sound_filter_info;
6228 knew.get = ae5_sound_filter_get;
6229 knew.put = ae5_sound_filter_put;
6230 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM,
6231 snd_ctl_new1(&knew, codec));
6232}
6233
d51434d4
CM		 6234static int zxr_add_headphone_gain_switch(struct hda_codec *codec)
6235{
6236 struct snd_kcontrol_new knew =
6237 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain",
6238 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT);
6239
6240 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN,
6241 snd_ctl_new1(&knew, codec));
6242}
6243
47cdf76e
CM		 6244/*
6245 * Need to create slave controls for the alternate codecs that have surround
6246 * capabilities.
6247 */
6248static const char * const ca0132_alt_slave_pfxs[] = {
6249 "Front", "Surround", "Center", "LFE", NULL,
6250};
6251
6252/*
6253 * Also need special channel map, because the default one is incorrect.
6254 * I think this has to do with the pin for rear surround being 0x11,
6255 * and the center/lfe being 0x10. Usually the pin order is the opposite.
6256 */
9c4a665e 6257static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
47cdf76e
CM		 6258 { .channels = 2,
6259 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
6260 { .channels = 4,
6261 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6262 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6263 { .channels = 6,
6264 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6265 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
6266 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6267 { }
6268};
6269
6270/* Add the correct chmap for streams with 6 channels. */
6271static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
6272{
6273 int err = 0;
6274 struct hda_pcm *pcm;
6275
6276 list_for_each_entry(pcm, &codec->pcm_list_head, list) {
6277 struct hda_pcm_stream *hinfo =
6278 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
6279 struct snd_pcm_chmap *chmap;
6280 const struct snd_pcm_chmap_elem *elem;
6281
6282 elem = ca0132_alt_chmaps;
6283 if (hinfo->channels_max == 6) {
6284 err = snd_pcm_add_chmap_ctls(pcm->pcm,
6285 SNDRV_PCM_STREAM_PLAYBACK,
6286 elem, hinfo->channels_max, 0, &chmap);
6287 if (err < 0)
6288 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
6289 }
6290 }
6291}
6292
a7e76271
IM		 6293/*
6294 * When changing Node IDs for Mixer Controls below, make sure to update
6295 * Node IDs in ca0132_config() as well.
6296 */
b0eaa072 6297static const struct snd_kcontrol_new ca0132_mixer[] = {
a7e76271
IM		 6298 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
6299 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
6300 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6301 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6302 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
6303 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
6304 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6305 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6306 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
6307 0x12, 1, HDA_INPUT),
6308 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
6309 VNID_HP_SEL, 1, HDA_OUTPUT),
6310 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
6311 VNID_AMIC1_SEL, 1, HDA_INPUT),
6312 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6313 VNID_HP_ASEL, 1, HDA_OUTPUT),
6314 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
6315 VNID_AMIC1_ASEL, 1, HDA_INPUT),
6316 { } /* end */
6317};
6318
017310fb 6319/*
e25e3445
CM		 6320 * Desktop specific control mixer. Removes auto-detect for mic, and adds
6321 * surround controls. Also sets both the Front Playback and Capture Volume
6322 * controls to alt so they set the DSP's decibel level.
017310fb 6323 */
e25e3445 6324static const struct snd_kcontrol_new desktop_mixer[] = {
017310fb
CM		 6325 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6326 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
47cdf76e
CM		 6327 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6328 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6329 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6330 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6331 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6332 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
017310fb
CM		 6333 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
6334 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6335 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6336 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6337 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6338 VNID_HP_ASEL, 1, HDA_OUTPUT),
6339 { } /* end */
6340};
6341
6342/*
6343 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
6344 * because it doesn't set decibel levels for the DSP for capture.
6345 */
b0eaa072 6346static const struct snd_kcontrol_new r3di_mixer[] = {
017310fb
CM		 6347 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6348 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
47cdf76e
CM		 6349 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6350 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6351 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6352 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6353 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6354 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
017310fb
CM		 6355 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6356 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6357 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6358 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6359 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6360 VNID_HP_ASEL, 1, HDA_OUTPUT),
6361 { } /* end */
6362};
6363
e90f29e4
IM		 6364static int ca0132_build_controls(struct hda_codec *codec)
6365{
6366 struct ca0132_spec *spec = codec->spec;
47cdf76e 6367 int i, num_fx, num_sliders;
e90f29e4
IM		 6368 int err = 0;
6369
6370 /* Add Mixer controls */
6371 for (i = 0; i < spec->num_mixers; i++) {
6372 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
6373 if (err < 0)
6374 return err;
6375 }
47cdf76e 6376 /* Setup vmaster with surround slaves for desktop ca0132 devices */
6da8f446 6377 if (ca0132_use_alt_functions(spec)) {
47cdf76e
CM		 6378 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
6379 spec->tlv);
6380 snd_hda_add_vmaster(codec, "Master Playback Volume",
6381 spec->tlv, ca0132_alt_slave_pfxs,
6382 "Playback Volume");
6383 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
6384 NULL, ca0132_alt_slave_pfxs,
6385 "Playback Switch",
6386 true, &spec->vmaster_mute.sw_kctl);
1502b432
CM		 6387 if (err < 0)
6388 return err;
47cdf76e 6389 }
e90f29e4
IM		 6390
6391 /* Add in and out effects controls.
6392 * VoiceFX, PE and CrystalVoice are added separately.
6393 */
6394 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
6395 for (i = 0; i < num_fx; i++) {
7a2dc84f 6396 /* Desktop cards break if Echo Cancellation is used. */
6da8f446 6397 if (ca0132_use_pci_mmio(spec)) {
47cdf76e
CM		 6398 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
6399 OUT_EFFECTS_COUNT))
6400 continue;
6401 }
6402
e90f29e4
IM		 6403 err = add_fx_switch(codec, ca0132_effects[i].nid,
6404 ca0132_effects[i].name,
6405 ca0132_effects[i].direct);
6406 if (err < 0)
6407 return err;
6408 }
47cdf76e
CM		 6409 /*
6410 * If codec has use_alt_controls set to true, add effect level sliders,
6411 * EQ presets, and Smart Volume presets. Also, change names to add FX
6412 * prefix, and change PlayEnhancement and CrystalVoice to match.
6413 */
6da8f446 6414 if (ca0132_use_alt_controls(spec)) {
1502b432
CM		 6415 err = ca0132_alt_add_svm_enum(codec);
6416 if (err < 0)
6417 return err;
6418
6419 err = add_ca0132_alt_eq_presets(codec);
6420 if (err < 0)
6421 return err;
6422
47cdf76e
CM		 6423 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6424 "Enable OutFX", 0);
6425 if (err < 0)
6426 return err;
e90f29e4 6427
47cdf76e
CM		 6428 err = add_fx_switch(codec, CRYSTAL_VOICE,
6429 "Enable InFX", 1);
6430 if (err < 0)
6431 return err;
e90f29e4 6432
47cdf76e
CM		 6433 num_sliders = OUT_EFFECTS_COUNT - 1;
6434 for (i = 0; i < num_sliders; i++) {
6435 err = ca0132_alt_add_effect_slider(codec,
6436 ca0132_effects[i].nid,
6437 ca0132_effects[i].name,
6438 ca0132_effects[i].direct);
6439 if (err < 0)
6440 return err;
6441 }
6442
6443 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
6444 "X-Bass Crossover", EFX_DIR_OUT);
6445
6446 if (err < 0)
6447 return err;
6448 } else {
6449 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6450 "PlayEnhancement", 0);
6451 if (err < 0)
6452 return err;
e90f29e4 6453
47cdf76e
CM		 6454 err = add_fx_switch(codec, CRYSTAL_VOICE,
6455 "CrystalVoice", 1);
6456 if (err < 0)
6457 return err;
6458 }
1502b432
CM		 6459 err = add_voicefx(codec);
6460 if (err < 0)
6461 return err;
e90f29e4 6462
7cb9d94c
CM		 6463 /*
6464 * If the codec uses alt_functions, you need the enumerated controls
6465 * to select the new outputs and inputs, plus add the new mic boost
6466 * setting control.
6467 */
6da8f446 6468 if (ca0132_use_alt_functions(spec)) {
1502b432
CM		 6469 err = ca0132_alt_add_output_enum(codec);
6470 if (err < 0)
6471 return err;
6472 err = ca0132_alt_add_mic_boost_enum(codec);
6473 if (err < 0)
6474 return err;
76dea4db
CM		 6475 /*
6476 * ZxR only has microphone input, there is no front panel
6477 * header on the card, and aux-in is handled by the DBPro board.
6478 */
6da8f446 6479 if (ca0132_quirk(spec) != QUIRK_ZXR) {
1502b432
CM		 6480 err = ca0132_alt_add_input_enum(codec);
6481 if (err < 0)
6482 return err;
6483 }
7cb9d94c 6484 }
212de2e7 6485
6da8f446 6486 if (ca0132_quirk(spec) == QUIRK_AE5) {
1502b432
CM		 6487 err = ae5_add_headphone_gain_enum(codec);
6488 if (err < 0)
6489 return err;
6490 err = ae5_add_sound_filter_enum(codec);
6491 if (err < 0)
6492 return err;
212de2e7 6493 }
d51434d4 6494
6da8f446 6495 if (ca0132_quirk(spec) == QUIRK_ZXR) {
1502b432
CM		 6496 err = zxr_add_headphone_gain_switch(codec);
6497 if (err < 0)
6498 return err;
6499 }
e90f29e4
IM		 6500#ifdef ENABLE_TUNING_CONTROLS
6501 add_tuning_ctls(codec);
6502#endif
6503
6504 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
6505 if (err < 0)
6506 return err;
6507
6508 if (spec->dig_out) {
6509 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
6510 spec->dig_out);
6511 if (err < 0)
6512 return err;
6513 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
6514 if (err < 0)
6515 return err;
6516 /* spec->multiout.share_spdif = 1; */
6517 }
6518
6519 if (spec->dig_in) {
6520 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
6521 if (err < 0)
6522 return err;
6523 }
47cdf76e 6524
6da8f446 6525 if (ca0132_use_alt_functions(spec))
47cdf76e
CM		 6526 ca0132_alt_add_chmap_ctls(codec);
6527
e90f29e4
IM		 6528 return 0;
6529}
6530
7675a2a9
CM		 6531static int dbpro_build_controls(struct hda_codec *codec)
6532{
6533 struct ca0132_spec *spec = codec->spec;
6534 int err = 0;
6535
6536 if (spec->dig_out) {
6537 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
6538 spec->dig_out);
6539 if (err < 0)
6540 return err;
6541 }
6542
6543 if (spec->dig_in) {
6544 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
6545 if (err < 0)
6546 return err;
6547 }
6548
6549 return 0;
6550}
6551
a7e76271 6552/*
e90f29e4 6553 * PCM
a7e76271 6554 */
071f1344 6555static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
a7e76271
IM		 6556 .substreams = 1,
6557 .channels_min = 2,
825315bc 6558 .channels_max = 6,
a7e76271 6559 .ops = {
a7e76271 6560 .prepare = ca0132_playback_pcm_prepare,
e8412ca4
DR		 6561 .cleanup = ca0132_playback_pcm_cleanup,
6562 .get_delay = ca0132_playback_pcm_delay,
a7e76271
IM		 6563 },
6564};
6565
071f1344 6566static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
a7e76271
IM		 6567 .substreams = 1,
6568 .channels_min = 2,
6569 .channels_max = 2,
825315bc
IM		 6570 .ops = {
6571 .prepare = ca0132_capture_pcm_prepare,
e8412ca4
DR		 6572 .cleanup = ca0132_capture_pcm_cleanup,
6573 .get_delay = ca0132_capture_pcm_delay,
825315bc 6574 },
a7e76271
IM		 6575};
6576
071f1344 6577static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
a7e76271
IM		 6578 .substreams = 1,
6579 .channels_min = 2,
6580 .channels_max = 2,
6581 .ops = {
6582 .open = ca0132_dig_playback_pcm_open,
6583 .close = ca0132_dig_playback_pcm_close,
6584 .prepare = ca0132_dig_playback_pcm_prepare,
6585 .cleanup = ca0132_dig_playback_pcm_cleanup
6586 },
6587};
6588
071f1344 6589static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
a7e76271
IM		 6590 .substreams = 1,
6591 .channels_min = 2,
6592 .channels_max = 2,
6593};
6594
6595static int ca0132_build_pcms(struct hda_codec *codec)
95c6e9cb
IM		 6596{
6597 struct ca0132_spec *spec = codec->spec;
bbbc7e85 6598 struct hda_pcm *info;
a7e76271 6599
bbbc7e85
TI		 6600 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
6601 if (!info)
6602 return -ENOMEM;
6da8f446 6603 if (ca0132_use_alt_functions(spec)) {
47cdf76e
CM		 6604 info->own_chmap = true;
6605 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
6606 = ca0132_alt_chmaps;
6607 }
a7e76271
IM		 6608 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
6609 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
6610 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
6611 spec->multiout.max_channels;
6612 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
825315bc 6613 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
a7e76271 6614 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
a7e76271 6615
009b8f97 6616 /* With the DSP enabled, desktops don't use this ADC. */
6da8f446 6617 if (!ca0132_use_alt_functions(spec)) {
009b8f97
CM		 6618 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
6619 if (!info)
6620 return -ENOMEM;
6621 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6622 ca0132_pcm_analog_capture;
6623 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6624 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
6625 }
825315bc 6626
bbbc7e85
TI		 6627 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
6628 if (!info)
6629 return -ENOMEM;
825315bc
IM		 6630 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6631 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6632 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
825315bc 6633
a7e76271
IM		 6634 if (!spec->dig_out && !spec->dig_in)
6635 return 0;
6636
bbbc7e85
TI		 6637 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6638 if (!info)
6639 return -ENOMEM;
a7e76271
IM		 6640 info->pcm_type = HDA_PCM_TYPE_SPDIF;
6641 if (spec->dig_out) {
6642 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6643 ca0132_pcm_digital_playback;
6644 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6645 }
6646 if (spec->dig_in) {
6647 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6648 ca0132_pcm_digital_capture;
6649 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6650 }
95c6e9cb 6651
a7e76271 6652 return 0;
95c6e9cb
IM		 6653}
6654
7675a2a9
CM		 6655static int dbpro_build_pcms(struct hda_codec *codec)
6656{
6657 struct ca0132_spec *spec = codec->spec;
6658 struct hda_pcm *info;
6659
6660 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog");
6661 if (!info)
6662 return -ENOMEM;
6663 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6664 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6665 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
6666
6667
6668 if (!spec->dig_out && !spec->dig_in)
6669 return 0;
6670
6671 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6672 if (!info)
6673 return -ENOMEM;
6674 info->pcm_type = HDA_PCM_TYPE_SPDIF;
6675 if (spec->dig_out) {
6676 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6677 ca0132_pcm_digital_playback;
6678 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6679 }
6680 if (spec->dig_in) {
6681 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6682 ca0132_pcm_digital_capture;
6683 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6684 }
6685
6686 return 0;
6687}
6688
441aa6a0
IM		 6689static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
6690{
6691 if (pin) {
a0c041cb 6692 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
441aa6a0
IM		 6693 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
6694 snd_hda_codec_write(codec, pin, 0,
6695 AC_VERB_SET_AMP_GAIN_MUTE,
6696 AMP_OUT_UNMUTE);
6697 }
6698 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
6699 snd_hda_codec_write(codec, dac, 0,
6700 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
6701}
6702
6703static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
6704{
6705 if (pin) {
a0c041cb 6706 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
441aa6a0
IM		 6707 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
6708 snd_hda_codec_write(codec, pin, 0,
6709 AC_VERB_SET_AMP_GAIN_MUTE,
6710 AMP_IN_UNMUTE(0));
6711 }
6712 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
6713 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
6714 AMP_IN_UNMUTE(0));
6715
6716 /* init to 0 dB and unmute. */
6717 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6718 HDA_AMP_VOLMASK, 0x5a);
6719 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6720 HDA_AMP_MUTE, 0);
6721 }
6722}
6723
5aaca44d
IM		 6724static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
6725{
6726 unsigned int caps;
6727
6728 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
6729 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
6730 snd_hda_override_amp_caps(codec, nid, dir, caps);
6731}
6732
6733/*
6734 * Switch between Digital built-in mic and analog mic.
6735 */
6736static void ca0132_set_dmic(struct hda_codec *codec, int enable)
6737{
6738 struct ca0132_spec *spec = codec->spec;
6739 unsigned int tmp;
6740 u8 val;
6741 unsigned int oldval;
6742
4e76a883 6743 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
5aaca44d
IM		 6744
6745 oldval = stop_mic1(codec);
6746 ca0132_set_vipsource(codec, 0);
6747 if (enable) {
6748 /* set DMic input as 2-ch */
6749 tmp = FLOAT_TWO;
6750 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6751
6752 val = spec->dmic_ctl;
6753 val |= 0x80;
6754 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6755 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6756
6757 if (!(spec->dmic_ctl & 0x20))
6758 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
6759 } else {
6760 /* set AMic input as mono */
6761 tmp = FLOAT_ONE;
6762 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6763
6764 val = spec->dmic_ctl;
6765 /* clear bit7 and bit5 to disable dmic */
6766 val &= 0x5f;
6767 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6768 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6769
6770 if (!(spec->dmic_ctl & 0x20))
6771 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
6772 }
6773 ca0132_set_vipsource(codec, 1);
6774 resume_mic1(codec, oldval);
6775}
6776
6777/*
6778 * Initialization for Digital Mic.
6779 */
6780static void ca0132_init_dmic(struct hda_codec *codec)
6781{
6782 struct ca0132_spec *spec = codec->spec;
6783 u8 val;
6784
6785 /* Setup Digital Mic here, but don't enable.
6786 * Enable based on jack detect.
6787 */
6788
6789 /* MCLK uses MPIO1, set to enable.
6790 * Bit 2-0: MPIO select
6791 * Bit 3: set to disable
6792 * Bit 7-4: reserved
6793 */
6794 val = 0x01;
6795 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6796 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
6797
6798 /* Data1 uses MPIO3. Data2 not use
6799 * Bit 2-0: Data1 MPIO select
6800 * Bit 3: set disable Data1
6801 * Bit 6-4: Data2 MPIO select
6802 * Bit 7: set disable Data2
6803 */
6804 val = 0x83;
6805 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6806 VENDOR_CHIPIO_DMIC_PIN_SET, val);
6807
6808 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
6809 * Bit 3-0: Channel mask
6810 * Bit 4: set for 48KHz, clear for 32KHz
6811 * Bit 5: mode
6812 * Bit 6: set to select Data2, clear for Data1
6813 * Bit 7: set to enable DMic, clear for AMic
6814 */
6da8f446 6815 if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4)
a57a46b9
AB		 6816 val = 0x33;
6817 else
6818 val = 0x23;
5aaca44d
IM		 6819 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
6820 spec->dmic_ctl = val;
6821 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6822 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6823}
6824
6825/*
6826 * Initialization for Analog Mic 2
6827 */
6828static void ca0132_init_analog_mic2(struct hda_codec *codec)
6829{
6830 struct ca0132_spec *spec = codec->spec;
6831
6832 mutex_lock(&spec->chipio_mutex);
6833 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6834 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
6835 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6836 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6837 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6838 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6839 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6840 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
6841 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6842 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6843 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6844 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6845 mutex_unlock(&spec->chipio_mutex);
6846}
6847
6848static void ca0132_refresh_widget_caps(struct hda_codec *codec)
6849{
6850 struct ca0132_spec *spec = codec->spec;
6851 int i;
5aaca44d 6852
4e76a883 6853 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7639a06c 6854 snd_hda_codec_update_widgets(codec);
5aaca44d
IM		 6855
6856 for (i = 0; i < spec->multiout.num_dacs; i++)
6857 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
6858
6859 for (i = 0; i < spec->num_outputs; i++)
6860 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
6861
6862 for (i = 0; i < spec->num_inputs; i++) {
6863 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
6864 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
6865 }
6866}
6867
7e6ed62e 6868/*
6ef0e91e
CM		 6869 * Creates a dummy stream to bind the output to. This seems to have to be done
6870 * after changing the main outputs source and destination streams.
7e6ed62e 6871 */
6ef0e91e 6872static void ca0132_alt_create_dummy_stream(struct hda_codec *codec)
447fd8e9 6873{
6ef0e91e
CM		 6874 struct ca0132_spec *spec = codec->spec;
6875 unsigned int stream_format;
447fd8e9 6876
6ef0e91e
CM		 6877 stream_format = snd_hdac_calc_stream_format(48000, 2,
6878 SNDRV_PCM_FORMAT_S32_LE, 32, 0);
7e6ed62e 6879
6ef0e91e
CM		 6880 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6881 0, stream_format);
7e6ed62e 6882
6ef0e91e 6883 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
7e6ed62e
CM		 6884}
6885
38ba69ff 6886/*
6ef0e91e 6887 * Initialize mic for non-chromebook ca0132 implementations.
38ba69ff 6888 */
6ef0e91e 6889static void ca0132_alt_init_analog_mics(struct hda_codec *codec)
38ba69ff 6890{
6ef0e91e 6891 struct ca0132_spec *spec = codec->spec;
38ba69ff
CM		 6892 unsigned int tmp;
6893
6894 /* Mic 1 Setup */
6895 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6896 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6da8f446 6897 if (ca0132_quirk(spec) == QUIRK_R3DI) {
6ef0e91e
CM		 6898 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6899 tmp = FLOAT_ONE;
6900 } else
6901 tmp = FLOAT_THREE;
38ba69ff
CM		 6902 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6903
6ef0e91e 6904 /* Mic 2 setup (not present on desktop cards) */
38ba69ff
CM		 6905 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6906 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6da8f446 6907 if (ca0132_quirk(spec) == QUIRK_R3DI)
6ef0e91e 6908 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
38ba69ff
CM		 6909 tmp = FLOAT_ZERO;
6910 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
38ba69ff
CM		 6911}
6912
6913/*
6914 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
6915 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
6916 * you get no sound. I'm guessing this has to do with the Sound Blaster Z
6917 * having an updated DAC, which changes the destination to that DAC.
6918 */
6919static void sbz_connect_streams(struct hda_codec *codec)
6920{
6921 struct ca0132_spec *spec = codec->spec;
6922
6923 mutex_lock(&spec->chipio_mutex);
6924
6925 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
6926
6927 chipio_set_stream_channels(codec, 0x0C, 6);
6928 chipio_set_stream_control(codec, 0x0C, 1);
6929
6930 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
6931 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
6932
6933 /* Setup stream 0x14 with it's source and destination points */
6934 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
6935 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
6936 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
6937 chipio_set_stream_channels(codec, 0x14, 2);
6938 chipio_set_stream_control(codec, 0x14, 1);
6939
6940 codec_dbg(codec, "Connect Streams exited, mutex released.\n");
6941
6942 mutex_unlock(&spec->chipio_mutex);
38ba69ff
CM		 6943}
6944
6945/*
6946 * Write data through ChipIO to setup proper stream destinations.
6947 * Not sure how it exactly works, but it seems to direct data
6948 * to different destinations. Example is f8 to c0, e0 to c0.
6949 * All I know is, if you don't set these, you get no sound.
6950 */
6951static void sbz_chipio_startup_data(struct hda_codec *codec)
6952{
6953 struct ca0132_spec *spec = codec->spec;
6954
6955 mutex_lock(&spec->chipio_mutex);
6956 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
6957
6958 /* These control audio output */
6959 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
6960 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
6961 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
6962 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
6963 /* Signal to update I think */
6964 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6965
6966 chipio_set_stream_channels(codec, 0x0C, 6);
6967 chipio_set_stream_control(codec, 0x0C, 1);
6968 /* No clue what these control */
6da8f446 6969 if (ca0132_quirk(spec) == QUIRK_SBZ) {
c25c73e0
CM		 6970 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
6971 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
6972 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
6973 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
6974 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
6975 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
6976 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
6977 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
6978 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
6979 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
6980 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
6981 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
6da8f446 6982 } else if (ca0132_quirk(spec) == QUIRK_ZXR) {
c25c73e0
CM		 6983 chipio_write_no_mutex(codec, 0x190038, 0x000140c2);
6984 chipio_write_no_mutex(codec, 0x19003c, 0x000141c3);
6985 chipio_write_no_mutex(codec, 0x190040, 0x000150c4);
6986 chipio_write_no_mutex(codec, 0x190044, 0x000151c5);
6987 chipio_write_no_mutex(codec, 0x190050, 0x000142c8);
6988 chipio_write_no_mutex(codec, 0x190054, 0x000143c9);
6989 chipio_write_no_mutex(codec, 0x190058, 0x000152ca);
6990 chipio_write_no_mutex(codec, 0x19005c, 0x000153cb);
6991 }
38ba69ff
CM		 6992 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6993
6994 codec_dbg(codec, "Startup Data exited, mutex released.\n");
6995 mutex_unlock(&spec->chipio_mutex);
6996}
6997
447fd8e9 6998/*
6ef0e91e
CM		 6999 * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. This is
7000 * done after the DSP is loaded.
447fd8e9 7001 */
6ef0e91e 7002static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec)
447fd8e9 7003{
6ef0e91e 7004 struct ca0132_spec *spec = codec->spec;
b5a22935 7005 unsigned int tmp, i;
447fd8e9 7006
b5a22935
CM		 7007 /*
7008 * Gotta run these twice, or else mic works inconsistently. Not clear
7009 * why this is, but multiple tests have confirmed it.
7010 */
7011 for (i = 0; i < 2; i++) {
6da8f446 7012 switch (ca0132_quirk(spec)) {
b5a22935
CM		 7013 case QUIRK_SBZ:
7014 case QUIRK_AE5:
7015 tmp = 0x00000003;
7016 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7017 tmp = 0x00000000;
7018 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
7019 tmp = 0x00000001;
7020 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
7021 tmp = 0x00000004;
7022 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7023 tmp = 0x00000005;
7024 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7025 tmp = 0x00000000;
7026 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7027 break;
7028 case QUIRK_R3D:
7029 case QUIRK_R3DI:
7030 tmp = 0x00000000;
7031 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
7032 tmp = 0x00000001;
7033 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
7034 tmp = 0x00000004;
7035 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7036 tmp = 0x00000005;
7037 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7038 tmp = 0x00000000;
7039 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7040 break;
6da8f446
TI		 7041 default:
7042 break;
b5a22935
CM		 7043 }
7044 msleep(100);
6ef0e91e 7045 }
447fd8e9
CM		 7046}
7047
6ef0e91e 7048static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
38ba69ff 7049{
6ef0e91e 7050 struct ca0132_spec *spec = codec->spec;
38ba69ff
CM		 7051 unsigned int tmp;
7052
7053 chipio_set_stream_control(codec, 0x03, 0);
7054 chipio_set_stream_control(codec, 0x04, 0);
7055
7056 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7057 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7058
7059 tmp = FLOAT_THREE;
7060 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7061
7062 chipio_set_stream_control(codec, 0x03, 1);
7063 chipio_set_stream_control(codec, 0x04, 1);
7064
6da8f446 7065 switch (ca0132_quirk(spec)) {
6ef0e91e
CM		 7066 case QUIRK_SBZ:
7067 chipio_write(codec, 0x18b098, 0x0000000c);
7068 chipio_write(codec, 0x18b09C, 0x0000000c);
7069 break;
7070 case QUIRK_AE5:
7071 chipio_write(codec, 0x18b098, 0x0000000c);
7072 chipio_write(codec, 0x18b09c, 0x0000004c);
7073 break;
6da8f446
TI		 7074 default:
7075 break;
6ef0e91e 7076 }
38ba69ff
CM		 7077}
7078
415cd844
CM		 7079static void ae5_post_dsp_register_set(struct hda_codec *codec)
7080{
7081 struct ca0132_spec *spec = codec->spec;
7082
7083 chipio_8051_write_direct(codec, 0x93, 0x10);
7084 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7085 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
7086 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7087 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
7088
7089 writeb(0xff, spec->mem_base + 0x304);
7090 writeb(0xff, spec->mem_base + 0x304);
7091 writeb(0xff, spec->mem_base + 0x304);
7092 writeb(0xff, spec->mem_base + 0x304);
7093 writeb(0x00, spec->mem_base + 0x100);
7094 writeb(0xff, spec->mem_base + 0x304);
7095 writeb(0x00, spec->mem_base + 0x100);
7096 writeb(0xff, spec->mem_base + 0x304);
7097 writeb(0x00, spec->mem_base + 0x100);
7098 writeb(0xff, spec->mem_base + 0x304);
7099 writeb(0x00, spec->mem_base + 0x100);
7100 writeb(0xff, spec->mem_base + 0x304);
7101
7102 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
7103 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
7104 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7105}
7106
7107static void ae5_post_dsp_param_setup(struct hda_codec *codec)
7108{
7109 /*
7110 * Param3 in the 8051's memory is represented by the ascii string 'mch'
7111 * which seems to be 'multichannel'. This is also mentioned in the
7112 * AE-5's registry values in Windows.
7113 */
7114 chipio_set_control_param(codec, 3, 0);
7115 /*
7116 * I believe ASI is 'audio serial interface' and that it's used to
7117 * change colors on the external LED strip connected to the AE-5.
7118 */
7119 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
7120
7121 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
7122 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7123
7124 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7125 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92);
7126 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7127 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa);
7128 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7129 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22);
7130}
7131
7132static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
7133{
7134 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7135 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41);
7136 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7137 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8);
7138
7139 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7140 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x45);
7141 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7142 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcc);
7143
7144 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7145 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x40);
7146 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7147 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcb);
7148
7149 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7150 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
7151 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7152 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
7153
7154 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7155 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x51);
7156 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7157 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x8d);
7158}
7159
7160static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
7161{
7162 struct ca0132_spec *spec = codec->spec;
7163
7164 mutex_lock(&spec->chipio_mutex);
7165
7166 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
7167
7168 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
7169
7170 chipio_set_stream_channels(codec, 0x0C, 6);
7171 chipio_set_stream_control(codec, 0x0C, 1);
7172
7173 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
7174
7175 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
7176 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
7177 chipio_set_stream_channels(codec, 0x18, 6);
7178 chipio_set_stream_control(codec, 0x18, 1);
7179
7180 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
7181
7182 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7183 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
7184 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7185 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
7186
7187 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
7188
7189 mutex_unlock(&spec->chipio_mutex);
7190}
7191
7192static void ae5_post_dsp_startup_data(struct hda_codec *codec)
7193{
7194 struct ca0132_spec *spec = codec->spec;
7195
7196 mutex_lock(&spec->chipio_mutex);
7197
7198 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
7199 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
7200 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
7201 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
7202
7203 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7204 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
7205 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
7206 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
7207 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
7208 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7209 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7210 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7211 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7212 ca0113_mmio_gpio_set(codec, 0, true);
7213 ca0113_mmio_gpio_set(codec, 1, true);
7214 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
7215
7216 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
7217
7218 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7219 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7220
7221 mutex_unlock(&spec->chipio_mutex);
7222}
7223
5aaca44d
IM		 7224/*
7225 * Setup default parameters for DSP
7226 */
7227static void ca0132_setup_defaults(struct hda_codec *codec)
7228{
e8f1bd5d 7229 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 7230 unsigned int tmp;
7231 int num_fx;
7232 int idx, i;
7233
e8f1bd5d 7234 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 7235 return;
7236
7237 /* out, in effects + voicefx */
7238 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7239 for (idx = 0; idx < num_fx; idx++) {
7240 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7241 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
7242 ca0132_effects[idx].reqs[i],
7243 ca0132_effects[idx].def_vals[i]);
7244 }
7245 }
7246
7247 /*remove DSP headroom*/
7248 tmp = FLOAT_ZERO;
7249 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7250
7251 /*set speaker EQ bypass attenuation*/
7252 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
7253
7254 /* set AMic1 and AMic2 as mono mic */
7255 tmp = FLOAT_ONE;
7256 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7257 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
7258
7259 /* set AMic1 as CrystalVoice input */
7260 tmp = FLOAT_ONE;
7261 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
7262
7263 /* set WUH source */
7264 tmp = FLOAT_TWO;
7265 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7266}
7267
7e6ed62e 7268/*
c986f50c 7269 * Setup default parameters for Recon3D/Recon3Di DSP.
7e6ed62e
CM		 7270 */
7271
c986f50c 7272static void r3d_setup_defaults(struct hda_codec *codec)
7e6ed62e
CM		 7273{
7274 struct ca0132_spec *spec = codec->spec;
7275 unsigned int tmp;
7276 int num_fx;
7277 int idx, i;
7278
7279 if (spec->dsp_state != DSP_DOWNLOADED)
7280 return;
7281
6ef0e91e
CM		 7282 ca0132_alt_dsp_scp_startup(codec);
7283 ca0132_alt_init_analog_mics(codec);
7e6ed62e
CM		 7284
7285 /*remove DSP headroom*/
7286 tmp = FLOAT_ZERO;
7287 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7288
7289 /* set WUH source */
7290 tmp = FLOAT_TWO;
7291 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7292 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7293
7294 /* Set speaker source? */
7295 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
7296
6da8f446 7297 if (ca0132_quirk(spec) == QUIRK_R3DI)
c986f50c 7298 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
7e6ed62e
CM		 7299
7300 /* Setup effect defaults */
7301 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7302 for (idx = 0; idx < num_fx; idx++) {
7303 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7304 dspio_set_uint_param(codec,
7305 ca0132_effects[idx].mid,
7306 ca0132_effects[idx].reqs[i],
7307 ca0132_effects[idx].def_vals[i]);
7308 }
7309 }
7e6ed62e
CM		 7310}
7311
38ba69ff
CM		 7312/*
7313 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
7314 * than the Chromebook setup.
7315 */
7316static void sbz_setup_defaults(struct hda_codec *codec)
7317{
7318 struct ca0132_spec *spec = codec->spec;
6ef0e91e 7319 unsigned int tmp;
38ba69ff
CM		 7320 int num_fx;
7321 int idx, i;
7322
7323 if (spec->dsp_state != DSP_DOWNLOADED)
7324 return;
7325
6ef0e91e
CM		 7326 ca0132_alt_dsp_scp_startup(codec);
7327 ca0132_alt_init_analog_mics(codec);
38ba69ff 7328 sbz_connect_streams(codec);
38ba69ff
CM		 7329 sbz_chipio_startup_data(codec);
7330
7331 chipio_set_stream_control(codec, 0x03, 1);
7332 chipio_set_stream_control(codec, 0x04, 1);
7333
7334 /*
7335 * Sets internal input loopback to off, used to have a switch to
7336 * enable input loopback, but turned out to be way too buggy.
7337 */
7338 tmp = FLOAT_ONE;
7339 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
7340 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
7341
7342 /*remove DSP headroom*/
7343 tmp = FLOAT_ZERO;
7344 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7345
7346 /* set WUH source */
7347 tmp = FLOAT_TWO;
7348 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7349 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7350
7351 /* Set speaker source? */
7352 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
7353
6ef0e91e 7354 ca0132_alt_dsp_initial_mic_setup(codec);
38ba69ff
CM		 7355
7356 /* out, in effects + voicefx */
7357 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7358 for (idx = 0; idx < num_fx; idx++) {
7359 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7360 dspio_set_uint_param(codec,
7361 ca0132_effects[idx].mid,
7362 ca0132_effects[idx].reqs[i],
7363 ca0132_effects[idx].def_vals[i]);
7364 }
7365 }
7366
6ef0e91e 7367 ca0132_alt_create_dummy_stream(codec);
38ba69ff
CM		 7368}
7369
415cd844
CM		 7370/*
7371 * Setup default parameters for the Sound BlasterX AE-5 DSP.
7372 */
7373static void ae5_setup_defaults(struct hda_codec *codec)
7374{
7375 struct ca0132_spec *spec = codec->spec;
7376 unsigned int tmp;
7377 int num_fx;
7378 int idx, i;
7379
7380 if (spec->dsp_state != DSP_DOWNLOADED)
7381 return;
7382
7383 ca0132_alt_dsp_scp_startup(codec);
7384 ca0132_alt_init_analog_mics(codec);
7385 chipio_set_stream_control(codec, 0x03, 1);
7386 chipio_set_stream_control(codec, 0x04, 1);
7387
7388 /* New, unknown SCP req's */
7389 tmp = FLOAT_ZERO;
7390 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
7391 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
7392 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
7393 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
7394
7395 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
7396 ca0113_mmio_gpio_set(codec, 0, false);
7397 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
7398
7399 /* Internal loopback off */
7400 tmp = FLOAT_ONE;
7401 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
7402 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
7403
7404 /*remove DSP headroom*/
7405 tmp = FLOAT_ZERO;
7406 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
7407
7408 /* set WUH source */
7409 tmp = FLOAT_TWO;
7410 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
7411 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7412
7413 /* Set speaker source? */
7414 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
7415
7416 ca0132_alt_dsp_initial_mic_setup(codec);
7417 ae5_post_dsp_register_set(codec);
7418 ae5_post_dsp_param_setup(codec);
7419 ae5_post_dsp_pll_setup(codec);
7420 ae5_post_dsp_stream_setup(codec);
7421 ae5_post_dsp_startup_data(codec);
7422
7423 /* out, in effects + voicefx */
7424 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
7425 for (idx = 0; idx < num_fx; idx++) {
7426 for (i = 0; i <= ca0132_effects[idx].params; i++) {
7427 dspio_set_uint_param(codec,
7428 ca0132_effects[idx].mid,
7429 ca0132_effects[idx].reqs[i],
7430 ca0132_effects[idx].def_vals[i]);
7431 }
7432 }
7433
7434 ca0132_alt_create_dummy_stream(codec);
7435}
7436
5aaca44d
IM		 7437/*
7438 * Initialization of flags in chip
7439 */
7440static void ca0132_init_flags(struct hda_codec *codec)
7441{
009b8f97
CM		 7442 struct ca0132_spec *spec = codec->spec;
7443
6da8f446 7444 if (ca0132_use_alt_functions(spec)) {
009b8f97
CM		 7445 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
7446 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
7447 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
7448 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
7449 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
7450 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
7451 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
7452 chipio_set_control_flag(codec,
7453 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
7454 chipio_set_control_flag(codec,
7455 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
7456 } else {
7457 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
7458 chipio_set_control_flag(codec,
7459 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
7460 chipio_set_control_flag(codec,
7461 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
7462 chipio_set_control_flag(codec,
7463 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
7464 chipio_set_control_flag(codec,
7465 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
7466 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
7467 }
5aaca44d
IM		 7468}
7469
7470/*
7471 * Initialization of parameters in chip
7472 */
7473static void ca0132_init_params(struct hda_codec *codec)
7474{
009b8f97
CM		 7475 struct ca0132_spec *spec = codec->spec;
7476
6da8f446 7477 if (ca0132_use_alt_functions(spec)) {
009b8f97
CM		 7478 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7479 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
7480 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
7481 chipio_set_control_param(codec, 0, 0);
7482 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
7483 }
7484
5aaca44d
IM		 7485 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
7486 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
7487}
95c6e9cb 7488
e90f29e4
IM		 7489static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
7490{
7491 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
7492 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
7493 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
7494 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
7495 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
7496 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
7497
406261ce
IM		 7498 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7499 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
e90f29e4
IM		 7500 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7501}
7502
7503static bool ca0132_download_dsp_images(struct hda_codec *codec)
7504{
7505 bool dsp_loaded = false;
8a19bcee 7506 struct ca0132_spec *spec = codec->spec;
e90f29e4 7507 const struct dsp_image_seg *dsp_os_image;
4fc90fb8 7508 const struct firmware *fw_entry = NULL;
8a19bcee
CM		 7509 /*
7510 * Alternate firmwares for different variants. The Recon3Di apparently
7511 * can use the default firmware, but I'll leave the option in case
7512 * it needs it again.
7513 */
6da8f446 7514 switch (ca0132_quirk(spec)) {
8a19bcee 7515 case QUIRK_SBZ:
7a928186
CM		 7516 case QUIRK_R3D:
7517 case QUIRK_AE5:
7518 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE,
4fc90fb8 7519 codec->card->dev) != 0)
6ef0e91e 7520 codec_dbg(codec, "Desktop firmware not found.");
4fc90fb8 7521 else
7a928186 7522 codec_dbg(codec, "Desktop firmware selected.");
8a19bcee
CM		 7523 break;
7524 case QUIRK_R3DI:
7525 if (request_firmware(&fw_entry, R3DI_EFX_FILE,
4fc90fb8 7526 codec->card->dev) != 0)
8a19bcee 7527 codec_dbg(codec, "Recon3Di alt firmware not detected.");
4fc90fb8 7528 else
8a19bcee 7529 codec_dbg(codec, "Recon3Di firmware selected.");
8a19bcee
CM		 7530 break;
7531 default:
8a19bcee
CM		 7532 break;
7533 }
7534 /*
7535 * Use default ctefx.bin if no alt firmware is detected, or if none
7536 * exists for your particular codec.
7537 */
4fc90fb8 7538 if (!fw_entry) {
8a19bcee
CM		 7539 codec_dbg(codec, "Default firmware selected.");
7540 if (request_firmware(&fw_entry, EFX_FILE,
7541 codec->card->dev) != 0)
7542 return false;
7543 }
e90f29e4 7544
15e4ba66 7545 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
d1d28500 7546 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
d9684bb5 7547 codec_err(codec, "ca0132 DSP load image failed\n");
d1d28500
DR		 7548 goto exit_download;
7549 }
7550
e90f29e4
IM		 7551 dsp_loaded = dspload_wait_loaded(codec);
7552
d1d28500 7553exit_download:
15e4ba66
TI		 7554 release_firmware(fw_entry);
7555
e90f29e4
IM		 7556 return dsp_loaded;
7557}
7558
7559static void ca0132_download_dsp(struct hda_codec *codec)
7560{
7561 struct ca0132_spec *spec = codec->spec;
7562
9a0869f4
TI		 7563#ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
7564 return; /* NOP */
7565#endif
e90f29e4 7566
e24aa0a4
TI		 7567 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
7568 return; /* don't retry failures */
7569
b714a710 7570 chipio_enable_clocks(codec);
e93ac30a
CM		 7571 if (spec->dsp_state != DSP_DOWNLOADED) {
7572 spec->dsp_state = DSP_DOWNLOADING;
7573
7574 if (!ca0132_download_dsp_images(codec))
7575 spec->dsp_state = DSP_DOWNLOAD_FAILED;
7576 else
7577 spec->dsp_state = DSP_DOWNLOADED;
7578 }
e90f29e4 7579
009b8f97 7580 /* For codecs using alt functions, this is already done earlier */
6da8f446 7581 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec))
e90f29e4
IM		 7582 ca0132_set_dsp_msr(codec, true);
7583}
7584
f8fb1170
TI		 7585static void ca0132_process_dsp_response(struct hda_codec *codec,
7586 struct hda_jack_callback *callback)
e90f29e4
IM		 7587{
7588 struct ca0132_spec *spec = codec->spec;
7589
4e76a883 7590 codec_dbg(codec, "ca0132_process_dsp_response\n");
e90f29e4
IM		 7591 if (spec->wait_scp) {
7592 if (dspio_get_response_data(codec) >= 0)
7593 spec->wait_scp = 0;
7594 }
7595
7596 dspio_clear_response_queue(codec);
7597}
7598
f8fb1170 7599static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
e90f29e4 7600{
993884f6 7601 struct ca0132_spec *spec = codec->spec;
2ebab40e 7602 struct hda_jack_tbl *tbl;
e90f29e4 7603
f8fb1170
TI		 7604 /* Delay enabling the HP amp, to let the mic-detection
7605 * state machine run.
7606 */
15c2b3cc 7607 cancel_delayed_work(&spec->unsol_hp_work);
2f35c630 7608 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
2ebab40e
TI		 7609 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
7610 if (tbl)
7611 tbl->block_report = 1;
f8fb1170
TI		 7612}
7613
7614static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
7615{
a1b7f016
CM		 7616 struct ca0132_spec *spec = codec->spec;
7617
6da8f446 7618 if (ca0132_use_alt_functions(spec))
a1b7f016
CM		 7619 ca0132_alt_select_in(codec);
7620 else
7621 ca0132_select_mic(codec);
f8fb1170
TI		 7622}
7623
7624static void ca0132_init_unsol(struct hda_codec *codec)
7625{
d5c016b5
GM		 7626 struct ca0132_spec *spec = codec->spec;
7627 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
7628 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
f8fb1170
TI		 7629 amic_callback);
7630 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
7631 ca0132_process_dsp_response);
63177afc 7632 /* Front headphone jack detection */
6da8f446 7633 if (ca0132_use_alt_functions(spec))
63177afc
CM		 7634 snd_hda_jack_detect_enable_callback(codec,
7635 spec->unsol_tag_front_hp, hp_callback);
e90f29e4
IM		 7636}
7637
5aaca44d
IM		 7638/*
7639 * Verbs tables.
7640 */
7641
7642/* Sends before DSP download. */
7643static struct hda_verb ca0132_base_init_verbs[] = {
7644 /*enable ct extension*/
7645 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
5aaca44d
IM		 7646 {}
7647};
7648
7649/* Send at exit. */
7650static struct hda_verb ca0132_base_exit_verbs[] = {
7651 /*set afg to D3*/
7652 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
7653 /*disable ct extension*/
7654 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
7655 {}
7656};
7657
8a19bcee 7658/* Other verbs tables. Sends after DSP download. */
e93ac30a 7659
5aaca44d
IM		 7660static struct hda_verb ca0132_init_verbs0[] = {
7661 /* chip init verbs */
7662 {0x15, 0x70D, 0xF0},
7663 {0x15, 0x70E, 0xFE},
7664 {0x15, 0x707, 0x75},
7665 {0x15, 0x707, 0xD3},
7666 {0x15, 0x707, 0x09},
7667 {0x15, 0x707, 0x53},
7668 {0x15, 0x707, 0xD4},
7669 {0x15, 0x707, 0xEF},
7670 {0x15, 0x707, 0x75},
7671 {0x15, 0x707, 0xD3},
7672 {0x15, 0x707, 0x09},
7673 {0x15, 0x707, 0x02},
7674 {0x15, 0x707, 0x37},
7675 {0x15, 0x707, 0x78},
7676 {0x15, 0x53C, 0xCE},
7677 {0x15, 0x575, 0xC9},
7678 {0x15, 0x53D, 0xCE},
7679 {0x15, 0x5B7, 0xC9},
7680 {0x15, 0x70D, 0xE8},
7681 {0x15, 0x70E, 0xFE},
7682 {0x15, 0x707, 0x02},
7683 {0x15, 0x707, 0x68},
7684 {0x15, 0x707, 0x62},
7685 {0x15, 0x53A, 0xCE},
7686 {0x15, 0x546, 0xC9},
7687 {0x15, 0x53B, 0xCE},
7688 {0x15, 0x5E8, 0xC9},
e93ac30a
CM		 7689 {}
7690};
7691
e42c7c73
CM		 7692/* Extra init verbs for desktop cards. */
7693static struct hda_verb ca0132_init_verbs1[] = {
e93ac30a
CM		 7694 {0x15, 0x70D, 0x20},
7695 {0x15, 0x70E, 0x19},
7696 {0x15, 0x707, 0x00},
7697 {0x15, 0x539, 0xCE},
7698 {0x15, 0x546, 0xC9},
7699 {0x15, 0x70D, 0xB7},
7700 {0x15, 0x70E, 0x09},
7701 {0x15, 0x707, 0x10},
7702 {0x15, 0x70D, 0xAF},
7703 {0x15, 0x70E, 0x09},
7704 {0x15, 0x707, 0x01},
7705 {0x15, 0x707, 0x05},
7706 {0x15, 0x70D, 0x73},
7707 {0x15, 0x70E, 0x09},
7708 {0x15, 0x707, 0x14},
7709 {0x15, 0x6FF, 0xC4},
5aaca44d
IM		 7710 {}
7711};
7712
95c6e9cb
IM		 7713static void ca0132_init_chip(struct hda_codec *codec)
7714{
7715 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 7716 int num_fx;
7717 int i;
7718 unsigned int on;
95c6e9cb
IM		 7719
7720 mutex_init(&spec->chipio_mutex);
5aaca44d
IM		 7721
7722 spec->cur_out_type = SPEAKER_OUT;
6da8f446 7723 if (!ca0132_use_alt_functions(spec))
7cb9d94c
CM		 7724 spec->cur_mic_type = DIGITAL_MIC;
7725 else
7726 spec->cur_mic_type = REAR_MIC;
7727
5aaca44d
IM		 7728 spec->cur_mic_boost = 0;
7729
7730 for (i = 0; i < VNODES_COUNT; i++) {
7731 spec->vnode_lvol[i] = 0x5a;
7732 spec->vnode_rvol[i] = 0x5a;
7733 spec->vnode_lswitch[i] = 0;
7734 spec->vnode_rswitch[i] = 0;
7735 }
7736
7737 /*
7738 * Default states for effects are in ca0132_effects[].
7739 */
7740 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
7741 for (i = 0; i < num_fx; i++) {
7742 on = (unsigned int)ca0132_effects[i].reqs[0];
7743 spec->effects_switch[i] = on ? 1 : 0;
7744 }
47cdf76e
CM		 7745 /*
7746 * Sets defaults for the effect slider controls, only for alternative
7747 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
7748 */
6da8f446 7749 if (ca0132_use_alt_controls(spec)) {
47cdf76e
CM		 7750 spec->xbass_xover_freq = 8;
7751 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
7752 spec->fx_ctl_val[i] = effect_slider_defaults[i];
7753 }
5aaca44d
IM		 7754
7755 spec->voicefx_val = 0;
7756 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
7757 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
7758
76dea4db
CM		 7759 /*
7760 * The ZxR doesn't have a front panel header, and it's line-in is on
7761 * the daughter board. So, there is no input enum control, and we need
7762 * to make sure that spec->in_enum_val is set properly.
7763 */
6da8f446 7764 if (ca0132_quirk(spec) == QUIRK_ZXR)
76dea4db
CM		 7765 spec->in_enum_val = REAR_MIC;
7766
44f0c978
IM		 7767#ifdef ENABLE_TUNING_CONTROLS
7768 ca0132_init_tuning_defaults(codec);
7769#endif
95c6e9cb
IM		 7770}
7771
2e48b2b7
CM		 7772/*
7773 * Recon3Di exit specific commands.
7774 */
7775/* prevents popping noise on shutdown */
7776static void r3di_gpio_shutdown(struct hda_codec *codec)
7777{
7778 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
7779}
7780
7781/*
7782 * Sound Blaster Z exit specific commands.
7783 */
7784static void sbz_region2_exit(struct hda_codec *codec)
7785{
7786 struct ca0132_spec *spec = codec->spec;
7787 unsigned int i;
7788
7789 for (i = 0; i < 4; i++)
7790 writeb(0x0, spec->mem_base + 0x100);
7791 for (i = 0; i < 8; i++)
7792 writeb(0xb3, spec->mem_base + 0x304);
a62e4739 7793
b9b41345
CM		 7794 ca0113_mmio_gpio_set(codec, 0, false);
7795 ca0113_mmio_gpio_set(codec, 1, false);
7796 ca0113_mmio_gpio_set(codec, 4, true);
7797 ca0113_mmio_gpio_set(codec, 5, false);
7798 ca0113_mmio_gpio_set(codec, 7, false);
2e48b2b7
CM		 7799}
7800
7801static void sbz_set_pin_ctl_default(struct hda_codec *codec)
7802{
7803 hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
7804 unsigned int i;
7805
7806 snd_hda_codec_write(codec, 0x11, 0,
7807 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
7808
7809 for (i = 0; i < 5; i++)
7810 snd_hda_codec_write(codec, pins[i], 0,
7811 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
7812}
7813
2f295f91 7814static void ca0132_clear_unsolicited(struct hda_codec *codec)
2e48b2b7
CM		 7815{
7816 hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
7817 unsigned int i;
7818
7819 for (i = 0; i < 7; i++) {
7820 snd_hda_codec_write(codec, pins[i], 0,
7821 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
7822 }
7823}
7824
7825/* On shutdown, sends commands in sets of three */
7826static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
7827 int mask, int data)
7828{
7829 if (dir >= 0)
7830 snd_hda_codec_write(codec, 0x01, 0,
7831 AC_VERB_SET_GPIO_DIRECTION, dir);
7832 if (mask >= 0)
7833 snd_hda_codec_write(codec, 0x01, 0,
7834 AC_VERB_SET_GPIO_MASK, mask);
7835
7836 if (data >= 0)
7837 snd_hda_codec_write(codec, 0x01, 0,
7838 AC_VERB_SET_GPIO_DATA, data);
7839}
7840
7675a2a9
CM		 7841static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec)
7842{
7843 hda_nid_t pins[7] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01};
7844 unsigned int i;
7845
7846 for (i = 0; i < 7; i++)
7847 snd_hda_codec_write(codec, pins[i], 0,
7848 AC_VERB_SET_POWER_STATE, 0x03);
7849}
7850
2e48b2b7
CM		 7851static void sbz_exit_chip(struct hda_codec *codec)
7852{
009b8f97
CM		 7853 chipio_set_stream_control(codec, 0x03, 0);
7854 chipio_set_stream_control(codec, 0x04, 0);
2e48b2b7
CM		 7855
7856 /* Mess with GPIO */
7857 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
7858 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
7859 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
7860
009b8f97
CM		 7861 chipio_set_stream_control(codec, 0x14, 0);
7862 chipio_set_stream_control(codec, 0x0C, 0);
2e48b2b7
CM		 7863
7864 chipio_set_conn_rate(codec, 0x41, SR_192_000);
7865 chipio_set_conn_rate(codec, 0x91, SR_192_000);
7866
7867 chipio_write(codec, 0x18a020, 0x00000083);
7868
7869 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
7870 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
7871 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
7872
009b8f97 7873 chipio_set_stream_control(codec, 0x0C, 0);
2e48b2b7
CM		 7874
7875 chipio_set_control_param(codec, 0x0D, 0x24);
7876
2f295f91 7877 ca0132_clear_unsolicited(codec);
2e48b2b7
CM		 7878 sbz_set_pin_ctl_default(codec);
7879
7880 snd_hda_codec_write(codec, 0x0B, 0,
7881 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
7882
2e48b2b7
CM		 7883 sbz_region2_exit(codec);
7884}
7885
2f295f91
CM		 7886static void r3d_exit_chip(struct hda_codec *codec)
7887{
7888 ca0132_clear_unsolicited(codec);
7889 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7890 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
7891}
7892
edb1b3ab
CM		 7893static void ae5_exit_chip(struct hda_codec *codec)
7894{
7895 chipio_set_stream_control(codec, 0x03, 0);
7896 chipio_set_stream_control(codec, 0x04, 0);
7897
7898 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
7899 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7900 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7901 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
7902 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
7903 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00);
7904 ca0113_mmio_gpio_set(codec, 0, false);
7905 ca0113_mmio_gpio_set(codec, 1, false);
7906
7907 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7908 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
7909
7910 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7911
7912 chipio_set_stream_control(codec, 0x18, 0);
7913 chipio_set_stream_control(codec, 0x0c, 0);
7914
7915 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83);
7916}
7917
96395e86
CM		 7918static void zxr_exit_chip(struct hda_codec *codec)
7919{
7920 chipio_set_stream_control(codec, 0x03, 0);
7921 chipio_set_stream_control(codec, 0x04, 0);
7922 chipio_set_stream_control(codec, 0x14, 0);
7923 chipio_set_stream_control(codec, 0x0C, 0);
7924
7925 chipio_set_conn_rate(codec, 0x41, SR_192_000);
7926 chipio_set_conn_rate(codec, 0x91, SR_192_000);
7927
7928 chipio_write(codec, 0x18a020, 0x00000083);
7929
7930 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7931 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
7932
7933 ca0132_clear_unsolicited(codec);
7934 sbz_set_pin_ctl_default(codec);
7935 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00);
7936
7937 ca0113_mmio_gpio_set(codec, 5, false);
7938 ca0113_mmio_gpio_set(codec, 2, false);
7939 ca0113_mmio_gpio_set(codec, 3, false);
7940 ca0113_mmio_gpio_set(codec, 0, false);
7941 ca0113_mmio_gpio_set(codec, 4, true);
7942 ca0113_mmio_gpio_set(codec, 0, true);
7943 ca0113_mmio_gpio_set(codec, 5, true);
7944 ca0113_mmio_gpio_set(codec, 2, false);
7945 ca0113_mmio_gpio_set(codec, 3, false);
7946}
7947
95c6e9cb
IM		 7948static void ca0132_exit_chip(struct hda_codec *codec)
7949{
7950 /* put any chip cleanup stuffs here. */
5aaca44d
IM		 7951
7952 if (dspload_is_loaded(codec))
7953 dsp_reset(codec);
95c6e9cb
IM		 7954}
7955
38ba69ff
CM		 7956/*
7957 * This fixes a problem that was hard to reproduce. Very rarely, I would
7958 * boot up, and there would be no sound, but the DSP indicated it had loaded
7959 * properly. I did a few memory dumps to see if anything was different, and
7960 * there were a few areas of memory uninitialized with a1a2a3a4. This function
7961 * checks if those areas are uninitialized, and if they are, it'll attempt to
7962 * reload the card 3 times. Usually it fixes by the second.
7963 */
7964static void sbz_dsp_startup_check(struct hda_codec *codec)
7965{
7966 struct ca0132_spec *spec = codec->spec;
7967 unsigned int dsp_data_check[4];
7968 unsigned int cur_address = 0x390;
7969 unsigned int i;
7970 unsigned int failure = 0;
7971 unsigned int reload = 3;
7972
7973 if (spec->startup_check_entered)
7974 return;
7975
7976 spec->startup_check_entered = true;
7977
7978 for (i = 0; i < 4; i++) {
7979 chipio_read(codec, cur_address, &dsp_data_check[i]);
7980 cur_address += 0x4;
7981 }
7982 for (i = 0; i < 4; i++) {
7983 if (dsp_data_check[i] == 0xa1a2a3a4)
7984 failure = 1;
7985 }
7986
7987 codec_dbg(codec, "Startup Check: %d ", failure);
7988 if (failure)
7989 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
7990 /*
7991 * While the failure condition is true, and we haven't reached our
7992 * three reload limit, continue trying to reload the driver and
7993 * fix the issue.
7994 */
7995 while (failure && (reload != 0)) {
7996 codec_info(codec, "Reloading... Tries left: %d", reload);
7997 sbz_exit_chip(codec);
7998 spec->dsp_state = DSP_DOWNLOAD_INIT;
7999 codec->patch_ops.init(codec);
8000 failure = 0;
8001 for (i = 0; i < 4; i++) {
8002 chipio_read(codec, cur_address, &dsp_data_check[i]);
8003 cur_address += 0x4;
8004 }
8005 for (i = 0; i < 4; i++) {
8006 if (dsp_data_check[i] == 0xa1a2a3a4)
8007 failure = 1;
8008 }
8009 reload--;
8010 }
8011
8012 if (!failure && reload < 3)
8013 codec_info(codec, "DSP fixed.");
8014
8015 if (!failure)
8016 return;
8017
8018 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
8019}
8020
e93ac30a
CM		 8021/*
8022 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
8023 * extra precision for decibel values. If you had the dB value in floating point
8024 * you would take the value after the decimal point, multiply by 64, and divide
8025 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
8026 * implement fixed point or floating point dB volumes. For now, I'll set them
8027 * to 0 just incase a value has lingered from a boot into Windows.
8028 */
8029static void ca0132_alt_vol_setup(struct hda_codec *codec)
8030{
8031 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
8032 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
8033 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
8034 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
8035 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
8036 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
8037 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
8038 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
8039}
8040
8041/*
8042 * Extra commands that don't really fit anywhere else.
8043 */
8044static void sbz_pre_dsp_setup(struct hda_codec *codec)
8045{
8046 struct ca0132_spec *spec = codec->spec;
8047
8048 writel(0x00820680, spec->mem_base + 0x01C);
8049 writel(0x00820680, spec->mem_base + 0x01C);
8050
e93ac30a
CM		 8051 chipio_write(codec, 0x18b0a4, 0x000000c2);
8052
8053 snd_hda_codec_write(codec, 0x11, 0,
8054 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
8055}
8056
e42c7c73
CM		 8057static void r3d_pre_dsp_setup(struct hda_codec *codec)
8058{
e42c7c73
CM		 8059 chipio_write(codec, 0x18b0a4, 0x000000c2);
8060
8061 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8062 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
8063 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8064 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
8065 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8066 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
8067
8068 snd_hda_codec_write(codec, 0x11, 0,
8069 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
8070}
8071
e93ac30a
CM		 8072static void r3di_pre_dsp_setup(struct hda_codec *codec)
8073{
8074 chipio_write(codec, 0x18b0a4, 0x000000c2);
8075
8076 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8077 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
8078 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8079 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
8080 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8081 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
8082
8083 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8084 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
8085 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8086 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
8087 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8088 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
8089 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8090 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
8091
8092 snd_hda_codec_write(codec, 0x11, 0,
8093 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
8094}
8095
e93ac30a
CM		 8096/*
8097 * These are sent before the DSP is downloaded. Not sure
8098 * what they do, or if they're necessary. Could possibly
8099 * be removed. Figure they're better to leave in.
8100 */
e42c7c73 8101static void ca0132_mmio_init(struct hda_codec *codec)
e93ac30a
CM		 8102{
8103 struct ca0132_spec *spec = codec->spec;
8104
6da8f446 8105 if (ca0132_quirk(spec) == QUIRK_AE5)
ce715448
CM		 8106 writel(0x00000001, spec->mem_base + 0x400);
8107 else
8108 writel(0x00000000, spec->mem_base + 0x400);
8109
6da8f446 8110 if (ca0132_quirk(spec) == QUIRK_AE5)
ce715448
CM		 8111 writel(0x00000001, spec->mem_base + 0x408);
8112 else
8113 writel(0x00000000, spec->mem_base + 0x408);
8114
6da8f446 8115 if (ca0132_quirk(spec) == QUIRK_AE5)
ce715448
CM		 8116 writel(0x00000001, spec->mem_base + 0x40c);
8117 else
8118 writel(0x00000000, spec->mem_base + 0x40C);
8119
6da8f446 8120 if (ca0132_quirk(spec) == QUIRK_ZXR)
2e492b8e
CM		 8121 writel(0x00880640, spec->mem_base + 0x01C);
8122 else
8123 writel(0x00880680, spec->mem_base + 0x01C);
ce715448 8124
6da8f446 8125 if (ca0132_quirk(spec) == QUIRK_AE5)
ce715448
CM		 8126 writel(0x00000080, spec->mem_base + 0xC0C);
8127 else
8128 writel(0x00000083, spec->mem_base + 0xC0C);
8129
e93ac30a
CM		 8130 writel(0x00000030, spec->mem_base + 0xC00);
8131 writel(0x00000000, spec->mem_base + 0xC04);
ce715448 8132
6da8f446 8133 if (ca0132_quirk(spec) == QUIRK_AE5)
ce715448
CM		 8134 writel(0x00000000, spec->mem_base + 0xC0C);
8135 else
8136 writel(0x00000003, spec->mem_base + 0xC0C);
8137
e93ac30a
CM		 8138 writel(0x00000003, spec->mem_base + 0xC0C);
8139 writel(0x00000003, spec->mem_base + 0xC0C);
8140 writel(0x00000003, spec->mem_base + 0xC0C);
ce715448 8141
6da8f446 8142 if (ca0132_quirk(spec) == QUIRK_AE5)
ce715448
CM		 8143 writel(0x00000001, spec->mem_base + 0xC08);
8144 else
8145 writel(0x000000C1, spec->mem_base + 0xC08);
8146
e93ac30a
CM		 8147 writel(0x000000F1, spec->mem_base + 0xC08);
8148 writel(0x00000001, spec->mem_base + 0xC08);
8149 writel(0x000000C7, spec->mem_base + 0xC08);
8150 writel(0x000000C1, spec->mem_base + 0xC08);
8151 writel(0x00000080, spec->mem_base + 0xC04);
ce715448 8152
6da8f446 8153 if (ca0132_quirk(spec) == QUIRK_AE5) {
ce715448
CM		 8154 writel(0x00000000, spec->mem_base + 0x42c);
8155 writel(0x00000000, spec->mem_base + 0x46c);
8156 writel(0x00000000, spec->mem_base + 0x4ac);
8157 writel(0x00000000, spec->mem_base + 0x4ec);
8158 writel(0x00000000, spec->mem_base + 0x43c);
8159 writel(0x00000000, spec->mem_base + 0x47c);
8160 writel(0x00000000, spec->mem_base + 0x4bc);
8161 writel(0x00000000, spec->mem_base + 0x4fc);
8162 writel(0x00000600, spec->mem_base + 0x100);
8163 writel(0x00000014, spec->mem_base + 0x410);
8164 writel(0x0000060f, spec->mem_base + 0x100);
8165 writel(0x0000070f, spec->mem_base + 0x100);
8166 writel(0x00000aff, spec->mem_base + 0x830);
8167 writel(0x00000000, spec->mem_base + 0x86c);
8168 writel(0x0000006b, spec->mem_base + 0x800);
8169 writel(0x00000001, spec->mem_base + 0x86c);
8170 writel(0x0000006b, spec->mem_base + 0x800);
8171 writel(0x00000057, spec->mem_base + 0x804);
8172 writel(0x00800000, spec->mem_base + 0x20c);
8173 }
e93ac30a
CM		 8174}
8175
b9b41345
CM		 8176/*
8177 * This function writes to some SFR's, does some region2 writes, and then
8178 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
8179 * what it does.
8180 */
8181static void ae5_register_set(struct hda_codec *codec)
8182{
8183 struct ca0132_spec *spec = codec->spec;
8184
8185 chipio_8051_write_direct(codec, 0x93, 0x10);
8186 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8187 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
8188 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8189 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
8190
8191 writeb(0x0f, spec->mem_base + 0x304);
8192 writeb(0x0f, spec->mem_base + 0x304);
8193 writeb(0x0f, spec->mem_base + 0x304);
8194 writeb(0x0f, spec->mem_base + 0x304);
8195 writeb(0x0e, spec->mem_base + 0x100);
8196 writeb(0x1f, spec->mem_base + 0x304);
8197 writeb(0x0c, spec->mem_base + 0x100);
8198 writeb(0x3f, spec->mem_base + 0x304);
8199 writeb(0x08, spec->mem_base + 0x100);
8200 writeb(0x7f, spec->mem_base + 0x304);
8201 writeb(0x00, spec->mem_base + 0x100);
8202 writeb(0xff, spec->mem_base + 0x304);
8203
8204 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
8205
8206 chipio_8051_write_direct(codec, 0x90, 0x00);
8207 chipio_8051_write_direct(codec, 0x90, 0x10);
8208
8209 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8210
8211 chipio_write(codec, 0x18b0a4, 0x000000c2);
8212
8213 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
8214 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
8215}
8216
e93ac30a
CM		 8217/*
8218 * Extra init functions for alternative ca0132 codecs. Done
8219 * here so they don't clutter up the main ca0132_init function
8220 * anymore than they have to.
8221 */
8222static void ca0132_alt_init(struct hda_codec *codec)
8223{
8224 struct ca0132_spec *spec = codec->spec;
8225
8226 ca0132_alt_vol_setup(codec);
8227
6da8f446 8228 switch (ca0132_quirk(spec)) {
e93ac30a
CM		 8229 case QUIRK_SBZ:
8230 codec_dbg(codec, "SBZ alt_init");
8231 ca0132_gpio_init(codec);
8232 sbz_pre_dsp_setup(codec);
8233 snd_hda_sequence_write(codec, spec->chip_init_verbs);
e42c7c73 8234 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
e93ac30a
CM		 8235 break;
8236 case QUIRK_R3DI:
8237 codec_dbg(codec, "R3DI alt_init");
8238 ca0132_gpio_init(codec);
8239 ca0132_gpio_setup(codec);
7e6ed62e 8240 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
e93ac30a
CM		 8241 r3di_pre_dsp_setup(codec);
8242 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8243 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
8244 break;
e42c7c73
CM		 8245 case QUIRK_R3D:
8246 r3d_pre_dsp_setup(codec);
8247 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8248 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
8249 break;
03c9b6b1
CM		 8250 case QUIRK_AE5:
8251 ca0132_gpio_init(codec);
8252 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8253 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49);
8254 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8255 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88);
8256 chipio_write(codec, 0x18b030, 0x00000020);
8257 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8258 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
8259 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8260 break;
2e492b8e
CM		 8261 case QUIRK_ZXR:
8262 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8263 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
8264 break;
6da8f446
TI		 8265 default:
8266 break;
e93ac30a
CM		 8267 }
8268}
8269
95c6e9cb
IM		 8270static int ca0132_init(struct hda_codec *codec)
8271{
8272 struct ca0132_spec *spec = codec->spec;
8273 struct auto_pin_cfg *cfg = &spec->autocfg;
8274 int i;
e93ac30a
CM		 8275 bool dsp_loaded;
8276
8277 /*
8278 * If the DSP is already downloaded, and init has been entered again,
8279 * there's only two reasons for it. One, the codec has awaken from a
8280 * suspended state, and in that case dspload_is_loaded will return
8281 * false, and the init will be ran again. The other reason it gets
8282 * re entered is on startup for some reason it triggers a suspend and
8283 * resume state. In this case, it will check if the DSP is downloaded,
8284 * and not run the init function again. For codecs using alt_functions,
8285 * it will check if the DSP is loaded properly.
8286 */
8287 if (spec->dsp_state == DSP_DOWNLOADED) {
8288 dsp_loaded = dspload_is_loaded(codec);
8289 if (!dsp_loaded) {
8290 spec->dsp_reload = true;
8291 spec->dsp_state = DSP_DOWNLOAD_INIT;
38ba69ff 8292 } else {
6da8f446 8293 if (ca0132_quirk(spec) == QUIRK_SBZ)
38ba69ff 8294 sbz_dsp_startup_check(codec);
e93ac30a 8295 return 0;
38ba69ff 8296 }
e93ac30a 8297 }
95c6e9cb 8298
e24aa0a4
TI		 8299 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
8300 spec->dsp_state = DSP_DOWNLOAD_INIT;
4a8b89f9 8301 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
5aaca44d 8302
6da8f446 8303 if (ca0132_use_pci_mmio(spec))
e42c7c73 8304 ca0132_mmio_init(codec);
e93ac30a 8305
664c7155 8306 snd_hda_power_up_pm(codec);
5aaca44d 8307
6da8f446 8308 if (ca0132_quirk(spec) == QUIRK_AE5)
b9b41345
CM		 8309 ae5_register_set(codec);
8310
f8fb1170 8311 ca0132_init_unsol(codec);
5aaca44d
IM		 8312 ca0132_init_params(codec);
8313 ca0132_init_flags(codec);
7e6ed62e 8314
5aaca44d 8315 snd_hda_sequence_write(codec, spec->base_init_verbs);
e93ac30a 8316
6da8f446 8317 if (ca0132_use_alt_functions(spec))
e93ac30a
CM		 8318 ca0132_alt_init(codec);
8319
01ef7dbf 8320 ca0132_download_dsp(codec);
7e6ed62e 8321
5aaca44d 8322 ca0132_refresh_widget_caps(codec);
e93ac30a 8323
6da8f446 8324 switch (ca0132_quirk(spec)) {
7e6ed62e 8325 case QUIRK_R3DI:
c986f50c
CM		 8326 case QUIRK_R3D:
8327 r3d_setup_defaults(codec);
7e6ed62e 8328 break;
126b75e0 8329 case QUIRK_SBZ:
c25c73e0 8330 case QUIRK_ZXR:
d97420d2 8331 sbz_setup_defaults(codec);
126b75e0 8332 break;
415cd844
CM		 8333 case QUIRK_AE5:
8334 ae5_setup_defaults(codec);
8335 break;
126b75e0 8336 default:
38ba69ff
CM		 8337 ca0132_setup_defaults(codec);
8338 ca0132_init_analog_mic2(codec);
8339 ca0132_init_dmic(codec);
7e6ed62e 8340 break;
38ba69ff 8341 }
5aaca44d
IM		 8342
8343 for (i = 0; i < spec->num_outputs; i++)
8344 init_output(codec, spec->out_pins[i], spec->dacs[0]);
01ef7dbf 8345
95c6e9cb
IM		 8346 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
8347
8348 for (i = 0; i < spec->num_inputs; i++)
8349 init_input(codec, spec->input_pins[i], spec->adcs[i]);
8350
8351 init_input(codec, cfg->dig_in_pin, spec->dig_in);
8352
6da8f446 8353 if (!ca0132_use_alt_functions(spec)) {
e93ac30a
CM		 8354 snd_hda_sequence_write(codec, spec->chip_init_verbs);
8355 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8356 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
8357 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8358 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
8359 }
8360
6da8f446 8361 if (ca0132_quirk(spec) == QUIRK_SBZ)
e93ac30a
CM		 8362 ca0132_gpio_setup(codec);
8363
d5c016b5 8364 snd_hda_sequence_write(codec, spec->spec_init_verbs);
6da8f446 8365 if (ca0132_use_alt_functions(spec)) {
7cb9d94c
CM		 8366 ca0132_alt_select_out(codec);
8367 ca0132_alt_select_in(codec);
d97420d2 8368 } else {
7cb9d94c
CM		 8369 ca0132_select_out(codec);
8370 ca0132_select_mic(codec);
7cb9d94c 8371 }
5aaca44d 8372
a73d511c
IM		 8373 snd_hda_jack_report_sync(codec);
8374
e93ac30a
CM		 8375 /*
8376 * Re set the PlayEnhancement switch on a resume event, because the
8377 * controls will not be reloaded.
8378 */
8379 if (spec->dsp_reload) {
8380 spec->dsp_reload = false;
8381 ca0132_pe_switch_set(codec);
8382 }
8383
664c7155 8384 snd_hda_power_down_pm(codec);
95c6e9cb
IM		 8385
8386 return 0;
8387}
8388
7675a2a9
CM		 8389static int dbpro_init(struct hda_codec *codec)
8390{
8391 struct ca0132_spec *spec = codec->spec;
8392 struct auto_pin_cfg *cfg = &spec->autocfg;
8393 unsigned int i;
8394
8395 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
8396 init_input(codec, cfg->dig_in_pin, spec->dig_in);
8397
8398 for (i = 0; i < spec->num_inputs; i++)
8399 init_input(codec, spec->input_pins[i], spec->adcs[i]);
8400
8401 return 0;
8402}
8403
95c6e9cb
IM		 8404static void ca0132_free(struct hda_codec *codec)
8405{
5aaca44d
IM		 8406 struct ca0132_spec *spec = codec->spec;
8407
993884f6 8408 cancel_delayed_work_sync(&spec->unsol_hp_work);
5aaca44d 8409 snd_hda_power_up(codec);
6da8f446 8410 switch (ca0132_quirk(spec)) {
2e48b2b7
CM		 8411 case QUIRK_SBZ:
8412 sbz_exit_chip(codec);
8413 break;
96395e86
CM		 8414 case QUIRK_ZXR:
8415 zxr_exit_chip(codec);
8416 break;
2f295f91
CM		 8417 case QUIRK_R3D:
8418 r3d_exit_chip(codec);
8419 break;
edb1b3ab
CM		 8420 case QUIRK_AE5:
8421 ae5_exit_chip(codec);
8422 break;
2e48b2b7
CM		 8423 case QUIRK_R3DI:
8424 r3di_gpio_shutdown(codec);
2e48b2b7 8425 break;
6da8f446
TI		 8426 default:
8427 break;
2e48b2b7 8428 }
2f295f91
CM		 8429
8430 snd_hda_sequence_write(codec, spec->base_exit_verbs);
8431 ca0132_exit_chip(codec);
8432
5aaca44d 8433 snd_hda_power_down(codec);
c97617a8
TI		 8434#ifdef CONFIG_PCI
8435 if (spec->mem_base)
d99501b8 8436 pci_iounmap(codec->bus->pci, spec->mem_base);
c97617a8 8437#endif
d5c016b5 8438 kfree(spec->spec_init_verbs);
95c6e9cb
IM		 8439 kfree(codec->spec);
8440}
8441
7675a2a9
CM		 8442static void dbpro_free(struct hda_codec *codec)
8443{
8444 struct ca0132_spec *spec = codec->spec;
8445
8446 zxr_dbpro_power_state_shutdown(codec);
8447
8448 kfree(spec->spec_init_verbs);
8449 kfree(codec->spec);
8450}
8451
2e48b2b7
CM		 8452static void ca0132_reboot_notify(struct hda_codec *codec)
8453{
8454 codec->patch_ops.free(codec);
8455}
8456
071f1344 8457static const struct hda_codec_ops ca0132_patch_ops = {
95c6e9cb
IM		 8458 .build_controls = ca0132_build_controls,
8459 .build_pcms = ca0132_build_pcms,
8460 .init = ca0132_init,
8461 .free = ca0132_free,
f8fb1170 8462 .unsol_event = snd_hda_jack_unsol_event,
2e48b2b7 8463 .reboot_notify = ca0132_reboot_notify,
95c6e9cb
IM		 8464};
8465
7675a2a9
CM		 8466static const struct hda_codec_ops dbpro_patch_ops = {
8467 .build_controls = dbpro_build_controls,
8468 .build_pcms = dbpro_build_pcms,
8469 .init = dbpro_init,
8470 .free = dbpro_free,
8471};
8472
441aa6a0
IM		 8473static void ca0132_config(struct hda_codec *codec)
8474{
8475 struct ca0132_spec *spec = codec->spec;
441aa6a0
IM		 8476
8477 spec->dacs[0] = 0x2;
8478 spec->dacs[1] = 0x3;
8479 spec->dacs[2] = 0x4;
8480
8481 spec->multiout.dac_nids = spec->dacs;
8482 spec->multiout.num_dacs = 3;
441aa6a0 8483
6da8f446 8484 if (!ca0132_use_alt_functions(spec))
63177afc
CM		 8485 spec->multiout.max_channels = 2;
8486 else
8487 spec->multiout.max_channels = 6;
8488
6da8f446 8489 switch (ca0132_quirk(spec)) {
63177afc 8490 case QUIRK_ALIENWARE:
d06feaf0 8491 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__);
fe14f39e 8492 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
d06feaf0
CM		 8493 break;
8494 case QUIRK_SBZ:
8495 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
8496 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
8497 break;
6dcd7244
CM		 8498 case QUIRK_ZXR:
8499 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__);
8500 snd_hda_apply_pincfgs(codec, zxr_pincfgs);
8501 break;
d06feaf0
CM		 8502 case QUIRK_R3D:
8503 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
8504 snd_hda_apply_pincfgs(codec, r3d_pincfgs);
8505 break;
8506 case QUIRK_R3DI:
8507 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
8508 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
8509 break;
8510 case QUIRK_AE5:
8511 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__);
a6b0961b 8512 snd_hda_apply_pincfgs(codec, ae5_pincfgs);
d06feaf0 8513 break;
6da8f446
TI		 8514 default:
8515 break;
d06feaf0 8516 }
fe14f39e 8517
6da8f446 8518 switch (ca0132_quirk(spec)) {
d06feaf0 8519 case QUIRK_ALIENWARE:
fe14f39e
TI		 8520 spec->num_outputs = 2;
8521 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 8522 spec->out_pins[1] = 0x0f;
fe14f39e
TI		 8523 spec->shared_out_nid = 0x2;
8524 spec->unsol_tag_hp = 0x0f;
8525
8526 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
8527 spec->adcs[1] = 0x8; /* analog mic2 */
8528 spec->adcs[2] = 0xa; /* what u hear */
8529
8530 spec->num_inputs = 3;
8531 spec->input_pins[0] = 0x12;
8532 spec->input_pins[1] = 0x11;
8533 spec->input_pins[2] = 0x13;
8534 spec->shared_mic_nid = 0x7;
8535 spec->unsol_tag_amic1 = 0x11;
63177afc
CM		 8536 break;
8537 case QUIRK_SBZ:
7f73df95 8538 case QUIRK_R3D:
63177afc
CM		 8539 spec->num_outputs = 2;
8540 spec->out_pins[0] = 0x0B; /* Line out */
8541 spec->out_pins[1] = 0x0F; /* Rear headphone out */
8542 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
8543 spec->out_pins[3] = 0x11; /* Rear surround */
8544 spec->shared_out_nid = 0x2;
8545 spec->unsol_tag_hp = spec->out_pins[1];
8546 spec->unsol_tag_front_hp = spec->out_pins[2];
8547
8548 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
8549 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
8550 spec->adcs[2] = 0xa; /* what u hear */
8551
8552 spec->num_inputs = 2;
8553 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8554 spec->input_pins[1] = 0x13; /* What U Hear */
8555 spec->shared_mic_nid = 0x7;
8556 spec->unsol_tag_amic1 = spec->input_pins[0];
8557
8558 /* SPDIF I/O */
8559 spec->dig_out = 0x05;
8560 spec->multiout.dig_out_nid = spec->dig_out;
6dcd7244
CM		 8561 spec->dig_in = 0x09;
8562 break;
8563 case QUIRK_ZXR:
8564 spec->num_outputs = 2;
8565 spec->out_pins[0] = 0x0B; /* Line out */
8566 spec->out_pins[1] = 0x0F; /* Rear headphone out */
8567 spec->out_pins[2] = 0x10; /* Center/LFE */
8568 spec->out_pins[3] = 0x11; /* Rear surround */
8569 spec->shared_out_nid = 0x2;
8570 spec->unsol_tag_hp = spec->out_pins[1];
8571 spec->unsol_tag_front_hp = spec->out_pins[2];
8572
8573 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
8574 spec->adcs[1] = 0x8; /* Not connected, no front mic */
8575 spec->adcs[2] = 0xa; /* what u hear */
8576
8577 spec->num_inputs = 2;
8578 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8579 spec->input_pins[1] = 0x13; /* What U Hear */
8580 spec->shared_mic_nid = 0x7;
8581 spec->unsol_tag_amic1 = spec->input_pins[0];
8582 break;
8583 case QUIRK_ZXR_DBPRO:
8584 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */
8585
8586 spec->num_inputs = 1;
8587 spec->input_pins[0] = 0x11; /* RCA Line-in */
8588
8589 spec->dig_out = 0x05;
8590 spec->multiout.dig_out_nid = spec->dig_out;
8591
63177afc 8592 spec->dig_in = 0x09;
63177afc 8593 break;
d06feaf0
CM		 8594 case QUIRK_AE5:
8595 spec->num_outputs = 2;
8596 spec->out_pins[0] = 0x0B; /* Line out */
8597 spec->out_pins[1] = 0x11; /* Rear headphone out */
8598 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
8599 spec->out_pins[3] = 0x0F; /* Rear surround */
8600 spec->shared_out_nid = 0x2;
8601 spec->unsol_tag_hp = spec->out_pins[1];
8602 spec->unsol_tag_front_hp = spec->out_pins[2];
8603
8604 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
8605 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
8606 spec->adcs[2] = 0xa; /* what u hear */
63177afc 8607
d06feaf0
CM		 8608 spec->num_inputs = 2;
8609 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8610 spec->input_pins[1] = 0x13; /* What U Hear */
8611 spec->shared_mic_nid = 0x7;
8612 spec->unsol_tag_amic1 = spec->input_pins[0];
8613
8614 /* SPDIF I/O */
8615 spec->dig_out = 0x05;
8616 spec->multiout.dig_out_nid = spec->dig_out;
8617 break;
8618 case QUIRK_R3DI:
63177afc
CM		 8619 spec->num_outputs = 2;
8620 spec->out_pins[0] = 0x0B; /* Line out */
8621 spec->out_pins[1] = 0x0F; /* Rear headphone out */
8622 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
8623 spec->out_pins[3] = 0x11; /* Rear surround */
8624 spec->shared_out_nid = 0x2;
8625 spec->unsol_tag_hp = spec->out_pins[1];
8626 spec->unsol_tag_front_hp = spec->out_pins[2];
8627
8628 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
8629 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
8630 spec->adcs[2] = 0x0a; /* what u hear */
8631
8632 spec->num_inputs = 2;
8633 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8634 spec->input_pins[1] = 0x13; /* What U Hear */
8635 spec->shared_mic_nid = 0x7;
8636 spec->unsol_tag_amic1 = spec->input_pins[0];
8637
8638 /* SPDIF I/O */
8639 spec->dig_out = 0x05;
8640 spec->multiout.dig_out_nid = spec->dig_out;
63177afc
CM		 8641 break;
8642 default:
fe14f39e
TI		 8643 spec->num_outputs = 2;
8644 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 8645 spec->out_pins[1] = 0x10; /* headphone out */
fe14f39e
TI		 8646 spec->shared_out_nid = 0x2;
8647 spec->unsol_tag_hp = spec->out_pins[1];
8648
8649 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
8650 spec->adcs[1] = 0x8; /* analog mic2 */
8651 spec->adcs[2] = 0xa; /* what u hear */
8652
8653 spec->num_inputs = 3;
8654 spec->input_pins[0] = 0x12;
8655 spec->input_pins[1] = 0x11;
8656 spec->input_pins[2] = 0x13;
8657 spec->shared_mic_nid = 0x7;
8658 spec->unsol_tag_amic1 = spec->input_pins[0];
8659
8660 /* SPDIF I/O */
8661 spec->dig_out = 0x05;
8662 spec->multiout.dig_out_nid = spec->dig_out;
fe14f39e 8663 spec->dig_in = 0x09;
63177afc 8664 break;
d5c016b5 8665 }
441aa6a0
IM		 8666}
8667
d5c016b5
GM		 8668static int ca0132_prepare_verbs(struct hda_codec *codec)
8669{
8670/* Verbs + terminator (an empty element) */
a3d90d67 8671#define NUM_SPEC_VERBS 2
d5c016b5
GM		 8672 struct ca0132_spec *spec = codec->spec;
8673
8674 spec->chip_init_verbs = ca0132_init_verbs0;
88268ce8
CM		 8675 /*
8676 * Since desktop cards use pci_mmio, this can be used to determine
8677 * whether or not to use these verbs instead of a separate bool.
8678 */
6da8f446 8679 if (ca0132_use_pci_mmio(spec))
e42c7c73 8680 spec->desktop_init_verbs = ca0132_init_verbs1;
6396bb22
KC		 8681 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
8682 sizeof(struct hda_verb),
8683 GFP_KERNEL);
d5c016b5
GM		 8684 if (!spec->spec_init_verbs)
8685 return -ENOMEM;
8686
d5c016b5 8687 /* config EAPD */
a3d90d67
AB		 8688 spec->spec_init_verbs[0].nid = 0x0b;
8689 spec->spec_init_verbs[0].param = 0x78D;
8690 spec->spec_init_verbs[0].verb = 0x00;
d5c016b5
GM		 8691
8692 /* Previously commented configuration */
8693 /*
a3d90d67
AB		 8694 spec->spec_init_verbs[2].nid = 0x0b;
8695 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
8696 spec->spec_init_verbs[2].verb = 0x02;
8697
8698 spec->spec_init_verbs[3].nid = 0x10;
8699 spec->spec_init_verbs[3].param = 0x78D;
d5c016b5
GM		 8700 spec->spec_init_verbs[3].verb = 0x02;
8701
8702 spec->spec_init_verbs[4].nid = 0x10;
a3d90d67 8703 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
d5c016b5 8704 spec->spec_init_verbs[4].verb = 0x02;
d5c016b5
GM		 8705 */
8706
8707 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
8708 return 0;
8709}
8710
b29733db
CM		 8711/*
8712 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular
8713 * Sound Blaster Z cards. However, they have different HDA codec subsystem
8714 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro
8715 * daughter boards ID.
8716 */
8717static void sbz_detect_quirk(struct hda_codec *codec)
8718{
8719 struct ca0132_spec *spec = codec->spec;
8720
8721 switch (codec->core.subsystem_id) {
8722 case 0x11020033:
8723 spec->quirk = QUIRK_ZXR;
8724 break;
8725 case 0x1102003f:
8726 spec->quirk = QUIRK_ZXR_DBPRO;
8727 break;
8728 default:
8729 spec->quirk = QUIRK_SBZ;
8730 break;
8731 }
8732}
8733
95c6e9cb
IM		 8734static int patch_ca0132(struct hda_codec *codec)
8735{
8736 struct ca0132_spec *spec;
a73d511c 8737 int err;
d5c016b5 8738 const struct snd_pci_quirk *quirk;
95c6e9cb 8739
4e76a883 8740 codec_dbg(codec, "patch_ca0132\n");
95c6e9cb
IM		 8741
8742 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
8743 if (!spec)
8744 return -ENOMEM;
8745 codec->spec = spec;
993884f6 8746 spec->codec = codec;
95c6e9cb 8747
d5c016b5
GM		 8748 /* Detect codec quirk */
8749 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
8750 if (quirk)
8751 spec->quirk = quirk->value;
8752 else
8753 spec->quirk = QUIRK_NONE;
6da8f446 8754 if (ca0132_quirk(spec) == QUIRK_SBZ)
b29733db
CM		 8755 sbz_detect_quirk(codec);
8756
6da8f446 8757 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO)
ebabde1e
CM		 8758 codec->patch_ops = dbpro_patch_ops;
8759 else
8760 codec->patch_ops = ca0132_patch_ops;
8761
8762 codec->pcm_format_first = 1;
8763 codec->no_sticky_stream = 1;
8764
8765
e24aa0a4 8766 spec->dsp_state = DSP_DOWNLOAD_INIT;
a7e76271 8767 spec->num_mixers = 1;
017310fb
CM		 8768
8769 /* Set which mixers each quirk uses. */
6da8f446 8770 switch (ca0132_quirk(spec)) {
017310fb 8771 case QUIRK_SBZ:
e25e3445 8772 spec->mixers[0] = desktop_mixer;
017310fb
CM		 8773 snd_hda_codec_set_name(codec, "Sound Blaster Z");
8774 break;
2e492b8e
CM		 8775 case QUIRK_ZXR:
8776 spec->mixers[0] = desktop_mixer;
8777 snd_hda_codec_set_name(codec, "Sound Blaster ZxR");
8778 break;
7675a2a9 8779 case QUIRK_ZXR_DBPRO:
7675a2a9 8780 break;
e25e3445
CM		 8781 case QUIRK_R3D:
8782 spec->mixers[0] = desktop_mixer;
8783 snd_hda_codec_set_name(codec, "Recon3D");
8784 break;
017310fb
CM		 8785 case QUIRK_R3DI:
8786 spec->mixers[0] = r3di_mixer;
8787 snd_hda_codec_set_name(codec, "Recon3Di");
8788 break;
88268ce8
CM		 8789 case QUIRK_AE5:
8790 spec->mixers[0] = desktop_mixer;
8791 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5");
8792 break;
017310fb
CM		 8793 default:
8794 spec->mixers[0] = ca0132_mixer;
8795 break;
8796 }
a7e76271 8797
08eca6b1 8798 /* Setup whether or not to use alt functions/controls/pci_mmio */
6da8f446 8799 switch (ca0132_quirk(spec)) {
009b8f97 8800 case QUIRK_SBZ:
e42c7c73 8801 case QUIRK_R3D:
88268ce8 8802 case QUIRK_AE5:
2e492b8e 8803 case QUIRK_ZXR:
08eca6b1
CM		 8804 spec->use_alt_controls = true;
8805 spec->use_alt_functions = true;
8806 spec->use_pci_mmio = true;
8807 break;
009b8f97 8808 case QUIRK_R3DI:
47cdf76e 8809 spec->use_alt_controls = true;
009b8f97 8810 spec->use_alt_functions = true;
08eca6b1 8811 spec->use_pci_mmio = false;
009b8f97
CM		 8812 break;
8813 default:
47cdf76e 8814 spec->use_alt_controls = false;
009b8f97 8815 spec->use_alt_functions = false;
08eca6b1 8816 spec->use_pci_mmio = false;
009b8f97
CM		 8817 break;
8818 }
8819
6da8f446 8820#ifdef CONFIG_PCI
08eca6b1
CM		 8821 if (spec->use_pci_mmio) {
8822 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
8823 if (spec->mem_base == NULL) {
8824 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
8825 spec->quirk = QUIRK_NONE;
8826 }
8827 }
6da8f446 8828#endif
08eca6b1 8829
5aaca44d
IM		 8830 spec->base_init_verbs = ca0132_base_init_verbs;
8831 spec->base_exit_verbs = ca0132_base_exit_verbs;
5aaca44d 8832
993884f6
CCC		 8833 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
8834
95c6e9cb
IM		 8835 ca0132_init_chip(codec);
8836
8837 ca0132_config(codec);
8838
d5c016b5
GM		 8839 err = ca0132_prepare_verbs(codec);
8840 if (err < 0)
cc91ceaf 8841 goto error;
d5c016b5 8842
a73d511c
IM		 8843 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
8844 if (err < 0)
cc91ceaf 8845 goto error;
a73d511c 8846
95c6e9cb 8847 return 0;
cc91ceaf
TI		 8848
8849 error:
8850 ca0132_free(codec);
8851 return err;
95c6e9cb
IM		 8852}
8853
8854/*
8855 * patch entries
8856 */
b9a94a9c
TI		 8857static struct hda_device_id snd_hda_id_ca0132[] = {
8858 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
95c6e9cb
IM		 8859 {} /* terminator */
8860};
b9a94a9c 8861MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
95c6e9cb
IM		 8862
8863MODULE_LICENSE("GPL");
406261ce 8864MODULE_DESCRIPTION("Creative Sound Core3D codec");
95c6e9cb 8865
d8a766a1 8866static struct hda_codec_driver ca0132_driver = {
b9a94a9c 8867 .id = snd_hda_id_ca0132,
95c6e9cb
IM		 8868};
8869
d8a766a1 8870module_hda_codec_driver(ca0132_driver);
Linux 6.x block layer and io_uring tree(s)