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Merge tag 'scsi-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
[linux-2.6-block.git] / sound / pci / hda / hda_intel.c
CommitLineData
1a59d1b8 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4
LT		 2/*
3 *
d01ce99f
TI		 4 * hda_intel.c - Implementation of primary alsa driver code base
5 * for Intel HD Audio.
1da177e4
LT		 6 *
7 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 *
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 *
1da177e4
LT		 12 * CONTACTS:
13 *
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
17 *
18 * CHANGES:
19 *
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
1da177e4
LT		 21 */
22
1da177e4
LT		 23#include <linux/delay.h>
24#include <linux/interrupt.h>
362775e2 25#include <linux/kernel.h>
1da177e4 26#include <linux/module.h>
24982c5f 27#include <linux/dma-mapping.h>
1da177e4
LT		 28#include <linux/moduleparam.h>
29#include <linux/init.h>
30#include <linux/slab.h>
31#include <linux/pci.h>
62932df8 32#include <linux/mutex.h>
27fe48d9 33#include <linux/io.h>
b8dfc462 34#include <linux/pm_runtime.h>
5d890f59
PLB		 35#include <linux/clocksource.h>
36#include <linux/time.h>
f4c482a4 37#include <linux/completion.h>
5d890f59 38
27fe48d9
TI		 39#ifdef CONFIG_X86
40/* for snoop control */
41#include <asm/pgtable.h>
7f80f513 42#include <asm/set_memory.h>
50279d9b 43#include <asm/cpufeature.h>
27fe48d9 44#endif
1da177e4
LT		 45#include <sound/core.h>
46#include <sound/initval.h>
98d8fc6c
ML		 47#include <sound/hdaudio.h>
48#include <sound/hda_i915.h>
8c575883 49#include <sound/intel-nhlt.h>
9121947d 50#include <linux/vgaarb.h>
a82d51ed 51#include <linux/vga_switcheroo.h>
4918cdab 52#include <linux/firmware.h>
be57bfff 53#include <sound/hda_codec.h>
05e84878 54#include "hda_controller.h"
347de1f8 55#include "hda_intel.h"
1da177e4 56
785d8c4b
LY		 57#define CREATE_TRACE_POINTS
58#include "hda_intel_trace.h"
59
b6050ef6
TI		 60/* position fix mode */
61enum {
62 POS_FIX_AUTO,
63 POS_FIX_LPIB,
64 POS_FIX_POSBUF,
65 POS_FIX_VIACOMBO,
66 POS_FIX_COMBO,
f87e7f25 67 POS_FIX_SKL,
c02f77d3 68 POS_FIX_FIFO,
b6050ef6
TI		 69};
70
9a34af4a
TI		 71/* Defines for ATI HD Audio support in SB450 south bridge */
72#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
73#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
74
75/* Defines for Nvidia HDA support */
76#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
77#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
78#define NVIDIA_HDA_ISTRM_COH 0x4d
79#define NVIDIA_HDA_OSTRM_COH 0x4c
80#define NVIDIA_HDA_ENABLE_COHBIT 0x01
81
82/* Defines for Intel SCH HDA snoop control */
6639484d
LY		 83#define INTEL_HDA_CGCTL 0x48
84#define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
9a34af4a
TI		 85#define INTEL_SCH_HDA_DEVC 0x78
86#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
87
9a34af4a
TI		 88/* Define VIA HD Audio Device ID*/
89#define VIA_HDAC_DEVICE_ID 0x3288
90
33124929
TI		 91/* max number of SDs */
92/* ICH, ATI and VIA have 4 playback and 4 capture */
93#define ICH6_NUM_CAPTURE 4
94#define ICH6_NUM_PLAYBACK 4
95
96/* ULI has 6 playback and 5 capture */
97#define ULI_NUM_CAPTURE 5
98#define ULI_NUM_PLAYBACK 6
99
100/* ATI HDMI may have up to 8 playbacks and 0 capture */
101#define ATIHDMI_NUM_CAPTURE 0
102#define ATIHDMI_NUM_PLAYBACK 8
103
104/* TERA has 4 playback and 3 capture */
105#define TERA_NUM_CAPTURE 3
106#define TERA_NUM_PLAYBACK 4
107
1da177e4 108
5aba4f8e
TI		 109static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
110static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 111static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 112static char *model[SNDRV_CARDS];
1dac6695 113static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 114static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 115static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 116static int probe_only[SNDRV_CARDS];
26a6cb6c 117static int jackpoll_ms[SNDRV_CARDS];
41438f13 118static int single_cmd = -1;
71623855 119static int enable_msi = -1;
4ea6fbc8
TI		 120#ifdef CONFIG_SND_HDA_PATCH_LOADER
121static char *patch[SNDRV_CARDS];
122#endif
2dca0bba 123#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 124static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 125 CONFIG_SND_HDA_INPUT_BEEP_MODE};
126#endif
8c575883 127static bool dmic_detect = IS_ENABLED(CONFIG_SND_HDA_INTEL_DETECT_DMIC);
1da177e4 128
5aba4f8e 129module_param_array(index, int, NULL, 0444);
1da177e4 130MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 131module_param_array(id, charp, NULL, 0444);
1da177e4 132MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 133module_param_array(enable, bool, NULL, 0444);
134MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
135module_param_array(model, charp, NULL, 0444);
1da177e4 136MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 137module_param_array(position_fix, int, NULL, 0444);
4cb36310 138MODULE_PARM_DESC(position_fix, "DMA pointer read method."
c02f77d3 139 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
555e219f
TI		 140module_param_array(bdl_pos_adj, int, NULL, 0644);
141MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 142module_param_array(probe_mask, int, NULL, 0444);
606ad75f 143MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 144module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 145MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 146module_param_array(jackpoll_ms, int, NULL, 0444);
147MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
41438f13 148module_param(single_cmd, bint, 0444);
d01ce99f
TI		 149MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
150 "(for debugging only).");
ac9ef6cf 151module_param(enable_msi, bint, 0444);
134a11f0 152MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 153#ifdef CONFIG_SND_HDA_PATCH_LOADER
154module_param_array(patch, charp, NULL, 0444);
155MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
156#endif
2dca0bba 157#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 158module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 159MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 160 "(0=off, 1=on) (default=1).");
2dca0bba 161#endif
8c575883
PLB		 162module_param(dmic_detect, bool, 0444);
163MODULE_PARM_DESC(dmic_detect, "DMIC detect on SKL+ platforms");
606ad75f 164
83012a7c 165#ifdef CONFIG_PM
65fcd41d 166static int param_set_xint(const char *val, const struct kernel_param *kp);
9c27847d 167static const struct kernel_param_ops param_ops_xint = {
65fcd41d
TI		 168 .set = param_set_xint,
169 .get = param_get_int,
170};
171#define param_check_xint param_check_int
172
fee2fba3 173static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 174module_param(power_save, xint, 0644);
fee2fba3
TI		 175MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
176 "(in second, 0 = disable).");
1da177e4 177
40088dc4
TI		 178static bool pm_blacklist = true;
179module_param(pm_blacklist, bool, 0644);
180MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
181
dee1b66c
TI		 182/* reset the HD-audio controller in power save mode.
183 * this may give more power-saving, but will take longer time to
184 * wake up.
185 */
8fc24426
TI		 186static bool power_save_controller = 1;
187module_param(power_save_controller, bool, 0644);
dee1b66c 188MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 189#else
bb573928 190#define power_save 0
83012a7c 191#endif /* CONFIG_PM */
dee1b66c 192
7bfe059e
TI		 193static int align_buffer_size = -1;
194module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 195MODULE_PARM_DESC(align_buffer_size,
196 "Force buffer and period sizes to be multiple of 128 bytes.");
197
27fe48d9 198#ifdef CONFIG_X86
7c732015
TI		 199static int hda_snoop = -1;
200module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 201MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 202#else
203#define hda_snoop true
27fe48d9
TI		 204#endif
205
206
1da177e4
LT		 207MODULE_LICENSE("GPL");
208MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
209 "{Intel, ICH6M},"
2f1b3818 210 "{Intel, ICH7},"
f5d40b30 211 "{Intel, ESB2},"
d2981393 212 "{Intel, ICH8},"
f9cc8a8b 213 "{Intel, ICH9},"
c34f5a04 214 "{Intel, ICH10},"
b29c2360 215 "{Intel, PCH},"
d2f2fcd2 216 "{Intel, CPT},"
d2edeb7c 217 "{Intel, PPT},"
8bc039a1 218 "{Intel, LPT},"
144dad99 219 "{Intel, LPT_LP},"
4eeca499 220 "{Intel, WPT_LP},"
c8b00fd2 221 "{Intel, SPT},"
b4565913 222 "{Intel, SPT_LP},"
e926f2c8 223 "{Intel, HPT},"
cea310e8 224 "{Intel, PBG},"
4979bca9 225 "{Intel, SCH},"
fc20a562 226 "{ATI, SB450},"
89be83f8 227 "{ATI, SB600},"
778b6e1b 228 "{ATI, RS600},"
5b15c95f 229 "{ATI, RS690},"
e6db1119
WL		 230 "{ATI, RS780},"
231 "{ATI, R600},"
2797f724
HRK		 232 "{ATI, RV630},"
233 "{ATI, RV610},"
27da1834
WL		 234 "{ATI, RV670},"
235 "{ATI, RV635},"
236 "{ATI, RV620},"
237 "{ATI, RV770},"
fc20a562 238 "{VIA, VT8251},"
47672310 239 "{VIA, VT8237A},"
07e4ca50
TI		 240 "{SiS, SIS966},"
241 "{ULI, M5461}}");
1da177e4
LT		 242MODULE_DESCRIPTION("Intel HDA driver");
243
a82d51ed 244#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 245#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 246#define SUPPORT_VGA_SWITCHEROO
247#endif
248#endif
249
250
1da177e4 251/*
1da177e4 252 */
1da177e4 253
07e4ca50
TI		 254/* driver types */
255enum {
256 AZX_DRIVER_ICH,
32679f95 257 AZX_DRIVER_PCH,
4979bca9 258 AZX_DRIVER_SCH,
a4b4793f 259 AZX_DRIVER_SKL,
fab1285a 260 AZX_DRIVER_HDMI,
07e4ca50 261 AZX_DRIVER_ATI,
778b6e1b 262 AZX_DRIVER_ATIHDMI,
1815b34a 263 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 264 AZX_DRIVER_VIA,
265 AZX_DRIVER_SIS,
266 AZX_DRIVER_ULI,
da3fca21 267 AZX_DRIVER_NVIDIA,
f269002e 268 AZX_DRIVER_TERA,
14d34f16 269 AZX_DRIVER_CTX,
5ae763b1 270 AZX_DRIVER_CTHDA,
c563f473 271 AZX_DRIVER_CMEDIA,
b6fcab14 272 AZX_DRIVER_ZHAOXIN,
c4da29ca 273 AZX_DRIVER_GENERIC,
2f5983f2 274 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 275};
276
37e661ee
TI		 277#define azx_get_snoop_type(chip) \
278 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
279#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
280
b42b4afb
TI		 281/* quirks for old Intel chipsets */
282#define AZX_DCAPS_INTEL_ICH \
103884a3 283 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 284
2ea3c6a2 285/* quirks for Intel PCH */
6603249d 286#define AZX_DCAPS_INTEL_PCH_BASE \
103884a3 287 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
bcb337d1 288 AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db 289
dba9b7b6 290/* PCH up to IVB; no runtime PM; bind with i915 gfx */
6603249d 291#define AZX_DCAPS_INTEL_PCH_NOPM \
dba9b7b6 292 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
6603249d 293
55913110 294/* PCH for HSW/BDW; with runtime PM */
dba9b7b6 295/* no i915 binding for this as HSW/BDW has another controller for HDMI */
d7dab4db 296#define AZX_DCAPS_INTEL_PCH \
6603249d 297 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
9477c58e 298
6603249d 299/* HSW HDMI */
33499a15 300#define AZX_DCAPS_INTEL_HASWELL \
103884a3 301 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
dba9b7b6 302 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
e454ff8e 303 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 304
54a0405d
LY		 305/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
306#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 307 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
dba9b7b6 308 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
e454ff8e 309 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 310
40cc2392 311#define AZX_DCAPS_INTEL_BAYTRAIL \
e454ff8e 312 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
40cc2392 313
2d846c74 314#define AZX_DCAPS_INTEL_BRASWELL \
dba9b7b6 315 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
e454ff8e 316 AZX_DCAPS_I915_COMPONENT)
2d846c74 317
d6795827 318#define AZX_DCAPS_INTEL_SKYLAKE \
dba9b7b6 319 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
2756d914 320 AZX_DCAPS_SYNC_WRITE |\
e454ff8e 321 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
d6795827 322
2756d914 323#define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
c87693da 324
9477c58e
TI		 325/* quirks for ATI SB / AMD Hudson */
326#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 327 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
328 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 329
330/* quirks for ATI/AMD HDMI */
331#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 332 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
333 AZX_DCAPS_NO_MSI64)
9477c58e 334
37e661ee
TI		 335/* quirks for ATI HDMI with snoop off */
336#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
337 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
338
c02f77d3
TI		 339/* quirks for AMD SB */
340#define AZX_DCAPS_PRESET_AMD_SB \
341 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\
342 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
343
9477c58e
TI		 344/* quirks for Nvidia */
345#define AZX_DCAPS_PRESET_NVIDIA \
3ab7511e 346 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
37e661ee 347 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 348
5ae763b1 349#define AZX_DCAPS_PRESET_CTHDA \
37e661ee 350 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
cadd16ea 351 AZX_DCAPS_NO_64BIT |\
37e661ee 352 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 353
a82d51ed 354/*
2b760d88 355 * vga_switcheroo support
a82d51ed
TI		 356 */
357#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db 358#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
dd23e1d5 359#define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
5cb543db
TI		 360#else
361#define use_vga_switcheroo(chip) 0
37a3a98e 362#define needs_eld_notify_link(chip) false
5cb543db
TI		 363#endif
364
03b135ce
LY		 365#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
366 ((pci)->device == 0x0c0c) || \
367 ((pci)->device == 0x0d0c) || \
368 ((pci)->device == 0x160c))
369
7e31a015 370#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
a8d7bde2 371#define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
fa763f1b 372#define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)
7c23b7c1 373
48c8b0eb 374static char *driver_short_names[] = {
07e4ca50 375 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 376 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 377 [AZX_DRIVER_SCH] = "HDA Intel MID",
a4b4793f 378 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
fab1285a 379 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 380 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 381 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 382 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 383 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
384 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 385 [AZX_DRIVER_ULI] = "HDA ULI M5461",
386 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 387 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 388 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 389 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 390 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
b6fcab14 391 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
c4da29ca 392 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 393};
394
68e7fffc 395static int azx_acquire_irq(struct azx *chip, int do_disconnect);
37a3a98e 396static void set_default_power_save(struct azx *chip);
111d3af5 397
cb53c626
TI		 398/*
399 * initialize the PCI registers
400 */
401/* update bits in a PCI register byte */
402static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
403 unsigned char mask, unsigned char val)
404{
405 unsigned char data;
406
407 pci_read_config_byte(pci, reg, &data);
408 data &= ~mask;
409 data |= (val & mask);
410 pci_write_config_byte(pci, reg, data);
411}
412
413static void azx_init_pci(struct azx *chip)
414{
37e661ee
TI		 415 int snoop_type = azx_get_snoop_type(chip);
416
cb53c626
TI		 417 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
418 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
419 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 420 * codecs.
421 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 422 */
46f2cc80 423 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 424 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 425 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 426 }
cb53c626 427
9477c58e
TI		 428 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
429 * we need to enable snoop.
430 */
37e661ee 431 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 432 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
433 azx_snoop(chip));
cb53c626 434 update_pci_byte(chip->pci,
27fe48d9
TI		 435 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
436 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 437 }
438
439 /* For NVIDIA HDA, enable snoop */
37e661ee 440 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 441 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
442 azx_snoop(chip));
cb53c626
TI		 443 update_pci_byte(chip->pci,
444 NVIDIA_HDA_TRANSREG_ADDR,
445 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 446 update_pci_byte(chip->pci,
447 NVIDIA_HDA_ISTRM_COH,
448 0x01, NVIDIA_HDA_ENABLE_COHBIT);
449 update_pci_byte(chip->pci,
450 NVIDIA_HDA_OSTRM_COH,
451 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 452 }
453
454 /* Enable SCH/PCH snoop if needed */
37e661ee 455 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 456 unsigned short snoop;
90a5ad52 457 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 458 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
459 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
460 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
461 if (!azx_snoop(chip))
462 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
463 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 464 pci_read_config_word(chip->pci,
465 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 466 }
4e76a883
TI		 467 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
468 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
469 "Disabled" : "Enabled");
da3fca21 470 }
1da177e4
LT		 471}
472
7c23b7c1
LH		 473/*
474 * In BXT-P A0, HD-Audio DMA requests is later than expected,
475 * and makes an audio stream sensitive to system latencies when
476 * 24/32 bits are playing.
477 * Adjusting threshold of DMA fifo to force the DMA request
478 * sooner to improve latency tolerance at the expense of power.
479 */
480static void bxt_reduce_dma_latency(struct azx *chip)
481{
482 u32 val;
483
70eafad8 484 val = azx_readl(chip, VS_EM4L);
7c23b7c1 485 val &= (0x3 << 20);
70eafad8 486 azx_writel(chip, VS_EM4L, val);
7c23b7c1
LH		 487}
488
1f9d3d98
LY		 489/*
490 * ML_LCAP bits:
491 * bit 0: 6 MHz Supported
492 * bit 1: 12 MHz Supported
493 * bit 2: 24 MHz Supported
494 * bit 3: 48 MHz Supported
495 * bit 4: 96 MHz Supported
496 * bit 5: 192 MHz Supported
497 */
498static int intel_get_lctl_scf(struct azx *chip)
499{
500 struct hdac_bus *bus = azx_bus(chip);
501 static int preferred_bits[] = { 2, 3, 1, 4, 5 };
502 u32 val, t;
503 int i;
504
505 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
506
507 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
508 t = preferred_bits[i];
509 if (val & (1 << t))
510 return t;
511 }
512
513 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
514 return 0;
515}
516
517static int intel_ml_lctl_set_power(struct azx *chip, int state)
518{
519 struct hdac_bus *bus = azx_bus(chip);
520 u32 val;
521 int timeout;
522
523 /*
524 * the codecs are sharing the first link setting by default
525 * If other links are enabled for stream, they need similar fix
526 */
527 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
528 val &= ~AZX_MLCTL_SPA;
529 val |= state << AZX_MLCTL_SPA_SHIFT;
530 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
531 /* wait for CPA */
532 timeout = 50;
533 while (timeout) {
534 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
535 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
536 return 0;
537 timeout--;
538 udelay(10);
539 }
540
541 return -1;
542}
543
544static void intel_init_lctl(struct azx *chip)
545{
546 struct hdac_bus *bus = azx_bus(chip);
547 u32 val;
548 int ret;
549
550 /* 0. check lctl register value is correct or not */
551 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
552 /* if SCF is already set, let's use it */
553 if ((val & ML_LCTL_SCF_MASK) != 0)
554 return;
555
556 /*
557 * Before operating on SPA, CPA must match SPA.
558 * Any deviation may result in undefined behavior.
559 */
560 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
561 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
562 return;
563
564 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
565 ret = intel_ml_lctl_set_power(chip, 0);
566 udelay(100);
567 if (ret)
568 goto set_spa;
569
570 /* 2. update SCF to select a properly audio clock*/
571 val &= ~ML_LCTL_SCF_MASK;
572 val |= intel_get_lctl_scf(chip);
573 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
574
575set_spa:
576 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
577 intel_ml_lctl_set_power(chip, 1);
578 udelay(100);
579}
580
0a673521
LH		 581static void hda_intel_init_chip(struct azx *chip, bool full_reset)
582{
98d8fc6c 583 struct hdac_bus *bus = azx_bus(chip);
7c23b7c1 584 struct pci_dev *pci = chip->pci;
6639484d 585 u32 val;
0a673521 586
e454ff8e 587 snd_hdac_set_codec_wakeup(bus, true);
a4b4793f 588 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 589 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
590 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
591 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
592 }
0a673521 593 azx_init_chip(chip, full_reset);
a4b4793f 594 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 595 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
596 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
597 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
598 }
e454ff8e
TI		 599
600 snd_hdac_set_codec_wakeup(bus, false);
7c23b7c1
LH		 601
602 /* reduce dma latency to avoid noise */
7e31a015 603 if (IS_BXT(pci))
7c23b7c1 604 bxt_reduce_dma_latency(chip);
1f9d3d98
LY		 605
606 if (bus->mlcap != NULL)
607 intel_init_lctl(chip);
0a673521
LH		 608}
609
b6050ef6
TI		 610/* calculate runtime delay from LPIB */
611static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
612 unsigned int pos)
613{
7833c3f8 614 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 615 int stream = substream->stream;
616 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
617 int delay;
618
619 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
620 delay = pos - lpib_pos;
621 else
622 delay = lpib_pos - pos;
623 if (delay < 0) {
7833c3f8 624 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 625 delay = 0;
626 else
7833c3f8 627 delay += azx_dev->core.bufsize;
b6050ef6
TI		 628 }
629
7833c3f8 630 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 631 dev_info(chip->card->dev,
632 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 633 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 634 delay = 0;
635 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
636 chip->get_delay[stream] = NULL;
637 }
638
639 return bytes_to_frames(substream->runtime, delay);
640}
641
9ad593f6
TI		 642static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
643
7ca954a8
DR		 644/* called from IRQ */
645static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
646{
9a34af4a 647 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 648 int ok;
649
650 ok = azx_position_ok(chip, azx_dev);
651 if (ok == 1) {
652 azx_dev->irq_pending = 0;
653 return ok;
2f35c630 654 } else if (ok == 0) {
7ca954a8
DR		 655 /* bogus IRQ, process it later */
656 azx_dev->irq_pending = 1;
2f35c630 657 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 658 }
659 return 0;
660}
661
029d92c2
TI		 662#define display_power(chip, enable) \
663 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
17eccb27 664
9ad593f6
TI		 665/*
666 * Check whether the current DMA position is acceptable for updating
667 * periods. Returns non-zero if it's OK.
668 *
669 * Many HD-audio controllers appear pretty inaccurate about
670 * the update-IRQ timing. The IRQ is issued before actually the
671 * data is processed. So, we need to process it afterwords in a
672 * workqueue.
673 */
674static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
675{
7833c3f8 676 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6 677 int stream = substream->stream;
e5463720 678 u32 wallclk;
9ad593f6
TI		 679 unsigned int pos;
680
7833c3f8
TI		 681 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
682 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 683 return -1; /* bogus (too early) interrupt */
fa00e046 684
b6050ef6
TI		 685 if (chip->get_position[stream])
686 pos = chip->get_position[stream](chip, azx_dev);
687 else { /* use the position buffer as default */
688 pos = azx_get_pos_posbuf(chip, azx_dev);
689 if (!pos || pos == (u32)-1) {
690 dev_info(chip->card->dev,
691 "Invalid position buffer, using LPIB read method instead.\n");
692 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 693 if (chip->get_position[0] == azx_get_pos_lpib &&
694 chip->get_position[1] == azx_get_pos_lpib)
695 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 696 pos = azx_get_pos_lpib(chip, azx_dev);
697 chip->get_delay[stream] = NULL;
698 } else {
699 chip->get_position[stream] = azx_get_pos_posbuf;
700 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
701 chip->get_delay[stream] = azx_get_delay_from_lpib;
702 }
703 }
704
7833c3f8 705 if (pos >= azx_dev->core.bufsize)
b6050ef6 706 pos = 0;
9ad593f6 707
7833c3f8 708 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 709 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 710 return -1; /* this shouldn't happen! */
7833c3f8
TI		 711 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
712 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 713 /* NG - it's below the first next period boundary */
4f0189be 714 return chip->bdl_pos_adj ? 0 : -1;
7833c3f8 715 azx_dev->core.start_wallclk += wallclk;
9ad593f6
TI		 716 return 1; /* OK, it's fine */
717}
718
719/*
720 * The work for pending PCM period updates.
721 */
722static void azx_irq_pending_work(struct work_struct *work)
723{
9a34af4a
TI		 724 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
725 struct azx *chip = &hda->chip;
7833c3f8
TI		 726 struct hdac_bus *bus = azx_bus(chip);
727 struct hdac_stream *s;
728 int pending, ok;
9ad593f6 729
9a34af4a 730 if (!hda->irq_pending_warned) {
4e76a883
TI		 731 dev_info(chip->card->dev,
732 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
733 chip->card->number);
9a34af4a 734 hda->irq_pending_warned = 1;
a6a950a8
TI		 735 }
736
9ad593f6
TI		 737 for (;;) {
738 pending = 0;
a41d1224 739 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 740 list_for_each_entry(s, &bus->stream_list, list) {
741 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 742 if (!azx_dev->irq_pending ||
7833c3f8
TI		 743 !s->substream ||
744 !s->running)
9ad593f6 745 continue;
e5463720
JK		 746 ok = azx_position_ok(chip, azx_dev);
747 if (ok > 0) {
9ad593f6 748 azx_dev->irq_pending = 0;
a41d1224 749 spin_unlock(&bus->reg_lock);
7833c3f8 750 snd_pcm_period_elapsed(s->substream);
a41d1224 751 spin_lock(&bus->reg_lock);
e5463720
JK		 752 } else if (ok < 0) {
753 pending = 0; /* too early */
9ad593f6
TI		 754 } else
755 pending++;
756 }
a41d1224 757 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 758 if (!pending)
759 return;
08af495f 760 msleep(1);
9ad593f6
TI		 761 }
762}
763
764/* clear irq_pending flags and assure no on-going workq */
765static void azx_clear_irq_pending(struct azx *chip)
766{
7833c3f8
TI		 767 struct hdac_bus *bus = azx_bus(chip);
768 struct hdac_stream *s;
9ad593f6 769
a41d1224 770 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 771 list_for_each_entry(s, &bus->stream_list, list) {
772 struct azx_dev *azx_dev = stream_to_azx_dev(s);
773 azx_dev->irq_pending = 0;
774 }
a41d1224 775 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 776}
777
68e7fffc
TI		 778static int azx_acquire_irq(struct azx *chip, int do_disconnect)
779{
a41d1224
TI		 780 struct hdac_bus *bus = azx_bus(chip);
781
437a5a46
TI		 782 if (request_irq(chip->pci->irq, azx_interrupt,
783 chip->msi ? 0 : IRQF_SHARED,
de65360b 784 chip->card->irq_descr, chip)) {
4e76a883
TI		 785 dev_err(chip->card->dev,
786 "unable to grab IRQ %d, disabling device\n",
787 chip->pci->irq);
68e7fffc
TI		 788 if (do_disconnect)
789 snd_card_disconnect(chip->card);
790 return -1;
791 }
a41d1224 792 bus->irq = chip->pci->irq;
69e13418 793 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 794 return 0;
795}
796
b6050ef6
TI		 797/* get the current DMA position with correction on VIA chips */
798static unsigned int azx_via_get_position(struct azx *chip,
799 struct azx_dev *azx_dev)
800{
801 unsigned int link_pos, mini_pos, bound_pos;
802 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
803 unsigned int fifo_size;
804
1604eeee 805 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 806 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 807 /* Playback, no problem using link position */
808 return link_pos;
809 }
810
811 /* Capture */
812 /* For new chipset,
813 * use mod to get the DMA position just like old chipset
814 */
7833c3f8
TI		 815 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
816 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6 817
7da20788 818 fifo_size = azx_stream(azx_dev)->fifo_size - 1;
b6050ef6
TI		 819
820 if (azx_dev->insufficient) {
821 /* Link position never gather than FIFO size */
822 if (link_pos <= fifo_size)
823 return 0;
824
825 azx_dev->insufficient = 0;
826 }
827
828 if (link_pos <= fifo_size)
7833c3f8 829 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 830 else
831 mini_pos = link_pos - fifo_size;
832
833 /* Find nearest previous boudary */
7833c3f8
TI		 834 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
835 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 836 if (mod_link_pos >= fifo_size)
837 bound_pos = link_pos - mod_link_pos;
838 else if (mod_dma_pos >= mod_mini_pos)
839 bound_pos = mini_pos - mod_mini_pos;
840 else {
7833c3f8
TI		 841 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
842 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 843 bound_pos = 0;
844 }
845
846 /* Calculate real DMA position we want */
847 return bound_pos + mod_dma_pos;
848}
849
c02f77d3
TI		 850#define AMD_FIFO_SIZE 32
851
852/* get the current DMA position with FIFO size correction */
853static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
854{
855 struct snd_pcm_substream *substream = azx_dev->core.substream;
856 struct snd_pcm_runtime *runtime = substream->runtime;
857 unsigned int pos, delay;
858
859 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
860 if (!runtime)
861 return pos;
862
863 runtime->delay = AMD_FIFO_SIZE;
864 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
865 if (azx_dev->insufficient) {
866 if (pos < delay) {
867 delay = pos;
868 runtime->delay = bytes_to_frames(runtime, pos);
869 } else {
870 azx_dev->insufficient = 0;
871 }
872 }
873
874 /* correct the DMA position for capture stream */
875 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
876 if (pos < delay)
877 pos += azx_dev->core.bufsize;
878 pos -= delay;
879 }
880
881 return pos;
882}
883
884static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
885 unsigned int pos)
886{
887 struct snd_pcm_substream *substream = azx_dev->core.substream;
888
889 /* just read back the calculated value in the above */
890 return substream->runtime->delay;
891}
892
f87e7f25
TI		 893static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
894 struct azx_dev *azx_dev)
895{
896 return _snd_hdac_chip_readl(azx_bus(chip),
897 AZX_REG_VS_SDXDPIB_XBASE +
898 (AZX_REG_VS_SDXDPIB_XINTERVAL *
899 azx_dev->core.index));
900}
901
902/* get the current DMA position with correction on SKL+ chips */
903static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
904{
905 /* DPIB register gives a more accurate position for playback */
906 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
907 return azx_skl_get_dpib_pos(chip, azx_dev);
908
909 /* For capture, we need to read posbuf, but it requires a delay
910 * for the possible boundary overlap; the read of DPIB fetches the
911 * actual posbuf
912 */
913 udelay(20);
914 azx_skl_get_dpib_pos(chip, azx_dev);
915 return azx_get_pos_posbuf(chip, azx_dev);
916}
917
83012a7c 918#ifdef CONFIG_PM
65fcd41d
TI		 919static DEFINE_MUTEX(card_list_lock);
920static LIST_HEAD(card_list);
921
922static void azx_add_card_list(struct azx *chip)
923{
9a34af4a 924 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 925 mutex_lock(&card_list_lock);
9a34af4a 926 list_add(&hda->list, &card_list);
65fcd41d
TI		 927 mutex_unlock(&card_list_lock);
928}
929
930static void azx_del_card_list(struct azx *chip)
931{
9a34af4a 932 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 933 mutex_lock(&card_list_lock);
9a34af4a 934 list_del_init(&hda->list);
65fcd41d
TI		 935 mutex_unlock(&card_list_lock);
936}
937
938/* trigger power-save check at writing parameter */
939static int param_set_xint(const char *val, const struct kernel_param *kp)
940{
9a34af4a 941 struct hda_intel *hda;
65fcd41d 942 struct azx *chip;
65fcd41d
TI		 943 int prev = power_save;
944 int ret = param_set_int(val, kp);
945
946 if (ret || prev == power_save)
947 return ret;
948
949 mutex_lock(&card_list_lock);
9a34af4a
TI		 950 list_for_each_entry(hda, &card_list, list) {
951 chip = &hda->chip;
a41d1224 952 if (!hda->probe_continued || chip->disabled)
65fcd41d 953 continue;
a41d1224 954 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 955 }
956 mutex_unlock(&card_list_lock);
957 return 0;
958}
5c0b9bec 959
5c0b9bec
TI		 960/*
961 * power management
962 */
3baffc4a 963static bool azx_is_pm_ready(struct snd_card *card)
1da177e4 964{
2d9772ef
TI		 965 struct azx *chip;
966 struct hda_intel *hda;
1da177e4 967
2d9772ef 968 if (!card)
3baffc4a 969 return false;
2d9772ef
TI		 970 chip = card->private_data;
971 hda = container_of(chip, struct hda_intel, chip);
342e8449 972 if (chip->disabled || hda->init_failed || !chip->running)
3baffc4a
TI		 973 return false;
974 return true;
975}
976
977static void __azx_runtime_suspend(struct azx *chip)
978{
3baffc4a
TI		 979 azx_stop_chip(chip);
980 azx_enter_link_reset(chip);
981 azx_clear_irq_pending(chip);
e454ff8e 982 display_power(chip, false);
3baffc4a
TI		 983}
984
744c67ff 985static void __azx_runtime_resume(struct azx *chip, bool from_rt)
3baffc4a
TI		 986{
987 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
988 struct hdac_bus *bus = azx_bus(chip);
989 struct hda_codec *codec;
990 int status;
991
e454ff8e
TI		 992 display_power(chip, true);
993 if (hda->need_i915_power)
994 snd_hdac_i915_set_bclk(bus);
3baffc4a
TI		 995
996 /* Read STATESTS before controller reset */
997 status = azx_readw(chip, STATESTS);
998
999 azx_init_pci(chip);
1000 hda_intel_init_chip(chip, true);
1001
744c67ff 1002 if (status && from_rt) {
3baffc4a
TI		 1003 list_for_each_codec(codec, &chip->bus)
1004 if (status & (1 << codec->addr))
1005 schedule_delayed_work(&codec->jackpoll_work,
1006 codec->jackpoll_interval);
1007 }
1008
1009 /* power down again for link-controlled chips */
e454ff8e 1010 if (!hda->need_i915_power)
029d92c2 1011 display_power(chip, false);
3baffc4a
TI		 1012}
1013
1014#ifdef CONFIG_PM_SLEEP
1015static int azx_suspend(struct device *dev)
1016{
1017 struct snd_card *card = dev_get_drvdata(dev);
1018 struct azx *chip;
1019 struct hdac_bus *bus;
1020
1021 if (!azx_is_pm_ready(card))
c5c21523
TI		 1022 return 0;
1023
3baffc4a 1024 chip = card->private_data;
a41d1224 1025 bus = azx_bus(chip);
421a1252 1026 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3baffc4a 1027 __azx_runtime_suspend(chip);
a41d1224
TI		 1028 if (bus->irq >= 0) {
1029 free_irq(bus->irq, chip);
1030 bus->irq = -1;
30b35399 1031 }
a07187c9 1032
68e7fffc 1033 if (chip->msi)
43001c95 1034 pci_disable_msi(chip->pci);
785d8c4b
LY		 1035
1036 trace_azx_suspend(chip);
1da177e4
LT		 1037 return 0;
1038}
1039
68cb2b55 1040static int azx_resume(struct device *dev)
1da177e4 1041{
68cb2b55 1042 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1043 struct azx *chip;
2d9772ef 1044
3baffc4a 1045 if (!azx_is_pm_ready(card))
2d9772ef 1046 return 0;
1da177e4 1047
2d9772ef 1048 chip = card->private_data;
68e7fffc 1049 if (chip->msi)
3baffc4a 1050 if (pci_enable_msi(chip->pci) < 0)
68e7fffc
TI		 1051 chip->msi = 0;
1052 if (azx_acquire_irq(chip, 1) < 0)
30b35399 1053 return -EIO;
744c67ff 1054 __azx_runtime_resume(chip, false);
421a1252 1055 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
785d8c4b
LY		 1056
1057 trace_azx_resume(chip);
1da177e4
LT		 1058 return 0;
1059}
b8dfc462 1060
3e6db33a
XZ		 1061/* put codec down to D3 at hibernation for Intel SKL+;
1062 * otherwise BIOS may still access the codec and screw up the driver
1063 */
3e6db33a
XZ		 1064static int azx_freeze_noirq(struct device *dev)
1065{
a4b4793f
TI		 1066 struct snd_card *card = dev_get_drvdata(dev);
1067 struct azx *chip = card->private_data;
3e6db33a
XZ		 1068 struct pci_dev *pci = to_pci_dev(dev);
1069
a4b4793f 1070 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1071 pci_set_power_state(pci, PCI_D3hot);
1072
1073 return 0;
1074}
1075
1076static int azx_thaw_noirq(struct device *dev)
1077{
a4b4793f
TI		 1078 struct snd_card *card = dev_get_drvdata(dev);
1079 struct azx *chip = card->private_data;
3e6db33a
XZ		 1080 struct pci_dev *pci = to_pci_dev(dev);
1081
a4b4793f 1082 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1083 pci_set_power_state(pci, PCI_D0);
1084
1085 return 0;
1086}
1087#endif /* CONFIG_PM_SLEEP */
1088
b8dfc462
ML		 1089static int azx_runtime_suspend(struct device *dev)
1090{
1091 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1092 struct azx *chip;
b8dfc462 1093
3baffc4a 1094 if (!azx_is_pm_ready(card))
2d9772ef 1095 return 0;
2d9772ef 1096 chip = card->private_data;
364aa716 1097 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 1098 return 0;
1099
7d4f606c
WX		 1100 /* enable controller wake up event */
1101 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1102 STATESTS_INT_MASK);
1103
3baffc4a 1104 __azx_runtime_suspend(chip);
785d8c4b 1105 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 1106 return 0;
1107}
1108
1109static int azx_runtime_resume(struct device *dev)
1110{
1111 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef 1112 struct azx *chip;
b8dfc462 1113
3baffc4a 1114 if (!azx_is_pm_ready(card))
2d9772ef 1115 return 0;
2d9772ef 1116 chip = card->private_data;
364aa716 1117 if (!azx_has_pm_runtime(chip))
246efa4a 1118 return 0;
744c67ff 1119 __azx_runtime_resume(chip, true);
7d4f606c
WX		 1120
1121 /* disable controller Wake Up event*/
1122 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1123 ~STATESTS_INT_MASK);
1124
785d8c4b 1125 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1126 return 0;
1127}
6eb827d2
TI		 1128
1129static int azx_runtime_idle(struct device *dev)
1130{
1131 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1132 struct azx *chip;
1133 struct hda_intel *hda;
1134
1135 if (!card)
1136 return 0;
6eb827d2 1137
2d9772ef
TI		 1138 chip = card->private_data;
1139 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1140 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1141 return 0;
1142
55ed9cd1 1143 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
342e8449 1144 azx_bus(chip)->codec_powered || !chip->running)
6eb827d2
TI		 1145 return -EBUSY;
1146
37a3a98e 1147 /* ELD notification gets broken when HD-audio bus is off */
dd23e1d5 1148 if (needs_eld_notify_link(chip))
37a3a98e
TI		 1149 return -EBUSY;
1150
6eb827d2
TI		 1151 return 0;
1152}
1153
b8dfc462
ML		 1154static const struct dev_pm_ops azx_pm = {
1155 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3e6db33a
XZ		 1156#ifdef CONFIG_PM_SLEEP
1157 .freeze_noirq = azx_freeze_noirq,
1158 .thaw_noirq = azx_thaw_noirq,
1159#endif
6eb827d2 1160 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1161};
1162
68cb2b55
TI		 1163#define AZX_PM_OPS &azx_pm
1164#else
3baffc4a
TI		 1165#define azx_add_card_list(chip) /* NOP */
1166#define azx_del_card_list(chip) /* NOP */
68cb2b55 1167#define AZX_PM_OPS NULL
b8dfc462 1168#endif /* CONFIG_PM */
1da177e4
LT		 1169
1170
48c8b0eb 1171static int azx_probe_continue(struct azx *chip);
a82d51ed 1172
8393ec4a 1173#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1174static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1175
a82d51ed
TI		 1176static void azx_vs_set_state(struct pci_dev *pci,
1177 enum vga_switcheroo_state state)
1178{
1179 struct snd_card *card = pci_get_drvdata(pci);
1180 struct azx *chip = card->private_data;
9a34af4a 1181 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
07f4f97d 1182 struct hda_codec *codec;
a82d51ed
TI		 1183 bool disabled;
1184
9a34af4a
TI		 1185 wait_for_completion(&hda->probe_wait);
1186 if (hda->init_failed)
a82d51ed
TI		 1187 return;
1188
1189 disabled = (state == VGA_SWITCHEROO_OFF);
1190 if (chip->disabled == disabled)
1191 return;
1192
a41d1224 1193 if (!hda->probe_continued) {
a82d51ed
TI		 1194 chip->disabled = disabled;
1195 if (!disabled) {
4e76a883
TI		 1196 dev_info(chip->card->dev,
1197 "Start delayed initialization\n");
5c90680e 1198 if (azx_probe_continue(chip) < 0) {
4e76a883 1199 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 1200 hda->init_failed = true;
a82d51ed
TI		 1201 }
1202 }
1203 } else {
2b760d88 1204 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
4e76a883 1205 disabled ? "Disabling" : "Enabling");
a82d51ed 1206 if (disabled) {
07f4f97d
LW		 1207 list_for_each_codec(codec, &chip->bus) {
1208 pm_runtime_suspend(hda_codec_dev(codec));
1209 pm_runtime_disable(hda_codec_dev(codec));
1210 }
1211 pm_runtime_suspend(card->dev);
1212 pm_runtime_disable(card->dev);
2b760d88 1213 /* when we get suspended by vga_switcheroo we end up in D3cold,
246efa4a
DA		 1214 * however we have no ACPI handle, so pci/acpi can't put us there,
1215 * put ourselves there */
1216 pci->current_state = PCI_D3cold;
a82d51ed 1217 chip->disabled = true;
a41d1224 1218 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1219 dev_warn(chip->card->dev,
1220 "Cannot lock devices!\n");
a82d51ed 1221 } else {
a41d1224 1222 snd_hda_unlock_devices(&chip->bus);
a82d51ed 1223 chip->disabled = false;
07f4f97d
LW		 1224 pm_runtime_enable(card->dev);
1225 list_for_each_codec(codec, &chip->bus) {
1226 pm_runtime_enable(hda_codec_dev(codec));
1227 pm_runtime_resume(hda_codec_dev(codec));
1228 }
a82d51ed
TI		 1229 }
1230 }
1231}
1232
1233static bool azx_vs_can_switch(struct pci_dev *pci)
1234{
1235 struct snd_card *card = pci_get_drvdata(pci);
1236 struct azx *chip = card->private_data;
9a34af4a 1237 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1238
9a34af4a
TI		 1239 wait_for_completion(&hda->probe_wait);
1240 if (hda->init_failed)
a82d51ed 1241 return false;
a41d1224 1242 if (chip->disabled || !hda->probe_continued)
a82d51ed 1243 return true;
a41d1224 1244 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1245 return false;
a41d1224 1246 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1247 return true;
1248}
1249
37a3a98e
TI		 1250/*
1251 * The discrete GPU cannot power down unless the HDA controller runtime
1252 * suspends, so activate runtime PM on codecs even if power_save == 0.
1253 */
1254static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1255{
1256 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1257 struct hda_codec *codec;
1258
dd23e1d5 1259 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
37a3a98e
TI		 1260 list_for_each_codec(codec, &chip->bus)
1261 codec->auto_runtime_pm = 1;
1262 /* reset the power save setup */
1263 if (chip->running)
1264 set_default_power_save(chip);
1265 }
1266}
1267
1268static void azx_vs_gpu_bound(struct pci_dev *pci,
1269 enum vga_switcheroo_client_id client_id)
1270{
1271 struct snd_card *card = pci_get_drvdata(pci);
1272 struct azx *chip = card->private_data;
37a3a98e
TI		 1273
1274 if (client_id == VGA_SWITCHEROO_DIS)
dd23e1d5 1275 chip->bus.keep_power = 0;
37a3a98e
TI		 1276 setup_vga_switcheroo_runtime_pm(chip);
1277}
1278
e23e7a14 1279static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1280{
9a34af4a 1281 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1282 struct pci_dev *p = get_bound_vga(chip->pci);
1283 if (p) {
4e76a883 1284 dev_info(chip->card->dev,
2b760d88 1285 "Handle vga_switcheroo audio client\n");
9a34af4a 1286 hda->use_vga_switcheroo = 1;
dd23e1d5 1287 chip->bus.keep_power = 1; /* cleared in either gpu_bound op or codec probe */
07f4f97d 1288 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
a82d51ed
TI		 1289 pci_dev_put(p);
1290 }
1291}
1292
1293static const struct vga_switcheroo_client_ops azx_vs_ops = {
1294 .set_gpu_state = azx_vs_set_state,
1295 .can_switch = azx_vs_can_switch,
37a3a98e 1296 .gpu_bound = azx_vs_gpu_bound,
a82d51ed
TI		 1297};
1298
e23e7a14 1299static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1300{
9a34af4a 1301 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
4aaf448f 1302 struct pci_dev *p;
128960a9
TI		 1303 int err;
1304
9a34af4a 1305 if (!hda->use_vga_switcheroo)
a82d51ed 1306 return 0;
4aaf448f
JQ		 1307
1308 p = get_bound_vga(chip->pci);
1309 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1310 pci_dev_put(p);
1311
128960a9
TI		 1312 if (err < 0)
1313 return err;
9a34af4a 1314 hda->vga_switcheroo_registered = 1;
246efa4a 1315
128960a9 1316 return 0;
a82d51ed
TI		 1317}
1318#else
1319#define init_vga_switcheroo(chip) /* NOP */
1320#define register_vga_switcheroo(chip) 0
8393ec4a 1321#define check_hdmi_disabled(pci) false
37a3a98e 1322#define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
a82d51ed
TI		 1323#endif /* SUPPORT_VGA_SWITCHER */
1324
1da177e4
LT		 1325/*
1326 * destructor
1327 */
a98f90fd 1328static int azx_free(struct azx *chip)
1da177e4 1329{
c67e2228 1330 struct pci_dev *pci = chip->pci;
a07187c9 1331 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1332 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1333
364aa716 1334 if (azx_has_pm_runtime(chip) && chip->running)
c67e2228 1335 pm_runtime_get_noresume(&pci->dev);
37a3a98e 1336 chip->running = 0;
c67e2228 1337
65fcd41d
TI		 1338 azx_del_card_list(chip);
1339
9a34af4a
TI		 1340 hda->init_failed = 1; /* to be sure */
1341 complete_all(&hda->probe_wait);
f4c482a4 1342
9a34af4a 1343 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1344 if (chip->disabled && hda->probe_continued)
1345 snd_hda_unlock_devices(&chip->bus);
07f4f97d 1346 if (hda->vga_switcheroo_registered)
128960a9 1347 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 1348 }
1349
a41d1224 1350 if (bus->chip_init) {
caa8422d 1351 azx_stop_chip(chip);
9ad593f6 1352 azx_clear_irq_pending(chip);
7833c3f8 1353 azx_stop_all_streams(chip);
1da177e4
LT		 1354 }
1355
a41d1224
TI		 1356 if (bus->irq >= 0)
1357 free_irq(bus->irq, (void*)chip);
68e7fffc 1358 if (chip->msi)
30b35399 1359 pci_disable_msi(chip->pci);
a41d1224 1360 iounmap(bus->remap_addr);
1da177e4 1361
67908994 1362 azx_free_stream_pages(chip);
a41d1224
TI		 1363 azx_free_streams(chip);
1364 snd_hdac_bus_exit(bus);
1365
a82d51ed
TI		 1366 if (chip->region_requested)
1367 pci_release_regions(chip->pci);
a41d1224 1368
1da177e4 1369 pci_disable_device(chip->pci);
4918cdab 1370#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1371 release_firmware(chip->fw);
4918cdab 1372#endif
e454ff8e 1373 display_power(chip, false);
98d8fc6c 1374
fc18282c 1375 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
fcc88d91 1376 snd_hdac_i915_exit(bus);
a07187c9 1377 kfree(hda);
1da177e4
LT		 1378
1379 return 0;
1380}
1381
a41d1224
TI		 1382static int azx_dev_disconnect(struct snd_device *device)
1383{
1384 struct azx *chip = device->device_data;
1385
1386 chip->bus.shutdown = 1;
1387 return 0;
1388}
1389
a98f90fd 1390static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1391{
1392 return azx_free(device->device_data);
1393}
1394
8393ec4a 1395#ifdef SUPPORT_VGA_SWITCHEROO
9121947d 1396/*
2b760d88 1397 * Check of disabled HDMI controller by vga_switcheroo
9121947d 1398 */
e23e7a14 1399static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1400{
1401 struct pci_dev *p;
1402
1403 /* check only discrete GPU */
1404 switch (pci->vendor) {
1405 case PCI_VENDOR_ID_ATI:
1406 case PCI_VENDOR_ID_AMD:
1407 case PCI_VENDOR_ID_NVIDIA:
1408 if (pci->devfn == 1) {
1409 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1410 pci->bus->number, 0);
1411 if (p) {
b6d7b362 1412 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
9121947d
TI		 1413 return p;
1414 pci_dev_put(p);
1415 }
1416 }
1417 break;
1418 }
1419 return NULL;
1420}
1421
e23e7a14 1422static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1423{
1424 bool vga_inactive = false;
1425 struct pci_dev *p = get_bound_vga(pci);
1426
1427 if (p) {
12b78a7f 1428 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1429 vga_inactive = true;
1430 pci_dev_put(p);
1431 }
1432 return vga_inactive;
1433}
8393ec4a 1434#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1435
3372a153
TI		 1436/*
1437 * white/black-listing for position_fix
1438 */
e23e7a14 1439static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1440 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1441 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1442 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1443 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1444 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1445 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1446 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1447 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1448 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1449 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1450 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1451 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1452 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1453 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1454 {}
1455};
1456
e23e7a14 1457static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1458{
1459 const struct snd_pci_quirk *q;
1460
c673ba1c 1461 switch (fix) {
1dac6695 1462 case POS_FIX_AUTO:
c673ba1c
TI		 1463 case POS_FIX_LPIB:
1464 case POS_FIX_POSBUF:
4cb36310 1465 case POS_FIX_VIACOMBO:
a6f2fd55 1466 case POS_FIX_COMBO:
f87e7f25 1467 case POS_FIX_SKL:
c02f77d3 1468 case POS_FIX_FIFO:
c673ba1c
TI		 1469 return fix;
1470 }
1471
c673ba1c
TI		 1472 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1473 if (q) {
4e76a883
TI		 1474 dev_info(chip->card->dev,
1475 "position_fix set to %d for device %04x:%04x\n",
1476 q->value, q->subvendor, q->subdevice);
c673ba1c 1477 return q->value;
3372a153 1478 }
bdd9ef24
DH		 1479
1480 /* Check VIA/ATI HD Audio Controller exist */
26f05717 1481 if (chip->driver_type == AZX_DRIVER_VIA) {
4e76a883 1482 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1483 return POS_FIX_VIACOMBO;
9477c58e 1484 }
c02f77d3
TI		 1485 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1486 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1487 return POS_FIX_FIFO;
1488 }
9477c58e 1489 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1490 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1491 return POS_FIX_LPIB;
bdd9ef24 1492 }
a4b4793f 1493 if (chip->driver_type == AZX_DRIVER_SKL) {
f87e7f25
TI		 1494 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1495 return POS_FIX_SKL;
1496 }
c673ba1c 1497 return POS_FIX_AUTO;
3372a153
TI		 1498}
1499
b6050ef6
TI		 1500static void assign_position_fix(struct azx *chip, int fix)
1501{
1502 static azx_get_pos_callback_t callbacks[] = {
1503 [POS_FIX_AUTO] = NULL,
1504 [POS_FIX_LPIB] = azx_get_pos_lpib,
1505 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1506 [POS_FIX_VIACOMBO] = azx_via_get_position,
1507 [POS_FIX_COMBO] = azx_get_pos_lpib,
f87e7f25 1508 [POS_FIX_SKL] = azx_get_pos_skl,
c02f77d3 1509 [POS_FIX_FIFO] = azx_get_pos_fifo,
b6050ef6
TI		 1510 };
1511
1512 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1513
1514 /* combo mode uses LPIB only for playback */
1515 if (fix == POS_FIX_COMBO)
1516 chip->get_position[1] = NULL;
1517
f87e7f25 1518 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
b6050ef6
TI		 1519 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1520 chip->get_delay[0] = chip->get_delay[1] =
1521 azx_get_delay_from_lpib;
1522 }
1523
c02f77d3
TI		 1524 if (fix == POS_FIX_FIFO)
1525 chip->get_delay[0] = chip->get_delay[1] =
1526 azx_get_delay_from_fifo;
b6050ef6
TI		 1527}
1528
669ba27a
TI		 1529/*
1530 * black-lists for probe_mask
1531 */
e23e7a14 1532static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1533 /* Thinkpad often breaks the controller communication when accessing
1534 * to the non-working (or non-existing) modem codec slot.
1535 */
1536 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1537 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1538 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1539 /* broken BIOS */
1540 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1541 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1542 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1543 /* forced codec slots */
93574844 1544 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1545 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1546 /* WinFast VP200 H (Teradici) user reported broken communication */
1547 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1548 {}
1549};
1550
f1eaaeec
TI		 1551#define AZX_FORCE_CODEC_MASK 0x100
1552
e23e7a14 1553static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1554{
1555 const struct snd_pci_quirk *q;
1556
f1eaaeec
TI		 1557 chip->codec_probe_mask = probe_mask[dev];
1558 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1559 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1560 if (q) {
4e76a883
TI		 1561 dev_info(chip->card->dev,
1562 "probe_mask set to 0x%x for device %04x:%04x\n",
1563 q->value, q->subvendor, q->subdevice);
f1eaaeec 1564 chip->codec_probe_mask = q->value;
669ba27a
TI		 1565 }
1566 }
f1eaaeec
TI		 1567
1568 /* check forced option */
1569 if (chip->codec_probe_mask != -1 &&
1570 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1571 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1572 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1573 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1574 }
669ba27a
TI		 1575}
1576
4d8e22e0 1577/*
71623855 1578 * white/black-list for enable_msi
4d8e22e0 1579 */
e23e7a14 1580static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1581 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1582 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1583 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1584 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1585 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1586 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1587 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1588 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1589 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1590 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1591 {}
1592};
1593
e23e7a14 1594static void check_msi(struct azx *chip)
4d8e22e0
TI		 1595{
1596 const struct snd_pci_quirk *q;
1597
71623855
TI		 1598 if (enable_msi >= 0) {
1599 chip->msi = !!enable_msi;
4d8e22e0 1600 return;
71623855
TI		 1601 }
1602 chip->msi = 1; /* enable MSI as default */
1603 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1604 if (q) {
4e76a883
TI		 1605 dev_info(chip->card->dev,
1606 "msi for device %04x:%04x set to %d\n",
1607 q->subvendor, q->subdevice, q->value);
4d8e22e0 1608 chip->msi = q->value;
80c43ed7
TI		 1609 return;
1610 }
1611
1612 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1613 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1614 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1615 chip->msi = 0;
4d8e22e0
TI		 1616 }
1617}
1618
a1585d76 1619/* check the snoop mode availability */
e23e7a14 1620static void azx_check_snoop_available(struct azx *chip)
a1585d76 1621{
7c732015 1622 int snoop = hda_snoop;
a1585d76 1623
7c732015
TI		 1624 if (snoop >= 0) {
1625 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1626 snoop ? "snoop" : "non-snoop");
1627 chip->snoop = snoop;
78c9be61 1628 chip->uc_buffer = !snoop;
7c732015
TI		 1629 return;
1630 }
1631
1632 snoop = true;
37e661ee
TI		 1633 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1634 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1635 /* force to non-snoop mode for a new VIA controller
1636 * when BIOS is set
1637 */
7c732015
TI		 1638 u8 val;
1639 pci_read_config_byte(chip->pci, 0x42, &val);
af52f998
DW		 1640 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1641 chip->pci->revision == 0x20))
7c732015 1642 snoop = false;
a1585d76
TI		 1643 }
1644
37e661ee
TI		 1645 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1646 snoop = false;
1647
7c732015 1648 chip->snoop = snoop;
78c9be61 1649 if (!snoop) {
7c732015 1650 dev_info(chip->card->dev, "Force to non-snoop mode\n");
78c9be61
TI		 1651 /* C-Media requires non-cached pages only for CORB/RIRB */
1652 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1653 chip->uc_buffer = true;
1654 }
a1585d76 1655}
669ba27a 1656
99a2008d
WX		 1657static void azx_probe_work(struct work_struct *work)
1658{
9a34af4a
TI		 1659 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1660 azx_probe_continue(&hda->chip);
99a2008d 1661}
99a2008d 1662
4f0189be
TI		 1663static int default_bdl_pos_adj(struct azx *chip)
1664{
2cf721db
TI		 1665 /* some exceptions: Atoms seem problematic with value 1 */
1666 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1667 switch (chip->pci->device) {
1668 case 0x0f04: /* Baytrail */
1669 case 0x2284: /* Braswell */
1670 return 32;
1671 }
1672 }
1673
4f0189be
TI		 1674 switch (chip->driver_type) {
1675 case AZX_DRIVER_ICH:
1676 case AZX_DRIVER_PCH:
1677 return 1;
1678 default:
1679 return 32;
1680 }
1681}
1682
1da177e4
LT		 1683/*
1684 * constructor
1685 */
a43ff5ba
TI		 1686static const struct hda_controller_ops pci_hda_ops;
1687
e23e7a14
BP		 1688static int azx_create(struct snd_card *card, struct pci_dev *pci,
1689 int dev, unsigned int driver_caps,
1690 struct azx **rchip)
1da177e4 1691{
a98f90fd 1692 static struct snd_device_ops ops = {
a41d1224 1693 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1694 .dev_free = azx_dev_free,
1695 };
a07187c9 1696 struct hda_intel *hda;
a82d51ed
TI		 1697 struct azx *chip;
1698 int err;
1da177e4
LT		 1699
1700 *rchip = NULL;
bcd72003 1701
927fc866
PM		 1702 err = pci_enable_device(pci);
1703 if (err < 0)
1da177e4
LT		 1704 return err;
1705
a07187c9
ML		 1706 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1707 if (!hda) {
1da177e4
LT		 1708 pci_disable_device(pci);
1709 return -ENOMEM;
1710 }
1711
a07187c9 1712 chip = &hda->chip;
62932df8 1713 mutex_init(&chip->open_mutex);
1da177e4
LT		 1714 chip->card = card;
1715 chip->pci = pci;
a43ff5ba 1716 chip->ops = &pci_hda_ops;
9477c58e
TI		 1717 chip->driver_caps = driver_caps;
1718 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1719 check_msi(chip);
555e219f 1720 chip->dev_index = dev;
3a182c84
TI		 1721 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1722 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
01b65bfb 1723 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1724 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1725 INIT_LIST_HEAD(&hda->list);
a82d51ed 1726 init_vga_switcheroo(chip);
9a34af4a 1727 init_completion(&hda->probe_wait);
1da177e4 1728
b6050ef6 1729 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1730
5aba4f8e 1731 check_probe_mask(chip, dev);
3372a153 1732
41438f13
TI		 1733 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1734 chip->fallback_to_single_cmd = 1;
1735 else /* explicitly set to single_cmd or not */
1736 chip->single_cmd = single_cmd;
1737
a1585d76 1738 azx_check_snoop_available(chip);
c74db86b 1739
4f0189be
TI		 1740 if (bdl_pos_adj[dev] < 0)
1741 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1742 else
1743 chip->bdl_pos_adj = bdl_pos_adj[dev];
5c0d7bc1 1744
19abfefd 1745 err = azx_bus_init(chip, model[dev]);
a41d1224
TI		 1746 if (err < 0) {
1747 kfree(hda);
1748 pci_disable_device(pci);
1749 return err;
1750 }
1751
619a1f19
TI		 1752 /* use the non-cached pages in non-snoop mode */
1753 if (!azx_snoop(chip))
1754 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC;
1755
bd2956e4
BL		 1756 /* Workaround for a communication error on CFL (bko#199007) and CNL */
1757 if (IS_CFL(pci) || IS_CNL(pci))
8af42130 1758 azx_bus(chip)->polling_mode = 1;
bd2956e4 1759
7d9a1808
TI		 1760 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1761 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1762 chip->bus.needs_damn_long_delay = 1;
1763 }
1764
a82d51ed
TI		 1765 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1766 if (err < 0) {
4e76a883 1767 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1768 azx_free(chip);
1769 return err;
1770 }
1771
99a2008d 1772 /* continue probing in work context as may trigger request module */
9a34af4a 1773 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1774
a82d51ed 1775 *rchip = chip;
99a2008d 1776
a82d51ed
TI		 1777 return 0;
1778}
1779
48c8b0eb 1780static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1781{
1782 int dev = chip->dev_index;
1783 struct pci_dev *pci = chip->pci;
1784 struct snd_card *card = chip->card;
a41d1224 1785 struct hdac_bus *bus = azx_bus(chip);
67908994 1786 int err;
a82d51ed 1787 unsigned short gcap;
413cbf46 1788 unsigned int dma_bits = 64;
a82d51ed 1789
07e4ca50
TI		 1790#if BITS_PER_LONG != 64
1791 /* Fix up base address on ULI M5461 */
1792 if (chip->driver_type == AZX_DRIVER_ULI) {
1793 u16 tmp3;
1794 pci_read_config_word(pci, 0x40, &tmp3);
1795 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1796 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1797 }
1798#endif
1799
927fc866 1800 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1801 if (err < 0)
1da177e4 1802 return err;
a82d51ed 1803 chip->region_requested = 1;
1da177e4 1804
a41d1224
TI		 1805 bus->addr = pci_resource_start(pci, 0);
1806 bus->remap_addr = pci_ioremap_bar(pci, 0);
1807 if (bus->remap_addr == NULL) {
4e76a883 1808 dev_err(card->dev, "ioremap error\n");
a82d51ed 1809 return -ENXIO;
1da177e4
LT		 1810 }
1811
a4b4793f 1812 if (chip->driver_type == AZX_DRIVER_SKL)
50279d9b
GS		 1813 snd_hdac_bus_parse_capabilities(bus);
1814
1815 /*
1816 * Some Intel CPUs has always running timer (ART) feature and
1817 * controller may have Global time sync reporting capability, so
1818 * check both of these before declaring synchronized time reporting
1819 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1820 */
1821 chip->gts_present = false;
1822
1823#ifdef CONFIG_X86
1824 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1825 chip->gts_present = true;
1826#endif
1827
db79afa1
BH		 1828 if (chip->msi) {
1829 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1830 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1831 pci->no_64bit_msi = true;
1832 }
68e7fffc
TI		 1833 if (pci_enable_msi(pci) < 0)
1834 chip->msi = 0;
db79afa1 1835 }
7376d013 1836
1da177e4 1837 pci_set_master(pci);
a41d1224 1838 synchronize_irq(bus->irq);
1da177e4 1839
bcd72003 1840 gcap = azx_readw(chip, GCAP);
4e76a883 1841 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1842
413cbf46
TI		 1843 /* AMD devices support 40 or 48bit DMA, take the safe one */
1844 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1845 dma_bits = 40;
1846
dc4c2e6b 1847 /* disable SB600 64bit support for safety */
9477c58e 1848 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1849 struct pci_dev *p_smbus;
413cbf46 1850 dma_bits = 40;
dc4c2e6b
AB		 1851 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1852 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1853 NULL);
1854 if (p_smbus) {
1855 if (p_smbus->revision < 0x30)
fb1d8ac2 1856 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1857 pci_dev_put(p_smbus);
1858 }
1859 }
09240cf4 1860
3ab7511e
AB		 1861 /* NVidia hardware normally only supports up to 40 bits of DMA */
1862 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1863 dma_bits = 40;
1864
9477c58e
TI		 1865 /* disable 64bit DMA address on some devices */
1866 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1867 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1868 gcap &= ~AZX_GCAP_64OK;
9477c58e 1869 }
396087ea 1870
2ae66c26 1871 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1872 if (align_buffer_size >= 0)
1873 chip->align_buffer_size = !!align_buffer_size;
1874 else {
103884a3 1875 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1876 chip->align_buffer_size = 0;
7bfe059e
TI		 1877 else
1878 chip->align_buffer_size = 1;
1879 }
2ae66c26 1880
cf7aaca8 1881 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1882 if (!(gcap & AZX_GCAP_64OK))
1883 dma_bits = 32;
412b979c
QL		 1884 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1885 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
413cbf46 1886 } else {
412b979c
QL		 1887 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1888 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
09240cf4 1889 }
cf7aaca8 1890
8b6ed8e7
TI		 1891 /* read number of streams from GCAP register instead of using
1892 * hardcoded value
1893 */
1894 chip->capture_streams = (gcap >> 8) & 0x0f;
1895 chip->playback_streams = (gcap >> 12) & 0x0f;
1896 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1897 /* gcap didn't give any info, switching to old method */
1898
1899 switch (chip->driver_type) {
1900 case AZX_DRIVER_ULI:
1901 chip->playback_streams = ULI_NUM_PLAYBACK;
1902 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1903 break;
1904 case AZX_DRIVER_ATIHDMI:
1815b34a 1905 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1906 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1907 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1908 break;
c4da29ca 1909 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1910 default:
1911 chip->playback_streams = ICH6_NUM_PLAYBACK;
1912 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1913 break;
1914 }
07e4ca50 1915 }
8b6ed8e7
TI		 1916 chip->capture_index_offset = 0;
1917 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1918 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1919
df56c3db
JK		 1920 /* sanity check for the SDxCTL.STRM field overflow */
1921 if (chip->num_streams > 15 &&
1922 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1923 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1924 "forcing separate stream tags", chip->num_streams);
1925 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1926 }
1927
a41d1224
TI		 1928 /* initialize streams */
1929 err = azx_init_streams(chip);
81740861 1930 if (err < 0)
a82d51ed 1931 return err;
1da177e4 1932
a41d1224
TI		 1933 err = azx_alloc_stream_pages(chip);
1934 if (err < 0)
1935 return err;
1da177e4
LT		 1936
1937 /* initialize chip */
cb53c626 1938 azx_init_pci(chip);
e4d9e513 1939
e454ff8e 1940 snd_hdac_i915_set_bclk(bus);
e4d9e513 1941
0a673521 1942 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1943
1944 /* codec detection */
a41d1224 1945 if (!azx_bus(chip)->codec_mask) {
4e76a883 1946 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1947 return -ENODEV;
1da177e4
LT		 1948 }
1949
f495222e
TI		 1950 if (azx_acquire_irq(chip, 0) < 0)
1951 return -EBUSY;
1952
07e4ca50 1953 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1954 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1955 sizeof(card->shortname));
1956 snprintf(card->longname, sizeof(card->longname),
1957 "%s at 0x%lx irq %i",
a41d1224 1958 card->shortname, bus->addr, bus->irq);
07e4ca50 1959
1da177e4 1960 return 0;
1da177e4
LT		 1961}
1962
97c6a3d1 1963#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1964/* callback from request_firmware_nowait() */
1965static void azx_firmware_cb(const struct firmware *fw, void *context)
1966{
1967 struct snd_card *card = context;
1968 struct azx *chip = card->private_data;
1969 struct pci_dev *pci = chip->pci;
1970
1971 if (!fw) {
4e76a883 1972 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1973 goto error;
1974 }
1975
1976 chip->fw = fw;
1977 if (!chip->disabled) {
1978 /* continue probing */
1979 if (azx_probe_continue(chip))
1980 goto error;
1981 }
1982 return; /* OK */
1983
1984 error:
1985 snd_card_free(card);
1986 pci_set_drvdata(pci, NULL);
1987}
97c6a3d1 1988#endif
5cb543db 1989
f46ea609
DR		 1990static int disable_msi_reset_irq(struct azx *chip)
1991{
a41d1224 1992 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 1993 int err;
1994
a41d1224
TI		 1995 free_irq(bus->irq, chip);
1996 bus->irq = -1;
f46ea609
DR		 1997 pci_disable_msi(chip->pci);
1998 chip->msi = 0;
1999 err = azx_acquire_irq(chip, 1);
2000 if (err < 0)
2001 return err;
2002
2003 return 0;
2004}
2005
8769b278
DR		 2006static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2007 struct vm_area_struct *area)
2008{
2009#ifdef CONFIG_X86
2010 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2011 struct azx *chip = apcm->chip;
78c9be61 2012 if (chip->uc_buffer)
8769b278
DR		 2013 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2014#endif
2015}
2016
a43ff5ba
TI		 2017static const struct hda_controller_ops pci_hda_ops = {
2018 .disable_msi_reset_irq = disable_msi_reset_irq,
8769b278 2019 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 2020 .position_check = azx_position_check,
40830813
DR		 2021};
2022
8c575883
PLB		 2023static int azx_check_dmic(struct pci_dev *pci, struct azx *chip)
2024{
2025 struct nhlt_acpi_table *nhlt;
2026 int ret = 0;
2027
2028 if (chip->driver_type == AZX_DRIVER_SKL &&
2029 pci->class != 0x040300) {
2030 nhlt = intel_nhlt_init(&pci->dev);
2031 if (nhlt) {
2032 if (intel_nhlt_get_dmic_geo(&pci->dev, nhlt)) {
2033 ret = -ENODEV;
2034 dev_info(&pci->dev, "Digital mics found on Skylake+ platform, aborting probe\n");
2035 }
2036 intel_nhlt_free(nhlt);
2037 }
2038 }
2039 return ret;
2040}
2041
e23e7a14
BP		 2042static int azx_probe(struct pci_dev *pci,
2043 const struct pci_device_id *pci_id)
1da177e4 2044{
5aba4f8e 2045 static int dev;
a98f90fd 2046 struct snd_card *card;
9a34af4a 2047 struct hda_intel *hda;
a98f90fd 2048 struct azx *chip;
aad730d0 2049 bool schedule_probe;
927fc866 2050 int err;
1da177e4 2051
5aba4f8e
TI		 2052 if (dev >= SNDRV_CARDS)
2053 return -ENODEV;
2054 if (!enable[dev]) {
2055 dev++;
2056 return -ENOENT;
2057 }
2058
60c5772b
TI		 2059 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2060 0, &card);
e58de7ba 2061 if (err < 0) {
4e76a883 2062 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 2063 return err;
1da177e4
LT		 2064 }
2065
a43ff5ba 2066 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2067 if (err < 0)
2068 goto out_free;
421a1252 2069 card->private_data = chip;
9a34af4a 2070 hda = container_of(chip, struct hda_intel, chip);
f4c482a4 2071
8c575883
PLB		 2072 /*
2073 * stop probe if digital microphones detected on Skylake+ platform
2074 * with the DSP enabled. This is an opt-in behavior defined at build
2075 * time or at run-time with a module parameter
2076 */
2077 if (dmic_detect) {
2078 err = azx_check_dmic(pci, chip);
2079 if (err < 0)
2080 goto out_free;
2081 }
2082
f4c482a4
TI		 2083 pci_set_drvdata(pci, card);
2084
2085 err = register_vga_switcheroo(chip);
2086 if (err < 0) {
2b760d88 2087 dev_err(card->dev, "Error registering vga_switcheroo client\n");
f4c482a4
TI		 2088 goto out_free;
2089 }
2090
2091 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 2092 dev_info(card->dev, "VGA controller is disabled\n");
2093 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 2094 chip->disabled = true;
2095 }
2096
aad730d0 2097 schedule_probe = !chip->disabled;
1da177e4 2098
4918cdab
TI		 2099#ifdef CONFIG_SND_HDA_PATCH_LOADER
2100 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 2101 dev_info(card->dev, "Applying patch firmware '%s'\n",
2102 patch[dev]);
5cb543db
TI		 2103 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2104 &pci->dev, GFP_KERNEL, card,
2105 azx_firmware_cb);
4918cdab
TI		 2106 if (err < 0)
2107 goto out_free;
aad730d0 2108 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 2109 }
2110#endif /* CONFIG_SND_HDA_PATCH_LOADER */
2111
aad730d0 2112#ifndef CONFIG_SND_HDA_I915
6ee8eeb4
TI		 2113 if (CONTROLLER_IN_GPU(pci))
2114 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
99a2008d 2115#endif
99a2008d 2116
aad730d0 2117 if (schedule_probe)
9a34af4a 2118 schedule_work(&hda->probe_work);
a82d51ed 2119
a82d51ed 2120 dev++;
88d071fc 2121 if (chip->disabled)
9a34af4a 2122 complete_all(&hda->probe_wait);
a82d51ed
TI		 2123 return 0;
2124
2125out_free:
2126 snd_card_free(card);
2127 return err;
2128}
2129
1ba8f9d3
HG		 2130#ifdef CONFIG_PM
2131/* On some boards setting power_save to a non 0 value leads to clicking /
2132 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2133 * figure out how to avoid these sounds, but that is not always feasible.
2134 * So we keep a list of devices where we disable powersaving as its known
2135 * to causes problems on these devices.
2136 */
2137static struct snd_pci_quirk power_save_blacklist[] = {
2138 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
8e82a728 2139 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
1ba8f9d3 2140 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
39070a98
HG		 2141 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2142 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
45e5fbc2
HG		 2143 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2144 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
1ba8f9d3 2145 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
b529ef24
HG		 2146 /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2147 SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
38d9c12c 2148 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
5cb6b5fc
HG		 2149 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2150 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
38d9c12c
HG		 2151 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2152 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
5cb6b5fc
HG		 2153 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2154 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
f91f1806
HG		 2155 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2156 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
cae30527
HW		 2157 /* https://bugs.launchpad.net/bugs/1821663 */
2158 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
dd6dd536
HG		 2159 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2160 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
1ba8f9d3
HG		 2161 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2162 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
721f1e6c
JK		 2163 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2164 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2165 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2166 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
cae30527
HW		 2167 /* https://bugs.launchpad.net/bugs/1821663 */
2168 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
1ba8f9d3
HG		 2169 {}
2170};
2171#endif /* CONFIG_PM */
2172
37a3a98e
TI		 2173static void set_default_power_save(struct azx *chip)
2174{
2175 int val = power_save;
2176
2177#ifdef CONFIG_PM
2178 if (pm_blacklist) {
2179 const struct snd_pci_quirk *q;
2180
2181 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2182 if (q && val) {
2183 dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2184 q->subvendor, q->subdevice);
2185 val = 0;
2186 }
2187 }
2188#endif /* CONFIG_PM */
2189 snd_hda_set_power_save(&chip->bus, val * 1000);
2190}
2191
e62a42ae
DR		 2192/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2193static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2194 [AZX_DRIVER_NVIDIA] = 8,
2195 [AZX_DRIVER_TERA] = 1,
2196};
2197
48c8b0eb 2198static int azx_probe_continue(struct azx *chip)
a82d51ed 2199{
9a34af4a 2200 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 2201 struct hdac_bus *bus = azx_bus(chip);
c67e2228 2202 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 2203 int dev = chip->dev_index;
2204 int err;
2205
305a0ade 2206 to_hda_bus(bus)->bus_probing = 1;
a41d1224 2207 hda->probe_continued = 1;
795614dd 2208
fcc88d91 2209 /* bind with i915 if needed */
dba9b7b6 2210 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
98d8fc6c 2211 err = snd_hdac_i915_init(bus);
535115b5
TI		 2212 if (err < 0) {
2213 /* if the controller is bound only with HDMI/DP
2214 * (for HSW and BDW), we need to abort the probe;
2215 * for other chips, still continue probing as other
2216 * codecs can be on the same link.
2217 */
bed2e98e
TI		 2218 if (CONTROLLER_IN_GPU(pci)) {
2219 dev_err(chip->card->dev,
2220 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
535115b5 2221 goto out_free;
fcc88d91
TI		 2222 } else {
2223 /* don't bother any longer */
e454ff8e 2224 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
fcc88d91 2225 }
535115b5 2226 }
e454ff8e
TI		 2227
2228 /* HSW/BDW controllers need this power */
2229 if (CONTROLLER_IN_GPU(pci))
2230 hda->need_i915_power = 1;
fcc88d91
TI		 2231 }
2232
2233 /* Request display power well for the HDA controller or codec. For
2234 * Haswell/Broadwell, both the display HDA controller and codec need
2235 * this power. For other platforms, like Baytrail/Braswell, only the
2236 * display codec needs the power and it can be released after probe.
2237 */
4f799e73 2238 display_power(chip, true);
99a2008d 2239
5c90680e
TI		 2240 err = azx_first_init(chip);
2241 if (err < 0)
2242 goto out_free;
2243
2dca0bba
JK		 2244#ifdef CONFIG_SND_HDA_INPUT_BEEP
2245 chip->beep_mode = beep_mode[dev];
2246#endif
2247
1da177e4 2248 /* create codec instances */
96d2bd6e 2249 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
41dda0fd
WF		 2250 if (err < 0)
2251 goto out_free;
96d2bd6e 2252
4ea6fbc8 2253#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2254 if (chip->fw) {
a41d1224 2255 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2256 chip->fw->data);
4ea6fbc8
TI		 2257 if (err < 0)
2258 goto out_free;
e39ae856 2259#ifndef CONFIG_PM
4918cdab
TI		 2260 release_firmware(chip->fw); /* no longer needed */
2261 chip->fw = NULL;
e39ae856 2262#endif
4ea6fbc8
TI		 2263 }
2264#endif
10e77dda 2265 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 2266 err = azx_codec_configure(chip);
2267 if (err < 0)
2268 goto out_free;
2269 }
1da177e4 2270
a82d51ed 2271 err = snd_card_register(chip->card);
41dda0fd
WF		 2272 if (err < 0)
2273 goto out_free;
1da177e4 2274
37a3a98e
TI		 2275 setup_vga_switcheroo_runtime_pm(chip);
2276
cb53c626 2277 chip->running = 1;
65fcd41d 2278 azx_add_card_list(chip);
07f4f97d 2279
37a3a98e 2280 set_default_power_save(chip);
07f4f97d 2281
07f4f97d 2282 if (azx_has_pm_runtime(chip))
30ff5957 2283 pm_runtime_put_autosuspend(&pci->dev);
1da177e4 2284
41dda0fd 2285out_free:
457f3c86 2286 if (err < 0 || !hda->need_i915_power)
029d92c2 2287 display_power(chip, false);
88d071fc 2288 if (err < 0)
9a34af4a
TI		 2289 hda->init_failed = 1;
2290 complete_all(&hda->probe_wait);
305a0ade 2291 to_hda_bus(bus)->bus_probing = 0;
41dda0fd 2292 return err;
1da177e4
LT		 2293}
2294
e23e7a14 2295static void azx_remove(struct pci_dev *pci)
1da177e4 2296{
9121947d 2297 struct snd_card *card = pci_get_drvdata(pci);
991f86d7
TI		 2298 struct azx *chip;
2299 struct hda_intel *hda;
2300
2301 if (card) {
0b8c8219 2302 /* cancel the pending probing work */
991f86d7
TI		 2303 chip = card->private_data;
2304 hda = container_of(chip, struct hda_intel, chip);
ab949d51
TI		 2305 /* FIXME: below is an ugly workaround.
2306 * Both device_release_driver() and driver_probe_device()
2307 * take *both* the device's and its parent's lock before
2308 * calling the remove() and probe() callbacks. The codec
2309 * probe takes the locks of both the codec itself and its
2310 * parent, i.e. the PCI controller dev. Meanwhile, when
2311 * the PCI controller is unbound, it takes its lock, too
2312 * ==> ouch, a deadlock!
2313 * As a workaround, we unlock temporarily here the controller
2314 * device during cancel_work_sync() call.
2315 */
2316 device_unlock(&pci->dev);
0b8c8219 2317 cancel_work_sync(&hda->probe_work);
ab949d51 2318 device_lock(&pci->dev);
b8dfc462 2319
9121947d 2320 snd_card_free(card);
991f86d7 2321 }
1da177e4
LT		 2322}
2323
b2a0bafa
TI		 2324static void azx_shutdown(struct pci_dev *pci)
2325{
2326 struct snd_card *card = pci_get_drvdata(pci);
2327 struct azx *chip;
2328
2329 if (!card)
2330 return;
2331 chip = card->private_data;
2332 if (chip && chip->running)
2333 azx_stop_chip(chip);
2334}
2335
1da177e4 2336/* PCI IDs */
6f51f6cf 2337static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2338 /* CPT */
9477c58e 2339 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 2340 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 2341 /* PBG */
9477c58e 2342 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2343 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2344 /* Panther Point */
9477c58e 2345 { PCI_DEVICE(0x8086, 0x1e20),
de5d0ad5 2346 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 2347 /* Lynx Point */
2348 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2349 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 2350 /* 9 Series */
2351 { PCI_DEVICE(0x8086, 0x8ca0),
2352 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2353 /* Wellsburg */
2354 { PCI_DEVICE(0x8086, 0x8d20),
2355 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2356 { PCI_DEVICE(0x8086, 0x8d21),
2357 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
5cf92c8b
AY		 2358 /* Lewisburg */
2359 { PCI_DEVICE(0x8086, 0xa1f0),
e7480b34 2360 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
5cf92c8b 2361 { PCI_DEVICE(0x8086, 0xa270),
e7480b34 2362 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
144dad99
JR		 2363 /* Lynx Point-LP */
2364 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2365 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2366 /* Lynx Point-LP */
2367 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2368 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2369 /* Wildcat Point-LP */
2370 { PCI_DEVICE(0x8086, 0x9ca0),
2371 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2372 /* Sunrise Point */
2373 { PCI_DEVICE(0x8086, 0xa170),
a4b4793f 2374 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
b4565913
DR		 2375 /* Sunrise Point-LP */
2376 { PCI_DEVICE(0x8086, 0x9d70),
3e9ad24b 2377 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2378 /* Kabylake */
2379 { PCI_DEVICE(0x8086, 0xa171),
a4b4793f 2380 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2381 /* Kabylake-LP */
2382 { PCI_DEVICE(0x8086, 0x9d71),
3e9ad24b 2383 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
6858107e
VK		 2384 /* Kabylake-H */
2385 { PCI_DEVICE(0x8086, 0xa2f0),
a4b4793f 2386 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
e79b0006
MD		 2387 /* Coffelake */
2388 { PCI_DEVICE(0x8086, 0xa348),
3e9ad24b 2389 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2357f6f0
GS		 2390 /* Cannonlake */
2391 { PCI_DEVICE(0x8086, 0x9dc8),
3e9ad24b 2392 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
d4c2ccdb
PLB		 2393 /* CometLake-LP */
2394 { PCI_DEVICE(0x8086, 0x02C8),
2395 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2396 /* CometLake-H */
2397 { PCI_DEVICE(0x8086, 0x06C8),
2398 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
491f8331
GS		 2399 /* Icelake */
2400 { PCI_DEVICE(0x8086, 0x34c8),
3e9ad24b 2401 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
f94287b6
LPS		 2402 /* Elkhart Lake */
2403 { PCI_DEVICE(0x8086, 0x4b55),
2404 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
c87693da
LH		 2405 /* Broxton-P(Apollolake) */
2406 { PCI_DEVICE(0x8086, 0x5a98),
3e9ad24b 2407 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
9859a971
LH		 2408 /* Broxton-T */
2409 { PCI_DEVICE(0x8086, 0x1a98),
a4b4793f 2410 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
44b46d73
VK		 2411 /* Gemini-Lake */
2412 { PCI_DEVICE(0x8086, 0x3198),
3e9ad24b 2413 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
e926f2c8 2414 /* Haswell */
4a7c516b 2415 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2416 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2417 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2418 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2419 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2420 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2421 /* Broadwell */
2422 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2423 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2424 /* 5 Series/3400 */
2425 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2426 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2427 /* Poulsbo */
9477c58e 2428 { PCI_DEVICE(0x8086, 0x811b),
6603249d 2429 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
f748abcc 2430 /* Oaktrail */
09904b95 2431 { PCI_DEVICE(0x8086, 0x080a),
6603249d 2432 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
e44007e0
CCE		 2433 /* BayTrail */
2434 { PCI_DEVICE(0x8086, 0x0f04),
40cc2392 2435 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
f31b2ffc
LY		 2436 /* Braswell */
2437 { PCI_DEVICE(0x8086, 0x2284),
2d846c74 2438 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
b42b4afb 2439 /* ICH6 */
8b0bd226 2440 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2441 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2442 /* ICH7 */
8b0bd226 2443 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2444 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2445 /* ESB2 */
8b0bd226 2446 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2447 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2448 /* ICH8 */
8b0bd226 2449 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2450 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2451 /* ICH9 */
8b0bd226 2452 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2453 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2454 /* ICH9 */
8b0bd226 2455 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2456 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2457 /* ICH10 */
8b0bd226 2458 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2459 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2460 /* ICH10 */
8b0bd226 2461 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2462 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2463 /* Generic Intel */
2464 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2465 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2466 .class_mask = 0xffffff,
103884a3 2467 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2468 /* ATI SB 450/600/700/800/900 */
2469 { PCI_DEVICE(0x1002, 0x437b),
2470 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2471 { PCI_DEVICE(0x1002, 0x4383),
2472 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2473 /* AMD Hudson */
2474 { PCI_DEVICE(0x1022, 0x780d),
2475 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
c02f77d3
TI		 2476 /* AMD, X370 & co */
2477 { PCI_DEVICE(0x1022, 0x1457),
2478 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
de768ce4
TI		 2479 /* AMD, X570 & co */
2480 { PCI_DEVICE(0x1022, 0x1487),
2481 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
3deef52c
KHF		 2482 /* AMD Stoney */
2483 { PCI_DEVICE(0x1022, 0x157a),
2484 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2485 AZX_DCAPS_PM_RUNTIME },
9ceace3c
VM		 2486 /* AMD Raven */
2487 { PCI_DEVICE(0x1022, 0x15e3),
d2c63b7d 2488 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
87218e9c 2489 /* ATI HDMI */
fd48331f
MSB		 2490 { PCI_DEVICE(0x1002, 0x0002),
2491 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
650474fb
AD		 2492 { PCI_DEVICE(0x1002, 0x1308),
2493 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2494 { PCI_DEVICE(0x1002, 0x157a),
2495 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
d716fb03
AB		 2496 { PCI_DEVICE(0x1002, 0x15b3),
2497 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2498 { PCI_DEVICE(0x1002, 0x793b),
2499 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2500 { PCI_DEVICE(0x1002, 0x7919),
2501 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2502 { PCI_DEVICE(0x1002, 0x960f),
2503 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2504 { PCI_DEVICE(0x1002, 0x970f),
2505 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
650474fb
AD		 2506 { PCI_DEVICE(0x1002, 0x9840),
2507 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2508 { PCI_DEVICE(0x1002, 0xaa00),
2509 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2510 { PCI_DEVICE(0x1002, 0xaa08),
2511 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2512 { PCI_DEVICE(0x1002, 0xaa10),
2513 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2514 { PCI_DEVICE(0x1002, 0xaa18),
2515 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2516 { PCI_DEVICE(0x1002, 0xaa20),
2517 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2518 { PCI_DEVICE(0x1002, 0xaa28),
2519 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2520 { PCI_DEVICE(0x1002, 0xaa30),
2521 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2522 { PCI_DEVICE(0x1002, 0xaa38),
2523 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2524 { PCI_DEVICE(0x1002, 0xaa40),
2525 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2526 { PCI_DEVICE(0x1002, 0xaa48),
2527 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2528 { PCI_DEVICE(0x1002, 0xaa50),
2529 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2530 { PCI_DEVICE(0x1002, 0xaa58),
2531 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2532 { PCI_DEVICE(0x1002, 0xaa60),
2533 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2534 { PCI_DEVICE(0x1002, 0xaa68),
2535 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2536 { PCI_DEVICE(0x1002, 0xaa80),
2537 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2538 { PCI_DEVICE(0x1002, 0xaa88),
2539 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2540 { PCI_DEVICE(0x1002, 0xaa90),
2541 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2542 { PCI_DEVICE(0x1002, 0xaa98),
2543 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2544 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2545 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2546 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2547 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2548 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2549 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2550 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2551 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2552 { PCI_DEVICE(0x1002, 0xaac0),
2553 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
0fa372b6
TI		 2554 { PCI_DEVICE(0x1002, 0xaac8),
2555 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2556 { PCI_DEVICE(0x1002, 0xaad8),
2557 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2558 { PCI_DEVICE(0x1002, 0xaae8),
2559 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
8eb22214
MSB		 2560 { PCI_DEVICE(0x1002, 0xaae0),
2561 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2562 { PCI_DEVICE(0x1002, 0xaaf0),
2563 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
87218e9c 2564 /* VIA VT8251/VT8237A */
26f05717 2565 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
754fdff8
AL		 2566 /* VIA GFX VT7122/VX900 */
2567 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2568 /* VIA GFX VT6122/VX11 */
2569 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2570 /* SIS966 */
2571 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2572 /* ULI M5461 */
2573 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2574 /* NVIDIA MCP */
0c2fd1bf
TI		 2575 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2576 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2577 .class_mask = 0xffffff,
9477c58e 2578 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2579 /* Teradici */
9477c58e
TI		 2580 { PCI_DEVICE(0x6549, 0x1200),
2581 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2582 { PCI_DEVICE(0x6549, 0x2200),
2583 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2584 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2585 /* CTHDA chips */
2586 { PCI_DEVICE(0x1102, 0x0010),
2587 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2588 { PCI_DEVICE(0x1102, 0x0012),
2589 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2590#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2591 /* the following entry conflicts with snd-ctxfi driver,
2592 * as ctxfi driver mutates from HD-audio to native mode with
2593 * a special command sequence.
2594 */
4e01f54b
TI		 2595 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2596 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2597 .class_mask = 0xffffff,
9477c58e 2598 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2599 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2600#else
2601 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2602 { PCI_DEVICE(0x1102, 0x0009),
2603 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2604 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2605#endif
c563f473
TI		 2606 /* CM8888 */
2607 { PCI_DEVICE(0x13f6, 0x5011),
2608 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2609 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2610 /* Vortex86MX */
2611 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2612 /* VMware HDAudio */
2613 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2614 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2615 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2616 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2617 .class_mask = 0xffffff,
9477c58e 2618 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2619 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2620 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2621 .class_mask = 0xffffff,
9477c58e 2622 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
b6fcab14
TW		 2623 /* Zhaoxin */
2624 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
1da177e4
LT		 2625 { 0, }
2626};
2627MODULE_DEVICE_TABLE(pci, azx_ids);
2628
2629/* pci_driver definition */
e9f66d9b 2630static struct pci_driver azx_driver = {
3733e424 2631 .name = KBUILD_MODNAME,
1da177e4
LT		 2632 .id_table = azx_ids,
2633 .probe = azx_probe,
e23e7a14 2634 .remove = azx_remove,
b2a0bafa 2635 .shutdown = azx_shutdown,
68cb2b55
TI		 2636 .driver = {
2637 .pm = AZX_PM_OPS,
2638 },
1da177e4
LT		 2639};
2640
e9f66d9b 2641module_pci_driver(azx_driver);
Linux 6.x block layer and io_uring tree(s)