[linux-2.6-block.git] / sound / arm / pxa2xx-ac97-lib.c

/*
 * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
 * which contain:
 *
 * Author:	Nicolas Pitre
 * Created:	Dec 02, 2004
 * Copyright:	MontaVista Software Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/gpio.h>

#include <sound/pxa2xx-lib.h>

#include <mach/irqs.h>
#include <mach/regs-ac97.h>
#include <mach/audio.h>

static DEFINE_MUTEX(car_mutex);
static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
static volatile long gsr_bits;
static struct clk *ac97_clk;
static struct clk *ac97conf_clk;
static int reset_gpio;

extern void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio);

/*
 * Beware PXA27x bugs:
 *
 *   o Slot 12 read from modem space will hang controller.
 *   o CDONE, SDONE interrupt fails after any slot 12 IO.
 *
 * We therefore have an hybrid approach for waiting on SDONE (interrupt or
 * 1 jiffy timeout if interrupt never comes).
 */

int pxa2xx_ac97_read(int slot, unsigned short reg)
{
	int val = -ENODEV;
	volatile u32 *reg_addr;

	if (slot > 0)
		return -ENODEV;

	mutex_lock(&car_mutex);

	/* set up primary or secondary codec space */
	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
		reg_addr = slot ? &SMC_REG_BASE : &PMC_REG_BASE;
	else
		reg_addr = slot ? &SAC_REG_BASE : &PAC_REG_BASE;
	reg_addr += (reg >> 1);

	/* start read access across the ac97 link */
	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	val = (*reg_addr & 0xffff);
	if (reg == AC97_GPIO_STATUS)
		goto out;
	if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
	    !((GSR | gsr_bits) & GSR_SDONE)) {
		printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
				__func__, reg, GSR | gsr_bits);
		val = -ETIMEDOUT;
		goto out;
	}

	/* valid data now */
	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	val = (*reg_addr & 0xffff);
	/* but we've just started another cycle... */
	wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);

out:	mutex_unlock(&car_mutex);
	return val;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);

int pxa2xx_ac97_write(int slot, unsigned short reg, unsigned short val)
{
	volatile u32 *reg_addr;
	int ret = 0;

	mutex_lock(&car_mutex);

	/* set up primary or secondary codec space */
	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
		reg_addr = slot ? &SMC_REG_BASE : &PMC_REG_BASE;
	else
		reg_addr = slot ? &SAC_REG_BASE : &PAC_REG_BASE;
	reg_addr += (reg >> 1);

	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	*reg_addr = val;
	if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
	    !((GSR | gsr_bits) & GSR_CDONE)) {
		printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
				__func__, reg, GSR | gsr_bits);
		ret = -EIO;
	}

	mutex_unlock(&car_mutex);
	return ret;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);

#ifdef CONFIG_PXA25x
static inline void pxa_ac97_warm_pxa25x(void)
{
	gsr_bits = 0;

	GCR |= GCR_WARM_RST;
}

static inline void pxa_ac97_cold_pxa25x(void)
{
	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */

	gsr_bits = 0;

	GCR = GCR_COLD_RST;
}
#endif

#ifdef CONFIG_PXA27x
static inline void pxa_ac97_warm_pxa27x(void)
{
	gsr_bits = 0;

	/* warm reset broken on Bulverde, so manually keep AC97 reset high */
	pxa27x_configure_ac97reset(reset_gpio, true);
	udelay(10);
	GCR |= GCR_WARM_RST;
	pxa27x_configure_ac97reset(reset_gpio, false);
	udelay(500);
}

static inline void pxa_ac97_cold_pxa27x(void)
{
	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */

	gsr_bits = 0;

	/* PXA27x Developers Manual section 13.5.2.2.1 */
	clk_prepare_enable(ac97conf_clk);
	udelay(5);
	clk_disable_unprepare(ac97conf_clk);
	GCR = GCR_COLD_RST | GCR_WARM_RST;
}
#endif

#ifdef CONFIG_PXA3xx
static inline void pxa_ac97_warm_pxa3xx(void)
{
	gsr_bits = 0;

	/* Can't use interrupts */
	GCR |= GCR_WARM_RST;
}

static inline void pxa_ac97_cold_pxa3xx(void)
{
	/* Hold CLKBPB for 100us */
	GCR = 0;
	GCR = GCR_CLKBPB;
	udelay(100);
	GCR = 0;

	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */

	gsr_bits = 0;

	/* Can't use interrupts on PXA3xx */
	GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);

	GCR = GCR_WARM_RST | GCR_COLD_RST;
}
#endif

bool pxa2xx_ac97_try_warm_reset(void)
{
	unsigned long gsr;
	unsigned int timeout = 100;

#ifdef CONFIG_PXA25x
	if (cpu_is_pxa25x())
		pxa_ac97_warm_pxa25x();
	else
#endif
#ifdef CONFIG_PXA27x
	if (cpu_is_pxa27x())
		pxa_ac97_warm_pxa27x();
	else
#endif
#ifdef CONFIG_PXA3xx
	if (cpu_is_pxa3xx())
		pxa_ac97_warm_pxa3xx();
	else
#endif
		snd_BUG();

	while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
		mdelay(1);

	gsr = GSR | gsr_bits;
	if (!(gsr & (GSR_PCR | GSR_SCR))) {
		printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
				 __func__, gsr);

		return false;
	}

	return true;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);

bool pxa2xx_ac97_try_cold_reset(void)
{
	unsigned long gsr;
	unsigned int timeout = 1000;

#ifdef CONFIG_PXA25x
	if (cpu_is_pxa25x())
		pxa_ac97_cold_pxa25x();
	else
#endif
#ifdef CONFIG_PXA27x
	if (cpu_is_pxa27x())
		pxa_ac97_cold_pxa27x();
	else
#endif
#ifdef CONFIG_PXA3xx
	if (cpu_is_pxa3xx())
		pxa_ac97_cold_pxa3xx();
	else
#endif
		snd_BUG();

	while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
		mdelay(1);

	gsr = GSR | gsr_bits;
	if (!(gsr & (GSR_PCR | GSR_SCR))) {
		printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
				 __func__, gsr);

		return false;
	}

	return true;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);


void pxa2xx_ac97_finish_reset(void)
{
	GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
	GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);

static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
{
	long status;

	status = GSR;
	if (status) {
		GSR = status;
		gsr_bits |= status;
		wake_up(&gsr_wq);

		/* Although we don't use those we still need to clear them
		   since they tend to spuriously trigger when MMC is used
		   (hardware bug? go figure)... */
		if (cpu_is_pxa27x()) {
			MISR = MISR_EOC;
			PISR = PISR_EOC;
			MCSR = MCSR_EOC;
		}

		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

#ifdef CONFIG_PM
int pxa2xx_ac97_hw_suspend(void)
{
	GCR |= GCR_ACLINK_OFF;
	clk_disable_unprepare(ac97_clk);
	return 0;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);

int pxa2xx_ac97_hw_resume(void)
{
	clk_prepare_enable(ac97_clk);
	return 0;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
#endif

int pxa2xx_ac97_hw_probe(struct platform_device *dev)
{
	int ret;
	pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;

	if (pdata) {
		switch (pdata->reset_gpio) {
		case 95:
		case 113:
			reset_gpio = pdata->reset_gpio;
			break;
		case 0:
			reset_gpio = 113;
			break;
		case -1:
			break;
		default:
			dev_err(&dev->dev, "Invalid reset GPIO %d\n",
				pdata->reset_gpio);
		}
	} else {
		if (cpu_is_pxa27x())
			reset_gpio = 113;
	}

	if (cpu_is_pxa27x()) {
		/*
		 * This gpio is needed for a work-around to a bug in the ac97
		 * controller during warm reset.  The direction and level is set
		 * here so that it is an output driven high when switching from
		 * AC97_nRESET alt function to generic gpio.
		 */
		ret = gpio_request_one(reset_gpio, GPIOF_OUT_INIT_HIGH,
				       "pxa27x ac97 reset");
		if (ret < 0) {
			pr_err("%s: gpio_request_one() failed: %d\n",
			       __func__, ret);
			goto err_conf;
		}
		pxa27x_configure_ac97reset(reset_gpio, false);

		ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
		if (IS_ERR(ac97conf_clk)) {
			ret = PTR_ERR(ac97conf_clk);
			ac97conf_clk = NULL;
			goto err_conf;
		}
	}

	ac97_clk = clk_get(&dev->dev, "AC97CLK");
	if (IS_ERR(ac97_clk)) {
		ret = PTR_ERR(ac97_clk);
		ac97_clk = NULL;
		goto err_clk;
	}

	ret = clk_prepare_enable(ac97_clk);
	if (ret)
		goto err_clk2;

	ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
	if (ret < 0)
		goto err_irq;

	return 0;

err_irq:
	GCR |= GCR_ACLINK_OFF;
err_clk2:
	clk_put(ac97_clk);
	ac97_clk = NULL;
err_clk:
	if (ac97conf_clk) {
		clk_put(ac97conf_clk);
		ac97conf_clk = NULL;
	}
err_conf:
	return ret;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);

void pxa2xx_ac97_hw_remove(struct platform_device *dev)
{
	if (cpu_is_pxa27x())
		gpio_free(reset_gpio);
	GCR |= GCR_ACLINK_OFF;
	free_irq(IRQ_AC97, NULL);
	if (ac97conf_clk) {
		clk_put(ac97conf_clk);
		ac97conf_clk = NULL;
	}
	clk_disable_unprepare(ac97_clk);
	clk_put(ac97_clk);
	ac97_clk = NULL;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);

MODULE_AUTHOR("Nicolas Pitre");
MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
MODULE_LICENSE("GPL");
Commit	Line	Data
9c636342 DB	1	/*
	2	* Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
	3	* which contain:
	4	*
	5	* Author: Nicolas Pitre
	6	* Created: Dec 02, 2004
	7	* Copyright: MontaVista Software Inc.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/clk.h>
	18	#include <linux/delay.h>
da155d5b	19	#include <linux/module.h>
23019a73	20	#include <linux/io.h>
3b4bc7bc	21	#include <linux/gpio.h>
9c636342	22
9c636342 DB	23	#include <sound/pxa2xx-lib.h>
9c636342 DB	24
9482ee71	25	#include <mach/irqs.h>
1f017a99	26	#include <mach/regs-ac97.h>
9c636342 DB	27	#include <mach/audio.h>
	28
	29	static DEFINE_MUTEX(car_mutex);
	30	static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
	31	static volatile long gsr_bits;
	32	static struct clk *ac97_clk;
9c636342	33	static struct clk *ac97conf_clk;
26ade896	34	static int reset_gpio;
9c636342	35
053fe0f1	36	extern void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio);
fb1bf8cd	37
9c636342 DB	38	/*
	39	* Beware PXA27x bugs:
	40	*
	41	* o Slot 12 read from modem space will hang controller.
	42	* o CDONE, SDONE interrupt fails after any slot 12 IO.
	43	*
	44	* We therefore have an hybrid approach for waiting on SDONE (interrupt or
	45	* 1 jiffy timeout if interrupt never comes).
	46	*/
	47
6f8acad6	48	int pxa2xx_ac97_read(int slot, unsigned short reg)
9c636342	49	{
6f8acad6	50	int val = -ENODEV;
9c636342 DB	51	volatile u32 *reg_addr;
9c636342 DB	52
6f8acad6 RJ	53	if (slot > 0)
	54	return -ENODEV;
	55
9c636342 DB	56	mutex_lock(&car_mutex);
	57
	58	/* set up primary or secondary codec space */
8825e8e8	59	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
6f8acad6	60	reg_addr = slot ? &SMC_REG_BASE : &PMC_REG_BASE;
9c636342	61	else
6f8acad6	62	reg_addr = slot ? &SAC_REG_BASE : &PAC_REG_BASE;
9c636342 DB	63	reg_addr += (reg >> 1);
	64
	65	/* start read access across the ac97 link */
	66	GSR = GSR_CDONE \| GSR_SDONE;
	67	gsr_bits = 0;
6f8acad6	68	val = (*reg_addr & 0xffff);
9c636342 DB	69	if (reg == AC97_GPIO_STATUS)
	70	goto out;
	71	if (wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_SDONE, 1) <= 0 &&
	72	!((GSR \| gsr_bits) & GSR_SDONE)) {
	73	printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
	74	__func__, reg, GSR \| gsr_bits);
6f8acad6	75	val = -ETIMEDOUT;
9c636342 DB	76	goto out;
	77	}
	78
	79	/* valid data now */
	80	GSR = GSR_CDONE \| GSR_SDONE;
	81	gsr_bits = 0;
6f8acad6	82	val = (*reg_addr & 0xffff);
9c636342 DB	83	/* but we've just started another cycle... */
	84	wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_SDONE, 1);
	85
	86	out: mutex_unlock(&car_mutex);
	87	return val;
	88	}
	89	EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);
	90
6f8acad6	91	int pxa2xx_ac97_write(int slot, unsigned short reg, unsigned short val)
9c636342 DB	92	{
9c636342 DB	93	volatile u32 *reg_addr;
6f8acad6	94	int ret = 0;
9c636342 DB	95
	96	mutex_lock(&car_mutex);
	97
	98	/* set up primary or secondary codec space */
8825e8e8	99	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
6f8acad6	100	reg_addr = slot ? &SMC_REG_BASE : &PMC_REG_BASE;
9c636342	101	else
6f8acad6	102	reg_addr = slot ? &SAC_REG_BASE : &PAC_REG_BASE;
9c636342 DB	103	reg_addr += (reg >> 1);
	104
	105	GSR = GSR_CDONE \| GSR_SDONE;
	106	gsr_bits = 0;
	107	*reg_addr = val;
	108	if (wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_CDONE, 1) <= 0 &&
6f8acad6	109	!((GSR \| gsr_bits) & GSR_CDONE)) {
9c636342 DB	110	printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
9c636342 DB	111	__func__, reg, GSR \| gsr_bits);
6f8acad6 RJ	112	ret = -EIO;
6f8acad6 RJ	113	}
9c636342 DB	114
9c636342 DB	115	mutex_unlock(&car_mutex);
6f8acad6	116	return ret;
9c636342 DB	117	}
	118	EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);
	119
9d1cf39b DB	120	#ifdef CONFIG_PXA25x
9d1cf39b DB	121	static inline void pxa_ac97_warm_pxa25x(void)
9c636342	122	{
9c636342 DB	123	gsr_bits = 0;
9c636342 DB	124
beb02cdd	125	GCR \|= GCR_WARM_RST;
9d1cf39b DB	126	}
	127
	128	static inline void pxa_ac97_cold_pxa25x(void)
	129	{
	130	GCR &= GCR_COLD_RST; /* clear everything but nCRST */
	131	GCR &= ~GCR_COLD_RST; /* then assert nCRST */
	132
	133	gsr_bits = 0;
	134
	135	GCR = GCR_COLD_RST;
9d1cf39b DB	136	}
	137	#endif
	138
9c636342	139	#ifdef CONFIG_PXA27x
9d1cf39b DB	140	static inline void pxa_ac97_warm_pxa27x(void)
	141	{
	142	gsr_bits = 0;
	143
fb1bf8cd	144	/* warm reset broken on Bulverde, so manually keep AC97 reset high */
053fe0f1	145	pxa27x_configure_ac97reset(reset_gpio, true);
9c636342 DB	146	udelay(10);
9c636342 DB	147	GCR \|= GCR_WARM_RST;
053fe0f1	148	pxa27x_configure_ac97reset(reset_gpio, false);
9c636342	149	udelay(500);
9d1cf39b DB	150	}
	151
	152	static inline void pxa_ac97_cold_pxa27x(void)
	153	{
	154	GCR &= GCR_COLD_RST; /* clear everything but nCRST */
	155	GCR &= ~GCR_COLD_RST; /* then assert nCRST */
	156
	157	gsr_bits = 0;
	158
	159	/* PXA27x Developers Manual section 13.5.2.2.1 */
4091d342	160	clk_prepare_enable(ac97conf_clk);
9d1cf39b	161	udelay(5);
4091d342	162	clk_disable_unprepare(ac97conf_clk);
41b645c8	163	GCR = GCR_COLD_RST \| GCR_WARM_RST;
9d1cf39b	164	}
9c636342 DB	165	#endif
9c636342 DB	166
9d1cf39b DB	167	#ifdef CONFIG_PXA3xx
	168	static inline void pxa_ac97_warm_pxa3xx(void)
	169	{
9d1cf39b	170	gsr_bits = 0;
9c636342	171
9d1cf39b DB	172	/* Can't use interrupts */
9d1cf39b DB	173	GCR \|= GCR_WARM_RST;
9c636342	174	}
9c636342	175
9d1cf39b	176	static inline void pxa_ac97_cold_pxa3xx(void)
9c636342	177	{
9c636342 DB	178	/* Hold CLKBPB for 100us */
	179	GCR = 0;
	180	GCR = GCR_CLKBPB;
	181	udelay(100);
	182	GCR = 0;
9c636342 DB	183
	184	GCR &= GCR_COLD_RST; /* clear everything but nCRST */
	185	GCR &= ~GCR_COLD_RST; /* then assert nCRST */
	186
	187	gsr_bits = 0;
9d1cf39b	188
9c636342 DB	189	/* Can't use interrupts on PXA3xx */
	190	GCR &= ~(GCR_PRIRDY_IEN\|GCR_SECRDY_IEN);
	191
	192	GCR = GCR_WARM_RST \| GCR_COLD_RST;
9d1cf39b DB	193	}
	194	#endif
	195
6f8acad6	196	bool pxa2xx_ac97_try_warm_reset(void)
9d1cf39b	197	{
057de50c	198	unsigned long gsr;
beb02cdd	199	unsigned int timeout = 100;
057de50c	200
9d1cf39b	201	#ifdef CONFIG_PXA25x
8825e8e8	202	if (cpu_is_pxa25x())
9d1cf39b DB	203	pxa_ac97_warm_pxa25x();
9d1cf39b DB	204	else
9c636342	205	#endif
9d1cf39b DB	206	#ifdef CONFIG_PXA27x
	207	if (cpu_is_pxa27x())
	208	pxa_ac97_warm_pxa27x();
	209	else
	210	#endif
	211	#ifdef CONFIG_PXA3xx
	212	if (cpu_is_pxa3xx())
	213	pxa_ac97_warm_pxa3xx();
	214	else
	215	#endif
88ec7ae8	216	snd_BUG();
beb02cdd DES	217
	218	while (!((GSR \| gsr_bits) & (GSR_PCR \| GSR_SCR)) && timeout--)
	219	mdelay(1);
	220
057de50c LF	221	gsr = GSR \| gsr_bits;
057de50c LF	222	if (!(gsr & (GSR_PCR \| GSR_SCR))) {
9d1cf39b	223	printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
057de50c	224	__func__, gsr);
9d1cf39b DB	225
	226	return false;
	227	}
	228
	229	return true;
	230	}
	231	EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);
	232
6f8acad6	233	bool pxa2xx_ac97_try_cold_reset(void)
9d1cf39b	234	{
057de50c	235	unsigned long gsr;
beb02cdd	236	unsigned int timeout = 1000;
057de50c	237
9d1cf39b	238	#ifdef CONFIG_PXA25x
8825e8e8	239	if (cpu_is_pxa25x())
9d1cf39b DB	240	pxa_ac97_cold_pxa25x();
	241	else
	242	#endif
	243	#ifdef CONFIG_PXA27x
	244	if (cpu_is_pxa27x())
	245	pxa_ac97_cold_pxa27x();
	246	else
	247	#endif
	248	#ifdef CONFIG_PXA3xx
	249	if (cpu_is_pxa3xx())
	250	pxa_ac97_cold_pxa3xx();
	251	else
	252	#endif
88ec7ae8	253	snd_BUG();
9c636342	254
beb02cdd DES	255	while (!((GSR \| gsr_bits) & (GSR_PCR \| GSR_SCR)) && timeout--)
	256	mdelay(1);
	257
057de50c LF	258	gsr = GSR \| gsr_bits;
057de50c LF	259	if (!(gsr & (GSR_PCR \| GSR_SCR))) {
9c636342	260	printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
057de50c	261	__func__, gsr);
9c636342 DB	262
	263	return false;
	264	}
	265
	266	return true;
	267	}
	268	EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);
	269
	270
6f8acad6	271	void pxa2xx_ac97_finish_reset(void)
9c636342 DB	272	{
	273	GCR &= ~(GCR_PRIRDY_IEN\|GCR_SECRDY_IEN);
	274	GCR \|= GCR_SDONE_IE\|GCR_CDONE_IE;
	275	}
	276	EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);
	277
	278	static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
	279	{
	280	long status;
	281
	282	status = GSR;
	283	if (status) {
	284	GSR = status;
	285	gsr_bits \|= status;
	286	wake_up(&gsr_wq);
	287
9c636342 DB	288	/* Although we don't use those we still need to clear them
	289	since they tend to spuriously trigger when MMC is used
	290	(hardware bug? go figure)... */
9d1cf39b DB	291	if (cpu_is_pxa27x()) {
	292	MISR = MISR_EOC;
	293	PISR = PISR_EOC;
	294	MCSR = MCSR_EOC;
	295	}
9c636342 DB	296
	297	return IRQ_HANDLED;
	298	}
	299
	300	return IRQ_NONE;
	301	}
	302
	303	#ifdef CONFIG_PM
	304	int pxa2xx_ac97_hw_suspend(void)
	305	{
	306	GCR \|= GCR_ACLINK_OFF;
4091d342	307	clk_disable_unprepare(ac97_clk);
9c636342 DB	308	return 0;
	309	}
	310	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);
	311
	312	int pxa2xx_ac97_hw_resume(void)
	313	{
4091d342	314	clk_prepare_enable(ac97_clk);
9c636342 DB	315	return 0;
	316	}
	317	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
	318	#endif
	319
e21596bb	320	int pxa2xx_ac97_hw_probe(struct platform_device *dev)
9c636342 DB	321	{
9c636342 DB	322	int ret;
eae17754	323	pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;
26ade896 RJ	324
	325	if (pdata) {
	326	switch (pdata->reset_gpio) {
	327	case 95:
	328	case 113:
	329	reset_gpio = pdata->reset_gpio;
	330	break;
	331	case 0:
	332	reset_gpio = 113;
	333	break;
	334	case -1:
	335	break;
	336	default:
1f218695	337	dev_err(&dev->dev, "Invalid reset GPIO %d\n",
26ade896 RJ	338	pdata->reset_gpio);
	339	}
	340	} else {
	341	if (cpu_is_pxa27x())
	342	reset_gpio = 113;
	343	}
9c636342	344
9d1cf39b	345	if (cpu_is_pxa27x()) {
3b4bc7bc MD	346	/*
	347	* This gpio is needed for a work-around to a bug in the ac97
	348	* controller during warm reset. The direction and level is set
	349	* here so that it is an output driven high when switching from
	350	* AC97_nRESET alt function to generic gpio.
	351	*/
	352	ret = gpio_request_one(reset_gpio, GPIOF_OUT_INIT_HIGH,
	353	"pxa27x ac97 reset");
	354	if (ret < 0) {
	355	pr_err("%s: gpio_request_one() failed: %d\n",
	356	__func__, ret);
	357	goto err_conf;
	358	}
053fe0f1	359	pxa27x_configure_ac97reset(reset_gpio, false);
3b4bc7bc	360
9d1cf39b DB	361	ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
	362	if (IS_ERR(ac97conf_clk)) {
	363	ret = PTR_ERR(ac97conf_clk);
	364	ac97conf_clk = NULL;
79612336	365	goto err_conf;
9d1cf39b	366	}
9c636342	367	}
9c636342 DB	368
	369	ac97_clk = clk_get(&dev->dev, "AC97CLK");
	370	if (IS_ERR(ac97_clk)) {
	371	ret = PTR_ERR(ac97_clk);
	372	ac97_clk = NULL;
79612336	373	goto err_clk;
9c636342 DB	374	}
9c636342 DB	375
4091d342	376	ret = clk_prepare_enable(ac97_clk);
79612336 DB	377	if (ret)
	378	goto err_clk2;
	379
88e24c3a	380	ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
79612336 DB	381	if (ret < 0)
	382	goto err_irq;
	383
	384	return 0;
9c636342 DB	385
	386	err_irq:
	387	GCR \|= GCR_ACLINK_OFF;
79612336 DB	388	err_clk2:
	389	clk_put(ac97_clk);
	390	ac97_clk = NULL;
	391	err_clk:
9c636342 DB	392	if (ac97conf_clk) {
	393	clk_put(ac97conf_clk);
	394	ac97conf_clk = NULL;
	395	}
79612336	396	err_conf:
9c636342 DB	397	return ret;
	398	}
	399	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);
	400
	401	void pxa2xx_ac97_hw_remove(struct platform_device *dev)
	402	{
3b4bc7bc MD	403	if (cpu_is_pxa27x())
3b4bc7bc MD	404	gpio_free(reset_gpio);
9c636342 DB	405	GCR \|= GCR_ACLINK_OFF;
9c636342 DB	406	free_irq(IRQ_AC97, NULL);
9d1cf39b DB	407	if (ac97conf_clk) {
	408	clk_put(ac97conf_clk);
	409	ac97conf_clk = NULL;
	410	}
4091d342	411	clk_disable_unprepare(ac97_clk);
9c636342 DB	412	clk_put(ac97_clk);
	413	ac97_clk = NULL;
	414	}
	415	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);
	416
	417	MODULE_AUTHOR("Nicolas Pitre");
	418	MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
	419	MODULE_LICENSE("GPL");
	420