[linux-2.6-block.git] / sound / arm / pxa2xx-ac97-lib.c

/*
 * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
 * which contain:
 *
 * Author:	Nicolas Pitre
 * Created:	Dec 02, 2004
 * Copyright:	MontaVista Software Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/gpio.h>

#include <sound/ac97_codec.h>
#include <sound/pxa2xx-lib.h>

#include <mach/irqs.h>
#include <mach/regs-ac97.h>
#include <mach/audio.h>

static DEFINE_MUTEX(car_mutex);
static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
static volatile long gsr_bits;
static struct clk *ac97_clk;
static struct clk *ac97conf_clk;
static int reset_gpio;

extern void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio);

/*
 * Beware PXA27x bugs:
 *
 *   o Slot 12 read from modem space will hang controller.
 *   o CDONE, SDONE interrupt fails after any slot 12 IO.
 *
 * We therefore have an hybrid approach for waiting on SDONE (interrupt or
 * 1 jiffy timeout if interrupt never comes).
 */

unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
{
	unsigned short val = -1;
	volatile u32 *reg_addr;

	mutex_lock(&car_mutex);

	/* set up primary or secondary codec space */
	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
		reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
	else
		reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
	reg_addr += (reg >> 1);

	/* start read access across the ac97 link */
	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	val = *reg_addr;
	if (reg == AC97_GPIO_STATUS)
		goto out;
	if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
	    !((GSR | gsr_bits) & GSR_SDONE)) {
		printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
				__func__, reg, GSR | gsr_bits);
		val = -1;
		goto out;
	}

	/* valid data now */
	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	val = *reg_addr;
	/* but we've just started another cycle... */
	wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);

out:	mutex_unlock(&car_mutex);
	return val;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);

void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
			unsigned short val)
{
	volatile u32 *reg_addr;

	mutex_lock(&car_mutex);

	/* set up primary or secondary codec space */
	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
		reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
	else
		reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
	reg_addr += (reg >> 1);

	GSR = GSR_CDONE | GSR_SDONE;
	gsr_bits = 0;
	*reg_addr = val;
	if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
	    !((GSR | gsr_bits) & GSR_CDONE))
		printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
				__func__, reg, GSR | gsr_bits);

	mutex_unlock(&car_mutex);
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);

#ifdef CONFIG_PXA25x
static inline void pxa_ac97_warm_pxa25x(void)
{
	gsr_bits = 0;

	GCR |= GCR_WARM_RST;
}

static inline void pxa_ac97_cold_pxa25x(void)
{
	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */

	gsr_bits = 0;

	GCR = GCR_COLD_RST;
}
#endif

#ifdef CONFIG_PXA27x
static inline void pxa_ac97_warm_pxa27x(void)
{
	gsr_bits = 0;

	/* warm reset broken on Bulverde, so manually keep AC97 reset high */
	pxa27x_configure_ac97reset(reset_gpio, true);
	udelay(10);
	GCR |= GCR_WARM_RST;
	pxa27x_configure_ac97reset(reset_gpio, false);
	udelay(500);
}

static inline void pxa_ac97_cold_pxa27x(void)
{
	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */

	gsr_bits = 0;

	/* PXA27x Developers Manual section 13.5.2.2.1 */
	clk_prepare_enable(ac97conf_clk);
	udelay(5);
	clk_disable_unprepare(ac97conf_clk);
	GCR = GCR_COLD_RST | GCR_WARM_RST;
}
#endif

#ifdef CONFIG_PXA3xx
static inline void pxa_ac97_warm_pxa3xx(void)
{
	gsr_bits = 0;

	/* Can't use interrupts */
	GCR |= GCR_WARM_RST;
}

static inline void pxa_ac97_cold_pxa3xx(void)
{
	/* Hold CLKBPB for 100us */
	GCR = 0;
	GCR = GCR_CLKBPB;
	udelay(100);
	GCR = 0;

	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */

	gsr_bits = 0;

	/* Can't use interrupts on PXA3xx */
	GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);

	GCR = GCR_WARM_RST | GCR_COLD_RST;
}
#endif

bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97)
{
	unsigned long gsr;
	unsigned int timeout = 100;

#ifdef CONFIG_PXA25x
	if (cpu_is_pxa25x())
		pxa_ac97_warm_pxa25x();
	else
#endif
#ifdef CONFIG_PXA27x
	if (cpu_is_pxa27x())
		pxa_ac97_warm_pxa27x();
	else
#endif
#ifdef CONFIG_PXA3xx
	if (cpu_is_pxa3xx())
		pxa_ac97_warm_pxa3xx();
	else
#endif
		snd_BUG();

	while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
		mdelay(1);

	gsr = GSR | gsr_bits;
	if (!(gsr & (GSR_PCR | GSR_SCR))) {
		printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
				 __func__, gsr);

		return false;
	}

	return true;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);

bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97)
{
	unsigned long gsr;
	unsigned int timeout = 1000;

#ifdef CONFIG_PXA25x
	if (cpu_is_pxa25x())
		pxa_ac97_cold_pxa25x();
	else
#endif
#ifdef CONFIG_PXA27x
	if (cpu_is_pxa27x())
		pxa_ac97_cold_pxa27x();
	else
#endif
#ifdef CONFIG_PXA3xx
	if (cpu_is_pxa3xx())
		pxa_ac97_cold_pxa3xx();
	else
#endif
		snd_BUG();

	while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
		mdelay(1);

	gsr = GSR | gsr_bits;
	if (!(gsr & (GSR_PCR | GSR_SCR))) {
		printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
				 __func__, gsr);

		return false;
	}

	return true;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);


void pxa2xx_ac97_finish_reset(struct snd_ac97 *ac97)
{
	GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
	GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);

static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
{
	long status;

	status = GSR;
	if (status) {
		GSR = status;
		gsr_bits |= status;
		wake_up(&gsr_wq);

		/* Although we don't use those we still need to clear them
		   since they tend to spuriously trigger when MMC is used
		   (hardware bug? go figure)... */
		if (cpu_is_pxa27x()) {
			MISR = MISR_EOC;
			PISR = PISR_EOC;
			MCSR = MCSR_EOC;
		}

		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

#ifdef CONFIG_PM
int pxa2xx_ac97_hw_suspend(void)
{
	GCR |= GCR_ACLINK_OFF;
	clk_disable_unprepare(ac97_clk);
	return 0;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);

int pxa2xx_ac97_hw_resume(void)
{
	clk_prepare_enable(ac97_clk);
	return 0;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
#endif

int pxa2xx_ac97_hw_probe(struct platform_device *dev)
{
	int ret;
	pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;

	if (pdata) {
		switch (pdata->reset_gpio) {
		case 95:
		case 113:
			reset_gpio = pdata->reset_gpio;
			break;
		case 0:
			reset_gpio = 113;
			break;
		case -1:
			break;
		default:
			dev_err(&dev->dev, "Invalid reset GPIO %d\n",
				pdata->reset_gpio);
		}
	} else {
		if (cpu_is_pxa27x())
			reset_gpio = 113;
	}

	if (cpu_is_pxa27x()) {
		/*
		 * This gpio is needed for a work-around to a bug in the ac97
		 * controller during warm reset.  The direction and level is set
		 * here so that it is an output driven high when switching from
		 * AC97_nRESET alt function to generic gpio.
		 */
		ret = gpio_request_one(reset_gpio, GPIOF_OUT_INIT_HIGH,
				       "pxa27x ac97 reset");
		if (ret < 0) {
			pr_err("%s: gpio_request_one() failed: %d\n",
			       __func__, ret);
			goto err_conf;
		}
		pxa27x_configure_ac97reset(reset_gpio, false);

		ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
		if (IS_ERR(ac97conf_clk)) {
			ret = PTR_ERR(ac97conf_clk);
			ac97conf_clk = NULL;
			goto err_conf;
		}
	}

	ac97_clk = clk_get(&dev->dev, "AC97CLK");
	if (IS_ERR(ac97_clk)) {
		ret = PTR_ERR(ac97_clk);
		ac97_clk = NULL;
		goto err_clk;
	}

	ret = clk_prepare_enable(ac97_clk);
	if (ret)
		goto err_clk2;

	ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
	if (ret < 0)
		goto err_irq;

	return 0;

err_irq:
	GCR |= GCR_ACLINK_OFF;
err_clk2:
	clk_put(ac97_clk);
	ac97_clk = NULL;
err_clk:
	if (ac97conf_clk) {
		clk_put(ac97conf_clk);
		ac97conf_clk = NULL;
	}
err_conf:
	return ret;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);

void pxa2xx_ac97_hw_remove(struct platform_device *dev)
{
	if (cpu_is_pxa27x())
		gpio_free(reset_gpio);
	GCR |= GCR_ACLINK_OFF;
	free_irq(IRQ_AC97, NULL);
	if (ac97conf_clk) {
		clk_put(ac97conf_clk);
		ac97conf_clk = NULL;
	}
	clk_disable_unprepare(ac97_clk);
	clk_put(ac97_clk);
	ac97_clk = NULL;
}
EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);

MODULE_AUTHOR("Nicolas Pitre");
MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
MODULE_LICENSE("GPL");
Commit	Line	Data
9c636342 DB	1	/*
	2	* Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
	3	* which contain:
	4	*
	5	* Author: Nicolas Pitre
	6	* Created: Dec 02, 2004
	7	* Copyright: MontaVista Software Inc.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/clk.h>
	18	#include <linux/delay.h>
da155d5b	19	#include <linux/module.h>
23019a73	20	#include <linux/io.h>
3b4bc7bc	21	#include <linux/gpio.h>
9c636342 DB	22
	23	#include <sound/ac97_codec.h>
	24	#include <sound/pxa2xx-lib.h>
	25
9482ee71	26	#include <mach/irqs.h>
1f017a99	27	#include <mach/regs-ac97.h>
9c636342 DB	28	#include <mach/audio.h>
	29
	30	static DEFINE_MUTEX(car_mutex);
	31	static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
	32	static volatile long gsr_bits;
	33	static struct clk *ac97_clk;
9c636342	34	static struct clk *ac97conf_clk;
26ade896	35	static int reset_gpio;
9c636342	36
053fe0f1	37	extern void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio);
fb1bf8cd	38
9c636342 DB	39	/*
	40	* Beware PXA27x bugs:
	41	*
	42	* o Slot 12 read from modem space will hang controller.
	43	* o CDONE, SDONE interrupt fails after any slot 12 IO.
	44	*
	45	* We therefore have an hybrid approach for waiting on SDONE (interrupt or
	46	* 1 jiffy timeout if interrupt never comes).
	47	*/
	48
	49	unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
	50	{
	51	unsigned short val = -1;
	52	volatile u32 *reg_addr;
	53
	54	mutex_lock(&car_mutex);
	55
	56	/* set up primary or secondary codec space */
8825e8e8	57	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
9c636342 DB	58	reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
	59	else
	60	reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
9c636342 DB	61	reg_addr += (reg >> 1);
	62
	63	/* start read access across the ac97 link */
	64	GSR = GSR_CDONE \| GSR_SDONE;
	65	gsr_bits = 0;
	66	val = *reg_addr;
	67	if (reg == AC97_GPIO_STATUS)
	68	goto out;
	69	if (wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_SDONE, 1) <= 0 &&
	70	!((GSR \| gsr_bits) & GSR_SDONE)) {
	71	printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
	72	__func__, reg, GSR \| gsr_bits);
	73	val = -1;
	74	goto out;
	75	}
	76
	77	/* valid data now */
	78	GSR = GSR_CDONE \| GSR_SDONE;
	79	gsr_bits = 0;
	80	val = *reg_addr;
	81	/* but we've just started another cycle... */
	82	wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_SDONE, 1);
	83
	84	out: mutex_unlock(&car_mutex);
	85	return val;
	86	}
	87	EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);
	88
	89	void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
	90	unsigned short val)
	91	{
	92	volatile u32 *reg_addr;
	93
	94	mutex_lock(&car_mutex);
	95
	96	/* set up primary or secondary codec space */
8825e8e8	97	if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
9c636342 DB	98	reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
	99	else
	100	reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
9c636342 DB	101	reg_addr += (reg >> 1);
	102
	103	GSR = GSR_CDONE \| GSR_SDONE;
	104	gsr_bits = 0;
	105	*reg_addr = val;
	106	if (wait_event_timeout(gsr_wq, (GSR \| gsr_bits) & GSR_CDONE, 1) <= 0 &&
	107	!((GSR \| gsr_bits) & GSR_CDONE))
	108	printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
	109	__func__, reg, GSR \| gsr_bits);
	110
	111	mutex_unlock(&car_mutex);
	112	}
	113	EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);
	114
9d1cf39b DB	115	#ifdef CONFIG_PXA25x
9d1cf39b DB	116	static inline void pxa_ac97_warm_pxa25x(void)
9c636342	117	{
9c636342 DB	118	gsr_bits = 0;
9c636342 DB	119
beb02cdd	120	GCR \|= GCR_WARM_RST;
9d1cf39b DB	121	}
	122
	123	static inline void pxa_ac97_cold_pxa25x(void)
	124	{
	125	GCR &= GCR_COLD_RST; /* clear everything but nCRST */
	126	GCR &= ~GCR_COLD_RST; /* then assert nCRST */
	127
	128	gsr_bits = 0;
	129
	130	GCR = GCR_COLD_RST;
9d1cf39b DB	131	}
	132	#endif
	133
9c636342	134	#ifdef CONFIG_PXA27x
9d1cf39b DB	135	static inline void pxa_ac97_warm_pxa27x(void)
	136	{
	137	gsr_bits = 0;
	138
fb1bf8cd	139	/* warm reset broken on Bulverde, so manually keep AC97 reset high */
053fe0f1	140	pxa27x_configure_ac97reset(reset_gpio, true);
9c636342 DB	141	udelay(10);
9c636342 DB	142	GCR \|= GCR_WARM_RST;
053fe0f1	143	pxa27x_configure_ac97reset(reset_gpio, false);
9c636342	144	udelay(500);
9d1cf39b DB	145	}
	146
	147	static inline void pxa_ac97_cold_pxa27x(void)
	148	{
	149	GCR &= GCR_COLD_RST; /* clear everything but nCRST */
	150	GCR &= ~GCR_COLD_RST; /* then assert nCRST */
	151
	152	gsr_bits = 0;
	153
	154	/* PXA27x Developers Manual section 13.5.2.2.1 */
4091d342	155	clk_prepare_enable(ac97conf_clk);
9d1cf39b	156	udelay(5);
4091d342	157	clk_disable_unprepare(ac97conf_clk);
41b645c8	158	GCR = GCR_COLD_RST \| GCR_WARM_RST;
9d1cf39b	159	}
9c636342 DB	160	#endif
9c636342 DB	161
9d1cf39b DB	162	#ifdef CONFIG_PXA3xx
	163	static inline void pxa_ac97_warm_pxa3xx(void)
	164	{
9d1cf39b	165	gsr_bits = 0;
9c636342	166
9d1cf39b DB	167	/* Can't use interrupts */
9d1cf39b DB	168	GCR \|= GCR_WARM_RST;
9c636342	169	}
9c636342	170
9d1cf39b	171	static inline void pxa_ac97_cold_pxa3xx(void)
9c636342	172	{
9c636342 DB	173	/* Hold CLKBPB for 100us */
	174	GCR = 0;
	175	GCR = GCR_CLKBPB;
	176	udelay(100);
	177	GCR = 0;
9c636342 DB	178
	179	GCR &= GCR_COLD_RST; /* clear everything but nCRST */
	180	GCR &= ~GCR_COLD_RST; /* then assert nCRST */
	181
	182	gsr_bits = 0;
9d1cf39b	183
9c636342 DB	184	/* Can't use interrupts on PXA3xx */
	185	GCR &= ~(GCR_PRIRDY_IEN\|GCR_SECRDY_IEN);
	186
	187	GCR = GCR_WARM_RST \| GCR_COLD_RST;
9d1cf39b DB	188	}
	189	#endif
	190
	191	bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97)
	192	{
057de50c	193	unsigned long gsr;
beb02cdd	194	unsigned int timeout = 100;
057de50c	195
9d1cf39b	196	#ifdef CONFIG_PXA25x
8825e8e8	197	if (cpu_is_pxa25x())
9d1cf39b DB	198	pxa_ac97_warm_pxa25x();
9d1cf39b DB	199	else
9c636342	200	#endif
9d1cf39b DB	201	#ifdef CONFIG_PXA27x
	202	if (cpu_is_pxa27x())
	203	pxa_ac97_warm_pxa27x();
	204	else
	205	#endif
	206	#ifdef CONFIG_PXA3xx
	207	if (cpu_is_pxa3xx())
	208	pxa_ac97_warm_pxa3xx();
	209	else
	210	#endif
88ec7ae8	211	snd_BUG();
beb02cdd DES	212
	213	while (!((GSR \| gsr_bits) & (GSR_PCR \| GSR_SCR)) && timeout--)
	214	mdelay(1);
	215
057de50c LF	216	gsr = GSR \| gsr_bits;
057de50c LF	217	if (!(gsr & (GSR_PCR \| GSR_SCR))) {
9d1cf39b	218	printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
057de50c	219	__func__, gsr);
9d1cf39b DB	220
	221	return false;
	222	}
	223
	224	return true;
	225	}
	226	EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);
	227
	228	bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97)
	229	{
057de50c	230	unsigned long gsr;
beb02cdd	231	unsigned int timeout = 1000;
057de50c	232
9d1cf39b	233	#ifdef CONFIG_PXA25x
8825e8e8	234	if (cpu_is_pxa25x())
9d1cf39b DB	235	pxa_ac97_cold_pxa25x();
	236	else
	237	#endif
	238	#ifdef CONFIG_PXA27x
	239	if (cpu_is_pxa27x())
	240	pxa_ac97_cold_pxa27x();
	241	else
	242	#endif
	243	#ifdef CONFIG_PXA3xx
	244	if (cpu_is_pxa3xx())
	245	pxa_ac97_cold_pxa3xx();
	246	else
	247	#endif
88ec7ae8	248	snd_BUG();
9c636342	249
beb02cdd DES	250	while (!((GSR \| gsr_bits) & (GSR_PCR \| GSR_SCR)) && timeout--)
	251	mdelay(1);
	252
057de50c LF	253	gsr = GSR \| gsr_bits;
057de50c LF	254	if (!(gsr & (GSR_PCR \| GSR_SCR))) {
9c636342	255	printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
057de50c	256	__func__, gsr);
9c636342 DB	257
	258	return false;
	259	}
	260
	261	return true;
	262	}
	263	EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);
	264
	265
	266	void pxa2xx_ac97_finish_reset(struct snd_ac97 *ac97)
	267	{
	268	GCR &= ~(GCR_PRIRDY_IEN\|GCR_SECRDY_IEN);
	269	GCR \|= GCR_SDONE_IE\|GCR_CDONE_IE;
	270	}
	271	EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);
	272
	273	static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
	274	{
	275	long status;
	276
	277	status = GSR;
	278	if (status) {
	279	GSR = status;
	280	gsr_bits \|= status;
	281	wake_up(&gsr_wq);
	282
9c636342 DB	283	/* Although we don't use those we still need to clear them
	284	since they tend to spuriously trigger when MMC is used
	285	(hardware bug? go figure)... */
9d1cf39b DB	286	if (cpu_is_pxa27x()) {
	287	MISR = MISR_EOC;
	288	PISR = PISR_EOC;
	289	MCSR = MCSR_EOC;
	290	}
9c636342 DB	291
	292	return IRQ_HANDLED;
	293	}
	294
	295	return IRQ_NONE;
	296	}
	297
	298	#ifdef CONFIG_PM
	299	int pxa2xx_ac97_hw_suspend(void)
	300	{
	301	GCR \|= GCR_ACLINK_OFF;
4091d342	302	clk_disable_unprepare(ac97_clk);
9c636342 DB	303	return 0;
	304	}
	305	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);
	306
	307	int pxa2xx_ac97_hw_resume(void)
	308	{
4091d342	309	clk_prepare_enable(ac97_clk);
9c636342 DB	310	return 0;
	311	}
	312	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
	313	#endif
	314
e21596bb	315	int pxa2xx_ac97_hw_probe(struct platform_device *dev)
9c636342 DB	316	{
9c636342 DB	317	int ret;
eae17754	318	pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;
26ade896 RJ	319
	320	if (pdata) {
	321	switch (pdata->reset_gpio) {
	322	case 95:
	323	case 113:
	324	reset_gpio = pdata->reset_gpio;
	325	break;
	326	case 0:
	327	reset_gpio = 113;
	328	break;
	329	case -1:
	330	break;
	331	default:
1f218695	332	dev_err(&dev->dev, "Invalid reset GPIO %d\n",
26ade896 RJ	333	pdata->reset_gpio);
	334	}
	335	} else {
	336	if (cpu_is_pxa27x())
	337	reset_gpio = 113;
	338	}
9c636342	339
9d1cf39b	340	if (cpu_is_pxa27x()) {
3b4bc7bc MD	341	/*
	342	* This gpio is needed for a work-around to a bug in the ac97
	343	* controller during warm reset. The direction and level is set
	344	* here so that it is an output driven high when switching from
	345	* AC97_nRESET alt function to generic gpio.
	346	*/
	347	ret = gpio_request_one(reset_gpio, GPIOF_OUT_INIT_HIGH,
	348	"pxa27x ac97 reset");
	349	if (ret < 0) {
	350	pr_err("%s: gpio_request_one() failed: %d\n",
	351	__func__, ret);
	352	goto err_conf;
	353	}
053fe0f1	354	pxa27x_configure_ac97reset(reset_gpio, false);
3b4bc7bc	355
9d1cf39b DB	356	ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
	357	if (IS_ERR(ac97conf_clk)) {
	358	ret = PTR_ERR(ac97conf_clk);
	359	ac97conf_clk = NULL;
79612336	360	goto err_conf;
9d1cf39b	361	}
9c636342	362	}
9c636342 DB	363
	364	ac97_clk = clk_get(&dev->dev, "AC97CLK");
	365	if (IS_ERR(ac97_clk)) {
	366	ret = PTR_ERR(ac97_clk);
	367	ac97_clk = NULL;
79612336	368	goto err_clk;
9c636342 DB	369	}
9c636342 DB	370
4091d342	371	ret = clk_prepare_enable(ac97_clk);
79612336 DB	372	if (ret)
	373	goto err_clk2;
	374
88e24c3a	375	ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
79612336 DB	376	if (ret < 0)
	377	goto err_irq;
	378
	379	return 0;
9c636342 DB	380
	381	err_irq:
	382	GCR \|= GCR_ACLINK_OFF;
79612336 DB	383	err_clk2:
	384	clk_put(ac97_clk);
	385	ac97_clk = NULL;
	386	err_clk:
9c636342 DB	387	if (ac97conf_clk) {
	388	clk_put(ac97conf_clk);
	389	ac97conf_clk = NULL;
	390	}
79612336	391	err_conf:
9c636342 DB	392	return ret;
	393	}
	394	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);
	395
	396	void pxa2xx_ac97_hw_remove(struct platform_device *dev)
	397	{
3b4bc7bc MD	398	if (cpu_is_pxa27x())
3b4bc7bc MD	399	gpio_free(reset_gpio);
9c636342 DB	400	GCR \|= GCR_ACLINK_OFF;
9c636342 DB	401	free_irq(IRQ_AC97, NULL);
9d1cf39b DB	402	if (ac97conf_clk) {
	403	clk_put(ac97conf_clk);
	404	ac97conf_clk = NULL;
	405	}
4091d342	406	clk_disable_unprepare(ac97_clk);
9c636342 DB	407	clk_put(ac97_clk);
	408	ac97_clk = NULL;
	409	}
	410	EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);
	411
	412	MODULE_AUTHOR("Nicolas Pitre");
	413	MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
	414	MODULE_LICENSE("GPL");
	415