[linux-2.6-block.git] / lib / jedec_ddr_data.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * DDR addressing details and AC timing parameters from JEDEC specs
 *
 * Copyright (C) 2012 Texas Instruments, Inc.
 *
 * Aneesh V <aneesh@ti.com>
 */

#include <memory/jedec_ddr.h>
#include <linux/module.h>

/* LPDDR2 addressing details from JESD209-2 section 2.4 */
const struct lpddr2_addressing
	lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES] = {
	{B4, T_REFI_15_6, T_RFC_90}, /* 64M */
	{B4, T_REFI_15_6, T_RFC_90}, /* 128M */
	{B4, T_REFI_7_8,  T_RFC_90}, /* 256M */
	{B4, T_REFI_7_8,  T_RFC_90}, /* 512M */
	{B8, T_REFI_7_8, T_RFC_130}, /* 1GS4 */
	{B8, T_REFI_3_9, T_RFC_130}, /* 2GS4 */
	{B8, T_REFI_3_9, T_RFC_130}, /* 4G */
	{B8, T_REFI_3_9, T_RFC_210}, /* 8G */
	{B4, T_REFI_7_8, T_RFC_130}, /* 1GS2 */
	{B4, T_REFI_3_9, T_RFC_130}, /* 2GS2 */
};
EXPORT_SYMBOL_GPL(lpddr2_jedec_addressing_table);

/* LPDDR2 AC timing parameters from JESD209-2 section 12 */
const struct lpddr2_timings
	lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES] = {
	/* Speed bin 400(200 MHz) */
	[0] = {
		.max_freq	= 200000000,
		.min_freq	= 10000000,
		.tRPab		= 21000,
		.tRCD		= 18000,
		.tWR		= 15000,
		.tRAS_min	= 42000,
		.tRRD		= 10000,
		.tWTR		= 10000,
		.tXP		= 7500,
		.tRTP		= 7500,
		.tCKESR		= 15000,
		.tDQSCK_max	= 5500,
		.tFAW		= 50000,
		.tZQCS		= 90000,
		.tZQCL		= 360000,
		.tZQinit	= 1000000,
		.tRAS_max_ns	= 70000,
		.tDQSCK_max_derated = 6000,
	},
	/* Speed bin 533(266 MHz) */
	[1] = {
		.max_freq	= 266666666,
		.min_freq	= 10000000,
		.tRPab		= 21000,
		.tRCD		= 18000,
		.tWR		= 15000,
		.tRAS_min	= 42000,
		.tRRD		= 10000,
		.tWTR		= 7500,
		.tXP		= 7500,
		.tRTP		= 7500,
		.tCKESR		= 15000,
		.tDQSCK_max	= 5500,
		.tFAW		= 50000,
		.tZQCS		= 90000,
		.tZQCL		= 360000,
		.tZQinit	= 1000000,
		.tRAS_max_ns	= 70000,
		.tDQSCK_max_derated = 6000,
	},
	/* Speed bin 800(400 MHz) */
	[2] = {
		.max_freq	= 400000000,
		.min_freq	= 10000000,
		.tRPab		= 21000,
		.tRCD		= 18000,
		.tWR		= 15000,
		.tRAS_min	= 42000,
		.tRRD		= 10000,
		.tWTR		= 7500,
		.tXP		= 7500,
		.tRTP		= 7500,
		.tCKESR		= 15000,
		.tDQSCK_max	= 5500,
		.tFAW		= 50000,
		.tZQCS		= 90000,
		.tZQCL		= 360000,
		.tZQinit	= 1000000,
		.tRAS_max_ns	= 70000,
		.tDQSCK_max_derated = 6000,
	},
	/* Speed bin 1066(533 MHz) */
	[3] = {
		.max_freq	= 533333333,
		.min_freq	= 10000000,
		.tRPab		= 21000,
		.tRCD		= 18000,
		.tWR		= 15000,
		.tRAS_min	= 42000,
		.tRRD		= 10000,
		.tWTR		= 7500,
		.tXP		= 7500,
		.tRTP		= 7500,
		.tCKESR		= 15000,
		.tDQSCK_max	= 5500,
		.tFAW		= 50000,
		.tZQCS		= 90000,
		.tZQCL		= 360000,
		.tZQinit	= 1000000,
		.tRAS_max_ns	= 70000,
		.tDQSCK_max_derated = 5620,
	},
};
EXPORT_SYMBOL_GPL(lpddr2_jedec_timings);

const struct lpddr2_min_tck lpddr2_jedec_min_tck = {
	.tRPab		= 3,
	.tRCD		= 3,
	.tWR		= 3,
	.tRASmin	= 3,
	.tRRD		= 2,
	.tWTR		= 2,
	.tXP		= 2,
	.tRTP		= 2,
	.tCKE		= 3,
	.tCKESR		= 3,
	.tFAW		= 8
};
EXPORT_SYMBOL_GPL(lpddr2_jedec_min_tck);
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
9c1c21a0 A	2	/*
	3	* DDR addressing details and AC timing parameters from JEDEC specs
	4	*
	5	* Copyright (C) 2012 Texas Instruments, Inc.
	6	*
	7	* Aneesh V <aneesh@ti.com>
9c1c21a0 A	8	*/
	9
	10	#include <memory/jedec_ddr.h>
	11	#include <linux/module.h>
	12
	13	/* LPDDR2 addressing details from JESD209-2 section 2.4 */
	14	const struct lpddr2_addressing
	15	lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES] = {
	16	{B4, T_REFI_15_6, T_RFC_90}, /* 64M */
	17	{B4, T_REFI_15_6, T_RFC_90}, /* 128M */
	18	{B4, T_REFI_7_8, T_RFC_90}, /* 256M */
	19	{B4, T_REFI_7_8, T_RFC_90}, /* 512M */
	20	{B8, T_REFI_7_8, T_RFC_130}, /* 1GS4 */
	21	{B8, T_REFI_3_9, T_RFC_130}, /* 2GS4 */
	22	{B8, T_REFI_3_9, T_RFC_130}, /* 4G */
	23	{B8, T_REFI_3_9, T_RFC_210}, /* 8G */
	24	{B4, T_REFI_7_8, T_RFC_130}, /* 1GS2 */
	25	{B4, T_REFI_3_9, T_RFC_130}, /* 2GS2 */
	26	};
	27	EXPORT_SYMBOL_GPL(lpddr2_jedec_addressing_table);
	28
	29	/* LPDDR2 AC timing parameters from JESD209-2 section 12 */
	30	const struct lpddr2_timings
	31	lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES] = {
	32	/* Speed bin 400(200 MHz) */
	33	[0] = {
	34	.max_freq = 200000000,
	35	.min_freq = 10000000,
	36	.tRPab = 21000,
	37	.tRCD = 18000,
	38	.tWR = 15000,
	39	.tRAS_min = 42000,
	40	.tRRD = 10000,
	41	.tWTR = 10000,
	42	.tXP = 7500,
	43	.tRTP = 7500,
	44	.tCKESR = 15000,
	45	.tDQSCK_max = 5500,
	46	.tFAW = 50000,
	47	.tZQCS = 90000,
	48	.tZQCL = 360000,
	49	.tZQinit = 1000000,
	50	.tRAS_max_ns = 70000,
	51	.tDQSCK_max_derated = 6000,
	52	},
	53	/* Speed bin 533(266 MHz) */
	54	[1] = {
	55	.max_freq = 266666666,
	56	.min_freq = 10000000,
	57	.tRPab = 21000,
	58	.tRCD = 18000,
	59	.tWR = 15000,
	60	.tRAS_min = 42000,
	61	.tRRD = 10000,
	62	.tWTR = 7500,
	63	.tXP = 7500,
	64	.tRTP = 7500,
	65	.tCKESR = 15000,
	66	.tDQSCK_max = 5500,
	67	.tFAW = 50000,
	68	.tZQCS = 90000,
	69	.tZQCL = 360000,
	70	.tZQinit = 1000000,
	71	.tRAS_max_ns = 70000,
72	.tDQSCK_max_derated = 6000,
73	},
74	/* Speed bin 800(400 MHz) */
75	[2] = {
76	.max_freq = 400000000,
77	.min_freq = 10000000,
78	.tRPab = 21000,
79	.tRCD = 18000,
80	.tWR = 15000,
81	.tRAS_min = 42000,
82	.tRRD = 10000,
83	.tWTR = 7500,
84	.tXP = 7500,
85	.tRTP = 7500,
86	.tCKESR = 15000,
87	.tDQSCK_max = 5500,
88	.tFAW = 50000,
89	.tZQCS = 90000,
90	.tZQCL = 360000,
91	.tZQinit = 1000000,
92	.tRAS_max_ns = 70000,
93	.tDQSCK_max_derated = 6000,
94	},
95	/* Speed bin 1066(533 MHz) */
96	[3] = {
97	.max_freq = 533333333,
98	.min_freq = 10000000,
99	.tRPab = 21000,
100	.tRCD = 18000,
101	.tWR = 15000,
102	.tRAS_min = 42000,
103	.tRRD = 10000,
104	.tWTR = 7500,
105	.tXP = 7500,
106	.tRTP = 7500,
107	.tCKESR = 15000,
108	.tDQSCK_max = 5500,
109	.tFAW = 50000,
110	.tZQCS = 90000,
111	.tZQCL = 360000,
112	.tZQinit = 1000000,
113	.tRAS_max_ns = 70000,
114	.tDQSCK_max_derated = 5620,
115	},
116	};
117	EXPORT_SYMBOL_GPL(lpddr2_jedec_timings);
118
119	const struct lpddr2_min_tck lpddr2_jedec_min_tck = {
120	.tRPab = 3,
121	.tRCD = 3,
122	.tWR = 3,
123	.tRASmin = 3,
124	.tRRD = 2,
125	.tWTR = 2,
126	.tXP = 2,
127	.tRTP = 2,
128	.tCKE = 3,
129	.tCKESR = 3,
130	.tFAW = 8
131	};
132	EXPORT_SYMBOL_GPL(lpddr2_jedec_min_tck);