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718dcedd DH |
1 | /* |
2 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the | |
14 | * next paragraph) shall be included in all copies or substantial portions | |
15 | * of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
18 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
20 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
21 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
22 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
23 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | */ | |
26 | ||
27 | #ifndef _UAPI_I915_DRM_H_ | |
28 | #define _UAPI_I915_DRM_H_ | |
29 | ||
30 | #include <drm/drm.h> | |
31 | ||
32 | /* Please note that modifications to all structs defined here are | |
33 | * subject to backwards-compatibility constraints. | |
34 | */ | |
35 | ||
cce723ed BW |
36 | /** |
37 | * DOC: uevents generated by i915 on it's device node | |
38 | * | |
39 | * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch | |
40 | * event from the gpu l3 cache. Additional information supplied is ROW, | |
35a85ac6 BW |
41 | * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep |
42 | * track of these events and if a specific cache-line seems to have a | |
43 | * persistent error remap it with the l3 remapping tool supplied in | |
44 | * intel-gpu-tools. The value supplied with the event is always 1. | |
cce723ed BW |
45 | * |
46 | * I915_ERROR_UEVENT - Generated upon error detection, currently only via | |
47 | * hangcheck. The error detection event is a good indicator of when things | |
48 | * began to go badly. The value supplied with the event is a 1 upon error | |
49 | * detection, and a 0 upon reset completion, signifying no more error | |
50 | * exists. NOTE: Disabling hangcheck or reset via module parameter will | |
51 | * cause the related events to not be seen. | |
52 | * | |
53 | * I915_RESET_UEVENT - Event is generated just before an attempt to reset the | |
54 | * the GPU. The value supplied with the event is always 1. NOTE: Disable | |
55 | * reset via module parameter will cause this event to not be seen. | |
56 | */ | |
57 | #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" | |
58 | #define I915_ERROR_UEVENT "ERROR" | |
59 | #define I915_RESET_UEVENT "RESET" | |
718dcedd DH |
60 | |
61 | /* Each region is a minimum of 16k, and there are at most 255 of them. | |
62 | */ | |
63 | #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use | |
64 | * of chars for next/prev indices */ | |
65 | #define I915_LOG_MIN_TEX_REGION_SIZE 14 | |
66 | ||
67 | typedef struct _drm_i915_init { | |
68 | enum { | |
69 | I915_INIT_DMA = 0x01, | |
70 | I915_CLEANUP_DMA = 0x02, | |
71 | I915_RESUME_DMA = 0x03 | |
72 | } func; | |
73 | unsigned int mmio_offset; | |
74 | int sarea_priv_offset; | |
75 | unsigned int ring_start; | |
76 | unsigned int ring_end; | |
77 | unsigned int ring_size; | |
78 | unsigned int front_offset; | |
79 | unsigned int back_offset; | |
80 | unsigned int depth_offset; | |
81 | unsigned int w; | |
82 | unsigned int h; | |
83 | unsigned int pitch; | |
84 | unsigned int pitch_bits; | |
85 | unsigned int back_pitch; | |
86 | unsigned int depth_pitch; | |
87 | unsigned int cpp; | |
88 | unsigned int chipset; | |
89 | } drm_i915_init_t; | |
90 | ||
91 | typedef struct _drm_i915_sarea { | |
92 | struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; | |
93 | int last_upload; /* last time texture was uploaded */ | |
94 | int last_enqueue; /* last time a buffer was enqueued */ | |
95 | int last_dispatch; /* age of the most recently dispatched buffer */ | |
96 | int ctxOwner; /* last context to upload state */ | |
97 | int texAge; | |
98 | int pf_enabled; /* is pageflipping allowed? */ | |
99 | int pf_active; | |
100 | int pf_current_page; /* which buffer is being displayed? */ | |
101 | int perf_boxes; /* performance boxes to be displayed */ | |
102 | int width, height; /* screen size in pixels */ | |
103 | ||
104 | drm_handle_t front_handle; | |
105 | int front_offset; | |
106 | int front_size; | |
107 | ||
108 | drm_handle_t back_handle; | |
109 | int back_offset; | |
110 | int back_size; | |
111 | ||
112 | drm_handle_t depth_handle; | |
113 | int depth_offset; | |
114 | int depth_size; | |
115 | ||
116 | drm_handle_t tex_handle; | |
117 | int tex_offset; | |
118 | int tex_size; | |
119 | int log_tex_granularity; | |
120 | int pitch; | |
121 | int rotation; /* 0, 90, 180 or 270 */ | |
122 | int rotated_offset; | |
123 | int rotated_size; | |
124 | int rotated_pitch; | |
125 | int virtualX, virtualY; | |
126 | ||
127 | unsigned int front_tiled; | |
128 | unsigned int back_tiled; | |
129 | unsigned int depth_tiled; | |
130 | unsigned int rotated_tiled; | |
131 | unsigned int rotated2_tiled; | |
132 | ||
133 | int pipeA_x; | |
134 | int pipeA_y; | |
135 | int pipeA_w; | |
136 | int pipeA_h; | |
137 | int pipeB_x; | |
138 | int pipeB_y; | |
139 | int pipeB_w; | |
140 | int pipeB_h; | |
141 | ||
142 | /* fill out some space for old userspace triple buffer */ | |
143 | drm_handle_t unused_handle; | |
144 | __u32 unused1, unused2, unused3; | |
145 | ||
146 | /* buffer object handles for static buffers. May change | |
147 | * over the lifetime of the client. | |
148 | */ | |
149 | __u32 front_bo_handle; | |
150 | __u32 back_bo_handle; | |
151 | __u32 unused_bo_handle; | |
152 | __u32 depth_bo_handle; | |
153 | ||
154 | } drm_i915_sarea_t; | |
155 | ||
156 | /* due to userspace building against these headers we need some compat here */ | |
157 | #define planeA_x pipeA_x | |
158 | #define planeA_y pipeA_y | |
159 | #define planeA_w pipeA_w | |
160 | #define planeA_h pipeA_h | |
161 | #define planeB_x pipeB_x | |
162 | #define planeB_y pipeB_y | |
163 | #define planeB_w pipeB_w | |
164 | #define planeB_h pipeB_h | |
165 | ||
166 | /* Flags for perf_boxes | |
167 | */ | |
168 | #define I915_BOX_RING_EMPTY 0x1 | |
169 | #define I915_BOX_FLIP 0x2 | |
170 | #define I915_BOX_WAIT 0x4 | |
171 | #define I915_BOX_TEXTURE_LOAD 0x8 | |
172 | #define I915_BOX_LOST_CONTEXT 0x10 | |
173 | ||
174 | /* I915 specific ioctls | |
175 | * The device specific ioctl range is 0x40 to 0x79. | |
176 | */ | |
177 | #define DRM_I915_INIT 0x00 | |
178 | #define DRM_I915_FLUSH 0x01 | |
179 | #define DRM_I915_FLIP 0x02 | |
180 | #define DRM_I915_BATCHBUFFER 0x03 | |
181 | #define DRM_I915_IRQ_EMIT 0x04 | |
182 | #define DRM_I915_IRQ_WAIT 0x05 | |
183 | #define DRM_I915_GETPARAM 0x06 | |
184 | #define DRM_I915_SETPARAM 0x07 | |
185 | #define DRM_I915_ALLOC 0x08 | |
186 | #define DRM_I915_FREE 0x09 | |
187 | #define DRM_I915_INIT_HEAP 0x0a | |
188 | #define DRM_I915_CMDBUFFER 0x0b | |
189 | #define DRM_I915_DESTROY_HEAP 0x0c | |
190 | #define DRM_I915_SET_VBLANK_PIPE 0x0d | |
191 | #define DRM_I915_GET_VBLANK_PIPE 0x0e | |
192 | #define DRM_I915_VBLANK_SWAP 0x0f | |
193 | #define DRM_I915_HWS_ADDR 0x11 | |
194 | #define DRM_I915_GEM_INIT 0x13 | |
195 | #define DRM_I915_GEM_EXECBUFFER 0x14 | |
196 | #define DRM_I915_GEM_PIN 0x15 | |
197 | #define DRM_I915_GEM_UNPIN 0x16 | |
198 | #define DRM_I915_GEM_BUSY 0x17 | |
199 | #define DRM_I915_GEM_THROTTLE 0x18 | |
200 | #define DRM_I915_GEM_ENTERVT 0x19 | |
201 | #define DRM_I915_GEM_LEAVEVT 0x1a | |
202 | #define DRM_I915_GEM_CREATE 0x1b | |
203 | #define DRM_I915_GEM_PREAD 0x1c | |
204 | #define DRM_I915_GEM_PWRITE 0x1d | |
205 | #define DRM_I915_GEM_MMAP 0x1e | |
206 | #define DRM_I915_GEM_SET_DOMAIN 0x1f | |
207 | #define DRM_I915_GEM_SW_FINISH 0x20 | |
208 | #define DRM_I915_GEM_SET_TILING 0x21 | |
209 | #define DRM_I915_GEM_GET_TILING 0x22 | |
210 | #define DRM_I915_GEM_GET_APERTURE 0x23 | |
211 | #define DRM_I915_GEM_MMAP_GTT 0x24 | |
212 | #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 | |
213 | #define DRM_I915_GEM_MADVISE 0x26 | |
214 | #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 | |
215 | #define DRM_I915_OVERLAY_ATTRS 0x28 | |
216 | #define DRM_I915_GEM_EXECBUFFER2 0x29 | |
217 | #define DRM_I915_GET_SPRITE_COLORKEY 0x2a | |
218 | #define DRM_I915_SET_SPRITE_COLORKEY 0x2b | |
219 | #define DRM_I915_GEM_WAIT 0x2c | |
220 | #define DRM_I915_GEM_CONTEXT_CREATE 0x2d | |
221 | #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e | |
222 | #define DRM_I915_GEM_SET_CACHING 0x2f | |
223 | #define DRM_I915_GEM_GET_CACHING 0x30 | |
224 | #define DRM_I915_REG_READ 0x31 | |
b6359918 | 225 | #define DRM_I915_GET_RESET_STATS 0x32 |
5cc9ed4b | 226 | #define DRM_I915_GEM_USERPTR 0x33 |
c9dc0f35 CW |
227 | #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 |
228 | #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 | |
718dcedd DH |
229 | |
230 | #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) | |
231 | #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) | |
232 | #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) | |
233 | #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) | |
234 | #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) | |
235 | #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) | |
236 | #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) | |
237 | #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) | |
238 | #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) | |
239 | #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) | |
240 | #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) | |
241 | #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) | |
242 | #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) | |
243 | #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) | |
244 | #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) | |
245 | #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) | |
246 | #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) | |
247 | #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) | |
248 | #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) | |
249 | #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) | |
250 | #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) | |
251 | #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) | |
252 | #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) | |
253 | #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) | |
254 | #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) | |
255 | #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) | |
256 | #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) | |
257 | #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) | |
258 | #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) | |
259 | #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) | |
260 | #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) | |
261 | #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) | |
262 | #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) | |
263 | #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) | |
264 | #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) | |
265 | #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) | |
266 | #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) | |
267 | #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) | |
268 | #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) | |
269 | #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) | |
270 | #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) | |
271 | #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) | |
272 | #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) | |
273 | #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) | |
274 | #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) | |
275 | #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) | |
276 | #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) | |
277 | #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) | |
b6359918 | 278 | #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) |
5cc9ed4b | 279 | #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) |
c9dc0f35 CW |
280 | #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) |
281 | #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) | |
718dcedd DH |
282 | |
283 | /* Allow drivers to submit batchbuffers directly to hardware, relying | |
284 | * on the security mechanisms provided by hardware. | |
285 | */ | |
286 | typedef struct drm_i915_batchbuffer { | |
287 | int start; /* agp offset */ | |
288 | int used; /* nr bytes in use */ | |
289 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ | |
290 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ | |
291 | int num_cliprects; /* mulitpass with multiple cliprects? */ | |
292 | struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ | |
293 | } drm_i915_batchbuffer_t; | |
294 | ||
295 | /* As above, but pass a pointer to userspace buffer which can be | |
296 | * validated by the kernel prior to sending to hardware. | |
297 | */ | |
298 | typedef struct _drm_i915_cmdbuffer { | |
299 | char __user *buf; /* pointer to userspace command buffer */ | |
300 | int sz; /* nr bytes in buf */ | |
301 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ | |
302 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ | |
303 | int num_cliprects; /* mulitpass with multiple cliprects? */ | |
304 | struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ | |
305 | } drm_i915_cmdbuffer_t; | |
306 | ||
307 | /* Userspace can request & wait on irq's: | |
308 | */ | |
309 | typedef struct drm_i915_irq_emit { | |
310 | int __user *irq_seq; | |
311 | } drm_i915_irq_emit_t; | |
312 | ||
313 | typedef struct drm_i915_irq_wait { | |
314 | int irq_seq; | |
315 | } drm_i915_irq_wait_t; | |
316 | ||
317 | /* Ioctl to query kernel params: | |
318 | */ | |
319 | #define I915_PARAM_IRQ_ACTIVE 1 | |
320 | #define I915_PARAM_ALLOW_BATCHBUFFER 2 | |
321 | #define I915_PARAM_LAST_DISPATCH 3 | |
322 | #define I915_PARAM_CHIPSET_ID 4 | |
323 | #define I915_PARAM_HAS_GEM 5 | |
324 | #define I915_PARAM_NUM_FENCES_AVAIL 6 | |
325 | #define I915_PARAM_HAS_OVERLAY 7 | |
326 | #define I915_PARAM_HAS_PAGEFLIPPING 8 | |
327 | #define I915_PARAM_HAS_EXECBUF2 9 | |
328 | #define I915_PARAM_HAS_BSD 10 | |
329 | #define I915_PARAM_HAS_BLT 11 | |
330 | #define I915_PARAM_HAS_RELAXED_FENCING 12 | |
331 | #define I915_PARAM_HAS_COHERENT_RINGS 13 | |
332 | #define I915_PARAM_HAS_EXEC_CONSTANTS 14 | |
333 | #define I915_PARAM_HAS_RELAXED_DELTA 15 | |
334 | #define I915_PARAM_HAS_GEN7_SOL_RESET 16 | |
335 | #define I915_PARAM_HAS_LLC 17 | |
336 | #define I915_PARAM_HAS_ALIASING_PPGTT 18 | |
337 | #define I915_PARAM_HAS_WAIT_TIMEOUT 19 | |
338 | #define I915_PARAM_HAS_SEMAPHORES 20 | |
339 | #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 | |
a1f2cc73 | 340 | #define I915_PARAM_HAS_VEBOX 22 |
c2fb7916 | 341 | #define I915_PARAM_HAS_SECURE_BATCHES 23 |
b45305fc | 342 | #define I915_PARAM_HAS_PINNED_BATCHES 24 |
ed5982e6 | 343 | #define I915_PARAM_HAS_EXEC_NO_RELOC 25 |
eef90ccb | 344 | #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 |
651d794f | 345 | #define I915_PARAM_HAS_WT 27 |
d728c8ef | 346 | #define I915_PARAM_CMD_PARSER_VERSION 28 |
6a2c4232 | 347 | #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 |
1816f923 | 348 | #define I915_PARAM_MMAP_VERSION 30 |
718dcedd DH |
349 | |
350 | typedef struct drm_i915_getparam { | |
351 | int param; | |
352 | int __user *value; | |
353 | } drm_i915_getparam_t; | |
354 | ||
355 | /* Ioctl to set kernel params: | |
356 | */ | |
357 | #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 | |
358 | #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 | |
359 | #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 | |
360 | #define I915_SETPARAM_NUM_USED_FENCES 4 | |
361 | ||
362 | typedef struct drm_i915_setparam { | |
363 | int param; | |
364 | int value; | |
365 | } drm_i915_setparam_t; | |
366 | ||
367 | /* A memory manager for regions of shared memory: | |
368 | */ | |
369 | #define I915_MEM_REGION_AGP 1 | |
370 | ||
371 | typedef struct drm_i915_mem_alloc { | |
372 | int region; | |
373 | int alignment; | |
374 | int size; | |
375 | int __user *region_offset; /* offset from start of fb or agp */ | |
376 | } drm_i915_mem_alloc_t; | |
377 | ||
378 | typedef struct drm_i915_mem_free { | |
379 | int region; | |
380 | int region_offset; | |
381 | } drm_i915_mem_free_t; | |
382 | ||
383 | typedef struct drm_i915_mem_init_heap { | |
384 | int region; | |
385 | int size; | |
386 | int start; | |
387 | } drm_i915_mem_init_heap_t; | |
388 | ||
389 | /* Allow memory manager to be torn down and re-initialized (eg on | |
390 | * rotate): | |
391 | */ | |
392 | typedef struct drm_i915_mem_destroy_heap { | |
393 | int region; | |
394 | } drm_i915_mem_destroy_heap_t; | |
395 | ||
396 | /* Allow X server to configure which pipes to monitor for vblank signals | |
397 | */ | |
398 | #define DRM_I915_VBLANK_PIPE_A 1 | |
399 | #define DRM_I915_VBLANK_PIPE_B 2 | |
400 | ||
401 | typedef struct drm_i915_vblank_pipe { | |
402 | int pipe; | |
403 | } drm_i915_vblank_pipe_t; | |
404 | ||
405 | /* Schedule buffer swap at given vertical blank: | |
406 | */ | |
407 | typedef struct drm_i915_vblank_swap { | |
408 | drm_drawable_t drawable; | |
409 | enum drm_vblank_seq_type seqtype; | |
410 | unsigned int sequence; | |
411 | } drm_i915_vblank_swap_t; | |
412 | ||
413 | typedef struct drm_i915_hws_addr { | |
414 | __u64 addr; | |
415 | } drm_i915_hws_addr_t; | |
416 | ||
417 | struct drm_i915_gem_init { | |
418 | /** | |
419 | * Beginning offset in the GTT to be managed by the DRM memory | |
420 | * manager. | |
421 | */ | |
422 | __u64 gtt_start; | |
423 | /** | |
424 | * Ending offset in the GTT to be managed by the DRM memory | |
425 | * manager. | |
426 | */ | |
427 | __u64 gtt_end; | |
428 | }; | |
429 | ||
430 | struct drm_i915_gem_create { | |
431 | /** | |
432 | * Requested size for the object. | |
433 | * | |
434 | * The (page-aligned) allocated size for the object will be returned. | |
435 | */ | |
436 | __u64 size; | |
437 | /** | |
438 | * Returned handle for the object. | |
439 | * | |
440 | * Object handles are nonzero. | |
441 | */ | |
442 | __u32 handle; | |
443 | __u32 pad; | |
444 | }; | |
445 | ||
446 | struct drm_i915_gem_pread { | |
447 | /** Handle for the object being read. */ | |
448 | __u32 handle; | |
449 | __u32 pad; | |
450 | /** Offset into the object to read from */ | |
451 | __u64 offset; | |
452 | /** Length of data to read */ | |
453 | __u64 size; | |
454 | /** | |
455 | * Pointer to write the data into. | |
456 | * | |
457 | * This is a fixed-size type for 32/64 compatibility. | |
458 | */ | |
459 | __u64 data_ptr; | |
460 | }; | |
461 | ||
462 | struct drm_i915_gem_pwrite { | |
463 | /** Handle for the object being written to. */ | |
464 | __u32 handle; | |
465 | __u32 pad; | |
466 | /** Offset into the object to write to */ | |
467 | __u64 offset; | |
468 | /** Length of data to write */ | |
469 | __u64 size; | |
470 | /** | |
471 | * Pointer to read the data from. | |
472 | * | |
473 | * This is a fixed-size type for 32/64 compatibility. | |
474 | */ | |
475 | __u64 data_ptr; | |
476 | }; | |
477 | ||
478 | struct drm_i915_gem_mmap { | |
479 | /** Handle for the object being mapped. */ | |
480 | __u32 handle; | |
481 | __u32 pad; | |
482 | /** Offset in the object to map. */ | |
483 | __u64 offset; | |
484 | /** | |
485 | * Length of data to map. | |
486 | * | |
487 | * The value will be page-aligned. | |
488 | */ | |
489 | __u64 size; | |
490 | /** | |
491 | * Returned pointer the data was mapped at. | |
492 | * | |
493 | * This is a fixed-size type for 32/64 compatibility. | |
494 | */ | |
495 | __u64 addr_ptr; | |
1816f923 AG |
496 | |
497 | /** | |
498 | * Flags for extended behaviour. | |
499 | * | |
500 | * Added in version 2. | |
501 | */ | |
502 | __u64 flags; | |
503 | #define I915_MMAP_WC 0x1 | |
718dcedd DH |
504 | }; |
505 | ||
506 | struct drm_i915_gem_mmap_gtt { | |
507 | /** Handle for the object being mapped. */ | |
508 | __u32 handle; | |
509 | __u32 pad; | |
510 | /** | |
511 | * Fake offset to use for subsequent mmap call | |
512 | * | |
513 | * This is a fixed-size type for 32/64 compatibility. | |
514 | */ | |
515 | __u64 offset; | |
516 | }; | |
517 | ||
518 | struct drm_i915_gem_set_domain { | |
519 | /** Handle for the object */ | |
520 | __u32 handle; | |
521 | ||
522 | /** New read domains */ | |
523 | __u32 read_domains; | |
524 | ||
525 | /** New write domain */ | |
526 | __u32 write_domain; | |
527 | }; | |
528 | ||
529 | struct drm_i915_gem_sw_finish { | |
530 | /** Handle for the object */ | |
531 | __u32 handle; | |
532 | }; | |
533 | ||
534 | struct drm_i915_gem_relocation_entry { | |
535 | /** | |
536 | * Handle of the buffer being pointed to by this relocation entry. | |
537 | * | |
538 | * It's appealing to make this be an index into the mm_validate_entry | |
539 | * list to refer to the buffer, but this allows the driver to create | |
540 | * a relocation list for state buffers and not re-write it per | |
541 | * exec using the buffer. | |
542 | */ | |
543 | __u32 target_handle; | |
544 | ||
545 | /** | |
546 | * Value to be added to the offset of the target buffer to make up | |
547 | * the relocation entry. | |
548 | */ | |
549 | __u32 delta; | |
550 | ||
551 | /** Offset in the buffer the relocation entry will be written into */ | |
552 | __u64 offset; | |
553 | ||
554 | /** | |
555 | * Offset value of the target buffer that the relocation entry was last | |
556 | * written as. | |
557 | * | |
558 | * If the buffer has the same offset as last time, we can skip syncing | |
559 | * and writing the relocation. This value is written back out by | |
560 | * the execbuffer ioctl when the relocation is written. | |
561 | */ | |
562 | __u64 presumed_offset; | |
563 | ||
564 | /** | |
565 | * Target memory domains read by this operation. | |
566 | */ | |
567 | __u32 read_domains; | |
568 | ||
569 | /** | |
570 | * Target memory domains written by this operation. | |
571 | * | |
572 | * Note that only one domain may be written by the whole | |
573 | * execbuffer operation, so that where there are conflicts, | |
574 | * the application will get -EINVAL back. | |
575 | */ | |
576 | __u32 write_domain; | |
577 | }; | |
578 | ||
579 | /** @{ | |
580 | * Intel memory domains | |
581 | * | |
582 | * Most of these just align with the various caches in | |
583 | * the system and are used to flush and invalidate as | |
584 | * objects end up cached in different domains. | |
585 | */ | |
586 | /** CPU cache */ | |
587 | #define I915_GEM_DOMAIN_CPU 0x00000001 | |
588 | /** Render cache, used by 2D and 3D drawing */ | |
589 | #define I915_GEM_DOMAIN_RENDER 0x00000002 | |
590 | /** Sampler cache, used by texture engine */ | |
591 | #define I915_GEM_DOMAIN_SAMPLER 0x00000004 | |
592 | /** Command queue, used to load batch buffers */ | |
593 | #define I915_GEM_DOMAIN_COMMAND 0x00000008 | |
594 | /** Instruction cache, used by shader programs */ | |
595 | #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 | |
596 | /** Vertex address cache */ | |
597 | #define I915_GEM_DOMAIN_VERTEX 0x00000020 | |
598 | /** GTT domain - aperture and scanout */ | |
599 | #define I915_GEM_DOMAIN_GTT 0x00000040 | |
600 | /** @} */ | |
601 | ||
602 | struct drm_i915_gem_exec_object { | |
603 | /** | |
604 | * User's handle for a buffer to be bound into the GTT for this | |
605 | * operation. | |
606 | */ | |
607 | __u32 handle; | |
608 | ||
609 | /** Number of relocations to be performed on this buffer */ | |
610 | __u32 relocation_count; | |
611 | /** | |
612 | * Pointer to array of struct drm_i915_gem_relocation_entry containing | |
613 | * the relocations to be performed in this buffer. | |
614 | */ | |
615 | __u64 relocs_ptr; | |
616 | ||
617 | /** Required alignment in graphics aperture */ | |
618 | __u64 alignment; | |
619 | ||
620 | /** | |
621 | * Returned value of the updated offset of the object, for future | |
622 | * presumed_offset writes. | |
623 | */ | |
624 | __u64 offset; | |
625 | }; | |
626 | ||
627 | struct drm_i915_gem_execbuffer { | |
628 | /** | |
629 | * List of buffers to be validated with their relocations to be | |
630 | * performend on them. | |
631 | * | |
632 | * This is a pointer to an array of struct drm_i915_gem_validate_entry. | |
633 | * | |
634 | * These buffers must be listed in an order such that all relocations | |
635 | * a buffer is performing refer to buffers that have already appeared | |
636 | * in the validate list. | |
637 | */ | |
638 | __u64 buffers_ptr; | |
639 | __u32 buffer_count; | |
640 | ||
641 | /** Offset in the batchbuffer to start execution from. */ | |
642 | __u32 batch_start_offset; | |
643 | /** Bytes used in batchbuffer from batch_start_offset */ | |
644 | __u32 batch_len; | |
645 | __u32 DR1; | |
646 | __u32 DR4; | |
647 | __u32 num_cliprects; | |
648 | /** This is a struct drm_clip_rect *cliprects */ | |
649 | __u64 cliprects_ptr; | |
650 | }; | |
651 | ||
652 | struct drm_i915_gem_exec_object2 { | |
653 | /** | |
654 | * User's handle for a buffer to be bound into the GTT for this | |
655 | * operation. | |
656 | */ | |
657 | __u32 handle; | |
658 | ||
659 | /** Number of relocations to be performed on this buffer */ | |
660 | __u32 relocation_count; | |
661 | /** | |
662 | * Pointer to array of struct drm_i915_gem_relocation_entry containing | |
663 | * the relocations to be performed in this buffer. | |
664 | */ | |
665 | __u64 relocs_ptr; | |
666 | ||
667 | /** Required alignment in graphics aperture */ | |
668 | __u64 alignment; | |
669 | ||
670 | /** | |
671 | * Returned value of the updated offset of the object, for future | |
672 | * presumed_offset writes. | |
673 | */ | |
674 | __u64 offset; | |
675 | ||
676 | #define EXEC_OBJECT_NEEDS_FENCE (1<<0) | |
ed5982e6 DV |
677 | #define EXEC_OBJECT_NEEDS_GTT (1<<1) |
678 | #define EXEC_OBJECT_WRITE (1<<2) | |
679 | #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1) | |
718dcedd | 680 | __u64 flags; |
ed5982e6 | 681 | |
718dcedd DH |
682 | __u64 rsvd1; |
683 | __u64 rsvd2; | |
684 | }; | |
685 | ||
686 | struct drm_i915_gem_execbuffer2 { | |
687 | /** | |
688 | * List of gem_exec_object2 structs | |
689 | */ | |
690 | __u64 buffers_ptr; | |
691 | __u32 buffer_count; | |
692 | ||
693 | /** Offset in the batchbuffer to start execution from. */ | |
694 | __u32 batch_start_offset; | |
695 | /** Bytes used in batchbuffer from batch_start_offset */ | |
696 | __u32 batch_len; | |
697 | __u32 DR1; | |
698 | __u32 DR4; | |
699 | __u32 num_cliprects; | |
700 | /** This is a struct drm_clip_rect *cliprects */ | |
701 | __u64 cliprects_ptr; | |
702 | #define I915_EXEC_RING_MASK (7<<0) | |
703 | #define I915_EXEC_DEFAULT (0<<0) | |
704 | #define I915_EXEC_RENDER (1<<0) | |
705 | #define I915_EXEC_BSD (2<<0) | |
706 | #define I915_EXEC_BLT (3<<0) | |
82f91b6e | 707 | #define I915_EXEC_VEBOX (4<<0) |
718dcedd DH |
708 | |
709 | /* Used for switching the constants addressing mode on gen4+ RENDER ring. | |
710 | * Gen6+ only supports relative addressing to dynamic state (default) and | |
711 | * absolute addressing. | |
712 | * | |
713 | * These flags are ignored for the BSD and BLT rings. | |
714 | */ | |
715 | #define I915_EXEC_CONSTANTS_MASK (3<<6) | |
716 | #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ | |
717 | #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) | |
718 | #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ | |
719 | __u64 flags; | |
720 | __u64 rsvd1; /* now used for context info */ | |
721 | __u64 rsvd2; | |
722 | }; | |
723 | ||
724 | /** Resets the SO write offset registers for transform feedback on gen7. */ | |
725 | #define I915_EXEC_GEN7_SOL_RESET (1<<8) | |
726 | ||
c2fb7916 DV |
727 | /** Request a privileged ("secure") batch buffer. Note only available for |
728 | * DRM_ROOT_ONLY | DRM_MASTER processes. | |
729 | */ | |
730 | #define I915_EXEC_SECURE (1<<9) | |
731 | ||
b45305fc DV |
732 | /** Inform the kernel that the batch is and will always be pinned. This |
733 | * negates the requirement for a workaround to be performed to avoid | |
734 | * an incoherent CS (such as can be found on 830/845). If this flag is | |
735 | * not passed, the kernel will endeavour to make sure the batch is | |
736 | * coherent with the CS before execution. If this flag is passed, | |
737 | * userspace assumes the responsibility for ensuring the same. | |
738 | */ | |
739 | #define I915_EXEC_IS_PINNED (1<<10) | |
740 | ||
c3d19d3c | 741 | /** Provide a hint to the kernel that the command stream and auxiliary |
ed5982e6 DV |
742 | * state buffers already holds the correct presumed addresses and so the |
743 | * relocation process may be skipped if no buffers need to be moved in | |
744 | * preparation for the execbuffer. | |
745 | */ | |
746 | #define I915_EXEC_NO_RELOC (1<<11) | |
747 | ||
eef90ccb CW |
748 | /** Use the reloc.handle as an index into the exec object array rather |
749 | * than as the per-file handle. | |
750 | */ | |
751 | #define I915_EXEC_HANDLE_LUT (1<<12) | |
752 | ||
8d360dff ZG |
753 | /** Used for switching BSD rings on the platforms with two BSD rings */ |
754 | #define I915_EXEC_BSD_MASK (3<<13) | |
755 | #define I915_EXEC_BSD_DEFAULT (0<<13) /* default ping-pong mode */ | |
756 | #define I915_EXEC_BSD_RING1 (1<<13) | |
757 | #define I915_EXEC_BSD_RING2 (2<<13) | |
758 | ||
759 | #define __I915_EXEC_UNKNOWN_FLAGS -(1<<15) | |
ed5982e6 | 760 | |
718dcedd DH |
761 | #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) |
762 | #define i915_execbuffer2_set_context_id(eb2, context) \ | |
763 | (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK | |
764 | #define i915_execbuffer2_get_context_id(eb2) \ | |
765 | ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) | |
766 | ||
767 | struct drm_i915_gem_pin { | |
768 | /** Handle of the buffer to be pinned. */ | |
769 | __u32 handle; | |
770 | __u32 pad; | |
771 | ||
772 | /** alignment required within the aperture */ | |
773 | __u64 alignment; | |
774 | ||
775 | /** Returned GTT offset of the buffer. */ | |
776 | __u64 offset; | |
777 | }; | |
778 | ||
779 | struct drm_i915_gem_unpin { | |
780 | /** Handle of the buffer to be unpinned. */ | |
781 | __u32 handle; | |
782 | __u32 pad; | |
783 | }; | |
784 | ||
785 | struct drm_i915_gem_busy { | |
786 | /** Handle of the buffer to check for busy */ | |
787 | __u32 handle; | |
788 | ||
789 | /** Return busy status (1 if busy, 0 if idle). | |
790 | * The high word is used to indicate on which rings the object | |
791 | * currently resides: | |
792 | * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) | |
793 | */ | |
794 | __u32 busy; | |
795 | }; | |
796 | ||
35c7ab42 DV |
797 | /** |
798 | * I915_CACHING_NONE | |
799 | * | |
800 | * GPU access is not coherent with cpu caches. Default for machines without an | |
801 | * LLC. | |
802 | */ | |
718dcedd | 803 | #define I915_CACHING_NONE 0 |
35c7ab42 DV |
804 | /** |
805 | * I915_CACHING_CACHED | |
806 | * | |
807 | * GPU access is coherent with cpu caches and furthermore the data is cached in | |
808 | * last-level caches shared between cpu cores and the gpu GT. Default on | |
809 | * machines with HAS_LLC. | |
810 | */ | |
718dcedd | 811 | #define I915_CACHING_CACHED 1 |
35c7ab42 DV |
812 | /** |
813 | * I915_CACHING_DISPLAY | |
814 | * | |
815 | * Special GPU caching mode which is coherent with the scanout engines. | |
816 | * Transparently falls back to I915_CACHING_NONE on platforms where no special | |
817 | * cache mode (like write-through or gfdt flushing) is available. The kernel | |
818 | * automatically sets this mode when using a buffer as a scanout target. | |
819 | * Userspace can manually set this mode to avoid a costly stall and clflush in | |
820 | * the hotpath of drawing the first frame. | |
821 | */ | |
822 | #define I915_CACHING_DISPLAY 2 | |
718dcedd DH |
823 | |
824 | struct drm_i915_gem_caching { | |
825 | /** | |
826 | * Handle of the buffer to set/get the caching level of. */ | |
827 | __u32 handle; | |
828 | ||
829 | /** | |
830 | * Cacheing level to apply or return value | |
831 | * | |
832 | * bits0-15 are for generic caching control (i.e. the above defined | |
833 | * values). bits16-31 are reserved for platform-specific variations | |
834 | * (e.g. l3$ caching on gen7). */ | |
835 | __u32 caching; | |
836 | }; | |
837 | ||
838 | #define I915_TILING_NONE 0 | |
839 | #define I915_TILING_X 1 | |
840 | #define I915_TILING_Y 2 | |
841 | ||
842 | #define I915_BIT_6_SWIZZLE_NONE 0 | |
843 | #define I915_BIT_6_SWIZZLE_9 1 | |
844 | #define I915_BIT_6_SWIZZLE_9_10 2 | |
845 | #define I915_BIT_6_SWIZZLE_9_11 3 | |
846 | #define I915_BIT_6_SWIZZLE_9_10_11 4 | |
847 | /* Not seen by userland */ | |
848 | #define I915_BIT_6_SWIZZLE_UNKNOWN 5 | |
849 | /* Seen by userland. */ | |
850 | #define I915_BIT_6_SWIZZLE_9_17 6 | |
851 | #define I915_BIT_6_SWIZZLE_9_10_17 7 | |
852 | ||
853 | struct drm_i915_gem_set_tiling { | |
854 | /** Handle of the buffer to have its tiling state updated */ | |
855 | __u32 handle; | |
856 | ||
857 | /** | |
858 | * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, | |
859 | * I915_TILING_Y). | |
860 | * | |
861 | * This value is to be set on request, and will be updated by the | |
862 | * kernel on successful return with the actual chosen tiling layout. | |
863 | * | |
864 | * The tiling mode may be demoted to I915_TILING_NONE when the system | |
865 | * has bit 6 swizzling that can't be managed correctly by GEM. | |
866 | * | |
867 | * Buffer contents become undefined when changing tiling_mode. | |
868 | */ | |
869 | __u32 tiling_mode; | |
870 | ||
871 | /** | |
872 | * Stride in bytes for the object when in I915_TILING_X or | |
873 | * I915_TILING_Y. | |
874 | */ | |
875 | __u32 stride; | |
876 | ||
877 | /** | |
878 | * Returned address bit 6 swizzling required for CPU access through | |
879 | * mmap mapping. | |
880 | */ | |
881 | __u32 swizzle_mode; | |
882 | }; | |
883 | ||
884 | struct drm_i915_gem_get_tiling { | |
885 | /** Handle of the buffer to get tiling state for. */ | |
886 | __u32 handle; | |
887 | ||
888 | /** | |
889 | * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, | |
890 | * I915_TILING_Y). | |
891 | */ | |
892 | __u32 tiling_mode; | |
893 | ||
894 | /** | |
895 | * Returned address bit 6 swizzling required for CPU access through | |
896 | * mmap mapping. | |
897 | */ | |
898 | __u32 swizzle_mode; | |
70f2f5c7 CW |
899 | |
900 | /** | |
901 | * Returned address bit 6 swizzling required for CPU access through | |
902 | * mmap mapping whilst bound. | |
903 | */ | |
904 | __u32 phys_swizzle_mode; | |
718dcedd DH |
905 | }; |
906 | ||
907 | struct drm_i915_gem_get_aperture { | |
908 | /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ | |
909 | __u64 aper_size; | |
910 | ||
911 | /** | |
912 | * Available space in the aperture used by i915_gem_execbuffer, in | |
913 | * bytes | |
914 | */ | |
915 | __u64 aper_available_size; | |
916 | }; | |
917 | ||
918 | struct drm_i915_get_pipe_from_crtc_id { | |
919 | /** ID of CRTC being requested **/ | |
920 | __u32 crtc_id; | |
921 | ||
922 | /** pipe of requested CRTC **/ | |
923 | __u32 pipe; | |
924 | }; | |
925 | ||
926 | #define I915_MADV_WILLNEED 0 | |
927 | #define I915_MADV_DONTNEED 1 | |
928 | #define __I915_MADV_PURGED 2 /* internal state */ | |
929 | ||
930 | struct drm_i915_gem_madvise { | |
931 | /** Handle of the buffer to change the backing store advice */ | |
932 | __u32 handle; | |
933 | ||
934 | /* Advice: either the buffer will be needed again in the near future, | |
935 | * or wont be and could be discarded under memory pressure. | |
936 | */ | |
937 | __u32 madv; | |
938 | ||
939 | /** Whether the backing store still exists. */ | |
940 | __u32 retained; | |
941 | }; | |
942 | ||
943 | /* flags */ | |
944 | #define I915_OVERLAY_TYPE_MASK 0xff | |
945 | #define I915_OVERLAY_YUV_PLANAR 0x01 | |
946 | #define I915_OVERLAY_YUV_PACKED 0x02 | |
947 | #define I915_OVERLAY_RGB 0x03 | |
948 | ||
949 | #define I915_OVERLAY_DEPTH_MASK 0xff00 | |
950 | #define I915_OVERLAY_RGB24 0x1000 | |
951 | #define I915_OVERLAY_RGB16 0x2000 | |
952 | #define I915_OVERLAY_RGB15 0x3000 | |
953 | #define I915_OVERLAY_YUV422 0x0100 | |
954 | #define I915_OVERLAY_YUV411 0x0200 | |
955 | #define I915_OVERLAY_YUV420 0x0300 | |
956 | #define I915_OVERLAY_YUV410 0x0400 | |
957 | ||
958 | #define I915_OVERLAY_SWAP_MASK 0xff0000 | |
959 | #define I915_OVERLAY_NO_SWAP 0x000000 | |
960 | #define I915_OVERLAY_UV_SWAP 0x010000 | |
961 | #define I915_OVERLAY_Y_SWAP 0x020000 | |
962 | #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 | |
963 | ||
964 | #define I915_OVERLAY_FLAGS_MASK 0xff000000 | |
965 | #define I915_OVERLAY_ENABLE 0x01000000 | |
966 | ||
967 | struct drm_intel_overlay_put_image { | |
968 | /* various flags and src format description */ | |
969 | __u32 flags; | |
970 | /* source picture description */ | |
971 | __u32 bo_handle; | |
972 | /* stride values and offsets are in bytes, buffer relative */ | |
973 | __u16 stride_Y; /* stride for packed formats */ | |
974 | __u16 stride_UV; | |
975 | __u32 offset_Y; /* offset for packet formats */ | |
976 | __u32 offset_U; | |
977 | __u32 offset_V; | |
978 | /* in pixels */ | |
979 | __u16 src_width; | |
980 | __u16 src_height; | |
981 | /* to compensate the scaling factors for partially covered surfaces */ | |
982 | __u16 src_scan_width; | |
983 | __u16 src_scan_height; | |
984 | /* output crtc description */ | |
985 | __u32 crtc_id; | |
986 | __u16 dst_x; | |
987 | __u16 dst_y; | |
988 | __u16 dst_width; | |
989 | __u16 dst_height; | |
990 | }; | |
991 | ||
992 | /* flags */ | |
993 | #define I915_OVERLAY_UPDATE_ATTRS (1<<0) | |
994 | #define I915_OVERLAY_UPDATE_GAMMA (1<<1) | |
995 | struct drm_intel_overlay_attrs { | |
996 | __u32 flags; | |
997 | __u32 color_key; | |
998 | __s32 brightness; | |
999 | __u32 contrast; | |
1000 | __u32 saturation; | |
1001 | __u32 gamma0; | |
1002 | __u32 gamma1; | |
1003 | __u32 gamma2; | |
1004 | __u32 gamma3; | |
1005 | __u32 gamma4; | |
1006 | __u32 gamma5; | |
1007 | }; | |
1008 | ||
1009 | /* | |
1010 | * Intel sprite handling | |
1011 | * | |
1012 | * Color keying works with a min/mask/max tuple. Both source and destination | |
1013 | * color keying is allowed. | |
1014 | * | |
1015 | * Source keying: | |
1016 | * Sprite pixels within the min & max values, masked against the color channels | |
1017 | * specified in the mask field, will be transparent. All other pixels will | |
1018 | * be displayed on top of the primary plane. For RGB surfaces, only the min | |
1019 | * and mask fields will be used; ranged compares are not allowed. | |
1020 | * | |
1021 | * Destination keying: | |
1022 | * Primary plane pixels that match the min value, masked against the color | |
1023 | * channels specified in the mask field, will be replaced by corresponding | |
1024 | * pixels from the sprite plane. | |
1025 | * | |
1026 | * Note that source & destination keying are exclusive; only one can be | |
1027 | * active on a given plane. | |
1028 | */ | |
1029 | ||
1030 | #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ | |
1031 | #define I915_SET_COLORKEY_DESTINATION (1<<1) | |
1032 | #define I915_SET_COLORKEY_SOURCE (1<<2) | |
1033 | struct drm_intel_sprite_colorkey { | |
1034 | __u32 plane_id; | |
1035 | __u32 min_value; | |
1036 | __u32 channel_mask; | |
1037 | __u32 max_value; | |
1038 | __u32 flags; | |
1039 | }; | |
1040 | ||
1041 | struct drm_i915_gem_wait { | |
1042 | /** Handle of BO we shall wait on */ | |
1043 | __u32 bo_handle; | |
1044 | __u32 flags; | |
1045 | /** Number of nanoseconds to wait, Returns time remaining. */ | |
1046 | __s64 timeout_ns; | |
1047 | }; | |
1048 | ||
1049 | struct drm_i915_gem_context_create { | |
1050 | /* output: id of new context*/ | |
1051 | __u32 ctx_id; | |
1052 | __u32 pad; | |
1053 | }; | |
1054 | ||
1055 | struct drm_i915_gem_context_destroy { | |
1056 | __u32 ctx_id; | |
1057 | __u32 pad; | |
1058 | }; | |
1059 | ||
1060 | struct drm_i915_reg_read { | |
1061 | __u64 offset; | |
1062 | __u64 val; /* Return value */ | |
1063 | }; | |
b6359918 MK |
1064 | |
1065 | struct drm_i915_reset_stats { | |
1066 | __u32 ctx_id; | |
1067 | __u32 flags; | |
1068 | ||
1069 | /* All resets since boot/module reload, for all contexts */ | |
1070 | __u32 reset_count; | |
1071 | ||
1072 | /* Number of batches lost when active in GPU, for this context */ | |
1073 | __u32 batch_active; | |
1074 | ||
1075 | /* Number of batches lost pending for execution, for this context */ | |
1076 | __u32 batch_pending; | |
1077 | ||
1078 | __u32 pad; | |
1079 | }; | |
1080 | ||
5cc9ed4b CW |
1081 | struct drm_i915_gem_userptr { |
1082 | __u64 user_ptr; | |
1083 | __u64 user_size; | |
1084 | __u32 flags; | |
1085 | #define I915_USERPTR_READ_ONLY 0x1 | |
1086 | #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 | |
1087 | /** | |
1088 | * Returned handle for the object. | |
1089 | * | |
1090 | * Object handles are nonzero. | |
1091 | */ | |
1092 | __u32 handle; | |
1093 | }; | |
1094 | ||
c9dc0f35 CW |
1095 | struct drm_i915_gem_context_param { |
1096 | __u32 ctx_id; | |
1097 | __u32 size; | |
1098 | __u64 param; | |
1099 | #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 | |
1100 | __u64 value; | |
1101 | }; | |
1102 | ||
718dcedd | 1103 | #endif /* _UAPI_I915_DRM_H_ */ |