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81629cba AD |
1 | /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- |
2 | * | |
3 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. | |
4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. | |
5 | * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. | |
6 | * Copyright 2014 Advanced Micro Devices, Inc. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
22 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
23 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
24 | * OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | * Authors: | |
27 | * Kevin E. Martin <martin@valinux.com> | |
28 | * Gareth Hughes <gareth@valinux.com> | |
29 | * Keith Whitwell <keith@tungstengraphics.com> | |
30 | */ | |
31 | ||
32 | #ifndef __AMDGPU_DRM_H__ | |
33 | #define __AMDGPU_DRM_H__ | |
34 | ||
b3fcf36a | 35 | #include "drm.h" |
81629cba | 36 | |
cfa7152f EV |
37 | #if defined(__cplusplus) |
38 | extern "C" { | |
39 | #endif | |
40 | ||
81629cba AD |
41 | #define DRM_AMDGPU_GEM_CREATE 0x00 |
42 | #define DRM_AMDGPU_GEM_MMAP 0x01 | |
43 | #define DRM_AMDGPU_CTX 0x02 | |
44 | #define DRM_AMDGPU_BO_LIST 0x03 | |
45 | #define DRM_AMDGPU_CS 0x04 | |
46 | #define DRM_AMDGPU_INFO 0x05 | |
47 | #define DRM_AMDGPU_GEM_METADATA 0x06 | |
48 | #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 | |
49 | #define DRM_AMDGPU_GEM_VA 0x08 | |
50 | #define DRM_AMDGPU_WAIT_CS 0x09 | |
51 | #define DRM_AMDGPU_GEM_OP 0x10 | |
52 | #define DRM_AMDGPU_GEM_USERPTR 0x11 | |
eef18a82 | 53 | #define DRM_AMDGPU_WAIT_FENCES 0x12 |
81629cba AD |
54 | |
55 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) | |
56 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) | |
57 | #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) | |
58 | #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) | |
59 | #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) | |
60 | #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) | |
61 | #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) | |
62 | #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) | |
34b5f6a6 | 63 | #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) |
81629cba AD |
64 | #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) |
65 | #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) | |
66 | #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) | |
eef18a82 | 67 | #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) |
81629cba AD |
68 | |
69 | #define AMDGPU_GEM_DOMAIN_CPU 0x1 | |
70 | #define AMDGPU_GEM_DOMAIN_GTT 0x2 | |
71 | #define AMDGPU_GEM_DOMAIN_VRAM 0x4 | |
72 | #define AMDGPU_GEM_DOMAIN_GDS 0x8 | |
73 | #define AMDGPU_GEM_DOMAIN_GWS 0x10 | |
74 | #define AMDGPU_GEM_DOMAIN_OA 0x20 | |
75 | ||
81629cba AD |
76 | /* Flag that CPU access will be required for the case of VRAM domain */ |
77 | #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) | |
78 | /* Flag that CPU access will not work, this VRAM domain is invisible */ | |
79 | #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) | |
81629cba | 80 | /* Flag that USWC attributes should be used for GTT */ |
88671288 | 81 | #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) |
4fea83ff FC |
82 | /* Flag that the memory should be in VRAM and cleared */ |
83 | #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) | |
e7893c4b CZ |
84 | /* Flag that create shadow bo(GTT) while allocating vram bo */ |
85 | #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) | |
03f48dd5 CK |
86 | /* Flag that allocating the BO should use linear VRAM */ |
87 | #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) | |
81629cba | 88 | |
81629cba AD |
89 | struct drm_amdgpu_gem_create_in { |
90 | /** the requested memory size */ | |
2ce9dde0 | 91 | __u64 bo_size; |
81629cba | 92 | /** physical start_addr alignment in bytes for some HW requirements */ |
2ce9dde0 | 93 | __u64 alignment; |
81629cba | 94 | /** the requested memory domains */ |
2ce9dde0 | 95 | __u64 domains; |
81629cba | 96 | /** allocation flags */ |
2ce9dde0 | 97 | __u64 domain_flags; |
81629cba AD |
98 | }; |
99 | ||
100 | struct drm_amdgpu_gem_create_out { | |
101 | /** returned GEM object handle */ | |
2ce9dde0 MR |
102 | __u32 handle; |
103 | __u32 _pad; | |
81629cba AD |
104 | }; |
105 | ||
106 | union drm_amdgpu_gem_create { | |
107 | struct drm_amdgpu_gem_create_in in; | |
108 | struct drm_amdgpu_gem_create_out out; | |
109 | }; | |
110 | ||
111 | /** Opcode to create new residency list. */ | |
112 | #define AMDGPU_BO_LIST_OP_CREATE 0 | |
113 | /** Opcode to destroy previously created residency list */ | |
114 | #define AMDGPU_BO_LIST_OP_DESTROY 1 | |
115 | /** Opcode to update resource information in the list */ | |
116 | #define AMDGPU_BO_LIST_OP_UPDATE 2 | |
117 | ||
118 | struct drm_amdgpu_bo_list_in { | |
119 | /** Type of operation */ | |
2ce9dde0 | 120 | __u32 operation; |
81629cba | 121 | /** Handle of list or 0 if we want to create one */ |
2ce9dde0 | 122 | __u32 list_handle; |
81629cba | 123 | /** Number of BOs in list */ |
2ce9dde0 | 124 | __u32 bo_number; |
81629cba | 125 | /** Size of each element describing BO */ |
2ce9dde0 | 126 | __u32 bo_info_size; |
81629cba | 127 | /** Pointer to array describing BOs */ |
2ce9dde0 | 128 | __u64 bo_info_ptr; |
81629cba AD |
129 | }; |
130 | ||
131 | struct drm_amdgpu_bo_list_entry { | |
132 | /** Handle of BO */ | |
2ce9dde0 | 133 | __u32 bo_handle; |
81629cba | 134 | /** New (if specified) BO priority to be used during migration */ |
2ce9dde0 | 135 | __u32 bo_priority; |
81629cba AD |
136 | }; |
137 | ||
138 | struct drm_amdgpu_bo_list_out { | |
139 | /** Handle of resource list */ | |
2ce9dde0 MR |
140 | __u32 list_handle; |
141 | __u32 _pad; | |
81629cba AD |
142 | }; |
143 | ||
144 | union drm_amdgpu_bo_list { | |
145 | struct drm_amdgpu_bo_list_in in; | |
146 | struct drm_amdgpu_bo_list_out out; | |
147 | }; | |
148 | ||
149 | /* context related */ | |
150 | #define AMDGPU_CTX_OP_ALLOC_CTX 1 | |
151 | #define AMDGPU_CTX_OP_FREE_CTX 2 | |
152 | #define AMDGPU_CTX_OP_QUERY_STATE 3 | |
153 | ||
d94aed5a MO |
154 | /* GPU reset status */ |
155 | #define AMDGPU_CTX_NO_RESET 0 | |
675da0dd CK |
156 | /* this the context caused it */ |
157 | #define AMDGPU_CTX_GUILTY_RESET 1 | |
158 | /* some other context caused it */ | |
159 | #define AMDGPU_CTX_INNOCENT_RESET 2 | |
160 | /* unknown cause */ | |
161 | #define AMDGPU_CTX_UNKNOWN_RESET 3 | |
d94aed5a | 162 | |
81629cba | 163 | struct drm_amdgpu_ctx_in { |
675da0dd | 164 | /** AMDGPU_CTX_OP_* */ |
2ce9dde0 | 165 | __u32 op; |
675da0dd | 166 | /** For future use, no flags defined so far */ |
2ce9dde0 MR |
167 | __u32 flags; |
168 | __u32 ctx_id; | |
169 | __u32 _pad; | |
81629cba AD |
170 | }; |
171 | ||
172 | union drm_amdgpu_ctx_out { | |
173 | struct { | |
2ce9dde0 MR |
174 | __u32 ctx_id; |
175 | __u32 _pad; | |
81629cba AD |
176 | } alloc; |
177 | ||
178 | struct { | |
675da0dd | 179 | /** For future use, no flags defined so far */ |
2ce9dde0 | 180 | __u64 flags; |
d94aed5a | 181 | /** Number of resets caused by this context so far. */ |
2ce9dde0 | 182 | __u32 hangs; |
d94aed5a | 183 | /** Reset status since the last call of the ioctl. */ |
2ce9dde0 | 184 | __u32 reset_status; |
81629cba AD |
185 | } state; |
186 | }; | |
187 | ||
188 | union drm_amdgpu_ctx { | |
189 | struct drm_amdgpu_ctx_in in; | |
190 | union drm_amdgpu_ctx_out out; | |
191 | }; | |
192 | ||
193 | /* | |
194 | * This is not a reliable API and you should expect it to fail for any | |
195 | * number of reasons and have fallback path that do not use userptr to | |
196 | * perform any operation. | |
197 | */ | |
198 | #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) | |
199 | #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) | |
200 | #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) | |
201 | #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) | |
202 | ||
203 | struct drm_amdgpu_gem_userptr { | |
2ce9dde0 MR |
204 | __u64 addr; |
205 | __u64 size; | |
675da0dd | 206 | /* AMDGPU_GEM_USERPTR_* */ |
2ce9dde0 | 207 | __u32 flags; |
675da0dd | 208 | /* Resulting GEM handle */ |
2ce9dde0 | 209 | __u32 handle; |
81629cba AD |
210 | }; |
211 | ||
00ac6f6b | 212 | /* SI-CI-VI: */ |
fbd76d59 MO |
213 | /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ |
214 | #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 | |
215 | #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf | |
216 | #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 | |
217 | #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f | |
218 | #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 | |
219 | #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 | |
220 | #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 | |
221 | #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 | |
222 | #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 | |
223 | #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 | |
224 | #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 | |
225 | #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 | |
226 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 | |
227 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 | |
228 | #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 | |
229 | #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 | |
230 | ||
00ac6f6b AD |
231 | /* GFX9 and later: */ |
232 | #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 | |
233 | #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f | |
234 | ||
235 | /* Set/Get helpers for tiling flags. */ | |
fbd76d59 | 236 | #define AMDGPU_TILING_SET(field, value) \ |
00ac6f6b | 237 | (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) |
fbd76d59 | 238 | #define AMDGPU_TILING_GET(value, field) \ |
00ac6f6b | 239 | (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) |
81629cba AD |
240 | |
241 | #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 | |
242 | #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 | |
243 | ||
244 | /** The same structure is shared for input/output */ | |
245 | struct drm_amdgpu_gem_metadata { | |
675da0dd | 246 | /** GEM Object handle */ |
2ce9dde0 | 247 | __u32 handle; |
675da0dd | 248 | /** Do we want get or set metadata */ |
2ce9dde0 | 249 | __u32 op; |
81629cba | 250 | struct { |
675da0dd | 251 | /** For future use, no flags defined so far */ |
2ce9dde0 | 252 | __u64 flags; |
675da0dd | 253 | /** family specific tiling info */ |
2ce9dde0 MR |
254 | __u64 tiling_info; |
255 | __u32 data_size_bytes; | |
256 | __u32 data[64]; | |
81629cba AD |
257 | } data; |
258 | }; | |
259 | ||
260 | struct drm_amdgpu_gem_mmap_in { | |
675da0dd | 261 | /** the GEM object handle */ |
2ce9dde0 MR |
262 | __u32 handle; |
263 | __u32 _pad; | |
81629cba AD |
264 | }; |
265 | ||
266 | struct drm_amdgpu_gem_mmap_out { | |
675da0dd | 267 | /** mmap offset from the vma offset manager */ |
2ce9dde0 | 268 | __u64 addr_ptr; |
81629cba AD |
269 | }; |
270 | ||
271 | union drm_amdgpu_gem_mmap { | |
272 | struct drm_amdgpu_gem_mmap_in in; | |
273 | struct drm_amdgpu_gem_mmap_out out; | |
274 | }; | |
275 | ||
276 | struct drm_amdgpu_gem_wait_idle_in { | |
675da0dd | 277 | /** GEM object handle */ |
2ce9dde0 | 278 | __u32 handle; |
675da0dd | 279 | /** For future use, no flags defined so far */ |
2ce9dde0 | 280 | __u32 flags; |
675da0dd | 281 | /** Absolute timeout to wait */ |
2ce9dde0 | 282 | __u64 timeout; |
81629cba AD |
283 | }; |
284 | ||
285 | struct drm_amdgpu_gem_wait_idle_out { | |
675da0dd | 286 | /** BO status: 0 - BO is idle, 1 - BO is busy */ |
2ce9dde0 | 287 | __u32 status; |
675da0dd | 288 | /** Returned current memory domain */ |
2ce9dde0 | 289 | __u32 domain; |
81629cba AD |
290 | }; |
291 | ||
292 | union drm_amdgpu_gem_wait_idle { | |
293 | struct drm_amdgpu_gem_wait_idle_in in; | |
294 | struct drm_amdgpu_gem_wait_idle_out out; | |
295 | }; | |
296 | ||
297 | struct drm_amdgpu_wait_cs_in { | |
675da0dd | 298 | /** Command submission handle */ |
2ce9dde0 | 299 | __u64 handle; |
675da0dd | 300 | /** Absolute timeout to wait */ |
2ce9dde0 MR |
301 | __u64 timeout; |
302 | __u32 ip_type; | |
303 | __u32 ip_instance; | |
304 | __u32 ring; | |
305 | __u32 ctx_id; | |
81629cba AD |
306 | }; |
307 | ||
308 | struct drm_amdgpu_wait_cs_out { | |
675da0dd | 309 | /** CS status: 0 - CS completed, 1 - CS still busy */ |
2ce9dde0 | 310 | __u64 status; |
81629cba AD |
311 | }; |
312 | ||
313 | union drm_amdgpu_wait_cs { | |
314 | struct drm_amdgpu_wait_cs_in in; | |
315 | struct drm_amdgpu_wait_cs_out out; | |
316 | }; | |
317 | ||
eef18a82 JZ |
318 | struct drm_amdgpu_fence { |
319 | __u32 ctx_id; | |
320 | __u32 ip_type; | |
321 | __u32 ip_instance; | |
322 | __u32 ring; | |
323 | __u64 seq_no; | |
324 | }; | |
325 | ||
326 | struct drm_amdgpu_wait_fences_in { | |
327 | /** This points to uint64_t * which points to fences */ | |
328 | __u64 fences; | |
329 | __u32 fence_count; | |
330 | __u32 wait_all; | |
331 | __u64 timeout_ns; | |
332 | }; | |
333 | ||
334 | struct drm_amdgpu_wait_fences_out { | |
335 | __u32 status; | |
336 | __u32 first_signaled; | |
337 | }; | |
338 | ||
339 | union drm_amdgpu_wait_fences { | |
340 | struct drm_amdgpu_wait_fences_in in; | |
341 | struct drm_amdgpu_wait_fences_out out; | |
342 | }; | |
343 | ||
675da0dd CK |
344 | #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 |
345 | #define AMDGPU_GEM_OP_SET_PLACEMENT 1 | |
346 | ||
81629cba AD |
347 | /* Sets or returns a value associated with a buffer. */ |
348 | struct drm_amdgpu_gem_op { | |
675da0dd | 349 | /** GEM object handle */ |
2ce9dde0 | 350 | __u32 handle; |
675da0dd | 351 | /** AMDGPU_GEM_OP_* */ |
2ce9dde0 | 352 | __u32 op; |
675da0dd | 353 | /** Input or return value */ |
2ce9dde0 | 354 | __u64 value; |
81629cba AD |
355 | }; |
356 | ||
81629cba AD |
357 | #define AMDGPU_VA_OP_MAP 1 |
358 | #define AMDGPU_VA_OP_UNMAP 2 | |
dc54d3d1 | 359 | #define AMDGPU_VA_OP_CLEAR 3 |
80f95c57 | 360 | #define AMDGPU_VA_OP_REPLACE 4 |
81629cba | 361 | |
fc220f65 CK |
362 | /* Delay the page table update till the next CS */ |
363 | #define AMDGPU_VM_DELAY_UPDATE (1 << 0) | |
364 | ||
81629cba AD |
365 | /* Mapping flags */ |
366 | /* readable mapping */ | |
367 | #define AMDGPU_VM_PAGE_READABLE (1 << 1) | |
368 | /* writable mapping */ | |
369 | #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) | |
370 | /* executable mapping, new for VI */ | |
371 | #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) | |
b85891bd JZ |
372 | /* partially resident texture */ |
373 | #define AMDGPU_VM_PAGE_PRT (1 << 4) | |
66e02bc3 AX |
374 | /* MTYPE flags use bit 5 to 8 */ |
375 | #define AMDGPU_VM_MTYPE_MASK (0xf << 5) | |
376 | /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ | |
377 | #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) | |
378 | /* Use NC MTYPE instead of default MTYPE */ | |
379 | #define AMDGPU_VM_MTYPE_NC (1 << 5) | |
380 | /* Use WC MTYPE instead of default MTYPE */ | |
381 | #define AMDGPU_VM_MTYPE_WC (2 << 5) | |
382 | /* Use CC MTYPE instead of default MTYPE */ | |
383 | #define AMDGPU_VM_MTYPE_CC (3 << 5) | |
384 | /* Use UC MTYPE instead of default MTYPE */ | |
385 | #define AMDGPU_VM_MTYPE_UC (4 << 5) | |
81629cba | 386 | |
34b5f6a6 | 387 | struct drm_amdgpu_gem_va { |
675da0dd | 388 | /** GEM object handle */ |
2ce9dde0 MR |
389 | __u32 handle; |
390 | __u32 _pad; | |
675da0dd | 391 | /** AMDGPU_VA_OP_* */ |
2ce9dde0 | 392 | __u32 operation; |
675da0dd | 393 | /** AMDGPU_VM_PAGE_* */ |
2ce9dde0 | 394 | __u32 flags; |
675da0dd | 395 | /** va address to assign . Must be correctly aligned.*/ |
2ce9dde0 | 396 | __u64 va_address; |
675da0dd | 397 | /** Specify offset inside of BO to assign. Must be correctly aligned.*/ |
2ce9dde0 | 398 | __u64 offset_in_bo; |
675da0dd | 399 | /** Specify mapping size. Must be correctly aligned. */ |
2ce9dde0 | 400 | __u64 map_size; |
81629cba AD |
401 | }; |
402 | ||
81629cba AD |
403 | #define AMDGPU_HW_IP_GFX 0 |
404 | #define AMDGPU_HW_IP_COMPUTE 1 | |
405 | #define AMDGPU_HW_IP_DMA 2 | |
406 | #define AMDGPU_HW_IP_UVD 3 | |
407 | #define AMDGPU_HW_IP_VCE 4 | |
a50798b6 LL |
408 | #define AMDGPU_HW_IP_UVD_ENC 5 |
409 | #define AMDGPU_HW_IP_NUM 6 | |
81629cba AD |
410 | |
411 | #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 | |
412 | ||
413 | #define AMDGPU_CHUNK_ID_IB 0x01 | |
414 | #define AMDGPU_CHUNK_ID_FENCE 0x02 | |
2b48d323 | 415 | #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 |
675da0dd | 416 | |
81629cba | 417 | struct drm_amdgpu_cs_chunk { |
2ce9dde0 MR |
418 | __u32 chunk_id; |
419 | __u32 length_dw; | |
420 | __u64 chunk_data; | |
81629cba AD |
421 | }; |
422 | ||
423 | struct drm_amdgpu_cs_in { | |
424 | /** Rendering context id */ | |
2ce9dde0 | 425 | __u32 ctx_id; |
81629cba | 426 | /** Handle of resource list associated with CS */ |
2ce9dde0 MR |
427 | __u32 bo_list_handle; |
428 | __u32 num_chunks; | |
429 | __u32 _pad; | |
430 | /** this points to __u64 * which point to cs chunks */ | |
431 | __u64 chunks; | |
81629cba AD |
432 | }; |
433 | ||
434 | struct drm_amdgpu_cs_out { | |
2ce9dde0 | 435 | __u64 handle; |
81629cba AD |
436 | }; |
437 | ||
438 | union drm_amdgpu_cs { | |
675da0dd CK |
439 | struct drm_amdgpu_cs_in in; |
440 | struct drm_amdgpu_cs_out out; | |
81629cba AD |
441 | }; |
442 | ||
443 | /* Specify flags to be used for IB */ | |
444 | ||
445 | /* This IB should be submitted to CE */ | |
446 | #define AMDGPU_IB_FLAG_CE (1<<0) | |
447 | ||
ed834af2 | 448 | /* Preamble flag, which means the IB could be dropped if no context switch */ |
cab6d57c | 449 | #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) |
aa2bdb24 | 450 | |
81629cba | 451 | struct drm_amdgpu_cs_chunk_ib { |
2ce9dde0 | 452 | __u32 _pad; |
675da0dd | 453 | /** AMDGPU_IB_FLAG_* */ |
2ce9dde0 | 454 | __u32 flags; |
675da0dd | 455 | /** Virtual address to begin IB execution */ |
2ce9dde0 | 456 | __u64 va_start; |
675da0dd | 457 | /** Size of submission */ |
2ce9dde0 | 458 | __u32 ib_bytes; |
675da0dd | 459 | /** HW IP to submit to */ |
2ce9dde0 | 460 | __u32 ip_type; |
675da0dd | 461 | /** HW IP index of the same type to submit to */ |
2ce9dde0 | 462 | __u32 ip_instance; |
675da0dd | 463 | /** Ring index to submit to */ |
2ce9dde0 | 464 | __u32 ring; |
81629cba AD |
465 | }; |
466 | ||
2b48d323 | 467 | struct drm_amdgpu_cs_chunk_dep { |
2ce9dde0 MR |
468 | __u32 ip_type; |
469 | __u32 ip_instance; | |
470 | __u32 ring; | |
471 | __u32 ctx_id; | |
472 | __u64 handle; | |
2b48d323 CK |
473 | }; |
474 | ||
81629cba | 475 | struct drm_amdgpu_cs_chunk_fence { |
2ce9dde0 MR |
476 | __u32 handle; |
477 | __u32 offset; | |
81629cba AD |
478 | }; |
479 | ||
480 | struct drm_amdgpu_cs_chunk_data { | |
481 | union { | |
482 | struct drm_amdgpu_cs_chunk_ib ib_data; | |
483 | struct drm_amdgpu_cs_chunk_fence fence_data; | |
484 | }; | |
485 | }; | |
486 | ||
487 | /** | |
488 | * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU | |
489 | * | |
490 | */ | |
491 | #define AMDGPU_IDS_FLAGS_FUSION 0x1 | |
aafcafa0 | 492 | #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 |
81629cba AD |
493 | |
494 | /* indicate if acceleration can be working */ | |
495 | #define AMDGPU_INFO_ACCEL_WORKING 0x00 | |
496 | /* get the crtc_id from the mode object id? */ | |
497 | #define AMDGPU_INFO_CRTC_FROM_ID 0x01 | |
498 | /* query hw IP info */ | |
499 | #define AMDGPU_INFO_HW_IP_INFO 0x02 | |
500 | /* query hw IP instance count for the specified type */ | |
501 | #define AMDGPU_INFO_HW_IP_COUNT 0x03 | |
502 | /* timestamp for GL_ARB_timer_query */ | |
503 | #define AMDGPU_INFO_TIMESTAMP 0x05 | |
504 | /* Query the firmware version */ | |
505 | #define AMDGPU_INFO_FW_VERSION 0x0e | |
506 | /* Subquery id: Query VCE firmware version */ | |
507 | #define AMDGPU_INFO_FW_VCE 0x1 | |
508 | /* Subquery id: Query UVD firmware version */ | |
509 | #define AMDGPU_INFO_FW_UVD 0x2 | |
510 | /* Subquery id: Query GMC firmware version */ | |
511 | #define AMDGPU_INFO_FW_GMC 0x03 | |
512 | /* Subquery id: Query GFX ME firmware version */ | |
513 | #define AMDGPU_INFO_FW_GFX_ME 0x04 | |
514 | /* Subquery id: Query GFX PFP firmware version */ | |
515 | #define AMDGPU_INFO_FW_GFX_PFP 0x05 | |
516 | /* Subquery id: Query GFX CE firmware version */ | |
517 | #define AMDGPU_INFO_FW_GFX_CE 0x06 | |
518 | /* Subquery id: Query GFX RLC firmware version */ | |
519 | #define AMDGPU_INFO_FW_GFX_RLC 0x07 | |
520 | /* Subquery id: Query GFX MEC firmware version */ | |
521 | #define AMDGPU_INFO_FW_GFX_MEC 0x08 | |
522 | /* Subquery id: Query SMC firmware version */ | |
523 | #define AMDGPU_INFO_FW_SMC 0x0a | |
524 | /* Subquery id: Query SDMA firmware version */ | |
525 | #define AMDGPU_INFO_FW_SDMA 0x0b | |
6a7ed07e HR |
526 | /* Subquery id: Query PSP SOS firmware version */ |
527 | #define AMDGPU_INFO_FW_SOS 0x0c | |
528 | /* Subquery id: Query PSP ASD firmware version */ | |
529 | #define AMDGPU_INFO_FW_ASD 0x0d | |
81629cba AD |
530 | /* number of bytes moved for TTM migration */ |
531 | #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f | |
532 | /* the used VRAM size */ | |
533 | #define AMDGPU_INFO_VRAM_USAGE 0x10 | |
534 | /* the used GTT size */ | |
535 | #define AMDGPU_INFO_GTT_USAGE 0x11 | |
536 | /* Information about GDS, etc. resource configuration */ | |
537 | #define AMDGPU_INFO_GDS_CONFIG 0x13 | |
538 | /* Query information about VRAM and GTT domains */ | |
539 | #define AMDGPU_INFO_VRAM_GTT 0x14 | |
540 | /* Query information about register in MMR address space*/ | |
541 | #define AMDGPU_INFO_READ_MMR_REG 0x15 | |
542 | /* Query information about device: rev id, family, etc. */ | |
543 | #define AMDGPU_INFO_DEV_INFO 0x16 | |
544 | /* visible vram usage */ | |
545 | #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 | |
83a59b63 MO |
546 | /* number of TTM buffer evictions */ |
547 | #define AMDGPU_INFO_NUM_EVICTIONS 0x18 | |
e0adf6c8 JZ |
548 | /* Query memory about VRAM and GTT domains */ |
549 | #define AMDGPU_INFO_MEMORY 0x19 | |
bbe87974 AD |
550 | /* Query vce clock table */ |
551 | #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A | |
40ee5888 EQ |
552 | /* Query vbios related information */ |
553 | #define AMDGPU_INFO_VBIOS 0x1B | |
554 | /* Subquery id: Query vbios size */ | |
555 | #define AMDGPU_INFO_VBIOS_SIZE 0x1 | |
556 | /* Subquery id: Query vbios image */ | |
557 | #define AMDGPU_INFO_VBIOS_IMAGE 0x2 | |
44879b62 AN |
558 | /* Query UVD handles */ |
559 | #define AMDGPU_INFO_NUM_HANDLES 0x1C | |
5ebbac4b AD |
560 | /* Query sensor related information */ |
561 | #define AMDGPU_INFO_SENSOR 0x1D | |
562 | /* Subquery id: Query GPU shader clock */ | |
563 | #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 | |
564 | /* Subquery id: Query GPU memory clock */ | |
565 | #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 | |
566 | /* Subquery id: Query GPU temperature */ | |
567 | #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 | |
568 | /* Subquery id: Query GPU load */ | |
569 | #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 | |
570 | /* Subquery id: Query average GPU power */ | |
571 | #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 | |
572 | /* Subquery id: Query northbridge voltage */ | |
573 | #define AMDGPU_INFO_SENSOR_VDDNB 0x6 | |
574 | /* Subquery id: Query graphics voltage */ | |
575 | #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 | |
81629cba AD |
576 | |
577 | #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 | |
578 | #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff | |
579 | #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 | |
580 | #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff | |
581 | ||
000cab9a HR |
582 | struct drm_amdgpu_query_fw { |
583 | /** AMDGPU_INFO_FW_* */ | |
584 | __u32 fw_type; | |
585 | /** | |
586 | * Index of the IP if there are more IPs of | |
587 | * the same type. | |
588 | */ | |
589 | __u32 ip_instance; | |
590 | /** | |
591 | * Index of the engine. Whether this is used depends | |
592 | * on the firmware type. (e.g. MEC, SDMA) | |
593 | */ | |
594 | __u32 index; | |
595 | __u32 _pad; | |
596 | }; | |
597 | ||
81629cba AD |
598 | /* Input structure for the INFO ioctl */ |
599 | struct drm_amdgpu_info { | |
600 | /* Where the return value will be stored */ | |
2ce9dde0 | 601 | __u64 return_pointer; |
81629cba AD |
602 | /* The size of the return value. Just like "size" in "snprintf", |
603 | * it limits how many bytes the kernel can write. */ | |
2ce9dde0 | 604 | __u32 return_size; |
81629cba | 605 | /* The query request id. */ |
2ce9dde0 | 606 | __u32 query; |
81629cba AD |
607 | |
608 | union { | |
609 | struct { | |
2ce9dde0 MR |
610 | __u32 id; |
611 | __u32 _pad; | |
81629cba AD |
612 | } mode_crtc; |
613 | ||
614 | struct { | |
615 | /** AMDGPU_HW_IP_* */ | |
2ce9dde0 | 616 | __u32 type; |
81629cba | 617 | /** |
675da0dd CK |
618 | * Index of the IP if there are more IPs of the same |
619 | * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. | |
81629cba | 620 | */ |
2ce9dde0 | 621 | __u32 ip_instance; |
81629cba AD |
622 | } query_hw_ip; |
623 | ||
624 | struct { | |
2ce9dde0 | 625 | __u32 dword_offset; |
675da0dd | 626 | /** number of registers to read */ |
2ce9dde0 MR |
627 | __u32 count; |
628 | __u32 instance; | |
675da0dd | 629 | /** For future use, no flags defined so far */ |
2ce9dde0 | 630 | __u32 flags; |
81629cba AD |
631 | } read_mmr_reg; |
632 | ||
000cab9a | 633 | struct drm_amdgpu_query_fw query_fw; |
40ee5888 EQ |
634 | |
635 | struct { | |
636 | __u32 type; | |
637 | __u32 offset; | |
638 | } vbios_info; | |
5ebbac4b AD |
639 | |
640 | struct { | |
641 | __u32 type; | |
642 | } sensor_info; | |
81629cba AD |
643 | }; |
644 | }; | |
645 | ||
646 | struct drm_amdgpu_info_gds { | |
647 | /** GDS GFX partition size */ | |
2ce9dde0 | 648 | __u32 gds_gfx_partition_size; |
81629cba | 649 | /** GDS compute partition size */ |
2ce9dde0 | 650 | __u32 compute_partition_size; |
81629cba | 651 | /** total GDS memory size */ |
2ce9dde0 | 652 | __u32 gds_total_size; |
81629cba | 653 | /** GWS size per GFX partition */ |
2ce9dde0 | 654 | __u32 gws_per_gfx_partition; |
81629cba | 655 | /** GSW size per compute partition */ |
2ce9dde0 | 656 | __u32 gws_per_compute_partition; |
81629cba | 657 | /** OA size per GFX partition */ |
2ce9dde0 | 658 | __u32 oa_per_gfx_partition; |
81629cba | 659 | /** OA size per compute partition */ |
2ce9dde0 MR |
660 | __u32 oa_per_compute_partition; |
661 | __u32 _pad; | |
81629cba AD |
662 | }; |
663 | ||
664 | struct drm_amdgpu_info_vram_gtt { | |
2ce9dde0 MR |
665 | __u64 vram_size; |
666 | __u64 vram_cpu_accessible_size; | |
667 | __u64 gtt_size; | |
81629cba AD |
668 | }; |
669 | ||
e0adf6c8 JZ |
670 | struct drm_amdgpu_heap_info { |
671 | /** max. physical memory */ | |
672 | __u64 total_heap_size; | |
673 | ||
674 | /** Theoretical max. available memory in the given heap */ | |
675 | __u64 usable_heap_size; | |
676 | ||
677 | /** | |
678 | * Number of bytes allocated in the heap. This includes all processes | |
679 | * and private allocations in the kernel. It changes when new buffers | |
680 | * are allocated, freed, and moved. It cannot be larger than | |
681 | * heap_size. | |
682 | */ | |
683 | __u64 heap_usage; | |
684 | ||
685 | /** | |
686 | * Theoretical possible max. size of buffer which | |
687 | * could be allocated in the given heap | |
688 | */ | |
689 | __u64 max_allocation; | |
9f6163e7 JZ |
690 | }; |
691 | ||
e0adf6c8 JZ |
692 | struct drm_amdgpu_memory_info { |
693 | struct drm_amdgpu_heap_info vram; | |
694 | struct drm_amdgpu_heap_info cpu_accessible_vram; | |
695 | struct drm_amdgpu_heap_info gtt; | |
cfa32556 JZ |
696 | }; |
697 | ||
81629cba | 698 | struct drm_amdgpu_info_firmware { |
2ce9dde0 MR |
699 | __u32 ver; |
700 | __u32 feature; | |
81629cba AD |
701 | }; |
702 | ||
81c59f54 KW |
703 | #define AMDGPU_VRAM_TYPE_UNKNOWN 0 |
704 | #define AMDGPU_VRAM_TYPE_GDDR1 1 | |
705 | #define AMDGPU_VRAM_TYPE_DDR2 2 | |
706 | #define AMDGPU_VRAM_TYPE_GDDR3 3 | |
707 | #define AMDGPU_VRAM_TYPE_GDDR4 4 | |
708 | #define AMDGPU_VRAM_TYPE_GDDR5 5 | |
709 | #define AMDGPU_VRAM_TYPE_HBM 6 | |
710 | #define AMDGPU_VRAM_TYPE_DDR3 7 | |
711 | ||
81629cba AD |
712 | struct drm_amdgpu_info_device { |
713 | /** PCI Device ID */ | |
2ce9dde0 | 714 | __u32 device_id; |
81629cba | 715 | /** Internal chip revision: A0, A1, etc.) */ |
2ce9dde0 MR |
716 | __u32 chip_rev; |
717 | __u32 external_rev; | |
81629cba | 718 | /** Revision id in PCI Config space */ |
2ce9dde0 MR |
719 | __u32 pci_rev; |
720 | __u32 family; | |
721 | __u32 num_shader_engines; | |
722 | __u32 num_shader_arrays_per_engine; | |
675da0dd | 723 | /* in KHz */ |
2ce9dde0 MR |
724 | __u32 gpu_counter_freq; |
725 | __u64 max_engine_clock; | |
726 | __u64 max_memory_clock; | |
81629cba | 727 | /* cu information */ |
2ce9dde0 MR |
728 | __u32 cu_active_number; |
729 | __u32 cu_ao_mask; | |
730 | __u32 cu_bitmap[4][4]; | |
81629cba | 731 | /** Render backend pipe mask. One render backend is CB+DB. */ |
2ce9dde0 MR |
732 | __u32 enabled_rb_pipes_mask; |
733 | __u32 num_rb_pipes; | |
734 | __u32 num_hw_gfx_contexts; | |
735 | __u32 _pad; | |
736 | __u64 ids_flags; | |
81629cba | 737 | /** Starting virtual address for UMDs. */ |
2ce9dde0 | 738 | __u64 virtual_address_offset; |
02b70c8c | 739 | /** The maximum virtual address */ |
2ce9dde0 | 740 | __u64 virtual_address_max; |
81629cba | 741 | /** Required alignment of virtual addresses. */ |
2ce9dde0 | 742 | __u32 virtual_address_alignment; |
81629cba | 743 | /** Page table entry - fragment size */ |
2ce9dde0 MR |
744 | __u32 pte_fragment_size; |
745 | __u32 gart_page_size; | |
a101a899 | 746 | /** constant engine ram size*/ |
2ce9dde0 | 747 | __u32 ce_ram_size; |
cab6d57c | 748 | /** video memory type info*/ |
2ce9dde0 | 749 | __u32 vram_type; |
81c59f54 | 750 | /** video memory bit width*/ |
2ce9dde0 | 751 | __u32 vram_bit_width; |
fa92754e | 752 | /* vce harvesting instance */ |
2ce9dde0 | 753 | __u32 vce_harvest_config; |
df6e2c4a JZ |
754 | /* gfx double offchip LDS buffers */ |
755 | __u32 gc_double_offchip_lds_buf; | |
bce23e00 AD |
756 | /* NGG Primitive Buffer */ |
757 | __u64 prim_buf_gpu_addr; | |
758 | /* NGG Position Buffer */ | |
759 | __u64 pos_buf_gpu_addr; | |
760 | /* NGG Control Sideband */ | |
761 | __u64 cntl_sb_buf_gpu_addr; | |
762 | /* NGG Parameter Cache */ | |
763 | __u64 param_buf_gpu_addr; | |
81629cba AD |
764 | }; |
765 | ||
766 | struct drm_amdgpu_info_hw_ip { | |
767 | /** Version of h/w IP */ | |
2ce9dde0 MR |
768 | __u32 hw_ip_version_major; |
769 | __u32 hw_ip_version_minor; | |
81629cba | 770 | /** Capabilities */ |
2ce9dde0 | 771 | __u64 capabilities_flags; |
71062f43 | 772 | /** command buffer address start alignment*/ |
2ce9dde0 | 773 | __u32 ib_start_alignment; |
71062f43 | 774 | /** command buffer size alignment*/ |
2ce9dde0 | 775 | __u32 ib_size_alignment; |
81629cba | 776 | /** Bitmask of available rings. Bit 0 means ring 0, etc. */ |
2ce9dde0 MR |
777 | __u32 available_rings; |
778 | __u32 _pad; | |
81629cba AD |
779 | }; |
780 | ||
44879b62 AN |
781 | struct drm_amdgpu_info_num_handles { |
782 | /** Max handles as supported by firmware for UVD */ | |
783 | __u32 uvd_max_handles; | |
784 | /** Handles currently in use for UVD */ | |
785 | __u32 uvd_used_handles; | |
786 | }; | |
787 | ||
bbe87974 AD |
788 | #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 |
789 | ||
790 | struct drm_amdgpu_info_vce_clock_table_entry { | |
791 | /** System clock */ | |
792 | __u32 sclk; | |
793 | /** Memory clock */ | |
794 | __u32 mclk; | |
795 | /** VCE clock */ | |
796 | __u32 eclk; | |
797 | __u32 pad; | |
798 | }; | |
799 | ||
800 | struct drm_amdgpu_info_vce_clock_table { | |
801 | struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; | |
802 | __u32 num_valid_entries; | |
803 | __u32 pad; | |
804 | }; | |
805 | ||
81629cba AD |
806 | /* |
807 | * Supported GPU families | |
808 | */ | |
809 | #define AMDGPU_FAMILY_UNKNOWN 0 | |
295d0daf | 810 | #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ |
81629cba AD |
811 | #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ |
812 | #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ | |
813 | #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ | |
39bb0c92 | 814 | #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ |
a8f1f1ce | 815 | #define AMDGPU_FAMILY_AI 141 /* Vega10 */ |
81629cba | 816 | |
cfa7152f EV |
817 | #if defined(__cplusplus) |
818 | } | |
819 | #endif | |
820 | ||
81629cba | 821 | #endif |