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81629cba AD |
1 | /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- |
2 | * | |
3 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. | |
4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. | |
5 | * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. | |
6 | * Copyright 2014 Advanced Micro Devices, Inc. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
22 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
23 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
24 | * OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | * Authors: | |
27 | * Kevin E. Martin <martin@valinux.com> | |
28 | * Gareth Hughes <gareth@valinux.com> | |
29 | * Keith Whitwell <keith@tungstengraphics.com> | |
30 | */ | |
31 | ||
32 | #ifndef __AMDGPU_DRM_H__ | |
33 | #define __AMDGPU_DRM_H__ | |
34 | ||
b3fcf36a | 35 | #include "drm.h" |
81629cba | 36 | |
cfa7152f EV |
37 | #if defined(__cplusplus) |
38 | extern "C" { | |
39 | #endif | |
40 | ||
81629cba AD |
41 | #define DRM_AMDGPU_GEM_CREATE 0x00 |
42 | #define DRM_AMDGPU_GEM_MMAP 0x01 | |
43 | #define DRM_AMDGPU_CTX 0x02 | |
44 | #define DRM_AMDGPU_BO_LIST 0x03 | |
45 | #define DRM_AMDGPU_CS 0x04 | |
46 | #define DRM_AMDGPU_INFO 0x05 | |
47 | #define DRM_AMDGPU_GEM_METADATA 0x06 | |
48 | #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 | |
49 | #define DRM_AMDGPU_GEM_VA 0x08 | |
50 | #define DRM_AMDGPU_WAIT_CS 0x09 | |
51 | #define DRM_AMDGPU_GEM_OP 0x10 | |
52 | #define DRM_AMDGPU_GEM_USERPTR 0x11 | |
eef18a82 | 53 | #define DRM_AMDGPU_WAIT_FENCES 0x12 |
cfbcacf4 | 54 | #define DRM_AMDGPU_VM 0x13 |
81629cba AD |
55 | |
56 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) | |
57 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) | |
58 | #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) | |
59 | #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) | |
60 | #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) | |
61 | #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) | |
62 | #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) | |
63 | #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) | |
34b5f6a6 | 64 | #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) |
81629cba AD |
65 | #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) |
66 | #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) | |
67 | #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) | |
eef18a82 | 68 | #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) |
cfbcacf4 | 69 | #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) |
81629cba AD |
70 | |
71 | #define AMDGPU_GEM_DOMAIN_CPU 0x1 | |
72 | #define AMDGPU_GEM_DOMAIN_GTT 0x2 | |
73 | #define AMDGPU_GEM_DOMAIN_VRAM 0x4 | |
74 | #define AMDGPU_GEM_DOMAIN_GDS 0x8 | |
75 | #define AMDGPU_GEM_DOMAIN_GWS 0x10 | |
76 | #define AMDGPU_GEM_DOMAIN_OA 0x20 | |
77 | ||
81629cba AD |
78 | /* Flag that CPU access will be required for the case of VRAM domain */ |
79 | #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) | |
80 | /* Flag that CPU access will not work, this VRAM domain is invisible */ | |
81 | #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) | |
81629cba | 82 | /* Flag that USWC attributes should be used for GTT */ |
88671288 | 83 | #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) |
4fea83ff FC |
84 | /* Flag that the memory should be in VRAM and cleared */ |
85 | #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) | |
e7893c4b CZ |
86 | /* Flag that create shadow bo(GTT) while allocating vram bo */ |
87 | #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) | |
03f48dd5 CK |
88 | /* Flag that allocating the BO should use linear VRAM */ |
89 | #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) | |
81629cba | 90 | |
81629cba AD |
91 | struct drm_amdgpu_gem_create_in { |
92 | /** the requested memory size */ | |
2ce9dde0 | 93 | __u64 bo_size; |
81629cba | 94 | /** physical start_addr alignment in bytes for some HW requirements */ |
2ce9dde0 | 95 | __u64 alignment; |
81629cba | 96 | /** the requested memory domains */ |
2ce9dde0 | 97 | __u64 domains; |
81629cba | 98 | /** allocation flags */ |
2ce9dde0 | 99 | __u64 domain_flags; |
81629cba AD |
100 | }; |
101 | ||
102 | struct drm_amdgpu_gem_create_out { | |
103 | /** returned GEM object handle */ | |
2ce9dde0 MR |
104 | __u32 handle; |
105 | __u32 _pad; | |
81629cba AD |
106 | }; |
107 | ||
108 | union drm_amdgpu_gem_create { | |
109 | struct drm_amdgpu_gem_create_in in; | |
110 | struct drm_amdgpu_gem_create_out out; | |
111 | }; | |
112 | ||
113 | /** Opcode to create new residency list. */ | |
114 | #define AMDGPU_BO_LIST_OP_CREATE 0 | |
115 | /** Opcode to destroy previously created residency list */ | |
116 | #define AMDGPU_BO_LIST_OP_DESTROY 1 | |
117 | /** Opcode to update resource information in the list */ | |
118 | #define AMDGPU_BO_LIST_OP_UPDATE 2 | |
119 | ||
120 | struct drm_amdgpu_bo_list_in { | |
121 | /** Type of operation */ | |
2ce9dde0 | 122 | __u32 operation; |
81629cba | 123 | /** Handle of list or 0 if we want to create one */ |
2ce9dde0 | 124 | __u32 list_handle; |
81629cba | 125 | /** Number of BOs in list */ |
2ce9dde0 | 126 | __u32 bo_number; |
81629cba | 127 | /** Size of each element describing BO */ |
2ce9dde0 | 128 | __u32 bo_info_size; |
81629cba | 129 | /** Pointer to array describing BOs */ |
2ce9dde0 | 130 | __u64 bo_info_ptr; |
81629cba AD |
131 | }; |
132 | ||
133 | struct drm_amdgpu_bo_list_entry { | |
134 | /** Handle of BO */ | |
2ce9dde0 | 135 | __u32 bo_handle; |
81629cba | 136 | /** New (if specified) BO priority to be used during migration */ |
2ce9dde0 | 137 | __u32 bo_priority; |
81629cba AD |
138 | }; |
139 | ||
140 | struct drm_amdgpu_bo_list_out { | |
141 | /** Handle of resource list */ | |
2ce9dde0 MR |
142 | __u32 list_handle; |
143 | __u32 _pad; | |
81629cba AD |
144 | }; |
145 | ||
146 | union drm_amdgpu_bo_list { | |
147 | struct drm_amdgpu_bo_list_in in; | |
148 | struct drm_amdgpu_bo_list_out out; | |
149 | }; | |
150 | ||
151 | /* context related */ | |
152 | #define AMDGPU_CTX_OP_ALLOC_CTX 1 | |
153 | #define AMDGPU_CTX_OP_FREE_CTX 2 | |
154 | #define AMDGPU_CTX_OP_QUERY_STATE 3 | |
155 | ||
d94aed5a MO |
156 | /* GPU reset status */ |
157 | #define AMDGPU_CTX_NO_RESET 0 | |
675da0dd CK |
158 | /* this the context caused it */ |
159 | #define AMDGPU_CTX_GUILTY_RESET 1 | |
160 | /* some other context caused it */ | |
161 | #define AMDGPU_CTX_INNOCENT_RESET 2 | |
162 | /* unknown cause */ | |
163 | #define AMDGPU_CTX_UNKNOWN_RESET 3 | |
d94aed5a | 164 | |
81629cba | 165 | struct drm_amdgpu_ctx_in { |
675da0dd | 166 | /** AMDGPU_CTX_OP_* */ |
2ce9dde0 | 167 | __u32 op; |
675da0dd | 168 | /** For future use, no flags defined so far */ |
2ce9dde0 MR |
169 | __u32 flags; |
170 | __u32 ctx_id; | |
171 | __u32 _pad; | |
81629cba AD |
172 | }; |
173 | ||
174 | union drm_amdgpu_ctx_out { | |
175 | struct { | |
2ce9dde0 MR |
176 | __u32 ctx_id; |
177 | __u32 _pad; | |
81629cba AD |
178 | } alloc; |
179 | ||
180 | struct { | |
675da0dd | 181 | /** For future use, no flags defined so far */ |
2ce9dde0 | 182 | __u64 flags; |
d94aed5a | 183 | /** Number of resets caused by this context so far. */ |
2ce9dde0 | 184 | __u32 hangs; |
d94aed5a | 185 | /** Reset status since the last call of the ioctl. */ |
2ce9dde0 | 186 | __u32 reset_status; |
81629cba AD |
187 | } state; |
188 | }; | |
189 | ||
190 | union drm_amdgpu_ctx { | |
191 | struct drm_amdgpu_ctx_in in; | |
192 | union drm_amdgpu_ctx_out out; | |
193 | }; | |
194 | ||
cfbcacf4 CZ |
195 | /* vm ioctl */ |
196 | #define AMDGPU_VM_OP_RESERVE_VMID 1 | |
197 | #define AMDGPU_VM_OP_UNRESERVE_VMID 2 | |
198 | ||
199 | struct drm_amdgpu_vm_in { | |
200 | /** AMDGPU_VM_OP_* */ | |
201 | __u32 op; | |
202 | __u32 flags; | |
203 | }; | |
204 | ||
205 | struct drm_amdgpu_vm_out { | |
206 | /** For future use, no flags defined so far */ | |
207 | __u64 flags; | |
208 | }; | |
209 | ||
210 | union drm_amdgpu_vm { | |
211 | struct drm_amdgpu_vm_in in; | |
212 | struct drm_amdgpu_vm_out out; | |
213 | }; | |
214 | ||
81629cba AD |
215 | /* |
216 | * This is not a reliable API and you should expect it to fail for any | |
217 | * number of reasons and have fallback path that do not use userptr to | |
218 | * perform any operation. | |
219 | */ | |
220 | #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) | |
221 | #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) | |
222 | #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) | |
223 | #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) | |
224 | ||
225 | struct drm_amdgpu_gem_userptr { | |
2ce9dde0 MR |
226 | __u64 addr; |
227 | __u64 size; | |
675da0dd | 228 | /* AMDGPU_GEM_USERPTR_* */ |
2ce9dde0 | 229 | __u32 flags; |
675da0dd | 230 | /* Resulting GEM handle */ |
2ce9dde0 | 231 | __u32 handle; |
81629cba AD |
232 | }; |
233 | ||
00ac6f6b | 234 | /* SI-CI-VI: */ |
fbd76d59 MO |
235 | /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ |
236 | #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 | |
237 | #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf | |
238 | #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 | |
239 | #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f | |
240 | #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 | |
241 | #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 | |
242 | #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 | |
243 | #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 | |
244 | #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 | |
245 | #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 | |
246 | #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 | |
247 | #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 | |
248 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 | |
249 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 | |
250 | #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 | |
251 | #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 | |
252 | ||
00ac6f6b AD |
253 | /* GFX9 and later: */ |
254 | #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 | |
255 | #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f | |
256 | ||
257 | /* Set/Get helpers for tiling flags. */ | |
fbd76d59 | 258 | #define AMDGPU_TILING_SET(field, value) \ |
00ac6f6b | 259 | (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) |
fbd76d59 | 260 | #define AMDGPU_TILING_GET(value, field) \ |
00ac6f6b | 261 | (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) |
81629cba AD |
262 | |
263 | #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 | |
264 | #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 | |
265 | ||
266 | /** The same structure is shared for input/output */ | |
267 | struct drm_amdgpu_gem_metadata { | |
675da0dd | 268 | /** GEM Object handle */ |
2ce9dde0 | 269 | __u32 handle; |
675da0dd | 270 | /** Do we want get or set metadata */ |
2ce9dde0 | 271 | __u32 op; |
81629cba | 272 | struct { |
675da0dd | 273 | /** For future use, no flags defined so far */ |
2ce9dde0 | 274 | __u64 flags; |
675da0dd | 275 | /** family specific tiling info */ |
2ce9dde0 MR |
276 | __u64 tiling_info; |
277 | __u32 data_size_bytes; | |
278 | __u32 data[64]; | |
81629cba AD |
279 | } data; |
280 | }; | |
281 | ||
282 | struct drm_amdgpu_gem_mmap_in { | |
675da0dd | 283 | /** the GEM object handle */ |
2ce9dde0 MR |
284 | __u32 handle; |
285 | __u32 _pad; | |
81629cba AD |
286 | }; |
287 | ||
288 | struct drm_amdgpu_gem_mmap_out { | |
675da0dd | 289 | /** mmap offset from the vma offset manager */ |
2ce9dde0 | 290 | __u64 addr_ptr; |
81629cba AD |
291 | }; |
292 | ||
293 | union drm_amdgpu_gem_mmap { | |
294 | struct drm_amdgpu_gem_mmap_in in; | |
295 | struct drm_amdgpu_gem_mmap_out out; | |
296 | }; | |
297 | ||
298 | struct drm_amdgpu_gem_wait_idle_in { | |
675da0dd | 299 | /** GEM object handle */ |
2ce9dde0 | 300 | __u32 handle; |
675da0dd | 301 | /** For future use, no flags defined so far */ |
2ce9dde0 | 302 | __u32 flags; |
675da0dd | 303 | /** Absolute timeout to wait */ |
2ce9dde0 | 304 | __u64 timeout; |
81629cba AD |
305 | }; |
306 | ||
307 | struct drm_amdgpu_gem_wait_idle_out { | |
675da0dd | 308 | /** BO status: 0 - BO is idle, 1 - BO is busy */ |
2ce9dde0 | 309 | __u32 status; |
675da0dd | 310 | /** Returned current memory domain */ |
2ce9dde0 | 311 | __u32 domain; |
81629cba AD |
312 | }; |
313 | ||
314 | union drm_amdgpu_gem_wait_idle { | |
315 | struct drm_amdgpu_gem_wait_idle_in in; | |
316 | struct drm_amdgpu_gem_wait_idle_out out; | |
317 | }; | |
318 | ||
319 | struct drm_amdgpu_wait_cs_in { | |
d7b1eeb2 ML |
320 | /* Command submission handle |
321 | * handle equals 0 means none to wait for | |
080b24eb | 322 | * handle equals ~0ull means wait for the latest sequence number |
d7b1eeb2 | 323 | */ |
2ce9dde0 | 324 | __u64 handle; |
675da0dd | 325 | /** Absolute timeout to wait */ |
2ce9dde0 MR |
326 | __u64 timeout; |
327 | __u32 ip_type; | |
328 | __u32 ip_instance; | |
329 | __u32 ring; | |
330 | __u32 ctx_id; | |
81629cba AD |
331 | }; |
332 | ||
333 | struct drm_amdgpu_wait_cs_out { | |
675da0dd | 334 | /** CS status: 0 - CS completed, 1 - CS still busy */ |
2ce9dde0 | 335 | __u64 status; |
81629cba AD |
336 | }; |
337 | ||
338 | union drm_amdgpu_wait_cs { | |
339 | struct drm_amdgpu_wait_cs_in in; | |
340 | struct drm_amdgpu_wait_cs_out out; | |
341 | }; | |
342 | ||
eef18a82 JZ |
343 | struct drm_amdgpu_fence { |
344 | __u32 ctx_id; | |
345 | __u32 ip_type; | |
346 | __u32 ip_instance; | |
347 | __u32 ring; | |
348 | __u64 seq_no; | |
349 | }; | |
350 | ||
351 | struct drm_amdgpu_wait_fences_in { | |
352 | /** This points to uint64_t * which points to fences */ | |
353 | __u64 fences; | |
354 | __u32 fence_count; | |
355 | __u32 wait_all; | |
356 | __u64 timeout_ns; | |
357 | }; | |
358 | ||
359 | struct drm_amdgpu_wait_fences_out { | |
360 | __u32 status; | |
361 | __u32 first_signaled; | |
362 | }; | |
363 | ||
364 | union drm_amdgpu_wait_fences { | |
365 | struct drm_amdgpu_wait_fences_in in; | |
366 | struct drm_amdgpu_wait_fences_out out; | |
367 | }; | |
368 | ||
675da0dd CK |
369 | #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 |
370 | #define AMDGPU_GEM_OP_SET_PLACEMENT 1 | |
371 | ||
81629cba AD |
372 | /* Sets or returns a value associated with a buffer. */ |
373 | struct drm_amdgpu_gem_op { | |
675da0dd | 374 | /** GEM object handle */ |
2ce9dde0 | 375 | __u32 handle; |
675da0dd | 376 | /** AMDGPU_GEM_OP_* */ |
2ce9dde0 | 377 | __u32 op; |
675da0dd | 378 | /** Input or return value */ |
2ce9dde0 | 379 | __u64 value; |
81629cba AD |
380 | }; |
381 | ||
81629cba AD |
382 | #define AMDGPU_VA_OP_MAP 1 |
383 | #define AMDGPU_VA_OP_UNMAP 2 | |
dc54d3d1 | 384 | #define AMDGPU_VA_OP_CLEAR 3 |
80f95c57 | 385 | #define AMDGPU_VA_OP_REPLACE 4 |
81629cba | 386 | |
fc220f65 CK |
387 | /* Delay the page table update till the next CS */ |
388 | #define AMDGPU_VM_DELAY_UPDATE (1 << 0) | |
389 | ||
81629cba AD |
390 | /* Mapping flags */ |
391 | /* readable mapping */ | |
392 | #define AMDGPU_VM_PAGE_READABLE (1 << 1) | |
393 | /* writable mapping */ | |
394 | #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) | |
395 | /* executable mapping, new for VI */ | |
396 | #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) | |
b85891bd JZ |
397 | /* partially resident texture */ |
398 | #define AMDGPU_VM_PAGE_PRT (1 << 4) | |
66e02bc3 AX |
399 | /* MTYPE flags use bit 5 to 8 */ |
400 | #define AMDGPU_VM_MTYPE_MASK (0xf << 5) | |
401 | /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ | |
402 | #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) | |
403 | /* Use NC MTYPE instead of default MTYPE */ | |
404 | #define AMDGPU_VM_MTYPE_NC (1 << 5) | |
405 | /* Use WC MTYPE instead of default MTYPE */ | |
406 | #define AMDGPU_VM_MTYPE_WC (2 << 5) | |
407 | /* Use CC MTYPE instead of default MTYPE */ | |
408 | #define AMDGPU_VM_MTYPE_CC (3 << 5) | |
409 | /* Use UC MTYPE instead of default MTYPE */ | |
410 | #define AMDGPU_VM_MTYPE_UC (4 << 5) | |
81629cba | 411 | |
34b5f6a6 | 412 | struct drm_amdgpu_gem_va { |
675da0dd | 413 | /** GEM object handle */ |
2ce9dde0 MR |
414 | __u32 handle; |
415 | __u32 _pad; | |
675da0dd | 416 | /** AMDGPU_VA_OP_* */ |
2ce9dde0 | 417 | __u32 operation; |
675da0dd | 418 | /** AMDGPU_VM_PAGE_* */ |
2ce9dde0 | 419 | __u32 flags; |
675da0dd | 420 | /** va address to assign . Must be correctly aligned.*/ |
2ce9dde0 | 421 | __u64 va_address; |
675da0dd | 422 | /** Specify offset inside of BO to assign. Must be correctly aligned.*/ |
2ce9dde0 | 423 | __u64 offset_in_bo; |
675da0dd | 424 | /** Specify mapping size. Must be correctly aligned. */ |
2ce9dde0 | 425 | __u64 map_size; |
81629cba AD |
426 | }; |
427 | ||
81629cba AD |
428 | #define AMDGPU_HW_IP_GFX 0 |
429 | #define AMDGPU_HW_IP_COMPUTE 1 | |
430 | #define AMDGPU_HW_IP_DMA 2 | |
431 | #define AMDGPU_HW_IP_UVD 3 | |
432 | #define AMDGPU_HW_IP_VCE 4 | |
a50798b6 LL |
433 | #define AMDGPU_HW_IP_UVD_ENC 5 |
434 | #define AMDGPU_HW_IP_NUM 6 | |
81629cba AD |
435 | |
436 | #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 | |
437 | ||
438 | #define AMDGPU_CHUNK_ID_IB 0x01 | |
439 | #define AMDGPU_CHUNK_ID_FENCE 0x02 | |
2b48d323 | 440 | #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 |
675da0dd | 441 | |
81629cba | 442 | struct drm_amdgpu_cs_chunk { |
2ce9dde0 MR |
443 | __u32 chunk_id; |
444 | __u32 length_dw; | |
445 | __u64 chunk_data; | |
81629cba AD |
446 | }; |
447 | ||
448 | struct drm_amdgpu_cs_in { | |
449 | /** Rendering context id */ | |
2ce9dde0 | 450 | __u32 ctx_id; |
81629cba | 451 | /** Handle of resource list associated with CS */ |
2ce9dde0 MR |
452 | __u32 bo_list_handle; |
453 | __u32 num_chunks; | |
454 | __u32 _pad; | |
455 | /** this points to __u64 * which point to cs chunks */ | |
456 | __u64 chunks; | |
81629cba AD |
457 | }; |
458 | ||
459 | struct drm_amdgpu_cs_out { | |
2ce9dde0 | 460 | __u64 handle; |
81629cba AD |
461 | }; |
462 | ||
463 | union drm_amdgpu_cs { | |
675da0dd CK |
464 | struct drm_amdgpu_cs_in in; |
465 | struct drm_amdgpu_cs_out out; | |
81629cba AD |
466 | }; |
467 | ||
468 | /* Specify flags to be used for IB */ | |
469 | ||
470 | /* This IB should be submitted to CE */ | |
471 | #define AMDGPU_IB_FLAG_CE (1<<0) | |
472 | ||
ed834af2 | 473 | /* Preamble flag, which means the IB could be dropped if no context switch */ |
cab6d57c | 474 | #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) |
aa2bdb24 | 475 | |
71aec257 ML |
476 | /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ |
477 | #define AMDGPU_IB_FLAG_PREEMPT (1<<2) | |
478 | ||
81629cba | 479 | struct drm_amdgpu_cs_chunk_ib { |
2ce9dde0 | 480 | __u32 _pad; |
675da0dd | 481 | /** AMDGPU_IB_FLAG_* */ |
2ce9dde0 | 482 | __u32 flags; |
675da0dd | 483 | /** Virtual address to begin IB execution */ |
2ce9dde0 | 484 | __u64 va_start; |
675da0dd | 485 | /** Size of submission */ |
2ce9dde0 | 486 | __u32 ib_bytes; |
675da0dd | 487 | /** HW IP to submit to */ |
2ce9dde0 | 488 | __u32 ip_type; |
675da0dd | 489 | /** HW IP index of the same type to submit to */ |
2ce9dde0 | 490 | __u32 ip_instance; |
675da0dd | 491 | /** Ring index to submit to */ |
2ce9dde0 | 492 | __u32 ring; |
81629cba AD |
493 | }; |
494 | ||
2b48d323 | 495 | struct drm_amdgpu_cs_chunk_dep { |
2ce9dde0 MR |
496 | __u32 ip_type; |
497 | __u32 ip_instance; | |
498 | __u32 ring; | |
499 | __u32 ctx_id; | |
500 | __u64 handle; | |
2b48d323 CK |
501 | }; |
502 | ||
81629cba | 503 | struct drm_amdgpu_cs_chunk_fence { |
2ce9dde0 MR |
504 | __u32 handle; |
505 | __u32 offset; | |
81629cba AD |
506 | }; |
507 | ||
508 | struct drm_amdgpu_cs_chunk_data { | |
509 | union { | |
510 | struct drm_amdgpu_cs_chunk_ib ib_data; | |
511 | struct drm_amdgpu_cs_chunk_fence fence_data; | |
512 | }; | |
513 | }; | |
514 | ||
515 | /** | |
516 | * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU | |
517 | * | |
518 | */ | |
519 | #define AMDGPU_IDS_FLAGS_FUSION 0x1 | |
aafcafa0 | 520 | #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 |
81629cba AD |
521 | |
522 | /* indicate if acceleration can be working */ | |
523 | #define AMDGPU_INFO_ACCEL_WORKING 0x00 | |
524 | /* get the crtc_id from the mode object id? */ | |
525 | #define AMDGPU_INFO_CRTC_FROM_ID 0x01 | |
526 | /* query hw IP info */ | |
527 | #define AMDGPU_INFO_HW_IP_INFO 0x02 | |
528 | /* query hw IP instance count for the specified type */ | |
529 | #define AMDGPU_INFO_HW_IP_COUNT 0x03 | |
530 | /* timestamp for GL_ARB_timer_query */ | |
531 | #define AMDGPU_INFO_TIMESTAMP 0x05 | |
532 | /* Query the firmware version */ | |
533 | #define AMDGPU_INFO_FW_VERSION 0x0e | |
534 | /* Subquery id: Query VCE firmware version */ | |
535 | #define AMDGPU_INFO_FW_VCE 0x1 | |
536 | /* Subquery id: Query UVD firmware version */ | |
537 | #define AMDGPU_INFO_FW_UVD 0x2 | |
538 | /* Subquery id: Query GMC firmware version */ | |
539 | #define AMDGPU_INFO_FW_GMC 0x03 | |
540 | /* Subquery id: Query GFX ME firmware version */ | |
541 | #define AMDGPU_INFO_FW_GFX_ME 0x04 | |
542 | /* Subquery id: Query GFX PFP firmware version */ | |
543 | #define AMDGPU_INFO_FW_GFX_PFP 0x05 | |
544 | /* Subquery id: Query GFX CE firmware version */ | |
545 | #define AMDGPU_INFO_FW_GFX_CE 0x06 | |
546 | /* Subquery id: Query GFX RLC firmware version */ | |
547 | #define AMDGPU_INFO_FW_GFX_RLC 0x07 | |
548 | /* Subquery id: Query GFX MEC firmware version */ | |
549 | #define AMDGPU_INFO_FW_GFX_MEC 0x08 | |
550 | /* Subquery id: Query SMC firmware version */ | |
551 | #define AMDGPU_INFO_FW_SMC 0x0a | |
552 | /* Subquery id: Query SDMA firmware version */ | |
553 | #define AMDGPU_INFO_FW_SDMA 0x0b | |
6a7ed07e HR |
554 | /* Subquery id: Query PSP SOS firmware version */ |
555 | #define AMDGPU_INFO_FW_SOS 0x0c | |
556 | /* Subquery id: Query PSP ASD firmware version */ | |
557 | #define AMDGPU_INFO_FW_ASD 0x0d | |
81629cba AD |
558 | /* number of bytes moved for TTM migration */ |
559 | #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f | |
560 | /* the used VRAM size */ | |
561 | #define AMDGPU_INFO_VRAM_USAGE 0x10 | |
562 | /* the used GTT size */ | |
563 | #define AMDGPU_INFO_GTT_USAGE 0x11 | |
564 | /* Information about GDS, etc. resource configuration */ | |
565 | #define AMDGPU_INFO_GDS_CONFIG 0x13 | |
566 | /* Query information about VRAM and GTT domains */ | |
567 | #define AMDGPU_INFO_VRAM_GTT 0x14 | |
568 | /* Query information about register in MMR address space*/ | |
569 | #define AMDGPU_INFO_READ_MMR_REG 0x15 | |
570 | /* Query information about device: rev id, family, etc. */ | |
571 | #define AMDGPU_INFO_DEV_INFO 0x16 | |
572 | /* visible vram usage */ | |
573 | #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 | |
83a59b63 MO |
574 | /* number of TTM buffer evictions */ |
575 | #define AMDGPU_INFO_NUM_EVICTIONS 0x18 | |
e0adf6c8 JZ |
576 | /* Query memory about VRAM and GTT domains */ |
577 | #define AMDGPU_INFO_MEMORY 0x19 | |
bbe87974 AD |
578 | /* Query vce clock table */ |
579 | #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A | |
40ee5888 EQ |
580 | /* Query vbios related information */ |
581 | #define AMDGPU_INFO_VBIOS 0x1B | |
582 | /* Subquery id: Query vbios size */ | |
583 | #define AMDGPU_INFO_VBIOS_SIZE 0x1 | |
584 | /* Subquery id: Query vbios image */ | |
585 | #define AMDGPU_INFO_VBIOS_IMAGE 0x2 | |
44879b62 AN |
586 | /* Query UVD handles */ |
587 | #define AMDGPU_INFO_NUM_HANDLES 0x1C | |
5ebbac4b AD |
588 | /* Query sensor related information */ |
589 | #define AMDGPU_INFO_SENSOR 0x1D | |
590 | /* Subquery id: Query GPU shader clock */ | |
591 | #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 | |
592 | /* Subquery id: Query GPU memory clock */ | |
593 | #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 | |
594 | /* Subquery id: Query GPU temperature */ | |
595 | #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 | |
596 | /* Subquery id: Query GPU load */ | |
597 | #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 | |
598 | /* Subquery id: Query average GPU power */ | |
599 | #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 | |
600 | /* Subquery id: Query northbridge voltage */ | |
601 | #define AMDGPU_INFO_SENSOR_VDDNB 0x6 | |
602 | /* Subquery id: Query graphics voltage */ | |
603 | #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 | |
81629cba AD |
604 | |
605 | #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 | |
606 | #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff | |
607 | #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 | |
608 | #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff | |
609 | ||
000cab9a HR |
610 | struct drm_amdgpu_query_fw { |
611 | /** AMDGPU_INFO_FW_* */ | |
612 | __u32 fw_type; | |
613 | /** | |
614 | * Index of the IP if there are more IPs of | |
615 | * the same type. | |
616 | */ | |
617 | __u32 ip_instance; | |
618 | /** | |
619 | * Index of the engine. Whether this is used depends | |
620 | * on the firmware type. (e.g. MEC, SDMA) | |
621 | */ | |
622 | __u32 index; | |
623 | __u32 _pad; | |
624 | }; | |
625 | ||
81629cba AD |
626 | /* Input structure for the INFO ioctl */ |
627 | struct drm_amdgpu_info { | |
628 | /* Where the return value will be stored */ | |
2ce9dde0 | 629 | __u64 return_pointer; |
81629cba AD |
630 | /* The size of the return value. Just like "size" in "snprintf", |
631 | * it limits how many bytes the kernel can write. */ | |
2ce9dde0 | 632 | __u32 return_size; |
81629cba | 633 | /* The query request id. */ |
2ce9dde0 | 634 | __u32 query; |
81629cba AD |
635 | |
636 | union { | |
637 | struct { | |
2ce9dde0 MR |
638 | __u32 id; |
639 | __u32 _pad; | |
81629cba AD |
640 | } mode_crtc; |
641 | ||
642 | struct { | |
643 | /** AMDGPU_HW_IP_* */ | |
2ce9dde0 | 644 | __u32 type; |
81629cba | 645 | /** |
675da0dd CK |
646 | * Index of the IP if there are more IPs of the same |
647 | * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. | |
81629cba | 648 | */ |
2ce9dde0 | 649 | __u32 ip_instance; |
81629cba AD |
650 | } query_hw_ip; |
651 | ||
652 | struct { | |
2ce9dde0 | 653 | __u32 dword_offset; |
675da0dd | 654 | /** number of registers to read */ |
2ce9dde0 MR |
655 | __u32 count; |
656 | __u32 instance; | |
675da0dd | 657 | /** For future use, no flags defined so far */ |
2ce9dde0 | 658 | __u32 flags; |
81629cba AD |
659 | } read_mmr_reg; |
660 | ||
000cab9a | 661 | struct drm_amdgpu_query_fw query_fw; |
40ee5888 EQ |
662 | |
663 | struct { | |
664 | __u32 type; | |
665 | __u32 offset; | |
666 | } vbios_info; | |
5ebbac4b AD |
667 | |
668 | struct { | |
669 | __u32 type; | |
670 | } sensor_info; | |
81629cba AD |
671 | }; |
672 | }; | |
673 | ||
674 | struct drm_amdgpu_info_gds { | |
675 | /** GDS GFX partition size */ | |
2ce9dde0 | 676 | __u32 gds_gfx_partition_size; |
81629cba | 677 | /** GDS compute partition size */ |
2ce9dde0 | 678 | __u32 compute_partition_size; |
81629cba | 679 | /** total GDS memory size */ |
2ce9dde0 | 680 | __u32 gds_total_size; |
81629cba | 681 | /** GWS size per GFX partition */ |
2ce9dde0 | 682 | __u32 gws_per_gfx_partition; |
81629cba | 683 | /** GSW size per compute partition */ |
2ce9dde0 | 684 | __u32 gws_per_compute_partition; |
81629cba | 685 | /** OA size per GFX partition */ |
2ce9dde0 | 686 | __u32 oa_per_gfx_partition; |
81629cba | 687 | /** OA size per compute partition */ |
2ce9dde0 MR |
688 | __u32 oa_per_compute_partition; |
689 | __u32 _pad; | |
81629cba AD |
690 | }; |
691 | ||
692 | struct drm_amdgpu_info_vram_gtt { | |
2ce9dde0 MR |
693 | __u64 vram_size; |
694 | __u64 vram_cpu_accessible_size; | |
695 | __u64 gtt_size; | |
81629cba AD |
696 | }; |
697 | ||
e0adf6c8 JZ |
698 | struct drm_amdgpu_heap_info { |
699 | /** max. physical memory */ | |
700 | __u64 total_heap_size; | |
701 | ||
702 | /** Theoretical max. available memory in the given heap */ | |
703 | __u64 usable_heap_size; | |
704 | ||
705 | /** | |
706 | * Number of bytes allocated in the heap. This includes all processes | |
707 | * and private allocations in the kernel. It changes when new buffers | |
708 | * are allocated, freed, and moved. It cannot be larger than | |
709 | * heap_size. | |
710 | */ | |
711 | __u64 heap_usage; | |
712 | ||
713 | /** | |
714 | * Theoretical possible max. size of buffer which | |
715 | * could be allocated in the given heap | |
716 | */ | |
717 | __u64 max_allocation; | |
9f6163e7 JZ |
718 | }; |
719 | ||
e0adf6c8 JZ |
720 | struct drm_amdgpu_memory_info { |
721 | struct drm_amdgpu_heap_info vram; | |
722 | struct drm_amdgpu_heap_info cpu_accessible_vram; | |
723 | struct drm_amdgpu_heap_info gtt; | |
cfa32556 JZ |
724 | }; |
725 | ||
81629cba | 726 | struct drm_amdgpu_info_firmware { |
2ce9dde0 MR |
727 | __u32 ver; |
728 | __u32 feature; | |
81629cba AD |
729 | }; |
730 | ||
81c59f54 KW |
731 | #define AMDGPU_VRAM_TYPE_UNKNOWN 0 |
732 | #define AMDGPU_VRAM_TYPE_GDDR1 1 | |
733 | #define AMDGPU_VRAM_TYPE_DDR2 2 | |
734 | #define AMDGPU_VRAM_TYPE_GDDR3 3 | |
735 | #define AMDGPU_VRAM_TYPE_GDDR4 4 | |
736 | #define AMDGPU_VRAM_TYPE_GDDR5 5 | |
737 | #define AMDGPU_VRAM_TYPE_HBM 6 | |
738 | #define AMDGPU_VRAM_TYPE_DDR3 7 | |
739 | ||
81629cba AD |
740 | struct drm_amdgpu_info_device { |
741 | /** PCI Device ID */ | |
2ce9dde0 | 742 | __u32 device_id; |
81629cba | 743 | /** Internal chip revision: A0, A1, etc.) */ |
2ce9dde0 MR |
744 | __u32 chip_rev; |
745 | __u32 external_rev; | |
81629cba | 746 | /** Revision id in PCI Config space */ |
2ce9dde0 MR |
747 | __u32 pci_rev; |
748 | __u32 family; | |
749 | __u32 num_shader_engines; | |
750 | __u32 num_shader_arrays_per_engine; | |
675da0dd | 751 | /* in KHz */ |
2ce9dde0 MR |
752 | __u32 gpu_counter_freq; |
753 | __u64 max_engine_clock; | |
754 | __u64 max_memory_clock; | |
81629cba | 755 | /* cu information */ |
2ce9dde0 MR |
756 | __u32 cu_active_number; |
757 | __u32 cu_ao_mask; | |
758 | __u32 cu_bitmap[4][4]; | |
81629cba | 759 | /** Render backend pipe mask. One render backend is CB+DB. */ |
2ce9dde0 MR |
760 | __u32 enabled_rb_pipes_mask; |
761 | __u32 num_rb_pipes; | |
762 | __u32 num_hw_gfx_contexts; | |
763 | __u32 _pad; | |
764 | __u64 ids_flags; | |
81629cba | 765 | /** Starting virtual address for UMDs. */ |
2ce9dde0 | 766 | __u64 virtual_address_offset; |
02b70c8c | 767 | /** The maximum virtual address */ |
2ce9dde0 | 768 | __u64 virtual_address_max; |
81629cba | 769 | /** Required alignment of virtual addresses. */ |
2ce9dde0 | 770 | __u32 virtual_address_alignment; |
81629cba | 771 | /** Page table entry - fragment size */ |
2ce9dde0 MR |
772 | __u32 pte_fragment_size; |
773 | __u32 gart_page_size; | |
a101a899 | 774 | /** constant engine ram size*/ |
2ce9dde0 | 775 | __u32 ce_ram_size; |
cab6d57c | 776 | /** video memory type info*/ |
2ce9dde0 | 777 | __u32 vram_type; |
81c59f54 | 778 | /** video memory bit width*/ |
2ce9dde0 | 779 | __u32 vram_bit_width; |
fa92754e | 780 | /* vce harvesting instance */ |
2ce9dde0 | 781 | __u32 vce_harvest_config; |
df6e2c4a JZ |
782 | /* gfx double offchip LDS buffers */ |
783 | __u32 gc_double_offchip_lds_buf; | |
bce23e00 AD |
784 | /* NGG Primitive Buffer */ |
785 | __u64 prim_buf_gpu_addr; | |
786 | /* NGG Position Buffer */ | |
787 | __u64 pos_buf_gpu_addr; | |
788 | /* NGG Control Sideband */ | |
789 | __u64 cntl_sb_buf_gpu_addr; | |
790 | /* NGG Parameter Cache */ | |
791 | __u64 param_buf_gpu_addr; | |
408bfe7c JZ |
792 | __u32 prim_buf_size; |
793 | __u32 pos_buf_size; | |
794 | __u32 cntl_sb_buf_size; | |
795 | __u32 param_buf_size; | |
796 | /* wavefront size*/ | |
797 | __u32 wave_front_size; | |
798 | /* shader visible vgprs*/ | |
799 | __u32 num_shader_visible_vgprs; | |
800 | /* CU per shader array*/ | |
801 | __u32 num_cu_per_sh; | |
802 | /* number of tcc blocks*/ | |
803 | __u32 num_tcc_blocks; | |
804 | /* gs vgt table depth*/ | |
805 | __u32 gs_vgt_table_depth; | |
806 | /* gs primitive buffer depth*/ | |
807 | __u32 gs_prim_buffer_depth; | |
808 | /* max gs wavefront per vgt*/ | |
809 | __u32 max_gs_waves_per_vgt; | |
810 | __u32 _pad1; | |
81629cba AD |
811 | }; |
812 | ||
813 | struct drm_amdgpu_info_hw_ip { | |
814 | /** Version of h/w IP */ | |
2ce9dde0 MR |
815 | __u32 hw_ip_version_major; |
816 | __u32 hw_ip_version_minor; | |
81629cba | 817 | /** Capabilities */ |
2ce9dde0 | 818 | __u64 capabilities_flags; |
71062f43 | 819 | /** command buffer address start alignment*/ |
2ce9dde0 | 820 | __u32 ib_start_alignment; |
71062f43 | 821 | /** command buffer size alignment*/ |
2ce9dde0 | 822 | __u32 ib_size_alignment; |
81629cba | 823 | /** Bitmask of available rings. Bit 0 means ring 0, etc. */ |
2ce9dde0 MR |
824 | __u32 available_rings; |
825 | __u32 _pad; | |
81629cba AD |
826 | }; |
827 | ||
44879b62 AN |
828 | struct drm_amdgpu_info_num_handles { |
829 | /** Max handles as supported by firmware for UVD */ | |
830 | __u32 uvd_max_handles; | |
831 | /** Handles currently in use for UVD */ | |
832 | __u32 uvd_used_handles; | |
833 | }; | |
834 | ||
bbe87974 AD |
835 | #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 |
836 | ||
837 | struct drm_amdgpu_info_vce_clock_table_entry { | |
838 | /** System clock */ | |
839 | __u32 sclk; | |
840 | /** Memory clock */ | |
841 | __u32 mclk; | |
842 | /** VCE clock */ | |
843 | __u32 eclk; | |
844 | __u32 pad; | |
845 | }; | |
846 | ||
847 | struct drm_amdgpu_info_vce_clock_table { | |
848 | struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; | |
849 | __u32 num_valid_entries; | |
850 | __u32 pad; | |
851 | }; | |
852 | ||
81629cba AD |
853 | /* |
854 | * Supported GPU families | |
855 | */ | |
856 | #define AMDGPU_FAMILY_UNKNOWN 0 | |
295d0daf | 857 | #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ |
81629cba AD |
858 | #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ |
859 | #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ | |
860 | #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ | |
39bb0c92 | 861 | #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ |
a8f1f1ce | 862 | #define AMDGPU_FAMILY_AI 141 /* Vega10 */ |
2ca8a5d2 | 863 | #define AMDGPU_FAMILY_RV 142 /* Raven */ |
81629cba | 864 | |
cfa7152f EV |
865 | #if defined(__cplusplus) |
866 | } | |
867 | #endif | |
868 | ||
81629cba | 869 | #endif |