[linux-2.6-block.git] / include / linux / tegra-powergate.h

/*
 * Copyright (c) 2010 Google, Inc
 *
 * Author:
 *	Colin Cross <ccross@google.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#ifndef _MACH_TEGRA_POWERGATE_H_
#define _MACH_TEGRA_POWERGATE_H_

struct clk;
struct reset_control;

#define TEGRA_POWERGATE_CPU	0
#define TEGRA_POWERGATE_3D	1
#define TEGRA_POWERGATE_VENC	2
#define TEGRA_POWERGATE_PCIE	3
#define TEGRA_POWERGATE_VDEC	4
#define TEGRA_POWERGATE_L2	5
#define TEGRA_POWERGATE_MPE	6
#define TEGRA_POWERGATE_HEG	7
#define TEGRA_POWERGATE_SATA	8
#define TEGRA_POWERGATE_CPU1	9
#define TEGRA_POWERGATE_CPU2	10
#define TEGRA_POWERGATE_CPU3	11
#define TEGRA_POWERGATE_CELP	12
#define TEGRA_POWERGATE_3D1	13
#define TEGRA_POWERGATE_CPU0	14
#define TEGRA_POWERGATE_C0NC	15
#define TEGRA_POWERGATE_C1NC	16
#define TEGRA_POWERGATE_SOR	17
#define TEGRA_POWERGATE_DIS	18
#define TEGRA_POWERGATE_DISB	19
#define TEGRA_POWERGATE_XUSBA	20
#define TEGRA_POWERGATE_XUSBB	21
#define TEGRA_POWERGATE_XUSBC	22
#define TEGRA_POWERGATE_VIC	23
#define TEGRA_POWERGATE_IRAM	24

#define TEGRA_POWERGATE_3D0	TEGRA_POWERGATE_3D

#define TEGRA_IO_RAIL_CSIA	0
#define TEGRA_IO_RAIL_CSIB	1
#define TEGRA_IO_RAIL_DSI	2
#define TEGRA_IO_RAIL_MIPI_BIAS	3
#define TEGRA_IO_RAIL_PEX_BIAS	4
#define TEGRA_IO_RAIL_PEX_CLK1	5
#define TEGRA_IO_RAIL_PEX_CLK2	6
#define TEGRA_IO_RAIL_USB0	9
#define TEGRA_IO_RAIL_USB1	10
#define TEGRA_IO_RAIL_USB2	11
#define TEGRA_IO_RAIL_USB_BIAS	12
#define TEGRA_IO_RAIL_NAND	13
#define TEGRA_IO_RAIL_UART	14
#define TEGRA_IO_RAIL_BB	15
#define TEGRA_IO_RAIL_AUDIO	17
#define TEGRA_IO_RAIL_HSIC	19
#define TEGRA_IO_RAIL_COMP	22
#define TEGRA_IO_RAIL_HDMI	28
#define TEGRA_IO_RAIL_PEX_CNTRL	32
#define TEGRA_IO_RAIL_SDMMC1	33
#define TEGRA_IO_RAIL_SDMMC3	34
#define TEGRA_IO_RAIL_SDMMC4	35
#define TEGRA_IO_RAIL_CAM	36
#define TEGRA_IO_RAIL_RES	37
#define TEGRA_IO_RAIL_HV	38
#define TEGRA_IO_RAIL_DSIB	39
#define TEGRA_IO_RAIL_DSIC	40
#define TEGRA_IO_RAIL_DSID	41
#define TEGRA_IO_RAIL_CSIE	44
#define TEGRA_IO_RAIL_LVDS	57
#define TEGRA_IO_RAIL_SYS_DDC	58

#ifdef CONFIG_ARCH_TEGRA
int tegra_powergate_is_powered(int id);
int tegra_powergate_power_on(int id);
int tegra_powergate_power_off(int id);
int tegra_powergate_remove_clamping(int id);

/* Must be called with clk disabled, and returns with clk enabled */
int tegra_powergate_sequence_power_up(int id, struct clk *clk,
				      struct reset_control *rst);

int tegra_io_rail_power_on(int id);
int tegra_io_rail_power_off(int id);
#else
static inline int tegra_powergate_is_powered(int id)
{
	return -ENOSYS;
}

static inline int tegra_powergate_power_on(int id)
{
	return -ENOSYS;
}

static inline int tegra_powergate_power_off(int id)
{
	return -ENOSYS;
}

static inline int tegra_powergate_remove_clamping(int id)
{
	return -ENOSYS;
}

static inline int tegra_powergate_sequence_power_up(int id, struct clk *clk,
						    struct reset_control *rst)
{
	return -ENOSYS;
}

static inline int tegra_io_rail_power_on(int id)
{
	return -ENOSYS;
}

static inline int tegra_io_rail_power_off(int id)
{
	return -ENOSYS;
}
#endif

#endif /* _MACH_TEGRA_POWERGATE_H_ */
Commit	Line	Data
ce1e3262	1	/*
ce1e3262 CC	2	* Copyright (c) 2010 Google, Inc
	3	*
	4	* Author:
	5	* Colin Cross <ccross@google.com>
	6	*
	7	* This software is licensed under the terms of the GNU General Public
	8	* License version 2, as published by the Free Software Foundation, and
	9	* may be copied, distributed, and modified under those terms.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	*/
	17
	18	#ifndef _MACH_TEGRA_POWERGATE_H_
	19	#define _MACH_TEGRA_POWERGATE_H_
	20
a25186eb	21	struct clk;
80b28791	22	struct reset_control;
a25186eb	23
ce1e3262 CC	24	#define TEGRA_POWERGATE_CPU 0
	25	#define TEGRA_POWERGATE_3D 1
	26	#define TEGRA_POWERGATE_VENC 2
	27	#define TEGRA_POWERGATE_PCIE 3
	28	#define TEGRA_POWERGATE_VDEC 4
	29	#define TEGRA_POWERGATE_L2 5
	30	#define TEGRA_POWERGATE_MPE 6
6cafa97d PDS	31	#define TEGRA_POWERGATE_HEG 7
	32	#define TEGRA_POWERGATE_SATA 8
	33	#define TEGRA_POWERGATE_CPU1 9
	34	#define TEGRA_POWERGATE_CPU2 10
	35	#define TEGRA_POWERGATE_CPU3 11
	36	#define TEGRA_POWERGATE_CELP 12
	37	#define TEGRA_POWERGATE_3D1 13
bd6a9ddc TR	38	#define TEGRA_POWERGATE_CPU0 14
	39	#define TEGRA_POWERGATE_C0NC 15
	40	#define TEGRA_POWERGATE_C1NC 16
9a716579	41	#define TEGRA_POWERGATE_SOR 17
bd6a9ddc TR	42	#define TEGRA_POWERGATE_DIS 18
	43	#define TEGRA_POWERGATE_DISB 19
	44	#define TEGRA_POWERGATE_XUSBA 20
	45	#define TEGRA_POWERGATE_XUSBB 21
	46	#define TEGRA_POWERGATE_XUSBC 22
9a716579 TR	47	#define TEGRA_POWERGATE_VIC 23
9a716579 TR	48	#define TEGRA_POWERGATE_IRAM 24
6cafa97d	49
6cafa97d	50	#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
ce1e3262	51
9d4450ae TR	52	#define TEGRA_IO_RAIL_CSIA 0
	53	#define TEGRA_IO_RAIL_CSIB 1
	54	#define TEGRA_IO_RAIL_DSI 2
	55	#define TEGRA_IO_RAIL_MIPI_BIAS 3
	56	#define TEGRA_IO_RAIL_PEX_BIAS 4
	57	#define TEGRA_IO_RAIL_PEX_CLK1 5
	58	#define TEGRA_IO_RAIL_PEX_CLK2 6
	59	#define TEGRA_IO_RAIL_USB0 9
	60	#define TEGRA_IO_RAIL_USB1 10
	61	#define TEGRA_IO_RAIL_USB2 11
	62	#define TEGRA_IO_RAIL_USB_BIAS 12
	63	#define TEGRA_IO_RAIL_NAND 13
	64	#define TEGRA_IO_RAIL_UART 14
	65	#define TEGRA_IO_RAIL_BB 15
	66	#define TEGRA_IO_RAIL_AUDIO 17
	67	#define TEGRA_IO_RAIL_HSIC 19
	68	#define TEGRA_IO_RAIL_COMP 22
	69	#define TEGRA_IO_RAIL_HDMI 28
	70	#define TEGRA_IO_RAIL_PEX_CNTRL 32
	71	#define TEGRA_IO_RAIL_SDMMC1 33
	72	#define TEGRA_IO_RAIL_SDMMC3 34
	73	#define TEGRA_IO_RAIL_SDMMC4 35
	74	#define TEGRA_IO_RAIL_CAM 36
	75	#define TEGRA_IO_RAIL_RES 37
	76	#define TEGRA_IO_RAIL_HV 38
	77	#define TEGRA_IO_RAIL_DSIB 39
	78	#define TEGRA_IO_RAIL_DSIC 40
	79	#define TEGRA_IO_RAIL_DSID 41
	80	#define TEGRA_IO_RAIL_CSIE 44
	81	#define TEGRA_IO_RAIL_LVDS 57
	82	#define TEGRA_IO_RAIL_SYS_DDC 58
	83
9886e1fd	84	#ifdef CONFIG_ARCH_TEGRA
6ac8cb5c	85	int tegra_powergate_is_powered(int id);
ce1e3262 CC	86	int tegra_powergate_power_on(int id);
ce1e3262 CC	87	int tegra_powergate_power_off(int id);
ce1e3262 CC	88	int tegra_powergate_remove_clamping(int id);
	89
	90	/* Must be called with clk disabled, and returns with clk enabled */
80b28791 SW	91	int tegra_powergate_sequence_power_up(int id, struct clk *clk,
80b28791 SW	92	struct reset_control *rst);
9d4450ae TR	93
	94	int tegra_io_rail_power_on(int id);
	95	int tegra_io_rail_power_off(int id);
9886e1fd TR	96	#else
	97	static inline int tegra_powergate_is_powered(int id)
	98	{
	99	return -ENOSYS;
	100	}
	101
	102	static inline int tegra_powergate_power_on(int id)
	103	{
	104	return -ENOSYS;
	105	}
	106
	107	static inline int tegra_powergate_power_off(int id)
	108	{
	109	return -ENOSYS;
	110	}
	111
	112	static inline int tegra_powergate_remove_clamping(int id)
	113	{
	114	return -ENOSYS;
	115	}
	116
80b28791	117	static inline int tegra_powergate_sequence_power_up(int id, struct clk *clk,
f53f4159	118	struct reset_control *rst)
9886e1fd TR	119	{
	120	return -ENOSYS;
	121	}
9d4450ae TR	122
	123	static inline int tegra_io_rail_power_on(int id)
	124	{
	125	return -ENOSYS;
	126	}
	127
	128	static inline int tegra_io_rail_power_off(int id)
	129	{
	130	return -ENOSYS;
	131	}
9886e1fd	132	#endif
ce1e3262 CC	133
ce1e3262 CC	134	#endif /* _MACH_TEGRA_POWERGATE_H_ */