[linux-2.6-block.git] / include / linux / serial_sci.h

#ifndef __LINUX_SERIAL_SCI_H
#define __LINUX_SERIAL_SCI_H

#include <linux/serial_core.h>
#include <linux/sh_dma.h>

/*
 * Generic header for SuperH (H)SCI(F) (used by sh/sh64 and related parts)
 */

#define SCIx_NOT_SUPPORTED	(-1)

/* SCSMR (Serial Mode Register) */
#define SCSMR_CHR	(1 << 6)	/* 7-bit Character Length */
#define SCSMR_PE	(1 << 5)	/* Parity Enable */
#define SCSMR_ODD	(1 << 4)	/* Odd Parity */
#define SCSMR_STOP	(1 << 3)	/* Stop Bit Length */
#define SCSMR_CKS	0x0003		/* Clock Select */

/* Serial Control Register (@ = not supported by all parts) */
#define SCSCR_TIE	(1 << 7)	/* Transmit Interrupt Enable */
#define SCSCR_RIE	(1 << 6)	/* Receive Interrupt Enable */
#define SCSCR_TE	(1 << 5)	/* Transmit Enable */
#define SCSCR_RE	(1 << 4)	/* Receive Enable */
#define SCSCR_REIE	(1 << 3)	/* Receive Error Interrupt Enable @ */
#define SCSCR_TOIE	(1 << 2)	/* Timeout Interrupt Enable @ */
#define SCSCR_CKE1	(1 << 1)	/* Clock Enable 1 */
#define SCSCR_CKE0	(1 << 0)	/* Clock Enable 0 */
/* SCIFA/SCIFB only */
#define SCSCR_TDRQE	(1 << 15)	/* Tx Data Transfer Request Enable */
#define SCSCR_RDRQE	(1 << 14)	/* Rx Data Transfer Request Enable */

/* SCxSR (Serial Status Register) on SCI */
#define SCI_TDRE  0x80			/* Transmit Data Register Empty */
#define SCI_RDRF  0x40			/* Receive Data Register Full */
#define SCI_ORER  0x20			/* Overrun Error */
#define SCI_FER   0x10			/* Framing Error */
#define SCI_PER   0x08			/* Parity Error */
#define SCI_TEND  0x04			/* Transmit End */

#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)

/* SCxSR (Serial Status Register) on SCIF, HSCIF */
#define SCIF_ER    0x0080		/* Receive Error */
#define SCIF_TEND  0x0040		/* Transmission End */
#define SCIF_TDFE  0x0020		/* Transmit FIFO Data Empty */
#define SCIF_BRK   0x0010		/* Break Detect */
#define SCIF_FER   0x0008		/* Framing Error */
#define SCIF_PER   0x0004		/* Parity Error */
#define SCIF_RDF   0x0002		/* Receive FIFO Data Full */
#define SCIF_DR    0x0001		/* Receive Data Ready */

#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)

/* SCFCR (FIFO Control Register) */
#define SCFCR_LOOP	(1 << 0)	/* Loopback Test */

/* SCSPTR (Serial Port Register), optional */
#define SCSPTR_RTSIO	(1 << 7)	/* Serial Port RTS Pin Input/Output */
#define SCSPTR_CTSIO	(1 << 5)	/* Serial Port CTS Pin Input/Output */
#define SCSPTR_SPB2IO	(1 << 1)	/* Serial Port Break Input/Output */
#define SCSPTR_SPB2DT	(1 << 0)	/* Serial Port Break Data */

/* HSSRR HSCIF */
#define HSCIF_SRE	0x8000		/* Sampling Rate Register Enable */

enum {
	SCIx_PROBE_REGTYPE,

	SCIx_SCI_REGTYPE,
	SCIx_IRDA_REGTYPE,
	SCIx_SCIFA_REGTYPE,
	SCIx_SCIFB_REGTYPE,
	SCIx_SH2_SCIF_FIFODATA_REGTYPE,
	SCIx_SH3_SCIF_REGTYPE,
	SCIx_SH4_SCIF_REGTYPE,
	SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
	SCIx_SH4_SCIF_FIFODATA_REGTYPE,
	SCIx_SH7705_SCIF_REGTYPE,
	SCIx_HSCIF_REGTYPE,

	SCIx_NR_REGTYPES,
};

/*
 * SCI register subset common for all port types.
 * Not all registers will exist on all parts.
 */
enum {
	SCSMR,				/* Serial Mode Register */
	SCBRR,				/* Bit Rate Register */
	SCSCR,				/* Serial Control Register */
	SCxSR,				/* Serial Status Register */
	SCFCR,				/* FIFO Control Register */
	SCFDR,				/* FIFO Data Count Register */
	SCxTDR,				/* Transmit (FIFO) Data Register */
	SCxRDR,				/* Receive (FIFO) Data Register */
	SCLSR,				/* Line Status Register */
	SCTFDR,				/* Transmit FIFO Data Count Register */
	SCRFDR,				/* Receive FIFO Data Count Register */
	SCSPTR,				/* Serial Port Register */
	HSSRR,				/* Sampling Rate Register */

	SCIx_NR_REGS,
};

struct device;

struct plat_sci_port_ops {
	void (*init_pins)(struct uart_port *, unsigned int cflag);
};

/*
 * Port-specific capabilities
 */
#define SCIx_HAVE_RTSCTS	(1 << 0)

/*
 * Platform device specific platform_data struct
 */
struct plat_sci_port {
	unsigned int	type;			/* SCI / SCIF / IRDA / HSCIF */
	upf_t		flags;			/* UPF_* flags */
	unsigned long	capabilities;		/* Port features/capabilities */

	unsigned int	sampling_rate;
	unsigned int	scscr;			/* SCSCR initialization */

	/*
	 * Platform overrides if necessary, defaults otherwise.
	 */
	int		port_reg;
	unsigned char	regshift;
	unsigned char	regtype;

	struct plat_sci_port_ops	*ops;

	unsigned int	dma_slave_tx;
	unsigned int	dma_slave_rx;
};

#endif /* __LINUX_SERIAL_SCI_H */
Commit	Line	Data
96de1a8f PM	1	#ifndef __LINUX_SERIAL_SCI_H
96de1a8f PM	2	#define __LINUX_SERIAL_SCI_H
ecd95616 PM	3
ecd95616 PM	4	#include <linux/serial_core.h>
14baf9d7	5	#include <linux/sh_dma.h>
ecd95616 PM	6
ecd95616 PM	7	/*
4b084784	8	* Generic header for SuperH (H)SCI(F) (used by sh/sh64 and related parts)
ecd95616 PM	9	*/
ecd95616 PM	10
debf9507 PM	11	#define SCIx_NOT_SUPPORTED (-1)
debf9507 PM	12
26de4f1b GU	13	/* SCSMR (Serial Mode Register) */
	14	#define SCSMR_CHR (1 << 6) /* 7-bit Character Length */
	15	#define SCSMR_PE (1 << 5) /* Parity Enable */
	16	#define SCSMR_ODD (1 << 4) /* Odd Parity */
	17	#define SCSMR_STOP (1 << 3) /* Stop Bit Length */
	18	#define SCSMR_CKS 0x0003 /* Clock Select */
	19
	20	/* Serial Control Register (@ = not supported by all parts) */
	21	#define SCSCR_TIE (1 << 7) /* Transmit Interrupt Enable */
	22	#define SCSCR_RIE (1 << 6) /* Receive Interrupt Enable */
	23	#define SCSCR_TE (1 << 5) /* Transmit Enable */
	24	#define SCSCR_RE (1 << 4) /* Receive Enable */
	25	#define SCSCR_REIE (1 << 3) /* Receive Error Interrupt Enable @ */
	26	#define SCSCR_TOIE (1 << 2) /* Timeout Interrupt Enable @ */
	27	#define SCSCR_CKE1 (1 << 1) /* Clock Enable 1 */
	28	#define SCSCR_CKE0 (1 << 0) /* Clock Enable 0 */
	29	/* SCIFA/SCIFB only */
	30	#define SCSCR_TDRQE (1 << 15) /* Tx Data Transfer Request Enable */
	31	#define SCSCR_RDRQE (1 << 14) /* Rx Data Transfer Request Enable */
	32
	33	/* SCxSR (Serial Status Register) on SCI */
	34	#define SCI_TDRE 0x80 /* Transmit Data Register Empty */
	35	#define SCI_RDRF 0x40 /* Receive Data Register Full */
	36	#define SCI_ORER 0x20 /* Overrun Error */
	37	#define SCI_FER 0x10 /* Framing Error */
	38	#define SCI_PER 0x08 /* Parity Error */
	39	#define SCI_TEND 0x04 /* Transmit End */
debf9507 PM	40
	41	#define SCI_DEFAULT_ERROR_MASK (SCI_PER \| SCI_FER)
	42
26de4f1b GU	43	/* SCxSR (Serial Status Register) on SCIF, HSCIF */
	44	#define SCIF_ER 0x0080 /* Receive Error */
	45	#define SCIF_TEND 0x0040 /* Transmission End */
	46	#define SCIF_TDFE 0x0020 /* Transmit FIFO Data Empty */
	47	#define SCIF_BRK 0x0010 /* Break Detect */
	48	#define SCIF_FER 0x0008 /* Framing Error */
	49	#define SCIF_PER 0x0004 /* Parity Error */
	50	#define SCIF_RDF 0x0002 /* Receive FIFO Data Full */
	51	#define SCIF_DR 0x0001 /* Receive Data Ready */
debf9507 PM	52
	53	#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER \| SCIF_FER \| SCIF_ER \| SCIF_BRK)
	54
26de4f1b GU	55	/* SCFCR (FIFO Control Register) */
	56	#define SCFCR_LOOP (1 << 0) /* Loopback Test */
	57
	58	/* SCSPTR (Serial Port Register), optional */
	59	#define SCSPTR_RTSIO (1 << 7) /* Serial Port RTS Pin Input/Output */
	60	#define SCSPTR_CTSIO (1 << 5) /* Serial Port CTS Pin Input/Output */
	61	#define SCSPTR_SPB2IO (1 << 1) /* Serial Port Break Input/Output */
	62	#define SCSPTR_SPB2DT (1 << 0) /* Serial Port Break Data */
faf02f8f	63
f303b364	64	/* HSSRR HSCIF */
26de4f1b	65	#define HSCIF_SRE 0x8000 /* Sampling Rate Register Enable */
f303b364	66
61a6976b PM	67	enum {
	68	SCIx_PROBE_REGTYPE,
	69
	70	SCIx_SCI_REGTYPE,
	71	SCIx_IRDA_REGTYPE,
	72	SCIx_SCIFA_REGTYPE,
	73	SCIx_SCIFB_REGTYPE,
3af1f8a4	74	SCIx_SH2_SCIF_FIFODATA_REGTYPE,
61a6976b PM	75	SCIx_SH3_SCIF_REGTYPE,
	76	SCIx_SH4_SCIF_REGTYPE,
	77	SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
	78	SCIx_SH4_SCIF_FIFODATA_REGTYPE,
	79	SCIx_SH7705_SCIF_REGTYPE,
f303b364	80	SCIx_HSCIF_REGTYPE,
61a6976b PM	81
	82	SCIx_NR_REGTYPES,
	83	};
	84
61a6976b PM	85	/*
	86	* SCI register subset common for all port types.
	87	* Not all registers will exist on all parts.
	88	*/
	89	enum {
26de4f1b GU	90	SCSMR, /* Serial Mode Register */
	91	SCBRR, /* Bit Rate Register */
	92	SCSCR, /* Serial Control Register */
	93	SCxSR, /* Serial Status Register */
	94	SCFCR, /* FIFO Control Register */
	95	SCFDR, /* FIFO Data Count Register */
	96	SCxTDR, /* Transmit (FIFO) Data Register */
	97	SCxRDR, /* Receive (FIFO) Data Register */
	98	SCLSR, /* Line Status Register */
	99	SCTFDR, /* Transmit FIFO Data Count Register */
	100	SCRFDR, /* Receive FIFO Data Count Register */
	101	SCSPTR, /* Serial Port Register */
	102	HSSRR, /* Sampling Rate Register */
61a6976b PM	103
	104	SCIx_NR_REGS,
	105	};
	106
73a19e4c GL	107	struct device;
73a19e4c GL	108
61a6976b PM	109	struct plat_sci_port_ops {
	110	void (init_pins)(struct uart_port , unsigned int cflag);
	111	};
	112
faf02f8f PM	113	/*
	114	* Port-specific capabilities
	115	*/
	116	#define SCIx_HAVE_RTSCTS (1 << 0)
	117
ecd95616 PM	118	/*
	119	* Platform device specific platform_data struct
	120	*/
	121	struct plat_sci_port {
f303b364	122	unsigned int type; /* SCI / SCIF / IRDA / HSCIF */
ecd95616	123	upf_t flags; /* UPF_* flags */
faf02f8f	124	unsigned long capabilities; /* Port features/capabilities */
00b9de9c	125
ec09c5eb	126	unsigned int sampling_rate;
00b9de9c	127	unsigned int scscr; /* SCSCR initialization */
f43dc23d	128
debf9507 PM	129	/*
	130	* Platform overrides if necessary, defaults otherwise.
	131	*/
514820eb	132	int port_reg;
61a6976b PM	133	unsigned char regshift;
	134	unsigned char regtype;
	135
	136	struct plat_sci_port_ops *ops;
514820eb	137
27bd1075 PM	138	unsigned int dma_slave_tx;
27bd1075 PM	139	unsigned int dma_slave_rx;
ecd95616 PM	140	};
ecd95616 PM	141
96de1a8f	142	#endif /* __LINUX_SERIAL_SCI_H */