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IB/core: Add vendor's specific data to alloc mw
[linux-2.6-block.git] / include / linux / mlx5 / mlx5_ifc.h
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d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e281682b
SM		 35enum {
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
60};
61
62enum {
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
67};
68
f91e6d89
EBE		 69enum {
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
72};
73
d29b796a
EC		 74enum {
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
d29b796a
EC		 86 MLX5_CMD_OP_CREATE_MKEY = 0x200,
87 MLX5_CMD_OP_QUERY_MKEY = 0x201,
88 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
89 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
90 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
91 MLX5_CMD_OP_CREATE_EQ = 0x301,
92 MLX5_CMD_OP_DESTROY_EQ = 0x302,
93 MLX5_CMD_OP_QUERY_EQ = 0x303,
94 MLX5_CMD_OP_GEN_EQE = 0x304,
95 MLX5_CMD_OP_CREATE_CQ = 0x400,
96 MLX5_CMD_OP_DESTROY_CQ = 0x401,
97 MLX5_CMD_OP_QUERY_CQ = 0x402,
98 MLX5_CMD_OP_MODIFY_CQ = 0x403,
99 MLX5_CMD_OP_CREATE_QP = 0x500,
100 MLX5_CMD_OP_DESTROY_QP = 0x501,
101 MLX5_CMD_OP_RST2INIT_QP = 0x502,
102 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
103 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
104 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
105 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
106 MLX5_CMD_OP_2ERR_QP = 0x507,
107 MLX5_CMD_OP_2RST_QP = 0x50a,
108 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 109 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 110 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
111 MLX5_CMD_OP_CREATE_PSV = 0x600,
112 MLX5_CMD_OP_DESTROY_PSV = 0x601,
113 MLX5_CMD_OP_CREATE_SRQ = 0x700,
114 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
115 MLX5_CMD_OP_QUERY_SRQ = 0x702,
116 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 117 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
118 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
119 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
120 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 121 MLX5_CMD_OP_CREATE_DCT = 0x710,
122 MLX5_CMD_OP_DESTROY_DCT = 0x711,
123 MLX5_CMD_OP_DRAIN_DCT = 0x712,
124 MLX5_CMD_OP_QUERY_DCT = 0x713,
125 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
126 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
127 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
128 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
129 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
130 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
131 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 132 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 133 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 134 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
135 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
136 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
137 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
d29b796a
EC		 138 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
139 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
140 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
141 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
142 MLX5_CMD_OP_ALLOC_PD = 0x800,
143 MLX5_CMD_OP_DEALLOC_PD = 0x801,
144 MLX5_CMD_OP_ALLOC_UAR = 0x802,
145 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
146 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
147 MLX5_CMD_OP_ACCESS_REG = 0x805,
148 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
e281682b 149 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807,
d29b796a
EC		 150 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
151 MLX5_CMD_OP_MAD_IFC = 0x50d,
152 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
153 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
154 MLX5_CMD_OP_NOP = 0x80d,
155 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
156 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 157 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
158 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
159 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
160 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
161 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
162 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
163 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
164 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
165 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
166 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
167 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
168 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
d29b796a
EC		 169 MLX5_CMD_OP_CREATE_TIR = 0x900,
170 MLX5_CMD_OP_MODIFY_TIR = 0x901,
171 MLX5_CMD_OP_DESTROY_TIR = 0x902,
172 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 173 MLX5_CMD_OP_CREATE_SQ = 0x904,
174 MLX5_CMD_OP_MODIFY_SQ = 0x905,
175 MLX5_CMD_OP_DESTROY_SQ = 0x906,
176 MLX5_CMD_OP_QUERY_SQ = 0x907,
177 MLX5_CMD_OP_CREATE_RQ = 0x908,
178 MLX5_CMD_OP_MODIFY_RQ = 0x909,
179 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
180 MLX5_CMD_OP_QUERY_RQ = 0x90b,
181 MLX5_CMD_OP_CREATE_RMP = 0x90c,
182 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
183 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
184 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 185 MLX5_CMD_OP_CREATE_TIS = 0x912,
186 MLX5_CMD_OP_MODIFY_TIS = 0x913,
187 MLX5_CMD_OP_DESTROY_TIS = 0x914,
188 MLX5_CMD_OP_QUERY_TIS = 0x915,
189 MLX5_CMD_OP_CREATE_RQT = 0x916,
190 MLX5_CMD_OP_MODIFY_RQT = 0x917,
191 MLX5_CMD_OP_DESTROY_RQT = 0x918,
192 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 193 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 194 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
195 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
196 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
197 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
198 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
199 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
200 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
201 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68
MG		 202 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
203 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c
e281682b
SM		 204};
205
206struct mlx5_ifc_flow_table_fields_supported_bits {
207 u8 outer_dmac[0x1];
208 u8 outer_smac[0x1];
209 u8 outer_ether_type[0x1];
b4ff3a36 210 u8 reserved_at_3[0x1];
e281682b
SM		 211 u8 outer_first_prio[0x1];
212 u8 outer_first_cfi[0x1];
213 u8 outer_first_vid[0x1];
b4ff3a36 214 u8 reserved_at_7[0x1];
e281682b
SM		 215 u8 outer_second_prio[0x1];
216 u8 outer_second_cfi[0x1];
217 u8 outer_second_vid[0x1];
b4ff3a36 218 u8 reserved_at_b[0x1];
e281682b
SM		 219 u8 outer_sip[0x1];
220 u8 outer_dip[0x1];
221 u8 outer_frag[0x1];
222 u8 outer_ip_protocol[0x1];
223 u8 outer_ip_ecn[0x1];
224 u8 outer_ip_dscp[0x1];
225 u8 outer_udp_sport[0x1];
226 u8 outer_udp_dport[0x1];
227 u8 outer_tcp_sport[0x1];
228 u8 outer_tcp_dport[0x1];
229 u8 outer_tcp_flags[0x1];
230 u8 outer_gre_protocol[0x1];
231 u8 outer_gre_key[0x1];
232 u8 outer_vxlan_vni[0x1];
b4ff3a36 233 u8 reserved_at_1a[0x5];
e281682b
SM		 234 u8 source_eswitch_port[0x1];
235
236 u8 inner_dmac[0x1];
237 u8 inner_smac[0x1];
238 u8 inner_ether_type[0x1];
b4ff3a36 239 u8 reserved_at_23[0x1];
e281682b
SM		 240 u8 inner_first_prio[0x1];
241 u8 inner_first_cfi[0x1];
242 u8 inner_first_vid[0x1];
b4ff3a36 243 u8 reserved_at_27[0x1];
e281682b
SM		 244 u8 inner_second_prio[0x1];
245 u8 inner_second_cfi[0x1];
246 u8 inner_second_vid[0x1];
b4ff3a36 247 u8 reserved_at_2b[0x1];
e281682b
SM		 248 u8 inner_sip[0x1];
249 u8 inner_dip[0x1];
250 u8 inner_frag[0x1];
251 u8 inner_ip_protocol[0x1];
252 u8 inner_ip_ecn[0x1];
253 u8 inner_ip_dscp[0x1];
254 u8 inner_udp_sport[0x1];
255 u8 inner_udp_dport[0x1];
256 u8 inner_tcp_sport[0x1];
257 u8 inner_tcp_dport[0x1];
258 u8 inner_tcp_flags[0x1];
b4ff3a36 259 u8 reserved_at_37[0x9];
e281682b 260
b4ff3a36 261 u8 reserved_at_40[0x40];
e281682b
SM		 262};
263
264struct mlx5_ifc_flow_table_prop_layout_bits {
265 u8 ft_support[0x1];
b4ff3a36 266 u8 reserved_at_1[0x2];
26a81453 267 u8 flow_modify_en[0x1];
2cc43b49 268 u8 modify_root[0x1];
34a40e68
MG		 269 u8 identified_miss_table_mode[0x1];
270 u8 flow_table_modify[0x1];
b4ff3a36 271 u8 reserved_at_7[0x19];
e281682b 272
b4ff3a36 273 u8 reserved_at_20[0x2];
e281682b 274 u8 log_max_ft_size[0x6];
b4ff3a36 275 u8 reserved_at_28[0x10];
e281682b
SM		 276 u8 max_ft_level[0x8];
277
b4ff3a36 278 u8 reserved_at_40[0x20];
e281682b 279
b4ff3a36 280 u8 reserved_at_60[0x18];
e281682b
SM		 281 u8 log_max_ft_num[0x8];
282
b4ff3a36 283 u8 reserved_at_80[0x18];
e281682b
SM		 284 u8 log_max_destination[0x8];
285
b4ff3a36 286 u8 reserved_at_a0[0x18];
e281682b
SM		 287 u8 log_max_flow[0x8];
288
b4ff3a36 289 u8 reserved_at_c0[0x40];
e281682b
SM		 290
291 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
292
293 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
294};
295
296struct mlx5_ifc_odp_per_transport_service_cap_bits {
297 u8 send[0x1];
298 u8 receive[0x1];
299 u8 write[0x1];
300 u8 read[0x1];
b4ff3a36 301 u8 reserved_at_4[0x1];
e281682b 302 u8 srq_receive[0x1];
b4ff3a36 303 u8 reserved_at_6[0x1a];
e281682b
SM		 304};
305
b4d1f032 306struct mlx5_ifc_ipv4_layout_bits {
b4ff3a36 307 u8 reserved_at_0[0x60];
b4d1f032
MG		 308
309 u8 ipv4[0x20];
310};
311
312struct mlx5_ifc_ipv6_layout_bits {
313 u8 ipv6[16][0x8];
314};
315
316union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
317 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
318 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
b4ff3a36 319 u8 reserved_at_0[0x80];
b4d1f032
MG		 320};
321
e281682b
SM		 322struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
323 u8 smac_47_16[0x20];
324
325 u8 smac_15_0[0x10];
326 u8 ethertype[0x10];
327
328 u8 dmac_47_16[0x20];
329
330 u8 dmac_15_0[0x10];
331 u8 first_prio[0x3];
332 u8 first_cfi[0x1];
333 u8 first_vid[0xc];
334
335 u8 ip_protocol[0x8];
336 u8 ip_dscp[0x6];
337 u8 ip_ecn[0x2];
338 u8 vlan_tag[0x1];
b4ff3a36 339 u8 reserved_at_91[0x1];
e281682b 340 u8 frag[0x1];
b4ff3a36 341 u8 reserved_at_93[0x4];
e281682b
SM		 342 u8 tcp_flags[0x9];
343
344 u8 tcp_sport[0x10];
345 u8 tcp_dport[0x10];
346
b4ff3a36 347 u8 reserved_at_c0[0x20];
e281682b
SM		 348
349 u8 udp_sport[0x10];
350 u8 udp_dport[0x10];
351
b4d1f032 352 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 353
b4d1f032 354 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 355};
356
357struct mlx5_ifc_fte_match_set_misc_bits {
b4ff3a36 358 u8 reserved_at_0[0x20];
e281682b 359
b4ff3a36 360 u8 reserved_at_20[0x10];
e281682b
SM		 361 u8 source_port[0x10];
362
363 u8 outer_second_prio[0x3];
364 u8 outer_second_cfi[0x1];
365 u8 outer_second_vid[0xc];
366 u8 inner_second_prio[0x3];
367 u8 inner_second_cfi[0x1];
368 u8 inner_second_vid[0xc];
369
370 u8 outer_second_vlan_tag[0x1];
371 u8 inner_second_vlan_tag[0x1];
b4ff3a36 372 u8 reserved_at_62[0xe];
e281682b
SM		 373 u8 gre_protocol[0x10];
374
375 u8 gre_key_h[0x18];
376 u8 gre_key_l[0x8];
377
378 u8 vxlan_vni[0x18];
b4ff3a36 379 u8 reserved_at_b8[0x8];
e281682b 380
b4ff3a36 381 u8 reserved_at_c0[0x20];
e281682b 382
b4ff3a36 383 u8 reserved_at_e0[0xc];
e281682b
SM		 384 u8 outer_ipv6_flow_label[0x14];
385
b4ff3a36 386 u8 reserved_at_100[0xc];
e281682b
SM		 387 u8 inner_ipv6_flow_label[0x14];
388
b4ff3a36 389 u8 reserved_at_120[0xe0];
e281682b
SM		 390};
391
392struct mlx5_ifc_cmd_pas_bits {
393 u8 pa_h[0x20];
394
395 u8 pa_l[0x14];
b4ff3a36 396 u8 reserved_at_34[0xc];
e281682b
SM		 397};
398
399struct mlx5_ifc_uint64_bits {
400 u8 hi[0x20];
401
402 u8 lo[0x20];
403};
404
405enum {
406 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
407 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
408 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
409 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
410 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
411 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
412 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
413 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
414 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
415 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
416};
417
418struct mlx5_ifc_ads_bits {
419 u8 fl[0x1];
420 u8 free_ar[0x1];
b4ff3a36 421 u8 reserved_at_2[0xe];
e281682b
SM		 422 u8 pkey_index[0x10];
423
b4ff3a36 424 u8 reserved_at_20[0x8];
e281682b
SM		 425 u8 grh[0x1];
426 u8 mlid[0x7];
427 u8 rlid[0x10];
428
429 u8 ack_timeout[0x5];
b4ff3a36 430 u8 reserved_at_45[0x3];
e281682b 431 u8 src_addr_index[0x8];
b4ff3a36 432 u8 reserved_at_50[0x4];
e281682b
SM		 433 u8 stat_rate[0x4];
434 u8 hop_limit[0x8];
435
b4ff3a36 436 u8 reserved_at_60[0x4];
e281682b
SM		 437 u8 tclass[0x8];
438 u8 flow_label[0x14];
439
440 u8 rgid_rip[16][0x8];
441
b4ff3a36 442 u8 reserved_at_100[0x4];
e281682b
SM		 443 u8 f_dscp[0x1];
444 u8 f_ecn[0x1];
b4ff3a36 445 u8 reserved_at_106[0x1];
e281682b
SM		 446 u8 f_eth_prio[0x1];
447 u8 ecn[0x2];
448 u8 dscp[0x6];
449 u8 udp_sport[0x10];
450
451 u8 dei_cfi[0x1];
452 u8 eth_prio[0x3];
453 u8 sl[0x4];
454 u8 port[0x8];
455 u8 rmac_47_32[0x10];
456
457 u8 rmac_31_0[0x20];
458};
459
460struct mlx5_ifc_flow_table_nic_cap_bits {
b4ff3a36 461 u8 reserved_at_0[0x200];
e281682b
SM		 462
463 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
464
b4ff3a36 465 u8 reserved_at_400[0x200];
e281682b
SM		 466
467 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
468
469 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
470
b4ff3a36 471 u8 reserved_at_a00[0x200];
e281682b
SM		 472
473 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
474
b4ff3a36 475 u8 reserved_at_e00[0x7200];
e281682b
SM		 476};
477
495716b1 478struct mlx5_ifc_flow_table_eswitch_cap_bits {
b4ff3a36 479 u8 reserved_at_0[0x200];
495716b1
SM		 480
481 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
482
483 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
484
485 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
486
b4ff3a36 487 u8 reserved_at_800[0x7800];
495716b1
SM		 488};
489
d6666753
SM		 490struct mlx5_ifc_e_switch_cap_bits {
491 u8 vport_svlan_strip[0x1];
492 u8 vport_cvlan_strip[0x1];
493 u8 vport_svlan_insert[0x1];
494 u8 vport_cvlan_insert_if_not_exist[0x1];
495 u8 vport_cvlan_insert_overwrite[0x1];
b4ff3a36 496 u8 reserved_at_5[0x1b];
d6666753 497
b4ff3a36 498 u8 reserved_at_20[0x7e0];
d6666753
SM		 499};
500
e281682b
SM		 501struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
502 u8 csum_cap[0x1];
503 u8 vlan_cap[0x1];
504 u8 lro_cap[0x1];
505 u8 lro_psh_flag[0x1];
506 u8 lro_time_stamp[0x1];
b4ff3a36 507 u8 reserved_at_5[0x3];
66189961 508 u8 self_lb_en_modifiable[0x1];
b4ff3a36 509 u8 reserved_at_9[0x2];
e281682b 510 u8 max_lso_cap[0x5];
b4ff3a36 511 u8 reserved_at_10[0x4];
e281682b 512 u8 rss_ind_tbl_cap[0x4];
b4ff3a36 513 u8 reserved_at_18[0x3];
e281682b 514 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 515 u8 reserved_at_1c[0x2];
e281682b
SM		 516 u8 tunnel_statless_gre[0x1];
517 u8 tunnel_stateless_vxlan[0x1];
518
b4ff3a36 519 u8 reserved_at_20[0x20];
e281682b 520
b4ff3a36 521 u8 reserved_at_40[0x10];
e281682b
SM		 522 u8 lro_min_mss_size[0x10];
523
b4ff3a36 524 u8 reserved_at_60[0x120];
e281682b
SM		 525
526 u8 lro_timer_supported_periods[4][0x20];
527
b4ff3a36 528 u8 reserved_at_200[0x600];
e281682b
SM		 529};
530
531struct mlx5_ifc_roce_cap_bits {
532 u8 roce_apm[0x1];
b4ff3a36 533 u8 reserved_at_1[0x1f];
e281682b 534
b4ff3a36 535 u8 reserved_at_20[0x60];
e281682b 536
b4ff3a36 537 u8 reserved_at_80[0xc];
e281682b 538 u8 l3_type[0x4];
b4ff3a36 539 u8 reserved_at_90[0x8];
e281682b
SM		 540 u8 roce_version[0x8];
541
b4ff3a36 542 u8 reserved_at_a0[0x10];
e281682b
SM		 543 u8 r_roce_dest_udp_port[0x10];
544
545 u8 r_roce_max_src_udp_port[0x10];
546 u8 r_roce_min_src_udp_port[0x10];
547
b4ff3a36 548 u8 reserved_at_e0[0x10];
e281682b
SM		 549 u8 roce_address_table_size[0x10];
550
b4ff3a36 551 u8 reserved_at_100[0x700];
e281682b
SM		 552};
553
554enum {
555 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
556 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
557 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
558 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
559 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
560 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
561 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
562 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
563 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
564};
565
566enum {
567 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
568 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
569 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
570 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
571 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
572 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
573 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
574 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
575 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
576};
577
578struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 579 u8 reserved_at_0[0x40];
e281682b 580
f91e6d89 581 u8 atomic_req_8B_endianess_mode[0x2];
b4ff3a36 582 u8 reserved_at_42[0x4];
f91e6d89 583 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
e281682b 584
b4ff3a36 585 u8 reserved_at_47[0x19];
e281682b 586
b4ff3a36 587 u8 reserved_at_60[0x20];
e281682b 588
b4ff3a36 589 u8 reserved_at_80[0x10];
f91e6d89 590 u8 atomic_operations[0x10];
e281682b 591
b4ff3a36 592 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 593 u8 atomic_size_qp[0x10];
594
b4ff3a36 595 u8 reserved_at_c0[0x10];
e281682b
SM		 596 u8 atomic_size_dc[0x10];
597
b4ff3a36 598 u8 reserved_at_e0[0x720];
e281682b
SM		 599};
600
601struct mlx5_ifc_odp_cap_bits {
b4ff3a36 602 u8 reserved_at_0[0x40];
e281682b
SM		 603
604 u8 sig[0x1];
b4ff3a36 605 u8 reserved_at_41[0x1f];
e281682b 606
b4ff3a36 607 u8 reserved_at_60[0x20];
e281682b
SM		 608
609 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
610
611 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
612
613 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
614
b4ff3a36 615 u8 reserved_at_e0[0x720];
e281682b
SM		 616};
617
618enum {
619 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
620 MLX5_WQ_TYPE_CYCLIC = 0x1,
621 MLX5_WQ_TYPE_STRQ = 0x2,
622};
623
624enum {
625 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
626 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
627};
628
629enum {
630 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
631 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
632 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
633 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
634 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
635};
636
637enum {
638 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
639 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
640 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
641 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
642 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
643 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
644};
645
646enum {
647 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
648 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
649};
650
651enum {
652 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
653 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
654 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
655};
656
657enum {
658 MLX5_CAP_PORT_TYPE_IB = 0x0,
659 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 660};
661
b775516b 662struct mlx5_ifc_cmd_hca_cap_bits {
b4ff3a36 663 u8 reserved_at_0[0x80];
b775516b
EC		 664
665 u8 log_max_srq_sz[0x8];
666 u8 log_max_qp_sz[0x8];
b4ff3a36 667 u8 reserved_at_90[0xb];
b775516b
EC		 668 u8 log_max_qp[0x5];
669
b4ff3a36 670 u8 reserved_at_a0[0xb];
e281682b 671 u8 log_max_srq[0x5];
b4ff3a36 672 u8 reserved_at_b0[0x10];
b775516b 673
b4ff3a36 674 u8 reserved_at_c0[0x8];
b775516b 675 u8 log_max_cq_sz[0x8];
b4ff3a36 676 u8 reserved_at_d0[0xb];
b775516b
EC		 677 u8 log_max_cq[0x5];
678
679 u8 log_max_eq_sz[0x8];
b4ff3a36 680 u8 reserved_at_e8[0x2];
b775516b 681 u8 log_max_mkey[0x6];
b4ff3a36 682 u8 reserved_at_f0[0xc];
b775516b
EC		 683 u8 log_max_eq[0x4];
684
685 u8 max_indirection[0x8];
b4ff3a36 686 u8 reserved_at_108[0x1];
b775516b 687 u8 log_max_mrw_sz[0x7];
b4ff3a36 688 u8 reserved_at_110[0x2];
b775516b 689 u8 log_max_bsf_list_size[0x6];
b4ff3a36 690 u8 reserved_at_118[0x2];
b775516b
EC		 691 u8 log_max_klm_list_size[0x6];
692
b4ff3a36 693 u8 reserved_at_120[0xa];
b775516b 694 u8 log_max_ra_req_dc[0x6];
b4ff3a36 695 u8 reserved_at_130[0xa];
b775516b
EC		 696 u8 log_max_ra_res_dc[0x6];
697
b4ff3a36 698 u8 reserved_at_140[0xa];
b775516b 699 u8 log_max_ra_req_qp[0x6];
b4ff3a36 700 u8 reserved_at_150[0xa];
b775516b
EC		 701 u8 log_max_ra_res_qp[0x6];
702
703 u8 pad_cap[0x1];
704 u8 cc_query_allowed[0x1];
705 u8 cc_modify_allowed[0x1];
b4ff3a36 706 u8 reserved_at_163[0xd];
e281682b 707 u8 gid_table_size[0x10];
b775516b 708
e281682b
SM		 709 u8 out_of_seq_cnt[0x1];
710 u8 vport_counters[0x1];
b4ff3a36 711 u8 reserved_at_182[0x4];
b775516b
EC		 712 u8 max_qp_cnt[0xa];
713 u8 pkey_table_size[0x10];
714
e281682b
SM		 715 u8 vport_group_manager[0x1];
716 u8 vhca_group_manager[0x1];
717 u8 ib_virt[0x1];
718 u8 eth_virt[0x1];
b4ff3a36 719 u8 reserved_at_1a4[0x1];
e281682b
SM		 720 u8 ets[0x1];
721 u8 nic_flow_table[0x1];
54f0a411 722 u8 eswitch_flow_table[0x1];
fc50db98 723 u8 early_vf_enable;
b4ff3a36 724 u8 reserved_at_1a8[0x2];
b775516b 725 u8 local_ca_ack_delay[0x5];
b4ff3a36 726 u8 reserved_at_1af[0x6];
e281682b 727 u8 port_type[0x2];
b775516b
EC		 728 u8 num_ports[0x8];
729
b4ff3a36 730 u8 reserved_at_1bf[0x3];
b775516b 731 u8 log_max_msg[0x5];
b4ff3a36 732 u8 reserved_at_1c7[0x18];
b775516b
EC		 733
734 u8 stat_rate_support[0x10];
b4ff3a36 735 u8 reserved_at_1ef[0xc];
e281682b 736 u8 cqe_version[0x4];
b775516b 737
e281682b 738 u8 compact_address_vector[0x1];
1015c2e8
ES		 739 u8 reserved_at_200[0x3];
740 u8 ipoib_basic_offloads[0x1];
741 u8 reserved_at_204[0xa];
e281682b 742 u8 drain_sigerr[0x1];
b775516b
EC		 743 u8 cmdif_checksum[0x2];
744 u8 sigerr_cqe[0x1];
b4ff3a36 745 u8 reserved_at_212[0x1];
b775516b
EC		 746 u8 wq_signature[0x1];
747 u8 sctr_data_cqe[0x1];
b4ff3a36 748 u8 reserved_at_215[0x1];
b775516b
EC		 749 u8 sho[0x1];
750 u8 tph[0x1];
751 u8 rf[0x1];
e281682b 752 u8 dct[0x1];
b4ff3a36 753 u8 reserved_at_21a[0x1];
e281682b 754 u8 eth_net_offloads[0x1];
b775516b
EC		 755 u8 roce[0x1];
756 u8 atomic[0x1];
b4ff3a36 757 u8 reserved_at_21e[0x1];
b775516b
EC		 758
759 u8 cq_oi[0x1];
760 u8 cq_resize[0x1];
761 u8 cq_moderation[0x1];
b4ff3a36 762 u8 reserved_at_222[0x3];
e281682b 763 u8 cq_eq_remap[0x1];
b775516b
EC		 764 u8 pg[0x1];
765 u8 block_lb_mc[0x1];
b4ff3a36 766 u8 reserved_at_228[0x1];
e281682b 767 u8 scqe_break_moderation[0x1];
b4ff3a36 768 u8 reserved_at_22a[0x1];
b775516b 769 u8 cd[0x1];
b4ff3a36 770 u8 reserved_at_22c[0x1];
b775516b 771 u8 apm[0x1];
b4ff3a36 772 u8 reserved_at_22e[0x7];
b775516b
EC		 773 u8 qkv[0x1];
774 u8 pkv[0x1];
b11a4f9c
HE		 775 u8 set_deth_sqpn[0x1];
776 u8 reserved_at_239[0x3];
b775516b
EC		 777 u8 xrc[0x1];
778 u8 ud[0x1];
779 u8 uc[0x1];
780 u8 rc[0x1];
781
b4ff3a36 782 u8 reserved_at_23f[0xa];
b775516b 783 u8 uar_sz[0x6];
b4ff3a36 784 u8 reserved_at_24f[0x8];
b775516b
EC		 785 u8 log_pg_sz[0x8];
786
787 u8 bf[0x1];
b4ff3a36 788 u8 reserved_at_260[0x1];
e281682b 789 u8 pad_tx_eth_packet[0x1];
b4ff3a36 790 u8 reserved_at_262[0x8];
b775516b 791 u8 log_bf_reg_size[0x5];
b4ff3a36 792 u8 reserved_at_26f[0x10];
b775516b 793
b4ff3a36 794 u8 reserved_at_27f[0x10];
b775516b
EC		 795 u8 max_wqe_sz_sq[0x10];
796
b4ff3a36 797 u8 reserved_at_29f[0x10];
b775516b
EC		 798 u8 max_wqe_sz_rq[0x10];
799
b4ff3a36 800 u8 reserved_at_2bf[0x10];
b775516b
EC		 801 u8 max_wqe_sz_sq_dc[0x10];
802
b4ff3a36 803 u8 reserved_at_2df[0x7];
b775516b
EC		 804 u8 max_qp_mcg[0x19];
805
b4ff3a36 806 u8 reserved_at_2ff[0x18];
b775516b
EC		 807 u8 log_max_mcg[0x8];
808
b4ff3a36 809 u8 reserved_at_31f[0x3];
e281682b 810 u8 log_max_transport_domain[0x5];
b4ff3a36 811 u8 reserved_at_327[0x3];
b775516b 812 u8 log_max_pd[0x5];
b4ff3a36 813 u8 reserved_at_32f[0xb];
b775516b
EC		 814 u8 log_max_xrcd[0x5];
815
b4ff3a36 816 u8 reserved_at_33f[0x20];
b775516b 817
b4ff3a36 818 u8 reserved_at_35f[0x3];
b775516b 819 u8 log_max_rq[0x5];
b4ff3a36 820 u8 reserved_at_367[0x3];
b775516b 821 u8 log_max_sq[0x5];
b4ff3a36 822 u8 reserved_at_36f[0x3];
b775516b 823 u8 log_max_tir[0x5];
b4ff3a36 824 u8 reserved_at_377[0x3];
b775516b
EC		 825 u8 log_max_tis[0x5];
826
e281682b 827 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 828 u8 reserved_at_380[0x2];
e281682b 829 u8 log_max_rmp[0x5];
b4ff3a36 830 u8 reserved_at_387[0x3];
e281682b 831 u8 log_max_rqt[0x5];
b4ff3a36 832 u8 reserved_at_38f[0x3];
e281682b 833 u8 log_max_rqt_size[0x5];
b4ff3a36 834 u8 reserved_at_397[0x3];
b775516b
EC		 835 u8 log_max_tis_per_sq[0x5];
836
b4ff3a36 837 u8 reserved_at_39f[0x3];
e281682b 838 u8 log_max_stride_sz_rq[0x5];
b4ff3a36 839 u8 reserved_at_3a7[0x3];
e281682b 840 u8 log_min_stride_sz_rq[0x5];
b4ff3a36 841 u8 reserved_at_3af[0x3];
e281682b 842 u8 log_max_stride_sz_sq[0x5];
b4ff3a36 843 u8 reserved_at_3b7[0x3];
e281682b
SM		 844 u8 log_min_stride_sz_sq[0x5];
845
b4ff3a36 846 u8 reserved_at_3bf[0x1b];
e281682b
SM		 847 u8 log_max_wq_sz[0x5];
848
54f0a411 849 u8 nic_vport_change_event[0x1];
b4ff3a36 850 u8 reserved_at_3e0[0xa];
54f0a411 851 u8 log_max_vlan_list[0x5];
b4ff3a36 852 u8 reserved_at_3ef[0x3];
54f0a411 853 u8 log_max_current_mc_list[0x5];
b4ff3a36 854 u8 reserved_at_3f7[0x3];
54f0a411
SM		 855 u8 log_max_current_uc_list[0x5];
856
b4ff3a36 857 u8 reserved_at_3ff[0x80];
54f0a411 858
b4ff3a36 859 u8 reserved_at_47f[0x3];
e281682b 860 u8 log_max_l2_table[0x5];
b4ff3a36 861 u8 reserved_at_487[0x8];
b775516b
EC		 862 u8 log_uar_page_sz[0x10];
863
b4ff3a36 864 u8 reserved_at_49f[0x20];
048ccca8 865 u8 device_frequency_mhz[0x20];
b0844444 866 u8 device_frequency_khz[0x20];
b4ff3a36 867 u8 reserved_at_4ff[0x5f];
b775516b
EC		 868 u8 cqe_zip[0x1];
869
870 u8 cqe_zip_timeout[0x10];
871 u8 cqe_zip_max_num[0x10];
872
b4ff3a36 873 u8 reserved_at_57f[0x220];
b775516b
EC		 874};
875
81848731
SM		 876enum mlx5_flow_destination_type {
877 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
878 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
879 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
e281682b 880};
b775516b 881
e281682b
SM		 882struct mlx5_ifc_dest_format_struct_bits {
883 u8 destination_type[0x8];
884 u8 destination_id[0x18];
b775516b 885
b4ff3a36 886 u8 reserved_at_20[0x20];
e281682b
SM		 887};
888
889struct mlx5_ifc_fte_match_param_bits {
890 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
891
892 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
893
894 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 895
b4ff3a36 896 u8 reserved_at_600[0xa00];
b775516b
EC		 897};
898
e281682b
SM		 899enum {
900 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
901 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
902 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
903 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
904 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
905};
b775516b 906
e281682b
SM		 907struct mlx5_ifc_rx_hash_field_select_bits {
908 u8 l3_prot_type[0x1];
909 u8 l4_prot_type[0x1];
910 u8 selected_fields[0x1e];
911};
b775516b 912
e281682b
SM		 913enum {
914 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
915 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 916};
917
e281682b
SM		 918enum {
919 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
920 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
921};
922
923struct mlx5_ifc_wq_bits {
924 u8 wq_type[0x4];
925 u8 wq_signature[0x1];
926 u8 end_padding_mode[0x2];
927 u8 cd_slave[0x1];
b4ff3a36 928 u8 reserved_at_8[0x18];
b775516b 929
e281682b
SM		 930 u8 hds_skip_first_sge[0x1];
931 u8 log2_hds_buf_size[0x3];
b4ff3a36 932 u8 reserved_at_24[0x7];
e281682b
SM		 933 u8 page_offset[0x5];
934 u8 lwm[0x10];
b775516b 935
b4ff3a36 936 u8 reserved_at_40[0x8];
e281682b
SM		 937 u8 pd[0x18];
938
b4ff3a36 939 u8 reserved_at_60[0x8];
e281682b
SM		 940 u8 uar_page[0x18];
941
942 u8 dbr_addr[0x40];
943
944 u8 hw_counter[0x20];
945
946 u8 sw_counter[0x20];
947
b4ff3a36 948 u8 reserved_at_100[0xc];
e281682b 949 u8 log_wq_stride[0x4];
b4ff3a36 950 u8 reserved_at_110[0x3];
e281682b 951 u8 log_wq_pg_sz[0x5];
b4ff3a36 952 u8 reserved_at_118[0x3];
e281682b
SM		 953 u8 log_wq_sz[0x5];
954
b4ff3a36 955 u8 reserved_at_120[0x4e0];
b775516b 956
e281682b 957 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 958};
959
e281682b 960struct mlx5_ifc_rq_num_bits {
b4ff3a36 961 u8 reserved_at_0[0x8];
e281682b
SM		 962 u8 rq_num[0x18];
963};
b775516b 964
e281682b 965struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 966 u8 reserved_at_0[0x10];
e281682b 967 u8 mac_addr_47_32[0x10];
b775516b 968
e281682b
SM		 969 u8 mac_addr_31_0[0x20];
970};
971
c0046cf7 972struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 973 u8 reserved_at_0[0x14];
c0046cf7
SM		 974 u8 vlan[0x0c];
975
b4ff3a36 976 u8 reserved_at_20[0x20];
c0046cf7
SM		 977};
978
e281682b 979struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 980 u8 reserved_at_0[0xa0];
e281682b
SM		 981
982 u8 min_time_between_cnps[0x20];
983
b4ff3a36 984 u8 reserved_at_c0[0x12];
e281682b 985 u8 cnp_dscp[0x6];
b4ff3a36 986 u8 reserved_at_d8[0x5];
e281682b
SM		 987 u8 cnp_802p_prio[0x3];
988
b4ff3a36 989 u8 reserved_at_e0[0x720];
e281682b
SM		 990};
991
992struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 993 u8 reserved_at_0[0x60];
e281682b 994
b4ff3a36 995 u8 reserved_at_60[0x4];
e281682b 996 u8 clamp_tgt_rate[0x1];
b4ff3a36 997 u8 reserved_at_65[0x3];
e281682b 998 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 999 u8 reserved_at_69[0x17];
e281682b 1000
b4ff3a36 1001 u8 reserved_at_80[0x20];
e281682b
SM		 1002
1003 u8 rpg_time_reset[0x20];
1004
1005 u8 rpg_byte_reset[0x20];
1006
1007 u8 rpg_threshold[0x20];
1008
1009 u8 rpg_max_rate[0x20];
1010
1011 u8 rpg_ai_rate[0x20];
1012
1013 u8 rpg_hai_rate[0x20];
1014
1015 u8 rpg_gd[0x20];
1016
1017 u8 rpg_min_dec_fac[0x20];
1018
1019 u8 rpg_min_rate[0x20];
1020
b4ff3a36 1021 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1022
1023 u8 rate_to_set_on_first_cnp[0x20];
1024
1025 u8 dce_tcp_g[0x20];
1026
1027 u8 dce_tcp_rtt[0x20];
1028
1029 u8 rate_reduce_monitor_period[0x20];
1030
b4ff3a36 1031 u8 reserved_at_320[0x20];
e281682b
SM		 1032
1033 u8 initial_alpha_value[0x20];
1034
b4ff3a36 1035 u8 reserved_at_360[0x4a0];
e281682b
SM		 1036};
1037
1038struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1039 u8 reserved_at_0[0x80];
e281682b
SM		 1040
1041 u8 rppp_max_rps[0x20];
1042
1043 u8 rpg_time_reset[0x20];
1044
1045 u8 rpg_byte_reset[0x20];
1046
1047 u8 rpg_threshold[0x20];
1048
1049 u8 rpg_max_rate[0x20];
1050
1051 u8 rpg_ai_rate[0x20];
1052
1053 u8 rpg_hai_rate[0x20];
1054
1055 u8 rpg_gd[0x20];
1056
1057 u8 rpg_min_dec_fac[0x20];
1058
1059 u8 rpg_min_rate[0x20];
1060
b4ff3a36 1061 u8 reserved_at_1c0[0x640];
e281682b
SM		 1062};
1063
1064enum {
1065 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1066 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1067 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1068};
1069
1070struct mlx5_ifc_resize_field_select_bits {
1071 u8 resize_field_select[0x20];
1072};
1073
1074enum {
1075 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1076 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1077 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1078 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1079};
1080
1081struct mlx5_ifc_modify_field_select_bits {
1082 u8 modify_field_select[0x20];
1083};
1084
1085struct mlx5_ifc_field_select_r_roce_np_bits {
1086 u8 field_select_r_roce_np[0x20];
1087};
1088
1089struct mlx5_ifc_field_select_r_roce_rp_bits {
1090 u8 field_select_r_roce_rp[0x20];
1091};
1092
1093enum {
1094 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1095 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1096 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1097 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1098 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1099 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1100 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1101 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1102 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1103 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1104};
1105
1106struct mlx5_ifc_field_select_802_1qau_rp_bits {
1107 u8 field_select_8021qaurp[0x20];
1108};
1109
1110struct mlx5_ifc_phys_layer_cntrs_bits {
1111 u8 time_since_last_clear_high[0x20];
1112
1113 u8 time_since_last_clear_low[0x20];
1114
1115 u8 symbol_errors_high[0x20];
1116
1117 u8 symbol_errors_low[0x20];
1118
1119 u8 sync_headers_errors_high[0x20];
1120
1121 u8 sync_headers_errors_low[0x20];
1122
1123 u8 edpl_bip_errors_lane0_high[0x20];
1124
1125 u8 edpl_bip_errors_lane0_low[0x20];
1126
1127 u8 edpl_bip_errors_lane1_high[0x20];
1128
1129 u8 edpl_bip_errors_lane1_low[0x20];
1130
1131 u8 edpl_bip_errors_lane2_high[0x20];
1132
1133 u8 edpl_bip_errors_lane2_low[0x20];
1134
1135 u8 edpl_bip_errors_lane3_high[0x20];
1136
1137 u8 edpl_bip_errors_lane3_low[0x20];
1138
1139 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1140
1141 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1142
1143 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1144
1145 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1146
1147 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1148
1149 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1150
1151 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1152
1153 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1154
1155 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1156
1157 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1158
1159 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1160
1161 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1162
1163 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1164
1165 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1166
1167 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1168
1169 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1170
1171 u8 rs_fec_corrected_blocks_high[0x20];
1172
1173 u8 rs_fec_corrected_blocks_low[0x20];
1174
1175 u8 rs_fec_uncorrectable_blocks_high[0x20];
1176
1177 u8 rs_fec_uncorrectable_blocks_low[0x20];
1178
1179 u8 rs_fec_no_errors_blocks_high[0x20];
1180
1181 u8 rs_fec_no_errors_blocks_low[0x20];
1182
1183 u8 rs_fec_single_error_blocks_high[0x20];
1184
1185 u8 rs_fec_single_error_blocks_low[0x20];
1186
1187 u8 rs_fec_corrected_symbols_total_high[0x20];
1188
1189 u8 rs_fec_corrected_symbols_total_low[0x20];
1190
1191 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1192
1193 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1194
1195 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1196
1197 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1198
1199 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1200
1201 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1202
1203 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1204
1205 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1206
1207 u8 link_down_events[0x20];
1208
1209 u8 successful_recovery_events[0x20];
1210
b4ff3a36 1211 u8 reserved_at_640[0x180];
e281682b
SM		 1212};
1213
1c64bf6f
MY		 1214struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1215 u8 symbol_error_counter[0x10];
1216
1217 u8 link_error_recovery_counter[0x8];
1218
1219 u8 link_downed_counter[0x8];
1220
1221 u8 port_rcv_errors[0x10];
1222
1223 u8 port_rcv_remote_physical_errors[0x10];
1224
1225 u8 port_rcv_switch_relay_errors[0x10];
1226
1227 u8 port_xmit_discards[0x10];
1228
1229 u8 port_xmit_constraint_errors[0x8];
1230
1231 u8 port_rcv_constraint_errors[0x8];
1232
1233 u8 reserved_at_70[0x8];
1234
1235 u8 link_overrun_errors[0x8];
1236
1237 u8 reserved_at_80[0x10];
1238
1239 u8 vl_15_dropped[0x10];
1240
1241 u8 reserved_at_a0[0xa0];
1242};
1243
e281682b
SM		 1244struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1245 u8 transmit_queue_high[0x20];
1246
1247 u8 transmit_queue_low[0x20];
1248
b4ff3a36 1249 u8 reserved_at_40[0x780];
e281682b
SM		 1250};
1251
1252struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1253 u8 rx_octets_high[0x20];
1254
1255 u8 rx_octets_low[0x20];
1256
b4ff3a36 1257 u8 reserved_at_40[0xc0];
e281682b
SM		 1258
1259 u8 rx_frames_high[0x20];
1260
1261 u8 rx_frames_low[0x20];
1262
1263 u8 tx_octets_high[0x20];
1264
1265 u8 tx_octets_low[0x20];
1266
b4ff3a36 1267 u8 reserved_at_180[0xc0];
e281682b
SM		 1268
1269 u8 tx_frames_high[0x20];
1270
1271 u8 tx_frames_low[0x20];
1272
1273 u8 rx_pause_high[0x20];
1274
1275 u8 rx_pause_low[0x20];
1276
1277 u8 rx_pause_duration_high[0x20];
1278
1279 u8 rx_pause_duration_low[0x20];
1280
1281 u8 tx_pause_high[0x20];
1282
1283 u8 tx_pause_low[0x20];
1284
1285 u8 tx_pause_duration_high[0x20];
1286
1287 u8 tx_pause_duration_low[0x20];
1288
1289 u8 rx_pause_transition_high[0x20];
1290
1291 u8 rx_pause_transition_low[0x20];
1292
b4ff3a36 1293 u8 reserved_at_3c0[0x400];
e281682b
SM		 1294};
1295
1296struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1297 u8 port_transmit_wait_high[0x20];
1298
1299 u8 port_transmit_wait_low[0x20];
1300
b4ff3a36 1301 u8 reserved_at_40[0x780];
e281682b
SM		 1302};
1303
1304struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1305 u8 dot3stats_alignment_errors_high[0x20];
1306
1307 u8 dot3stats_alignment_errors_low[0x20];
1308
1309 u8 dot3stats_fcs_errors_high[0x20];
1310
1311 u8 dot3stats_fcs_errors_low[0x20];
1312
1313 u8 dot3stats_single_collision_frames_high[0x20];
1314
1315 u8 dot3stats_single_collision_frames_low[0x20];
1316
1317 u8 dot3stats_multiple_collision_frames_high[0x20];
1318
1319 u8 dot3stats_multiple_collision_frames_low[0x20];
1320
1321 u8 dot3stats_sqe_test_errors_high[0x20];
1322
1323 u8 dot3stats_sqe_test_errors_low[0x20];
1324
1325 u8 dot3stats_deferred_transmissions_high[0x20];
1326
1327 u8 dot3stats_deferred_transmissions_low[0x20];
1328
1329 u8 dot3stats_late_collisions_high[0x20];
1330
1331 u8 dot3stats_late_collisions_low[0x20];
1332
1333 u8 dot3stats_excessive_collisions_high[0x20];
1334
1335 u8 dot3stats_excessive_collisions_low[0x20];
1336
1337 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1338
1339 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1340
1341 u8 dot3stats_carrier_sense_errors_high[0x20];
1342
1343 u8 dot3stats_carrier_sense_errors_low[0x20];
1344
1345 u8 dot3stats_frame_too_longs_high[0x20];
1346
1347 u8 dot3stats_frame_too_longs_low[0x20];
1348
1349 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1350
1351 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1352
1353 u8 dot3stats_symbol_errors_high[0x20];
1354
1355 u8 dot3stats_symbol_errors_low[0x20];
1356
1357 u8 dot3control_in_unknown_opcodes_high[0x20];
1358
1359 u8 dot3control_in_unknown_opcodes_low[0x20];
1360
1361 u8 dot3in_pause_frames_high[0x20];
1362
1363 u8 dot3in_pause_frames_low[0x20];
1364
1365 u8 dot3out_pause_frames_high[0x20];
1366
1367 u8 dot3out_pause_frames_low[0x20];
1368
b4ff3a36 1369 u8 reserved_at_400[0x3c0];
e281682b
SM		 1370};
1371
1372struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1373 u8 ether_stats_drop_events_high[0x20];
1374
1375 u8 ether_stats_drop_events_low[0x20];
1376
1377 u8 ether_stats_octets_high[0x20];
1378
1379 u8 ether_stats_octets_low[0x20];
1380
1381 u8 ether_stats_pkts_high[0x20];
1382
1383 u8 ether_stats_pkts_low[0x20];
1384
1385 u8 ether_stats_broadcast_pkts_high[0x20];
1386
1387 u8 ether_stats_broadcast_pkts_low[0x20];
1388
1389 u8 ether_stats_multicast_pkts_high[0x20];
1390
1391 u8 ether_stats_multicast_pkts_low[0x20];
1392
1393 u8 ether_stats_crc_align_errors_high[0x20];
1394
1395 u8 ether_stats_crc_align_errors_low[0x20];
1396
1397 u8 ether_stats_undersize_pkts_high[0x20];
1398
1399 u8 ether_stats_undersize_pkts_low[0x20];
1400
1401 u8 ether_stats_oversize_pkts_high[0x20];
1402
1403 u8 ether_stats_oversize_pkts_low[0x20];
1404
1405 u8 ether_stats_fragments_high[0x20];
1406
1407 u8 ether_stats_fragments_low[0x20];
1408
1409 u8 ether_stats_jabbers_high[0x20];
1410
1411 u8 ether_stats_jabbers_low[0x20];
1412
1413 u8 ether_stats_collisions_high[0x20];
1414
1415 u8 ether_stats_collisions_low[0x20];
1416
1417 u8 ether_stats_pkts64octets_high[0x20];
1418
1419 u8 ether_stats_pkts64octets_low[0x20];
1420
1421 u8 ether_stats_pkts65to127octets_high[0x20];
1422
1423 u8 ether_stats_pkts65to127octets_low[0x20];
1424
1425 u8 ether_stats_pkts128to255octets_high[0x20];
1426
1427 u8 ether_stats_pkts128to255octets_low[0x20];
1428
1429 u8 ether_stats_pkts256to511octets_high[0x20];
1430
1431 u8 ether_stats_pkts256to511octets_low[0x20];
1432
1433 u8 ether_stats_pkts512to1023octets_high[0x20];
1434
1435 u8 ether_stats_pkts512to1023octets_low[0x20];
1436
1437 u8 ether_stats_pkts1024to1518octets_high[0x20];
1438
1439 u8 ether_stats_pkts1024to1518octets_low[0x20];
1440
1441 u8 ether_stats_pkts1519to2047octets_high[0x20];
1442
1443 u8 ether_stats_pkts1519to2047octets_low[0x20];
1444
1445 u8 ether_stats_pkts2048to4095octets_high[0x20];
1446
1447 u8 ether_stats_pkts2048to4095octets_low[0x20];
1448
1449 u8 ether_stats_pkts4096to8191octets_high[0x20];
1450
1451 u8 ether_stats_pkts4096to8191octets_low[0x20];
1452
1453 u8 ether_stats_pkts8192to10239octets_high[0x20];
1454
1455 u8 ether_stats_pkts8192to10239octets_low[0x20];
1456
b4ff3a36 1457 u8 reserved_at_540[0x280];
e281682b
SM		 1458};
1459
1460struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1461 u8 if_in_octets_high[0x20];
1462
1463 u8 if_in_octets_low[0x20];
1464
1465 u8 if_in_ucast_pkts_high[0x20];
1466
1467 u8 if_in_ucast_pkts_low[0x20];
1468
1469 u8 if_in_discards_high[0x20];
1470
1471 u8 if_in_discards_low[0x20];
1472
1473 u8 if_in_errors_high[0x20];
1474
1475 u8 if_in_errors_low[0x20];
1476
1477 u8 if_in_unknown_protos_high[0x20];
1478
1479 u8 if_in_unknown_protos_low[0x20];
1480
1481 u8 if_out_octets_high[0x20];
1482
1483 u8 if_out_octets_low[0x20];
1484
1485 u8 if_out_ucast_pkts_high[0x20];
1486
1487 u8 if_out_ucast_pkts_low[0x20];
1488
1489 u8 if_out_discards_high[0x20];
1490
1491 u8 if_out_discards_low[0x20];
1492
1493 u8 if_out_errors_high[0x20];
1494
1495 u8 if_out_errors_low[0x20];
1496
1497 u8 if_in_multicast_pkts_high[0x20];
1498
1499 u8 if_in_multicast_pkts_low[0x20];
1500
1501 u8 if_in_broadcast_pkts_high[0x20];
1502
1503 u8 if_in_broadcast_pkts_low[0x20];
1504
1505 u8 if_out_multicast_pkts_high[0x20];
1506
1507 u8 if_out_multicast_pkts_low[0x20];
1508
1509 u8 if_out_broadcast_pkts_high[0x20];
1510
1511 u8 if_out_broadcast_pkts_low[0x20];
1512
b4ff3a36 1513 u8 reserved_at_340[0x480];
e281682b
SM		 1514};
1515
1516struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1517 u8 a_frames_transmitted_ok_high[0x20];
1518
1519 u8 a_frames_transmitted_ok_low[0x20];
1520
1521 u8 a_frames_received_ok_high[0x20];
1522
1523 u8 a_frames_received_ok_low[0x20];
1524
1525 u8 a_frame_check_sequence_errors_high[0x20];
1526
1527 u8 a_frame_check_sequence_errors_low[0x20];
1528
1529 u8 a_alignment_errors_high[0x20];
1530
1531 u8 a_alignment_errors_low[0x20];
1532
1533 u8 a_octets_transmitted_ok_high[0x20];
1534
1535 u8 a_octets_transmitted_ok_low[0x20];
1536
1537 u8 a_octets_received_ok_high[0x20];
1538
1539 u8 a_octets_received_ok_low[0x20];
1540
1541 u8 a_multicast_frames_xmitted_ok_high[0x20];
1542
1543 u8 a_multicast_frames_xmitted_ok_low[0x20];
1544
1545 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1546
1547 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1548
1549 u8 a_multicast_frames_received_ok_high[0x20];
1550
1551 u8 a_multicast_frames_received_ok_low[0x20];
1552
1553 u8 a_broadcast_frames_received_ok_high[0x20];
1554
1555 u8 a_broadcast_frames_received_ok_low[0x20];
1556
1557 u8 a_in_range_length_errors_high[0x20];
1558
1559 u8 a_in_range_length_errors_low[0x20];
1560
1561 u8 a_out_of_range_length_field_high[0x20];
1562
1563 u8 a_out_of_range_length_field_low[0x20];
1564
1565 u8 a_frame_too_long_errors_high[0x20];
1566
1567 u8 a_frame_too_long_errors_low[0x20];
1568
1569 u8 a_symbol_error_during_carrier_high[0x20];
1570
1571 u8 a_symbol_error_during_carrier_low[0x20];
1572
1573 u8 a_mac_control_frames_transmitted_high[0x20];
1574
1575 u8 a_mac_control_frames_transmitted_low[0x20];
1576
1577 u8 a_mac_control_frames_received_high[0x20];
1578
1579 u8 a_mac_control_frames_received_low[0x20];
1580
1581 u8 a_unsupported_opcodes_received_high[0x20];
1582
1583 u8 a_unsupported_opcodes_received_low[0x20];
1584
1585 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1586
1587 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1588
1589 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1590
1591 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1592
b4ff3a36 1593 u8 reserved_at_4c0[0x300];
e281682b
SM		 1594};
1595
1596struct mlx5_ifc_cmd_inter_comp_event_bits {
1597 u8 command_completion_vector[0x20];
1598
b4ff3a36 1599 u8 reserved_at_20[0xc0];
e281682b
SM		 1600};
1601
1602struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 1603 u8 reserved_at_0[0x18];
e281682b 1604 u8 port_num[0x1];
b4ff3a36 1605 u8 reserved_at_19[0x3];
e281682b
SM		 1606 u8 vl[0x4];
1607
b4ff3a36 1608 u8 reserved_at_20[0xa0];
e281682b
SM		 1609};
1610
1611struct mlx5_ifc_db_bf_congestion_event_bits {
1612 u8 event_subtype[0x8];
b4ff3a36 1613 u8 reserved_at_8[0x8];
e281682b 1614 u8 congestion_level[0x8];
b4ff3a36 1615 u8 reserved_at_18[0x8];
e281682b 1616
b4ff3a36 1617 u8 reserved_at_20[0xa0];
e281682b
SM		 1618};
1619
1620struct mlx5_ifc_gpio_event_bits {
b4ff3a36 1621 u8 reserved_at_0[0x60];
e281682b
SM		 1622
1623 u8 gpio_event_hi[0x20];
1624
1625 u8 gpio_event_lo[0x20];
1626
b4ff3a36 1627 u8 reserved_at_a0[0x40];
e281682b
SM		 1628};
1629
1630struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 1631 u8 reserved_at_0[0x40];
e281682b
SM		 1632
1633 u8 port_num[0x4];
b4ff3a36 1634 u8 reserved_at_44[0x1c];
e281682b 1635
b4ff3a36 1636 u8 reserved_at_60[0x80];
e281682b
SM		 1637};
1638
1639struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 1640 u8 reserved_at_0[0xe0];
e281682b
SM		 1641};
1642
1643enum {
1644 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1645 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1646};
1647
1648struct mlx5_ifc_cq_error_bits {
b4ff3a36 1649 u8 reserved_at_0[0x8];
e281682b
SM		 1650 u8 cqn[0x18];
1651
b4ff3a36 1652 u8 reserved_at_20[0x20];
e281682b 1653
b4ff3a36 1654 u8 reserved_at_40[0x18];
e281682b
SM		 1655 u8 syndrome[0x8];
1656
b4ff3a36 1657 u8 reserved_at_60[0x80];
e281682b
SM		 1658};
1659
1660struct mlx5_ifc_rdma_page_fault_event_bits {
1661 u8 bytes_committed[0x20];
1662
1663 u8 r_key[0x20];
1664
b4ff3a36 1665 u8 reserved_at_40[0x10];
e281682b
SM		 1666 u8 packet_len[0x10];
1667
1668 u8 rdma_op_len[0x20];
1669
1670 u8 rdma_va[0x40];
1671
b4ff3a36 1672 u8 reserved_at_c0[0x5];
e281682b
SM		 1673 u8 rdma[0x1];
1674 u8 write[0x1];
1675 u8 requestor[0x1];
1676 u8 qp_number[0x18];
1677};
1678
1679struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1680 u8 bytes_committed[0x20];
1681
b4ff3a36 1682 u8 reserved_at_20[0x10];
e281682b
SM		 1683 u8 wqe_index[0x10];
1684
b4ff3a36 1685 u8 reserved_at_40[0x10];
e281682b
SM		 1686 u8 len[0x10];
1687
b4ff3a36 1688 u8 reserved_at_60[0x60];
e281682b 1689
b4ff3a36 1690 u8 reserved_at_c0[0x5];
e281682b
SM		 1691 u8 rdma[0x1];
1692 u8 write_read[0x1];
1693 u8 requestor[0x1];
1694 u8 qpn[0x18];
1695};
1696
1697struct mlx5_ifc_qp_events_bits {
b4ff3a36 1698 u8 reserved_at_0[0xa0];
e281682b
SM		 1699
1700 u8 type[0x8];
b4ff3a36 1701 u8 reserved_at_a8[0x18];
e281682b 1702
b4ff3a36 1703 u8 reserved_at_c0[0x8];
e281682b
SM		 1704 u8 qpn_rqn_sqn[0x18];
1705};
1706
1707struct mlx5_ifc_dct_events_bits {
b4ff3a36 1708 u8 reserved_at_0[0xc0];
e281682b 1709
b4ff3a36 1710 u8 reserved_at_c0[0x8];
e281682b
SM		 1711 u8 dct_number[0x18];
1712};
1713
1714struct mlx5_ifc_comp_event_bits {
b4ff3a36 1715 u8 reserved_at_0[0xc0];
e281682b 1716
b4ff3a36 1717 u8 reserved_at_c0[0x8];
e281682b
SM		 1718 u8 cq_number[0x18];
1719};
1720
1721enum {
1722 MLX5_QPC_STATE_RST = 0x0,
1723 MLX5_QPC_STATE_INIT = 0x1,
1724 MLX5_QPC_STATE_RTR = 0x2,
1725 MLX5_QPC_STATE_RTS = 0x3,
1726 MLX5_QPC_STATE_SQER = 0x4,
1727 MLX5_QPC_STATE_ERR = 0x6,
1728 MLX5_QPC_STATE_SQD = 0x7,
1729 MLX5_QPC_STATE_SUSPENDED = 0x9,
1730};
1731
1732enum {
1733 MLX5_QPC_ST_RC = 0x0,
1734 MLX5_QPC_ST_UC = 0x1,
1735 MLX5_QPC_ST_UD = 0x2,
1736 MLX5_QPC_ST_XRC = 0x3,
1737 MLX5_QPC_ST_DCI = 0x5,
1738 MLX5_QPC_ST_QP0 = 0x7,
1739 MLX5_QPC_ST_QP1 = 0x8,
1740 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1741 MLX5_QPC_ST_REG_UMR = 0xc,
1742};
1743
1744enum {
1745 MLX5_QPC_PM_STATE_ARMED = 0x0,
1746 MLX5_QPC_PM_STATE_REARM = 0x1,
1747 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1748 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1749};
1750
1751enum {
1752 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1753 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1754};
1755
1756enum {
1757 MLX5_QPC_MTU_256_BYTES = 0x1,
1758 MLX5_QPC_MTU_512_BYTES = 0x2,
1759 MLX5_QPC_MTU_1K_BYTES = 0x3,
1760 MLX5_QPC_MTU_2K_BYTES = 0x4,
1761 MLX5_QPC_MTU_4K_BYTES = 0x5,
1762 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1763};
1764
1765enum {
1766 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1767 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1768 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1769 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1770 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1771 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1772 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1773 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1774};
1775
1776enum {
1777 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1778 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1779 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1780};
1781
1782enum {
1783 MLX5_QPC_CS_RES_DISABLE = 0x0,
1784 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1785 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1786};
1787
1788struct mlx5_ifc_qpc_bits {
1789 u8 state[0x4];
b4ff3a36 1790 u8 reserved_at_4[0x4];
e281682b 1791 u8 st[0x8];
b4ff3a36 1792 u8 reserved_at_10[0x3];
e281682b 1793 u8 pm_state[0x2];
b4ff3a36 1794 u8 reserved_at_15[0x7];
e281682b 1795 u8 end_padding_mode[0x2];
b4ff3a36 1796 u8 reserved_at_1e[0x2];
e281682b
SM		 1797
1798 u8 wq_signature[0x1];
1799 u8 block_lb_mc[0x1];
1800 u8 atomic_like_write_en[0x1];
1801 u8 latency_sensitive[0x1];
b4ff3a36 1802 u8 reserved_at_24[0x1];
e281682b 1803 u8 drain_sigerr[0x1];
b4ff3a36 1804 u8 reserved_at_26[0x2];
e281682b
SM		 1805 u8 pd[0x18];
1806
1807 u8 mtu[0x3];
1808 u8 log_msg_max[0x5];
b4ff3a36 1809 u8 reserved_at_48[0x1];
e281682b
SM		 1810 u8 log_rq_size[0x4];
1811 u8 log_rq_stride[0x3];
1812 u8 no_sq[0x1];
1813 u8 log_sq_size[0x4];
b4ff3a36 1814 u8 reserved_at_55[0x6];
e281682b 1815 u8 rlky[0x1];
1015c2e8 1816 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 1817
1818 u8 counter_set_id[0x8];
1819 u8 uar_page[0x18];
1820
b4ff3a36 1821 u8 reserved_at_80[0x8];
e281682b
SM		 1822 u8 user_index[0x18];
1823
b4ff3a36 1824 u8 reserved_at_a0[0x3];
e281682b
SM		 1825 u8 log_page_size[0x5];
1826 u8 remote_qpn[0x18];
1827
1828 struct mlx5_ifc_ads_bits primary_address_path;
1829
1830 struct mlx5_ifc_ads_bits secondary_address_path;
1831
1832 u8 log_ack_req_freq[0x4];
b4ff3a36 1833 u8 reserved_at_384[0x4];
e281682b 1834 u8 log_sra_max[0x3];
b4ff3a36 1835 u8 reserved_at_38b[0x2];
e281682b
SM		 1836 u8 retry_count[0x3];
1837 u8 rnr_retry[0x3];
b4ff3a36 1838 u8 reserved_at_393[0x1];
e281682b
SM		 1839 u8 fre[0x1];
1840 u8 cur_rnr_retry[0x3];
1841 u8 cur_retry_count[0x3];
b4ff3a36 1842 u8 reserved_at_39b[0x5];
e281682b 1843
b4ff3a36 1844 u8 reserved_at_3a0[0x20];
e281682b 1845
b4ff3a36 1846 u8 reserved_at_3c0[0x8];
e281682b
SM		 1847 u8 next_send_psn[0x18];
1848
b4ff3a36 1849 u8 reserved_at_3e0[0x8];
e281682b
SM		 1850 u8 cqn_snd[0x18];
1851
b4ff3a36 1852 u8 reserved_at_400[0x40];
e281682b 1853
b4ff3a36 1854 u8 reserved_at_440[0x8];
e281682b
SM		 1855 u8 last_acked_psn[0x18];
1856
b4ff3a36 1857 u8 reserved_at_460[0x8];
e281682b
SM		 1858 u8 ssn[0x18];
1859
b4ff3a36 1860 u8 reserved_at_480[0x8];
e281682b 1861 u8 log_rra_max[0x3];
b4ff3a36 1862 u8 reserved_at_48b[0x1];
e281682b
SM		 1863 u8 atomic_mode[0x4];
1864 u8 rre[0x1];
1865 u8 rwe[0x1];
1866 u8 rae[0x1];
b4ff3a36 1867 u8 reserved_at_493[0x1];
e281682b 1868 u8 page_offset[0x6];
b4ff3a36 1869 u8 reserved_at_49a[0x3];
e281682b
SM		 1870 u8 cd_slave_receive[0x1];
1871 u8 cd_slave_send[0x1];
1872 u8 cd_master[0x1];
1873
b4ff3a36 1874 u8 reserved_at_4a0[0x3];
e281682b
SM		 1875 u8 min_rnr_nak[0x5];
1876 u8 next_rcv_psn[0x18];
1877
b4ff3a36 1878 u8 reserved_at_4c0[0x8];
e281682b
SM		 1879 u8 xrcd[0x18];
1880
b4ff3a36 1881 u8 reserved_at_4e0[0x8];
e281682b
SM		 1882 u8 cqn_rcv[0x18];
1883
1884 u8 dbr_addr[0x40];
1885
1886 u8 q_key[0x20];
1887
b4ff3a36 1888 u8 reserved_at_560[0x5];
e281682b
SM		 1889 u8 rq_type[0x3];
1890 u8 srqn_rmpn[0x18];
1891
b4ff3a36 1892 u8 reserved_at_580[0x8];
e281682b
SM		 1893 u8 rmsn[0x18];
1894
1895 u8 hw_sq_wqebb_counter[0x10];
1896 u8 sw_sq_wqebb_counter[0x10];
1897
1898 u8 hw_rq_counter[0x20];
1899
1900 u8 sw_rq_counter[0x20];
1901
b4ff3a36 1902 u8 reserved_at_600[0x20];
e281682b 1903
b4ff3a36 1904 u8 reserved_at_620[0xf];
e281682b
SM		 1905 u8 cgs[0x1];
1906 u8 cs_req[0x8];
1907 u8 cs_res[0x8];
1908
1909 u8 dc_access_key[0x40];
1910
b4ff3a36 1911 u8 reserved_at_680[0xc0];
e281682b
SM		 1912};
1913
1914struct mlx5_ifc_roce_addr_layout_bits {
1915 u8 source_l3_address[16][0x8];
1916
b4ff3a36 1917 u8 reserved_at_80[0x3];
e281682b
SM		 1918 u8 vlan_valid[0x1];
1919 u8 vlan_id[0xc];
1920 u8 source_mac_47_32[0x10];
1921
1922 u8 source_mac_31_0[0x20];
1923
b4ff3a36 1924 u8 reserved_at_c0[0x14];
e281682b
SM		 1925 u8 roce_l3_type[0x4];
1926 u8 roce_version[0x8];
1927
b4ff3a36 1928 u8 reserved_at_e0[0x20];
e281682b
SM		 1929};
1930
1931union mlx5_ifc_hca_cap_union_bits {
1932 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1933 struct mlx5_ifc_odp_cap_bits odp_cap;
1934 struct mlx5_ifc_atomic_caps_bits atomic_caps;
1935 struct mlx5_ifc_roce_cap_bits roce_cap;
1936 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1937 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 1938 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 1939 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
b4ff3a36 1940 u8 reserved_at_0[0x8000];
e281682b
SM		 1941};
1942
1943enum {
1944 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
1945 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
1946 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
1947};
1948
1949struct mlx5_ifc_flow_context_bits {
b4ff3a36 1950 u8 reserved_at_0[0x20];
e281682b
SM		 1951
1952 u8 group_id[0x20];
1953
b4ff3a36 1954 u8 reserved_at_40[0x8];
e281682b
SM		 1955 u8 flow_tag[0x18];
1956
b4ff3a36 1957 u8 reserved_at_60[0x10];
e281682b
SM		 1958 u8 action[0x10];
1959
b4ff3a36 1960 u8 reserved_at_80[0x8];
e281682b
SM		 1961 u8 destination_list_size[0x18];
1962
b4ff3a36 1963 u8 reserved_at_a0[0x160];
e281682b
SM		 1964
1965 struct mlx5_ifc_fte_match_param_bits match_value;
1966
b4ff3a36 1967 u8 reserved_at_1200[0x600];
e281682b
SM		 1968
1969 struct mlx5_ifc_dest_format_struct_bits destination[0];
1970};
1971
1972enum {
1973 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
1974 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
1975};
1976
1977struct mlx5_ifc_xrc_srqc_bits {
1978 u8 state[0x4];
1979 u8 log_xrc_srq_size[0x4];
b4ff3a36 1980 u8 reserved_at_8[0x18];
e281682b
SM		 1981
1982 u8 wq_signature[0x1];
1983 u8 cont_srq[0x1];
b4ff3a36 1984 u8 reserved_at_22[0x1];
e281682b
SM		 1985 u8 rlky[0x1];
1986 u8 basic_cyclic_rcv_wqe[0x1];
1987 u8 log_rq_stride[0x3];
1988 u8 xrcd[0x18];
1989
1990 u8 page_offset[0x6];
b4ff3a36 1991 u8 reserved_at_46[0x2];
e281682b
SM		 1992 u8 cqn[0x18];
1993
b4ff3a36 1994 u8 reserved_at_60[0x20];
e281682b
SM		 1995
1996 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 1997 u8 reserved_at_81[0x1];
e281682b
SM		 1998 u8 log_page_size[0x6];
1999 u8 user_index[0x18];
2000
b4ff3a36 2001 u8 reserved_at_a0[0x20];
e281682b 2002
b4ff3a36 2003 u8 reserved_at_c0[0x8];
e281682b
SM		 2004 u8 pd[0x18];
2005
2006 u8 lwm[0x10];
2007 u8 wqe_cnt[0x10];
2008
b4ff3a36 2009 u8 reserved_at_100[0x40];
e281682b
SM		 2010
2011 u8 db_record_addr_h[0x20];
2012
2013 u8 db_record_addr_l[0x1e];
b4ff3a36 2014 u8 reserved_at_17e[0x2];
e281682b 2015
b4ff3a36 2016 u8 reserved_at_180[0x80];
e281682b
SM		 2017};
2018
2019struct mlx5_ifc_traffic_counter_bits {
2020 u8 packets[0x40];
2021
2022 u8 octets[0x40];
2023};
2024
2025struct mlx5_ifc_tisc_bits {
b4ff3a36 2026 u8 reserved_at_0[0xc];
e281682b 2027 u8 prio[0x4];
b4ff3a36 2028 u8 reserved_at_10[0x10];
e281682b 2029
b4ff3a36 2030 u8 reserved_at_20[0x100];
e281682b 2031
b4ff3a36 2032 u8 reserved_at_120[0x8];
e281682b
SM		 2033 u8 transport_domain[0x18];
2034
b4ff3a36 2035 u8 reserved_at_140[0x3c0];
e281682b
SM		 2036};
2037
2038enum {
2039 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2040 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2041};
2042
2043enum {
2044 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2045 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2046};
2047
2048enum {
2be6967c
SM		 2049 MLX5_RX_HASH_FN_NONE = 0x0,
2050 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2051 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2052};
2053
2054enum {
2055 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2056 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2057};
2058
2059struct mlx5_ifc_tirc_bits {
b4ff3a36 2060 u8 reserved_at_0[0x20];
e281682b
SM		 2061
2062 u8 disp_type[0x4];
b4ff3a36 2063 u8 reserved_at_24[0x1c];
e281682b 2064
b4ff3a36 2065 u8 reserved_at_40[0x40];
e281682b 2066
b4ff3a36 2067 u8 reserved_at_80[0x4];
e281682b
SM		 2068 u8 lro_timeout_period_usecs[0x10];
2069 u8 lro_enable_mask[0x4];
2070 u8 lro_max_ip_payload_size[0x8];
2071
b4ff3a36 2072 u8 reserved_at_a0[0x40];
e281682b 2073
b4ff3a36 2074 u8 reserved_at_e0[0x8];
e281682b
SM		 2075 u8 inline_rqn[0x18];
2076
2077 u8 rx_hash_symmetric[0x1];
b4ff3a36 2078 u8 reserved_at_101[0x1];
e281682b 2079 u8 tunneled_offload_en[0x1];
b4ff3a36 2080 u8 reserved_at_103[0x5];
e281682b
SM		 2081 u8 indirect_table[0x18];
2082
2083 u8 rx_hash_fn[0x4];
b4ff3a36 2084 u8 reserved_at_124[0x2];
e281682b
SM		 2085 u8 self_lb_block[0x2];
2086 u8 transport_domain[0x18];
2087
2088 u8 rx_hash_toeplitz_key[10][0x20];
2089
2090 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2091
2092 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2093
b4ff3a36 2094 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2095};
2096
2097enum {
2098 MLX5_SRQC_STATE_GOOD = 0x0,
2099 MLX5_SRQC_STATE_ERROR = 0x1,
2100};
2101
2102struct mlx5_ifc_srqc_bits {
2103 u8 state[0x4];
2104 u8 log_srq_size[0x4];
b4ff3a36 2105 u8 reserved_at_8[0x18];
e281682b
SM		 2106
2107 u8 wq_signature[0x1];
2108 u8 cont_srq[0x1];
b4ff3a36 2109 u8 reserved_at_22[0x1];
e281682b 2110 u8 rlky[0x1];
b4ff3a36 2111 u8 reserved_at_24[0x1];
e281682b
SM		 2112 u8 log_rq_stride[0x3];
2113 u8 xrcd[0x18];
2114
2115 u8 page_offset[0x6];
b4ff3a36 2116 u8 reserved_at_46[0x2];
e281682b
SM		 2117 u8 cqn[0x18];
2118
b4ff3a36 2119 u8 reserved_at_60[0x20];
e281682b 2120
b4ff3a36 2121 u8 reserved_at_80[0x2];
e281682b 2122 u8 log_page_size[0x6];
b4ff3a36 2123 u8 reserved_at_88[0x18];
e281682b 2124
b4ff3a36 2125 u8 reserved_at_a0[0x20];
e281682b 2126
b4ff3a36 2127 u8 reserved_at_c0[0x8];
e281682b
SM		 2128 u8 pd[0x18];
2129
2130 u8 lwm[0x10];
2131 u8 wqe_cnt[0x10];
2132
b4ff3a36 2133 u8 reserved_at_100[0x40];
e281682b 2134
01949d01 2135 u8 dbr_addr[0x40];
e281682b 2136
b4ff3a36 2137 u8 reserved_at_180[0x80];
e281682b
SM		 2138};
2139
2140enum {
2141 MLX5_SQC_STATE_RST = 0x0,
2142 MLX5_SQC_STATE_RDY = 0x1,
2143 MLX5_SQC_STATE_ERR = 0x3,
2144};
2145
2146struct mlx5_ifc_sqc_bits {
2147 u8 rlky[0x1];
2148 u8 cd_master[0x1];
2149 u8 fre[0x1];
2150 u8 flush_in_error_en[0x1];
b4ff3a36 2151 u8 reserved_at_4[0x4];
e281682b 2152 u8 state[0x4];
b4ff3a36 2153 u8 reserved_at_c[0x14];
e281682b 2154
b4ff3a36 2155 u8 reserved_at_20[0x8];
e281682b
SM		 2156 u8 user_index[0x18];
2157
b4ff3a36 2158 u8 reserved_at_40[0x8];
e281682b
SM		 2159 u8 cqn[0x18];
2160
b4ff3a36 2161 u8 reserved_at_60[0xa0];
e281682b
SM		 2162
2163 u8 tis_lst_sz[0x10];
b4ff3a36 2164 u8 reserved_at_110[0x10];
e281682b 2165
b4ff3a36 2166 u8 reserved_at_120[0x40];
e281682b 2167
b4ff3a36 2168 u8 reserved_at_160[0x8];
e281682b
SM		 2169 u8 tis_num_0[0x18];
2170
2171 struct mlx5_ifc_wq_bits wq;
2172};
2173
2174struct mlx5_ifc_rqtc_bits {
b4ff3a36 2175 u8 reserved_at_0[0xa0];
e281682b 2176
b4ff3a36 2177 u8 reserved_at_a0[0x10];
e281682b
SM		 2178 u8 rqt_max_size[0x10];
2179
b4ff3a36 2180 u8 reserved_at_c0[0x10];
e281682b
SM		 2181 u8 rqt_actual_size[0x10];
2182
b4ff3a36 2183 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2184
2185 struct mlx5_ifc_rq_num_bits rq_num[0];
2186};
2187
2188enum {
2189 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2190 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2191};
2192
2193enum {
2194 MLX5_RQC_STATE_RST = 0x0,
2195 MLX5_RQC_STATE_RDY = 0x1,
2196 MLX5_RQC_STATE_ERR = 0x3,
2197};
2198
2199struct mlx5_ifc_rqc_bits {
2200 u8 rlky[0x1];
b4ff3a36 2201 u8 reserved_at_1[0x2];
e281682b
SM		 2202 u8 vsd[0x1];
2203 u8 mem_rq_type[0x4];
2204 u8 state[0x4];
b4ff3a36 2205 u8 reserved_at_c[0x1];
e281682b 2206 u8 flush_in_error_en[0x1];
b4ff3a36 2207 u8 reserved_at_e[0x12];
e281682b 2208
b4ff3a36 2209 u8 reserved_at_20[0x8];
e281682b
SM		 2210 u8 user_index[0x18];
2211
b4ff3a36 2212 u8 reserved_at_40[0x8];
e281682b
SM		 2213 u8 cqn[0x18];
2214
2215 u8 counter_set_id[0x8];
b4ff3a36 2216 u8 reserved_at_68[0x18];
e281682b 2217
b4ff3a36 2218 u8 reserved_at_80[0x8];
e281682b
SM		 2219 u8 rmpn[0x18];
2220
b4ff3a36 2221 u8 reserved_at_a0[0xe0];
e281682b
SM		 2222
2223 struct mlx5_ifc_wq_bits wq;
2224};
2225
2226enum {
2227 MLX5_RMPC_STATE_RDY = 0x1,
2228 MLX5_RMPC_STATE_ERR = 0x3,
2229};
2230
2231struct mlx5_ifc_rmpc_bits {
b4ff3a36 2232 u8 reserved_at_0[0x8];
e281682b 2233 u8 state[0x4];
b4ff3a36 2234 u8 reserved_at_c[0x14];
e281682b
SM		 2235
2236 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2237 u8 reserved_at_21[0x1f];
e281682b 2238
b4ff3a36 2239 u8 reserved_at_40[0x140];
e281682b
SM		 2240
2241 struct mlx5_ifc_wq_bits wq;
2242};
2243
e281682b 2244struct mlx5_ifc_nic_vport_context_bits {
b4ff3a36 2245 u8 reserved_at_0[0x1f];
e281682b
SM		 2246 u8 roce_en[0x1];
2247
d82b7318 2248 u8 arm_change_event[0x1];
b4ff3a36 2249 u8 reserved_at_21[0x1a];
d82b7318
SM		 2250 u8 event_on_mtu[0x1];
2251 u8 event_on_promisc_change[0x1];
2252 u8 event_on_vlan_change[0x1];
2253 u8 event_on_mc_address_change[0x1];
2254 u8 event_on_uc_address_change[0x1];
e281682b 2255
b4ff3a36 2256 u8 reserved_at_40[0xf0];
d82b7318
SM		 2257
2258 u8 mtu[0x10];
2259
9efa7525
AS		 2260 u8 system_image_guid[0x40];
2261 u8 port_guid[0x40];
2262 u8 node_guid[0x40];
2263
b4ff3a36 2264 u8 reserved_at_200[0x140];
9efa7525 2265 u8 qkey_violation_counter[0x10];
b4ff3a36 2266 u8 reserved_at_350[0x430];
d82b7318
SM		 2267
2268 u8 promisc_uc[0x1];
2269 u8 promisc_mc[0x1];
2270 u8 promisc_all[0x1];
b4ff3a36 2271 u8 reserved_at_783[0x2];
e281682b 2272 u8 allowed_list_type[0x3];
b4ff3a36 2273 u8 reserved_at_788[0xc];
e281682b
SM		 2274 u8 allowed_list_size[0xc];
2275
2276 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2277
b4ff3a36 2278 u8 reserved_at_7e0[0x20];
e281682b
SM		 2279
2280 u8 current_uc_mac_address[0][0x40];
2281};
2282
2283enum {
2284 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2285 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2286 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2287};
2288
2289struct mlx5_ifc_mkc_bits {
b4ff3a36 2290 u8 reserved_at_0[0x1];
e281682b 2291 u8 free[0x1];
b4ff3a36 2292 u8 reserved_at_2[0xd];
e281682b
SM		 2293 u8 small_fence_on_rdma_read_response[0x1];
2294 u8 umr_en[0x1];
2295 u8 a[0x1];
2296 u8 rw[0x1];
2297 u8 rr[0x1];
2298 u8 lw[0x1];
2299 u8 lr[0x1];
2300 u8 access_mode[0x2];
b4ff3a36 2301 u8 reserved_at_18[0x8];
e281682b
SM		 2302
2303 u8 qpn[0x18];
2304 u8 mkey_7_0[0x8];
2305
b4ff3a36 2306 u8 reserved_at_40[0x20];
e281682b
SM		 2307
2308 u8 length64[0x1];
2309 u8 bsf_en[0x1];
2310 u8 sync_umr[0x1];
b4ff3a36 2311 u8 reserved_at_63[0x2];
e281682b 2312 u8 expected_sigerr_count[0x1];
b4ff3a36 2313 u8 reserved_at_66[0x1];
e281682b
SM		 2314 u8 en_rinval[0x1];
2315 u8 pd[0x18];
2316
2317 u8 start_addr[0x40];
2318
2319 u8 len[0x40];
2320
2321 u8 bsf_octword_size[0x20];
2322
b4ff3a36 2323 u8 reserved_at_120[0x80];
e281682b
SM		 2324
2325 u8 translations_octword_size[0x20];
2326
b4ff3a36 2327 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2328 u8 log_page_size[0x5];
2329
b4ff3a36 2330 u8 reserved_at_1e0[0x20];
e281682b
SM		 2331};
2332
2333struct mlx5_ifc_pkey_bits {
b4ff3a36 2334 u8 reserved_at_0[0x10];
e281682b
SM		 2335 u8 pkey[0x10];
2336};
2337
2338struct mlx5_ifc_array128_auto_bits {
2339 u8 array128_auto[16][0x8];
2340};
2341
2342struct mlx5_ifc_hca_vport_context_bits {
2343 u8 field_select[0x20];
2344
b4ff3a36 2345 u8 reserved_at_20[0xe0];
e281682b
SM		 2346
2347 u8 sm_virt_aware[0x1];
2348 u8 has_smi[0x1];
2349 u8 has_raw[0x1];
2350 u8 grh_required[0x1];
b4ff3a36 2351 u8 reserved_at_104[0xc];
707c4602
MD		 2352 u8 port_physical_state[0x4];
2353 u8 vport_state_policy[0x4];
2354 u8 port_state[0x4];
e281682b
SM		 2355 u8 vport_state[0x4];
2356
b4ff3a36 2357 u8 reserved_at_120[0x20];
707c4602
MD		 2358
2359 u8 system_image_guid[0x40];
e281682b
SM		 2360
2361 u8 port_guid[0x40];
2362
2363 u8 node_guid[0x40];
2364
2365 u8 cap_mask1[0x20];
2366
2367 u8 cap_mask1_field_select[0x20];
2368
2369 u8 cap_mask2[0x20];
2370
2371 u8 cap_mask2_field_select[0x20];
2372
b4ff3a36 2373 u8 reserved_at_280[0x80];
e281682b
SM		 2374
2375 u8 lid[0x10];
b4ff3a36 2376 u8 reserved_at_310[0x4];
e281682b
SM		 2377 u8 init_type_reply[0x4];
2378 u8 lmc[0x3];
2379 u8 subnet_timeout[0x5];
2380
2381 u8 sm_lid[0x10];
2382 u8 sm_sl[0x4];
b4ff3a36 2383 u8 reserved_at_334[0xc];
e281682b
SM		 2384
2385 u8 qkey_violation_counter[0x10];
2386 u8 pkey_violation_counter[0x10];
2387
b4ff3a36 2388 u8 reserved_at_360[0xca0];
e281682b
SM		 2389};
2390
d6666753 2391struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 2392 u8 reserved_at_0[0x3];
d6666753
SM		 2393 u8 vport_svlan_strip[0x1];
2394 u8 vport_cvlan_strip[0x1];
2395 u8 vport_svlan_insert[0x1];
2396 u8 vport_cvlan_insert[0x2];
b4ff3a36 2397 u8 reserved_at_8[0x18];
d6666753 2398
b4ff3a36 2399 u8 reserved_at_20[0x20];
d6666753
SM		 2400
2401 u8 svlan_cfi[0x1];
2402 u8 svlan_pcp[0x3];
2403 u8 svlan_id[0xc];
2404 u8 cvlan_cfi[0x1];
2405 u8 cvlan_pcp[0x3];
2406 u8 cvlan_id[0xc];
2407
b4ff3a36 2408 u8 reserved_at_60[0x7a0];
d6666753
SM		 2409};
2410
e281682b
SM		 2411enum {
2412 MLX5_EQC_STATUS_OK = 0x0,
2413 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2414};
2415
2416enum {
2417 MLX5_EQC_ST_ARMED = 0x9,
2418 MLX5_EQC_ST_FIRED = 0xa,
2419};
2420
2421struct mlx5_ifc_eqc_bits {
2422 u8 status[0x4];
b4ff3a36 2423 u8 reserved_at_4[0x9];
e281682b
SM		 2424 u8 ec[0x1];
2425 u8 oi[0x1];
b4ff3a36 2426 u8 reserved_at_f[0x5];
e281682b 2427 u8 st[0x4];
b4ff3a36 2428 u8 reserved_at_18[0x8];
e281682b 2429
b4ff3a36 2430 u8 reserved_at_20[0x20];
e281682b 2431
b4ff3a36 2432 u8 reserved_at_40[0x14];
e281682b 2433 u8 page_offset[0x6];
b4ff3a36 2434 u8 reserved_at_5a[0x6];
e281682b 2435
b4ff3a36 2436 u8 reserved_at_60[0x3];
e281682b
SM		 2437 u8 log_eq_size[0x5];
2438 u8 uar_page[0x18];
2439
b4ff3a36 2440 u8 reserved_at_80[0x20];
e281682b 2441
b4ff3a36 2442 u8 reserved_at_a0[0x18];
e281682b
SM		 2443 u8 intr[0x8];
2444
b4ff3a36 2445 u8 reserved_at_c0[0x3];
e281682b 2446 u8 log_page_size[0x5];
b4ff3a36 2447 u8 reserved_at_c8[0x18];
e281682b 2448
b4ff3a36 2449 u8 reserved_at_e0[0x60];
e281682b 2450
b4ff3a36 2451 u8 reserved_at_140[0x8];
e281682b
SM		 2452 u8 consumer_counter[0x18];
2453
b4ff3a36 2454 u8 reserved_at_160[0x8];
e281682b
SM		 2455 u8 producer_counter[0x18];
2456
b4ff3a36 2457 u8 reserved_at_180[0x80];
e281682b
SM		 2458};
2459
2460enum {
2461 MLX5_DCTC_STATE_ACTIVE = 0x0,
2462 MLX5_DCTC_STATE_DRAINING = 0x1,
2463 MLX5_DCTC_STATE_DRAINED = 0x2,
2464};
2465
2466enum {
2467 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2468 MLX5_DCTC_CS_RES_NA = 0x1,
2469 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2470};
2471
2472enum {
2473 MLX5_DCTC_MTU_256_BYTES = 0x1,
2474 MLX5_DCTC_MTU_512_BYTES = 0x2,
2475 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2476 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2477 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2478};
2479
2480struct mlx5_ifc_dctc_bits {
b4ff3a36 2481 u8 reserved_at_0[0x4];
e281682b 2482 u8 state[0x4];
b4ff3a36 2483 u8 reserved_at_8[0x18];
e281682b 2484
b4ff3a36 2485 u8 reserved_at_20[0x8];
e281682b
SM		 2486 u8 user_index[0x18];
2487
b4ff3a36 2488 u8 reserved_at_40[0x8];
e281682b
SM		 2489 u8 cqn[0x18];
2490
2491 u8 counter_set_id[0x8];
2492 u8 atomic_mode[0x4];
2493 u8 rre[0x1];
2494 u8 rwe[0x1];
2495 u8 rae[0x1];
2496 u8 atomic_like_write_en[0x1];
2497 u8 latency_sensitive[0x1];
2498 u8 rlky[0x1];
2499 u8 free_ar[0x1];
b4ff3a36 2500 u8 reserved_at_73[0xd];
e281682b 2501
b4ff3a36 2502 u8 reserved_at_80[0x8];
e281682b 2503 u8 cs_res[0x8];
b4ff3a36 2504 u8 reserved_at_90[0x3];
e281682b 2505 u8 min_rnr_nak[0x5];
b4ff3a36 2506 u8 reserved_at_98[0x8];
e281682b 2507
b4ff3a36 2508 u8 reserved_at_a0[0x8];
e281682b
SM		 2509 u8 srqn[0x18];
2510
b4ff3a36 2511 u8 reserved_at_c0[0x8];
e281682b
SM		 2512 u8 pd[0x18];
2513
2514 u8 tclass[0x8];
b4ff3a36 2515 u8 reserved_at_e8[0x4];
e281682b
SM		 2516 u8 flow_label[0x14];
2517
2518 u8 dc_access_key[0x40];
2519
b4ff3a36 2520 u8 reserved_at_140[0x5];
e281682b
SM		 2521 u8 mtu[0x3];
2522 u8 port[0x8];
2523 u8 pkey_index[0x10];
2524
b4ff3a36 2525 u8 reserved_at_160[0x8];
e281682b 2526 u8 my_addr_index[0x8];
b4ff3a36 2527 u8 reserved_at_170[0x8];
e281682b
SM		 2528 u8 hop_limit[0x8];
2529
2530 u8 dc_access_key_violation_count[0x20];
2531
b4ff3a36 2532 u8 reserved_at_1a0[0x14];
e281682b
SM		 2533 u8 dei_cfi[0x1];
2534 u8 eth_prio[0x3];
2535 u8 ecn[0x2];
2536 u8 dscp[0x6];
2537
b4ff3a36 2538 u8 reserved_at_1c0[0x40];
e281682b
SM		 2539};
2540
2541enum {
2542 MLX5_CQC_STATUS_OK = 0x0,
2543 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2544 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2545};
2546
2547enum {
2548 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2549 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2550};
2551
2552enum {
2553 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2554 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2555 MLX5_CQC_ST_FIRED = 0xa,
2556};
2557
2558struct mlx5_ifc_cqc_bits {
2559 u8 status[0x4];
b4ff3a36 2560 u8 reserved_at_4[0x4];
e281682b
SM		 2561 u8 cqe_sz[0x3];
2562 u8 cc[0x1];
b4ff3a36 2563 u8 reserved_at_c[0x1];
e281682b
SM		 2564 u8 scqe_break_moderation_en[0x1];
2565 u8 oi[0x1];
b4ff3a36 2566 u8 reserved_at_f[0x2];
e281682b
SM		 2567 u8 cqe_zip_en[0x1];
2568 u8 mini_cqe_res_format[0x2];
2569 u8 st[0x4];
b4ff3a36 2570 u8 reserved_at_18[0x8];
e281682b 2571
b4ff3a36 2572 u8 reserved_at_20[0x20];
e281682b 2573
b4ff3a36 2574 u8 reserved_at_40[0x14];
e281682b 2575 u8 page_offset[0x6];
b4ff3a36 2576 u8 reserved_at_5a[0x6];
e281682b 2577
b4ff3a36 2578 u8 reserved_at_60[0x3];
e281682b
SM		 2579 u8 log_cq_size[0x5];
2580 u8 uar_page[0x18];
2581
b4ff3a36 2582 u8 reserved_at_80[0x4];
e281682b
SM		 2583 u8 cq_period[0xc];
2584 u8 cq_max_count[0x10];
2585
b4ff3a36 2586 u8 reserved_at_a0[0x18];
e281682b
SM		 2587 u8 c_eqn[0x8];
2588
b4ff3a36 2589 u8 reserved_at_c0[0x3];
e281682b 2590 u8 log_page_size[0x5];
b4ff3a36 2591 u8 reserved_at_c8[0x18];
e281682b 2592
b4ff3a36 2593 u8 reserved_at_e0[0x20];
e281682b 2594
b4ff3a36 2595 u8 reserved_at_100[0x8];
e281682b
SM		 2596 u8 last_notified_index[0x18];
2597
b4ff3a36 2598 u8 reserved_at_120[0x8];
e281682b
SM		 2599 u8 last_solicit_index[0x18];
2600
b4ff3a36 2601 u8 reserved_at_140[0x8];
e281682b
SM		 2602 u8 consumer_counter[0x18];
2603
b4ff3a36 2604 u8 reserved_at_160[0x8];
e281682b
SM		 2605 u8 producer_counter[0x18];
2606
b4ff3a36 2607 u8 reserved_at_180[0x40];
e281682b
SM		 2608
2609 u8 dbr_addr[0x40];
2610};
2611
2612union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2613 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2614 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2615 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 2616 u8 reserved_at_0[0x800];
e281682b
SM		 2617};
2618
2619struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 2620 u8 reserved_at_0[0xc0];
e281682b 2621
b4ff3a36 2622 u8 reserved_at_c0[0x8];
211e6c80
MD		 2623 u8 ieee_vendor_id[0x18];
2624
b4ff3a36 2625 u8 reserved_at_e0[0x10];
e281682b
SM		 2626 u8 vsd_vendor_id[0x10];
2627
2628 u8 vsd[208][0x8];
2629
2630 u8 vsd_contd_psid[16][0x8];
2631};
2632
2633union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2634 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2635 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 2636 u8 reserved_at_0[0x20];
e281682b
SM		 2637};
2638
2639union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2640 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2641 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2642 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 2643 u8 reserved_at_0[0x20];
e281682b
SM		 2644};
2645
2646union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2647 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2648 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2649 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2650 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2651 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2652 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2653 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 2654 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 2655 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
b4ff3a36 2656 u8 reserved_at_0[0x7c0];
e281682b
SM		 2657};
2658
2659union mlx5_ifc_event_auto_bits {
2660 struct mlx5_ifc_comp_event_bits comp_event;
2661 struct mlx5_ifc_dct_events_bits dct_events;
2662 struct mlx5_ifc_qp_events_bits qp_events;
2663 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2664 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2665 struct mlx5_ifc_cq_error_bits cq_error;
2666 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2667 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2668 struct mlx5_ifc_gpio_event_bits gpio_event;
2669 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2670 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2671 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 2672 u8 reserved_at_0[0xe0];
e281682b
SM		 2673};
2674
2675struct mlx5_ifc_health_buffer_bits {
b4ff3a36 2676 u8 reserved_at_0[0x100];
e281682b
SM		 2677
2678 u8 assert_existptr[0x20];
2679
2680 u8 assert_callra[0x20];
2681
b4ff3a36 2682 u8 reserved_at_140[0x40];
e281682b
SM		 2683
2684 u8 fw_version[0x20];
2685
2686 u8 hw_id[0x20];
2687
b4ff3a36 2688 u8 reserved_at_1c0[0x20];
e281682b
SM		 2689
2690 u8 irisc_index[0x8];
2691 u8 synd[0x8];
2692 u8 ext_synd[0x10];
2693};
2694
2695struct mlx5_ifc_register_loopback_control_bits {
2696 u8 no_lb[0x1];
b4ff3a36 2697 u8 reserved_at_1[0x7];
e281682b 2698 u8 port[0x8];
b4ff3a36 2699 u8 reserved_at_10[0x10];
e281682b 2700
b4ff3a36 2701 u8 reserved_at_20[0x60];
e281682b
SM		 2702};
2703
2704struct mlx5_ifc_teardown_hca_out_bits {
2705 u8 status[0x8];
b4ff3a36 2706 u8 reserved_at_8[0x18];
e281682b
SM		 2707
2708 u8 syndrome[0x20];
2709
b4ff3a36 2710 u8 reserved_at_40[0x40];
e281682b
SM		 2711};
2712
2713enum {
2714 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2715 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2716};
2717
2718struct mlx5_ifc_teardown_hca_in_bits {
2719 u8 opcode[0x10];
b4ff3a36 2720 u8 reserved_at_10[0x10];
e281682b 2721
b4ff3a36 2722 u8 reserved_at_20[0x10];
e281682b
SM		 2723 u8 op_mod[0x10];
2724
b4ff3a36 2725 u8 reserved_at_40[0x10];
e281682b
SM		 2726 u8 profile[0x10];
2727
b4ff3a36 2728 u8 reserved_at_60[0x20];
e281682b
SM		 2729};
2730
2731struct mlx5_ifc_sqerr2rts_qp_out_bits {
2732 u8 status[0x8];
b4ff3a36 2733 u8 reserved_at_8[0x18];
e281682b
SM		 2734
2735 u8 syndrome[0x20];
2736
b4ff3a36 2737 u8 reserved_at_40[0x40];
e281682b
SM		 2738};
2739
2740struct mlx5_ifc_sqerr2rts_qp_in_bits {
2741 u8 opcode[0x10];
b4ff3a36 2742 u8 reserved_at_10[0x10];
e281682b 2743
b4ff3a36 2744 u8 reserved_at_20[0x10];
e281682b
SM		 2745 u8 op_mod[0x10];
2746
b4ff3a36 2747 u8 reserved_at_40[0x8];
e281682b
SM		 2748 u8 qpn[0x18];
2749
b4ff3a36 2750 u8 reserved_at_60[0x20];
e281682b
SM		 2751
2752 u8 opt_param_mask[0x20];
2753
b4ff3a36 2754 u8 reserved_at_a0[0x20];
e281682b
SM		 2755
2756 struct mlx5_ifc_qpc_bits qpc;
2757
b4ff3a36 2758 u8 reserved_at_800[0x80];
e281682b
SM		 2759};
2760
2761struct mlx5_ifc_sqd2rts_qp_out_bits {
2762 u8 status[0x8];
b4ff3a36 2763 u8 reserved_at_8[0x18];
e281682b
SM		 2764
2765 u8 syndrome[0x20];
2766
b4ff3a36 2767 u8 reserved_at_40[0x40];
e281682b
SM		 2768};
2769
2770struct mlx5_ifc_sqd2rts_qp_in_bits {
2771 u8 opcode[0x10];
b4ff3a36 2772 u8 reserved_at_10[0x10];
e281682b 2773
b4ff3a36 2774 u8 reserved_at_20[0x10];
e281682b
SM		 2775 u8 op_mod[0x10];
2776
b4ff3a36 2777 u8 reserved_at_40[0x8];
e281682b
SM		 2778 u8 qpn[0x18];
2779
b4ff3a36 2780 u8 reserved_at_60[0x20];
e281682b
SM		 2781
2782 u8 opt_param_mask[0x20];
2783
b4ff3a36 2784 u8 reserved_at_a0[0x20];
e281682b
SM		 2785
2786 struct mlx5_ifc_qpc_bits qpc;
2787
b4ff3a36 2788 u8 reserved_at_800[0x80];
e281682b
SM		 2789};
2790
2791struct mlx5_ifc_set_roce_address_out_bits {
2792 u8 status[0x8];
b4ff3a36 2793 u8 reserved_at_8[0x18];
e281682b
SM		 2794
2795 u8 syndrome[0x20];
2796
b4ff3a36 2797 u8 reserved_at_40[0x40];
e281682b
SM		 2798};
2799
2800struct mlx5_ifc_set_roce_address_in_bits {
2801 u8 opcode[0x10];
b4ff3a36 2802 u8 reserved_at_10[0x10];
e281682b 2803
b4ff3a36 2804 u8 reserved_at_20[0x10];
e281682b
SM		 2805 u8 op_mod[0x10];
2806
2807 u8 roce_address_index[0x10];
b4ff3a36 2808 u8 reserved_at_50[0x10];
e281682b 2809
b4ff3a36 2810 u8 reserved_at_60[0x20];
e281682b
SM		 2811
2812 struct mlx5_ifc_roce_addr_layout_bits roce_address;
2813};
2814
2815struct mlx5_ifc_set_mad_demux_out_bits {
2816 u8 status[0x8];
b4ff3a36 2817 u8 reserved_at_8[0x18];
e281682b
SM		 2818
2819 u8 syndrome[0x20];
2820
b4ff3a36 2821 u8 reserved_at_40[0x40];
e281682b
SM		 2822};
2823
2824enum {
2825 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
2826 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
2827};
2828
2829struct mlx5_ifc_set_mad_demux_in_bits {
2830 u8 opcode[0x10];
b4ff3a36 2831 u8 reserved_at_10[0x10];
e281682b 2832
b4ff3a36 2833 u8 reserved_at_20[0x10];
e281682b
SM		 2834 u8 op_mod[0x10];
2835
b4ff3a36 2836 u8 reserved_at_40[0x20];
e281682b 2837
b4ff3a36 2838 u8 reserved_at_60[0x6];
e281682b 2839 u8 demux_mode[0x2];
b4ff3a36 2840 u8 reserved_at_68[0x18];
e281682b
SM		 2841};
2842
2843struct mlx5_ifc_set_l2_table_entry_out_bits {
2844 u8 status[0x8];
b4ff3a36 2845 u8 reserved_at_8[0x18];
e281682b
SM		 2846
2847 u8 syndrome[0x20];
2848
b4ff3a36 2849 u8 reserved_at_40[0x40];
e281682b
SM		 2850};
2851
2852struct mlx5_ifc_set_l2_table_entry_in_bits {
2853 u8 opcode[0x10];
b4ff3a36 2854 u8 reserved_at_10[0x10];
e281682b 2855
b4ff3a36 2856 u8 reserved_at_20[0x10];
e281682b
SM		 2857 u8 op_mod[0x10];
2858
b4ff3a36 2859 u8 reserved_at_40[0x60];
e281682b 2860
b4ff3a36 2861 u8 reserved_at_a0[0x8];
e281682b
SM		 2862 u8 table_index[0x18];
2863
b4ff3a36 2864 u8 reserved_at_c0[0x20];
e281682b 2865
b4ff3a36 2866 u8 reserved_at_e0[0x13];
e281682b
SM		 2867 u8 vlan_valid[0x1];
2868 u8 vlan[0xc];
2869
2870 struct mlx5_ifc_mac_address_layout_bits mac_address;
2871
b4ff3a36 2872 u8 reserved_at_140[0xc0];
e281682b
SM		 2873};
2874
2875struct mlx5_ifc_set_issi_out_bits {
2876 u8 status[0x8];
b4ff3a36 2877 u8 reserved_at_8[0x18];
e281682b
SM		 2878
2879 u8 syndrome[0x20];
2880
b4ff3a36 2881 u8 reserved_at_40[0x40];
e281682b
SM		 2882};
2883
2884struct mlx5_ifc_set_issi_in_bits {
2885 u8 opcode[0x10];
b4ff3a36 2886 u8 reserved_at_10[0x10];
e281682b 2887
b4ff3a36 2888 u8 reserved_at_20[0x10];
e281682b
SM		 2889 u8 op_mod[0x10];
2890
b4ff3a36 2891 u8 reserved_at_40[0x10];
e281682b
SM		 2892 u8 current_issi[0x10];
2893
b4ff3a36 2894 u8 reserved_at_60[0x20];
e281682b
SM		 2895};
2896
2897struct mlx5_ifc_set_hca_cap_out_bits {
2898 u8 status[0x8];
b4ff3a36 2899 u8 reserved_at_8[0x18];
e281682b
SM		 2900
2901 u8 syndrome[0x20];
2902
b4ff3a36 2903 u8 reserved_at_40[0x40];
e281682b
SM		 2904};
2905
2906struct mlx5_ifc_set_hca_cap_in_bits {
2907 u8 opcode[0x10];
b4ff3a36 2908 u8 reserved_at_10[0x10];
e281682b 2909
b4ff3a36 2910 u8 reserved_at_20[0x10];
e281682b
SM		 2911 u8 op_mod[0x10];
2912
b4ff3a36 2913 u8 reserved_at_40[0x40];
e281682b
SM		 2914
2915 union mlx5_ifc_hca_cap_union_bits capability;
2916};
2917
26a81453
MG		 2918enum {
2919 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
2920 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
2921 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
2922 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
2923};
2924
e281682b
SM		 2925struct mlx5_ifc_set_fte_out_bits {
2926 u8 status[0x8];
b4ff3a36 2927 u8 reserved_at_8[0x18];
e281682b
SM		 2928
2929 u8 syndrome[0x20];
2930
b4ff3a36 2931 u8 reserved_at_40[0x40];
e281682b
SM		 2932};
2933
2934struct mlx5_ifc_set_fte_in_bits {
2935 u8 opcode[0x10];
b4ff3a36 2936 u8 reserved_at_10[0x10];
e281682b 2937
b4ff3a36 2938 u8 reserved_at_20[0x10];
e281682b
SM		 2939 u8 op_mod[0x10];
2940
b4ff3a36 2941 u8 reserved_at_40[0x40];
e281682b
SM		 2942
2943 u8 table_type[0x8];
b4ff3a36 2944 u8 reserved_at_88[0x18];
e281682b 2945
b4ff3a36 2946 u8 reserved_at_a0[0x8];
e281682b
SM		 2947 u8 table_id[0x18];
2948
b4ff3a36 2949 u8 reserved_at_c0[0x18];
26a81453
MG		 2950 u8 modify_enable_mask[0x8];
2951
b4ff3a36 2952 u8 reserved_at_e0[0x20];
e281682b
SM		 2953
2954 u8 flow_index[0x20];
2955
b4ff3a36 2956 u8 reserved_at_120[0xe0];
e281682b
SM		 2957
2958 struct mlx5_ifc_flow_context_bits flow_context;
2959};
2960
2961struct mlx5_ifc_rts2rts_qp_out_bits {
2962 u8 status[0x8];
b4ff3a36 2963 u8 reserved_at_8[0x18];
e281682b
SM		 2964
2965 u8 syndrome[0x20];
2966
b4ff3a36 2967 u8 reserved_at_40[0x40];
e281682b
SM		 2968};
2969
2970struct mlx5_ifc_rts2rts_qp_in_bits {
2971 u8 opcode[0x10];
b4ff3a36 2972 u8 reserved_at_10[0x10];
e281682b 2973
b4ff3a36 2974 u8 reserved_at_20[0x10];
e281682b
SM		 2975 u8 op_mod[0x10];
2976
b4ff3a36 2977 u8 reserved_at_40[0x8];
e281682b
SM		 2978 u8 qpn[0x18];
2979
b4ff3a36 2980 u8 reserved_at_60[0x20];
e281682b
SM		 2981
2982 u8 opt_param_mask[0x20];
2983
b4ff3a36 2984 u8 reserved_at_a0[0x20];
e281682b
SM		 2985
2986 struct mlx5_ifc_qpc_bits qpc;
2987
b4ff3a36 2988 u8 reserved_at_800[0x80];
e281682b
SM		 2989};
2990
2991struct mlx5_ifc_rtr2rts_qp_out_bits {
2992 u8 status[0x8];
b4ff3a36 2993 u8 reserved_at_8[0x18];
e281682b
SM		 2994
2995 u8 syndrome[0x20];
2996
b4ff3a36 2997 u8 reserved_at_40[0x40];
e281682b
SM		 2998};
2999
3000struct mlx5_ifc_rtr2rts_qp_in_bits {
3001 u8 opcode[0x10];
b4ff3a36 3002 u8 reserved_at_10[0x10];
e281682b 3003
b4ff3a36 3004 u8 reserved_at_20[0x10];
e281682b
SM		 3005 u8 op_mod[0x10];
3006
b4ff3a36 3007 u8 reserved_at_40[0x8];
e281682b
SM		 3008 u8 qpn[0x18];
3009
b4ff3a36 3010 u8 reserved_at_60[0x20];
e281682b
SM		 3011
3012 u8 opt_param_mask[0x20];
3013
b4ff3a36 3014 u8 reserved_at_a0[0x20];
e281682b
SM		 3015
3016 struct mlx5_ifc_qpc_bits qpc;
3017
b4ff3a36 3018 u8 reserved_at_800[0x80];
e281682b
SM		 3019};
3020
3021struct mlx5_ifc_rst2init_qp_out_bits {
3022 u8 status[0x8];
b4ff3a36 3023 u8 reserved_at_8[0x18];
e281682b
SM		 3024
3025 u8 syndrome[0x20];
3026
b4ff3a36 3027 u8 reserved_at_40[0x40];
e281682b
SM		 3028};
3029
3030struct mlx5_ifc_rst2init_qp_in_bits {
3031 u8 opcode[0x10];
b4ff3a36 3032 u8 reserved_at_10[0x10];
e281682b 3033
b4ff3a36 3034 u8 reserved_at_20[0x10];
e281682b
SM		 3035 u8 op_mod[0x10];
3036
b4ff3a36 3037 u8 reserved_at_40[0x8];
e281682b
SM		 3038 u8 qpn[0x18];
3039
b4ff3a36 3040 u8 reserved_at_60[0x20];
e281682b
SM		 3041
3042 u8 opt_param_mask[0x20];
3043
b4ff3a36 3044 u8 reserved_at_a0[0x20];
e281682b
SM		 3045
3046 struct mlx5_ifc_qpc_bits qpc;
3047
b4ff3a36 3048 u8 reserved_at_800[0x80];
e281682b
SM		 3049};
3050
3051struct mlx5_ifc_query_xrc_srq_out_bits {
3052 u8 status[0x8];
b4ff3a36 3053 u8 reserved_at_8[0x18];
e281682b
SM		 3054
3055 u8 syndrome[0x20];
3056
b4ff3a36 3057 u8 reserved_at_40[0x40];
e281682b
SM		 3058
3059 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3060
b4ff3a36 3061 u8 reserved_at_280[0x600];
e281682b
SM		 3062
3063 u8 pas[0][0x40];
3064};
3065
3066struct mlx5_ifc_query_xrc_srq_in_bits {
3067 u8 opcode[0x10];
b4ff3a36 3068 u8 reserved_at_10[0x10];
e281682b 3069
b4ff3a36 3070 u8 reserved_at_20[0x10];
e281682b
SM		 3071 u8 op_mod[0x10];
3072
b4ff3a36 3073 u8 reserved_at_40[0x8];
e281682b
SM		 3074 u8 xrc_srqn[0x18];
3075
b4ff3a36 3076 u8 reserved_at_60[0x20];
e281682b
SM		 3077};
3078
3079enum {
3080 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3081 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3082};
3083
3084struct mlx5_ifc_query_vport_state_out_bits {
3085 u8 status[0x8];
b4ff3a36 3086 u8 reserved_at_8[0x18];
e281682b
SM		 3087
3088 u8 syndrome[0x20];
3089
b4ff3a36 3090 u8 reserved_at_40[0x20];
e281682b 3091
b4ff3a36 3092 u8 reserved_at_60[0x18];
e281682b
SM		 3093 u8 admin_state[0x4];
3094 u8 state[0x4];
3095};
3096
3097enum {
3098 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 3099 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3100};
3101
3102struct mlx5_ifc_query_vport_state_in_bits {
3103 u8 opcode[0x10];
b4ff3a36 3104 u8 reserved_at_10[0x10];
e281682b 3105
b4ff3a36 3106 u8 reserved_at_20[0x10];
e281682b
SM		 3107 u8 op_mod[0x10];
3108
3109 u8 other_vport[0x1];
b4ff3a36 3110 u8 reserved_at_41[0xf];
e281682b
SM		 3111 u8 vport_number[0x10];
3112
b4ff3a36 3113 u8 reserved_at_60[0x20];
e281682b
SM		 3114};
3115
3116struct mlx5_ifc_query_vport_counter_out_bits {
3117 u8 status[0x8];
b4ff3a36 3118 u8 reserved_at_8[0x18];
e281682b
SM		 3119
3120 u8 syndrome[0x20];
3121
b4ff3a36 3122 u8 reserved_at_40[0x40];
e281682b
SM		 3123
3124 struct mlx5_ifc_traffic_counter_bits received_errors;
3125
3126 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3127
3128 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3129
3130 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3131
3132 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3133
3134 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3135
3136 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3137
3138 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3139
3140 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3141
3142 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3143
3144 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3145
3146 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3147
b4ff3a36 3148 u8 reserved_at_680[0xa00];
e281682b
SM		 3149};
3150
3151enum {
3152 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3153};
3154
3155struct mlx5_ifc_query_vport_counter_in_bits {
3156 u8 opcode[0x10];
b4ff3a36 3157 u8 reserved_at_10[0x10];
e281682b 3158
b4ff3a36 3159 u8 reserved_at_20[0x10];
e281682b
SM		 3160 u8 op_mod[0x10];
3161
3162 u8 other_vport[0x1];
b54ba277
MY		 3163 u8 reserved_at_41[0xb];
3164 u8 port_num[0x4];
e281682b
SM		 3165 u8 vport_number[0x10];
3166
b4ff3a36 3167 u8 reserved_at_60[0x60];
e281682b
SM		 3168
3169 u8 clear[0x1];
b4ff3a36 3170 u8 reserved_at_c1[0x1f];
e281682b 3171
b4ff3a36 3172 u8 reserved_at_e0[0x20];
e281682b
SM		 3173};
3174
3175struct mlx5_ifc_query_tis_out_bits {
3176 u8 status[0x8];
b4ff3a36 3177 u8 reserved_at_8[0x18];
e281682b
SM		 3178
3179 u8 syndrome[0x20];
3180
b4ff3a36 3181 u8 reserved_at_40[0x40];
e281682b
SM		 3182
3183 struct mlx5_ifc_tisc_bits tis_context;
3184};
3185
3186struct mlx5_ifc_query_tis_in_bits {
3187 u8 opcode[0x10];
b4ff3a36 3188 u8 reserved_at_10[0x10];
e281682b 3189
b4ff3a36 3190 u8 reserved_at_20[0x10];
e281682b
SM		 3191 u8 op_mod[0x10];
3192
b4ff3a36 3193 u8 reserved_at_40[0x8];
e281682b
SM		 3194 u8 tisn[0x18];
3195
b4ff3a36 3196 u8 reserved_at_60[0x20];
e281682b
SM		 3197};
3198
3199struct mlx5_ifc_query_tir_out_bits {
3200 u8 status[0x8];
b4ff3a36 3201 u8 reserved_at_8[0x18];
e281682b
SM		 3202
3203 u8 syndrome[0x20];
3204
b4ff3a36 3205 u8 reserved_at_40[0xc0];
e281682b
SM		 3206
3207 struct mlx5_ifc_tirc_bits tir_context;
3208};
3209
3210struct mlx5_ifc_query_tir_in_bits {
3211 u8 opcode[0x10];
b4ff3a36 3212 u8 reserved_at_10[0x10];
e281682b 3213
b4ff3a36 3214 u8 reserved_at_20[0x10];
e281682b
SM		 3215 u8 op_mod[0x10];
3216
b4ff3a36 3217 u8 reserved_at_40[0x8];
e281682b
SM		 3218 u8 tirn[0x18];
3219
b4ff3a36 3220 u8 reserved_at_60[0x20];
e281682b
SM		 3221};
3222
3223struct mlx5_ifc_query_srq_out_bits {
3224 u8 status[0x8];
b4ff3a36 3225 u8 reserved_at_8[0x18];
e281682b
SM		 3226
3227 u8 syndrome[0x20];
3228
b4ff3a36 3229 u8 reserved_at_40[0x40];
e281682b
SM		 3230
3231 struct mlx5_ifc_srqc_bits srq_context_entry;
3232
b4ff3a36 3233 u8 reserved_at_280[0x600];
e281682b
SM		 3234
3235 u8 pas[0][0x40];
3236};
3237
3238struct mlx5_ifc_query_srq_in_bits {
3239 u8 opcode[0x10];
b4ff3a36 3240 u8 reserved_at_10[0x10];
e281682b 3241
b4ff3a36 3242 u8 reserved_at_20[0x10];
e281682b
SM		 3243 u8 op_mod[0x10];
3244
b4ff3a36 3245 u8 reserved_at_40[0x8];
e281682b
SM		 3246 u8 srqn[0x18];
3247
b4ff3a36 3248 u8 reserved_at_60[0x20];
e281682b
SM		 3249};
3250
3251struct mlx5_ifc_query_sq_out_bits {
3252 u8 status[0x8];
b4ff3a36 3253 u8 reserved_at_8[0x18];
e281682b
SM		 3254
3255 u8 syndrome[0x20];
3256
b4ff3a36 3257 u8 reserved_at_40[0xc0];
e281682b
SM		 3258
3259 struct mlx5_ifc_sqc_bits sq_context;
3260};
3261
3262struct mlx5_ifc_query_sq_in_bits {
3263 u8 opcode[0x10];
b4ff3a36 3264 u8 reserved_at_10[0x10];
e281682b 3265
b4ff3a36 3266 u8 reserved_at_20[0x10];
e281682b
SM		 3267 u8 op_mod[0x10];
3268
b4ff3a36 3269 u8 reserved_at_40[0x8];
e281682b
SM		 3270 u8 sqn[0x18];
3271
b4ff3a36 3272 u8 reserved_at_60[0x20];
e281682b
SM		 3273};
3274
3275struct mlx5_ifc_query_special_contexts_out_bits {
3276 u8 status[0x8];
b4ff3a36 3277 u8 reserved_at_8[0x18];
e281682b
SM		 3278
3279 u8 syndrome[0x20];
3280
b4ff3a36 3281 u8 reserved_at_40[0x20];
e281682b
SM		 3282
3283 u8 resd_lkey[0x20];
3284};
3285
3286struct mlx5_ifc_query_special_contexts_in_bits {
3287 u8 opcode[0x10];
b4ff3a36 3288 u8 reserved_at_10[0x10];
e281682b 3289
b4ff3a36 3290 u8 reserved_at_20[0x10];
e281682b
SM		 3291 u8 op_mod[0x10];
3292
b4ff3a36 3293 u8 reserved_at_40[0x40];
e281682b
SM		 3294};
3295
3296struct mlx5_ifc_query_rqt_out_bits {
3297 u8 status[0x8];
b4ff3a36 3298 u8 reserved_at_8[0x18];
e281682b
SM		 3299
3300 u8 syndrome[0x20];
3301
b4ff3a36 3302 u8 reserved_at_40[0xc0];
e281682b
SM		 3303
3304 struct mlx5_ifc_rqtc_bits rqt_context;
3305};
3306
3307struct mlx5_ifc_query_rqt_in_bits {
3308 u8 opcode[0x10];
b4ff3a36 3309 u8 reserved_at_10[0x10];
e281682b 3310
b4ff3a36 3311 u8 reserved_at_20[0x10];
e281682b
SM		 3312 u8 op_mod[0x10];
3313
b4ff3a36 3314 u8 reserved_at_40[0x8];
e281682b
SM		 3315 u8 rqtn[0x18];
3316
b4ff3a36 3317 u8 reserved_at_60[0x20];
e281682b
SM		 3318};
3319
3320struct mlx5_ifc_query_rq_out_bits {
3321 u8 status[0x8];
b4ff3a36 3322 u8 reserved_at_8[0x18];
e281682b
SM		 3323
3324 u8 syndrome[0x20];
3325
b4ff3a36 3326 u8 reserved_at_40[0xc0];
e281682b
SM		 3327
3328 struct mlx5_ifc_rqc_bits rq_context;
3329};
3330
3331struct mlx5_ifc_query_rq_in_bits {
3332 u8 opcode[0x10];
b4ff3a36 3333 u8 reserved_at_10[0x10];
e281682b 3334
b4ff3a36 3335 u8 reserved_at_20[0x10];
e281682b
SM		 3336 u8 op_mod[0x10];
3337
b4ff3a36 3338 u8 reserved_at_40[0x8];
e281682b
SM		 3339 u8 rqn[0x18];
3340
b4ff3a36 3341 u8 reserved_at_60[0x20];
e281682b
SM		 3342};
3343
3344struct mlx5_ifc_query_roce_address_out_bits {
3345 u8 status[0x8];
b4ff3a36 3346 u8 reserved_at_8[0x18];
e281682b
SM		 3347
3348 u8 syndrome[0x20];
3349
b4ff3a36 3350 u8 reserved_at_40[0x40];
e281682b
SM		 3351
3352 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3353};
3354
3355struct mlx5_ifc_query_roce_address_in_bits {
3356 u8 opcode[0x10];
b4ff3a36 3357 u8 reserved_at_10[0x10];
e281682b 3358
b4ff3a36 3359 u8 reserved_at_20[0x10];
e281682b
SM		 3360 u8 op_mod[0x10];
3361
3362 u8 roce_address_index[0x10];
b4ff3a36 3363 u8 reserved_at_50[0x10];
e281682b 3364
b4ff3a36 3365 u8 reserved_at_60[0x20];
e281682b
SM		 3366};
3367
3368struct mlx5_ifc_query_rmp_out_bits {
3369 u8 status[0x8];
b4ff3a36 3370 u8 reserved_at_8[0x18];
e281682b
SM		 3371
3372 u8 syndrome[0x20];
3373
b4ff3a36 3374 u8 reserved_at_40[0xc0];
e281682b
SM		 3375
3376 struct mlx5_ifc_rmpc_bits rmp_context;
3377};
3378
3379struct mlx5_ifc_query_rmp_in_bits {
3380 u8 opcode[0x10];
b4ff3a36 3381 u8 reserved_at_10[0x10];
e281682b 3382
b4ff3a36 3383 u8 reserved_at_20[0x10];
e281682b
SM		 3384 u8 op_mod[0x10];
3385
b4ff3a36 3386 u8 reserved_at_40[0x8];
e281682b
SM		 3387 u8 rmpn[0x18];
3388
b4ff3a36 3389 u8 reserved_at_60[0x20];
e281682b
SM		 3390};
3391
3392struct mlx5_ifc_query_qp_out_bits {
3393 u8 status[0x8];
b4ff3a36 3394 u8 reserved_at_8[0x18];
e281682b
SM		 3395
3396 u8 syndrome[0x20];
3397
b4ff3a36 3398 u8 reserved_at_40[0x40];
e281682b
SM		 3399
3400 u8 opt_param_mask[0x20];
3401
b4ff3a36 3402 u8 reserved_at_a0[0x20];
e281682b
SM		 3403
3404 struct mlx5_ifc_qpc_bits qpc;
3405
b4ff3a36 3406 u8 reserved_at_800[0x80];
e281682b
SM		 3407
3408 u8 pas[0][0x40];
3409};
3410
3411struct mlx5_ifc_query_qp_in_bits {
3412 u8 opcode[0x10];
b4ff3a36 3413 u8 reserved_at_10[0x10];
e281682b 3414
b4ff3a36 3415 u8 reserved_at_20[0x10];
e281682b
SM		 3416 u8 op_mod[0x10];
3417
b4ff3a36 3418 u8 reserved_at_40[0x8];
e281682b
SM		 3419 u8 qpn[0x18];
3420
b4ff3a36 3421 u8 reserved_at_60[0x20];
e281682b
SM		 3422};
3423
3424struct mlx5_ifc_query_q_counter_out_bits {
3425 u8 status[0x8];
b4ff3a36 3426 u8 reserved_at_8[0x18];
e281682b
SM		 3427
3428 u8 syndrome[0x20];
3429
b4ff3a36 3430 u8 reserved_at_40[0x40];
e281682b
SM		 3431
3432 u8 rx_write_requests[0x20];
3433
b4ff3a36 3434 u8 reserved_at_a0[0x20];
e281682b
SM		 3435
3436 u8 rx_read_requests[0x20];
3437
b4ff3a36 3438 u8 reserved_at_e0[0x20];
e281682b
SM		 3439
3440 u8 rx_atomic_requests[0x20];
3441
b4ff3a36 3442 u8 reserved_at_120[0x20];
e281682b
SM		 3443
3444 u8 rx_dct_connect[0x20];
3445
b4ff3a36 3446 u8 reserved_at_160[0x20];
e281682b
SM		 3447
3448 u8 out_of_buffer[0x20];
3449
b4ff3a36 3450 u8 reserved_at_1a0[0x20];
e281682b
SM		 3451
3452 u8 out_of_sequence[0x20];
3453
b4ff3a36 3454 u8 reserved_at_1e0[0x620];
e281682b
SM		 3455};
3456
3457struct mlx5_ifc_query_q_counter_in_bits {
3458 u8 opcode[0x10];
b4ff3a36 3459 u8 reserved_at_10[0x10];
e281682b 3460
b4ff3a36 3461 u8 reserved_at_20[0x10];
e281682b
SM		 3462 u8 op_mod[0x10];
3463
b4ff3a36 3464 u8 reserved_at_40[0x80];
e281682b
SM		 3465
3466 u8 clear[0x1];
b4ff3a36 3467 u8 reserved_at_c1[0x1f];
e281682b 3468
b4ff3a36 3469 u8 reserved_at_e0[0x18];
e281682b
SM		 3470 u8 counter_set_id[0x8];
3471};
3472
3473struct mlx5_ifc_query_pages_out_bits {
3474 u8 status[0x8];
b4ff3a36 3475 u8 reserved_at_8[0x18];
e281682b
SM		 3476
3477 u8 syndrome[0x20];
3478
b4ff3a36 3479 u8 reserved_at_40[0x10];
e281682b
SM		 3480 u8 function_id[0x10];
3481
3482 u8 num_pages[0x20];
3483};
3484
3485enum {
3486 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3487 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3488 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3489};
3490
3491struct mlx5_ifc_query_pages_in_bits {
3492 u8 opcode[0x10];
b4ff3a36 3493 u8 reserved_at_10[0x10];
e281682b 3494
b4ff3a36 3495 u8 reserved_at_20[0x10];
e281682b
SM		 3496 u8 op_mod[0x10];
3497
b4ff3a36 3498 u8 reserved_at_40[0x10];
e281682b
SM		 3499 u8 function_id[0x10];
3500
b4ff3a36 3501 u8 reserved_at_60[0x20];
e281682b
SM		 3502};
3503
3504struct mlx5_ifc_query_nic_vport_context_out_bits {
3505 u8 status[0x8];
b4ff3a36 3506 u8 reserved_at_8[0x18];
e281682b
SM		 3507
3508 u8 syndrome[0x20];
3509
b4ff3a36 3510 u8 reserved_at_40[0x40];
e281682b
SM		 3511
3512 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3513};
3514
3515struct mlx5_ifc_query_nic_vport_context_in_bits {
3516 u8 opcode[0x10];
b4ff3a36 3517 u8 reserved_at_10[0x10];
e281682b 3518
b4ff3a36 3519 u8 reserved_at_20[0x10];
e281682b
SM		 3520 u8 op_mod[0x10];
3521
3522 u8 other_vport[0x1];
b4ff3a36 3523 u8 reserved_at_41[0xf];
e281682b
SM		 3524 u8 vport_number[0x10];
3525
b4ff3a36 3526 u8 reserved_at_60[0x5];
e281682b 3527 u8 allowed_list_type[0x3];
b4ff3a36 3528 u8 reserved_at_68[0x18];
e281682b
SM		 3529};
3530
3531struct mlx5_ifc_query_mkey_out_bits {
3532 u8 status[0x8];
b4ff3a36 3533 u8 reserved_at_8[0x18];
e281682b
SM		 3534
3535 u8 syndrome[0x20];
3536
b4ff3a36 3537 u8 reserved_at_40[0x40];
e281682b
SM		 3538
3539 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3540
b4ff3a36 3541 u8 reserved_at_280[0x600];
e281682b
SM		 3542
3543 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3544
3545 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3546};
3547
3548struct mlx5_ifc_query_mkey_in_bits {
3549 u8 opcode[0x10];
b4ff3a36 3550 u8 reserved_at_10[0x10];
e281682b 3551
b4ff3a36 3552 u8 reserved_at_20[0x10];
e281682b
SM		 3553 u8 op_mod[0x10];
3554
b4ff3a36 3555 u8 reserved_at_40[0x8];
e281682b
SM		 3556 u8 mkey_index[0x18];
3557
3558 u8 pg_access[0x1];
b4ff3a36 3559 u8 reserved_at_61[0x1f];
e281682b
SM		 3560};
3561
3562struct mlx5_ifc_query_mad_demux_out_bits {
3563 u8 status[0x8];
b4ff3a36 3564 u8 reserved_at_8[0x18];
e281682b
SM		 3565
3566 u8 syndrome[0x20];
3567
b4ff3a36 3568 u8 reserved_at_40[0x40];
e281682b
SM		 3569
3570 u8 mad_dumux_parameters_block[0x20];
3571};
3572
3573struct mlx5_ifc_query_mad_demux_in_bits {
3574 u8 opcode[0x10];
b4ff3a36 3575 u8 reserved_at_10[0x10];
e281682b 3576
b4ff3a36 3577 u8 reserved_at_20[0x10];
e281682b
SM		 3578 u8 op_mod[0x10];
3579
b4ff3a36 3580 u8 reserved_at_40[0x40];
e281682b
SM		 3581};
3582
3583struct mlx5_ifc_query_l2_table_entry_out_bits {
3584 u8 status[0x8];
b4ff3a36 3585 u8 reserved_at_8[0x18];
e281682b
SM		 3586
3587 u8 syndrome[0x20];
3588
b4ff3a36 3589 u8 reserved_at_40[0xa0];
e281682b 3590
b4ff3a36 3591 u8 reserved_at_e0[0x13];
e281682b
SM		 3592 u8 vlan_valid[0x1];
3593 u8 vlan[0xc];
3594
3595 struct mlx5_ifc_mac_address_layout_bits mac_address;
3596
b4ff3a36 3597 u8 reserved_at_140[0xc0];
e281682b
SM		 3598};
3599
3600struct mlx5_ifc_query_l2_table_entry_in_bits {
3601 u8 opcode[0x10];
b4ff3a36 3602 u8 reserved_at_10[0x10];
e281682b 3603
b4ff3a36 3604 u8 reserved_at_20[0x10];
e281682b
SM		 3605 u8 op_mod[0x10];
3606
b4ff3a36 3607 u8 reserved_at_40[0x60];
e281682b 3608
b4ff3a36 3609 u8 reserved_at_a0[0x8];
e281682b
SM		 3610 u8 table_index[0x18];
3611
b4ff3a36 3612 u8 reserved_at_c0[0x140];
e281682b
SM		 3613};
3614
3615struct mlx5_ifc_query_issi_out_bits {
3616 u8 status[0x8];
b4ff3a36 3617 u8 reserved_at_8[0x18];
e281682b
SM		 3618
3619 u8 syndrome[0x20];
3620
b4ff3a36 3621 u8 reserved_at_40[0x10];
e281682b
SM		 3622 u8 current_issi[0x10];
3623
b4ff3a36 3624 u8 reserved_at_60[0xa0];
e281682b 3625
b4ff3a36 3626 u8 reserved_at_100[76][0x8];
e281682b
SM		 3627 u8 supported_issi_dw0[0x20];
3628};
3629
3630struct mlx5_ifc_query_issi_in_bits {
3631 u8 opcode[0x10];
b4ff3a36 3632 u8 reserved_at_10[0x10];
e281682b 3633
b4ff3a36 3634 u8 reserved_at_20[0x10];
e281682b
SM		 3635 u8 op_mod[0x10];
3636
b4ff3a36 3637 u8 reserved_at_40[0x40];
e281682b
SM		 3638};
3639
3640struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3641 u8 status[0x8];
b4ff3a36 3642 u8 reserved_at_8[0x18];
e281682b
SM		 3643
3644 u8 syndrome[0x20];
3645
b4ff3a36 3646 u8 reserved_at_40[0x40];
e281682b
SM		 3647
3648 struct mlx5_ifc_pkey_bits pkey[0];
3649};
3650
3651struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3652 u8 opcode[0x10];
b4ff3a36 3653 u8 reserved_at_10[0x10];
e281682b 3654
b4ff3a36 3655 u8 reserved_at_20[0x10];
e281682b
SM		 3656 u8 op_mod[0x10];
3657
3658 u8 other_vport[0x1];
b4ff3a36 3659 u8 reserved_at_41[0xb];
707c4602 3660 u8 port_num[0x4];
e281682b
SM		 3661 u8 vport_number[0x10];
3662
b4ff3a36 3663 u8 reserved_at_60[0x10];
e281682b
SM		 3664 u8 pkey_index[0x10];
3665};
3666
3667struct mlx5_ifc_query_hca_vport_gid_out_bits {
3668 u8 status[0x8];
b4ff3a36 3669 u8 reserved_at_8[0x18];
e281682b
SM		 3670
3671 u8 syndrome[0x20];
3672
b4ff3a36 3673 u8 reserved_at_40[0x20];
e281682b
SM		 3674
3675 u8 gids_num[0x10];
b4ff3a36 3676 u8 reserved_at_70[0x10];
e281682b
SM		 3677
3678 struct mlx5_ifc_array128_auto_bits gid[0];
3679};
3680
3681struct mlx5_ifc_query_hca_vport_gid_in_bits {
3682 u8 opcode[0x10];
b4ff3a36 3683 u8 reserved_at_10[0x10];
e281682b 3684
b4ff3a36 3685 u8 reserved_at_20[0x10];
e281682b
SM		 3686 u8 op_mod[0x10];
3687
3688 u8 other_vport[0x1];
b4ff3a36 3689 u8 reserved_at_41[0xb];
707c4602 3690 u8 port_num[0x4];
e281682b
SM		 3691 u8 vport_number[0x10];
3692
b4ff3a36 3693 u8 reserved_at_60[0x10];
e281682b
SM		 3694 u8 gid_index[0x10];
3695};
3696
3697struct mlx5_ifc_query_hca_vport_context_out_bits {
3698 u8 status[0x8];
b4ff3a36 3699 u8 reserved_at_8[0x18];
e281682b
SM		 3700
3701 u8 syndrome[0x20];
3702
b4ff3a36 3703 u8 reserved_at_40[0x40];
e281682b
SM		 3704
3705 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3706};
3707
3708struct mlx5_ifc_query_hca_vport_context_in_bits {
3709 u8 opcode[0x10];
b4ff3a36 3710 u8 reserved_at_10[0x10];
e281682b 3711
b4ff3a36 3712 u8 reserved_at_20[0x10];
e281682b
SM		 3713 u8 op_mod[0x10];
3714
3715 u8 other_vport[0x1];
b4ff3a36 3716 u8 reserved_at_41[0xb];
707c4602 3717 u8 port_num[0x4];
e281682b
SM		 3718 u8 vport_number[0x10];
3719
b4ff3a36 3720 u8 reserved_at_60[0x20];
e281682b
SM		 3721};
3722
3723struct mlx5_ifc_query_hca_cap_out_bits {
3724 u8 status[0x8];
b4ff3a36 3725 u8 reserved_at_8[0x18];
e281682b
SM		 3726
3727 u8 syndrome[0x20];
3728
b4ff3a36 3729 u8 reserved_at_40[0x40];
e281682b
SM		 3730
3731 union mlx5_ifc_hca_cap_union_bits capability;
3732};
3733
3734struct mlx5_ifc_query_hca_cap_in_bits {
3735 u8 opcode[0x10];
b4ff3a36 3736 u8 reserved_at_10[0x10];
e281682b 3737
b4ff3a36 3738 u8 reserved_at_20[0x10];
e281682b
SM		 3739 u8 op_mod[0x10];
3740
b4ff3a36 3741 u8 reserved_at_40[0x40];
e281682b
SM		 3742};
3743
3744struct mlx5_ifc_query_flow_table_out_bits {
3745 u8 status[0x8];
b4ff3a36 3746 u8 reserved_at_8[0x18];
e281682b
SM		 3747
3748 u8 syndrome[0x20];
3749
b4ff3a36 3750 u8 reserved_at_40[0x80];
e281682b 3751
b4ff3a36 3752 u8 reserved_at_c0[0x8];
e281682b 3753 u8 level[0x8];
b4ff3a36 3754 u8 reserved_at_d0[0x8];
e281682b
SM		 3755 u8 log_size[0x8];
3756
b4ff3a36 3757 u8 reserved_at_e0[0x120];
e281682b
SM		 3758};
3759
3760struct mlx5_ifc_query_flow_table_in_bits {
3761 u8 opcode[0x10];
b4ff3a36 3762 u8 reserved_at_10[0x10];
e281682b 3763
b4ff3a36 3764 u8 reserved_at_20[0x10];
e281682b
SM		 3765 u8 op_mod[0x10];
3766
b4ff3a36 3767 u8 reserved_at_40[0x40];
e281682b
SM		 3768
3769 u8 table_type[0x8];
b4ff3a36 3770 u8 reserved_at_88[0x18];
e281682b 3771
b4ff3a36 3772 u8 reserved_at_a0[0x8];
e281682b
SM		 3773 u8 table_id[0x18];
3774
b4ff3a36 3775 u8 reserved_at_c0[0x140];
e281682b
SM		 3776};
3777
3778struct mlx5_ifc_query_fte_out_bits {
3779 u8 status[0x8];
b4ff3a36 3780 u8 reserved_at_8[0x18];
e281682b
SM		 3781
3782 u8 syndrome[0x20];
3783
b4ff3a36 3784 u8 reserved_at_40[0x1c0];
e281682b
SM		 3785
3786 struct mlx5_ifc_flow_context_bits flow_context;
3787};
3788
3789struct mlx5_ifc_query_fte_in_bits {
3790 u8 opcode[0x10];
b4ff3a36 3791 u8 reserved_at_10[0x10];
e281682b 3792
b4ff3a36 3793 u8 reserved_at_20[0x10];
e281682b
SM		 3794 u8 op_mod[0x10];
3795
b4ff3a36 3796 u8 reserved_at_40[0x40];
e281682b
SM		 3797
3798 u8 table_type[0x8];
b4ff3a36 3799 u8 reserved_at_88[0x18];
e281682b 3800
b4ff3a36 3801 u8 reserved_at_a0[0x8];
e281682b
SM		 3802 u8 table_id[0x18];
3803
b4ff3a36 3804 u8 reserved_at_c0[0x40];
e281682b
SM		 3805
3806 u8 flow_index[0x20];
3807
b4ff3a36 3808 u8 reserved_at_120[0xe0];
e281682b
SM		 3809};
3810
3811enum {
3812 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
3813 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
3814 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
3815};
3816
3817struct mlx5_ifc_query_flow_group_out_bits {
3818 u8 status[0x8];
b4ff3a36 3819 u8 reserved_at_8[0x18];
e281682b
SM		 3820
3821 u8 syndrome[0x20];
3822
b4ff3a36 3823 u8 reserved_at_40[0xa0];
e281682b
SM		 3824
3825 u8 start_flow_index[0x20];
3826
b4ff3a36 3827 u8 reserved_at_100[0x20];
e281682b
SM		 3828
3829 u8 end_flow_index[0x20];
3830
b4ff3a36 3831 u8 reserved_at_140[0xa0];
e281682b 3832
b4ff3a36 3833 u8 reserved_at_1e0[0x18];
e281682b
SM		 3834 u8 match_criteria_enable[0x8];
3835
3836 struct mlx5_ifc_fte_match_param_bits match_criteria;
3837
b4ff3a36 3838 u8 reserved_at_1200[0xe00];
e281682b
SM		 3839};
3840
3841struct mlx5_ifc_query_flow_group_in_bits {
3842 u8 opcode[0x10];
b4ff3a36 3843 u8 reserved_at_10[0x10];
e281682b 3844
b4ff3a36 3845 u8 reserved_at_20[0x10];
e281682b
SM		 3846 u8 op_mod[0x10];
3847
b4ff3a36 3848 u8 reserved_at_40[0x40];
e281682b
SM		 3849
3850 u8 table_type[0x8];
b4ff3a36 3851 u8 reserved_at_88[0x18];
e281682b 3852
b4ff3a36 3853 u8 reserved_at_a0[0x8];
e281682b
SM		 3854 u8 table_id[0x18];
3855
3856 u8 group_id[0x20];
3857
b4ff3a36 3858 u8 reserved_at_e0[0x120];
e281682b
SM		 3859};
3860
d6666753
SM		 3861struct mlx5_ifc_query_esw_vport_context_out_bits {
3862 u8 status[0x8];
b4ff3a36 3863 u8 reserved_at_8[0x18];
d6666753
SM		 3864
3865 u8 syndrome[0x20];
3866
b4ff3a36 3867 u8 reserved_at_40[0x40];
d6666753
SM		 3868
3869 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3870};
3871
3872struct mlx5_ifc_query_esw_vport_context_in_bits {
3873 u8 opcode[0x10];
b4ff3a36 3874 u8 reserved_at_10[0x10];
d6666753 3875
b4ff3a36 3876 u8 reserved_at_20[0x10];
d6666753
SM		 3877 u8 op_mod[0x10];
3878
3879 u8 other_vport[0x1];
b4ff3a36 3880 u8 reserved_at_41[0xf];
d6666753
SM		 3881 u8 vport_number[0x10];
3882
b4ff3a36 3883 u8 reserved_at_60[0x20];
d6666753
SM		 3884};
3885
3886struct mlx5_ifc_modify_esw_vport_context_out_bits {
3887 u8 status[0x8];
b4ff3a36 3888 u8 reserved_at_8[0x18];
d6666753
SM		 3889
3890 u8 syndrome[0x20];
3891
b4ff3a36 3892 u8 reserved_at_40[0x40];
d6666753
SM		 3893};
3894
3895struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 3896 u8 reserved_at_0[0x1c];
d6666753
SM		 3897 u8 vport_cvlan_insert[0x1];
3898 u8 vport_svlan_insert[0x1];
3899 u8 vport_cvlan_strip[0x1];
3900 u8 vport_svlan_strip[0x1];
3901};
3902
3903struct mlx5_ifc_modify_esw_vport_context_in_bits {
3904 u8 opcode[0x10];
b4ff3a36 3905 u8 reserved_at_10[0x10];
d6666753 3906
b4ff3a36 3907 u8 reserved_at_20[0x10];
d6666753
SM		 3908 u8 op_mod[0x10];
3909
3910 u8 other_vport[0x1];
b4ff3a36 3911 u8 reserved_at_41[0xf];
d6666753
SM		 3912 u8 vport_number[0x10];
3913
3914 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
3915
3916 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3917};
3918
e281682b
SM		 3919struct mlx5_ifc_query_eq_out_bits {
3920 u8 status[0x8];
b4ff3a36 3921 u8 reserved_at_8[0x18];
e281682b
SM		 3922
3923 u8 syndrome[0x20];
3924
b4ff3a36 3925 u8 reserved_at_40[0x40];
e281682b
SM		 3926
3927 struct mlx5_ifc_eqc_bits eq_context_entry;
3928
b4ff3a36 3929 u8 reserved_at_280[0x40];
e281682b
SM		 3930
3931 u8 event_bitmask[0x40];
3932
b4ff3a36 3933 u8 reserved_at_300[0x580];
e281682b
SM		 3934
3935 u8 pas[0][0x40];
3936};
3937
3938struct mlx5_ifc_query_eq_in_bits {
3939 u8 opcode[0x10];
b4ff3a36 3940 u8 reserved_at_10[0x10];
e281682b 3941
b4ff3a36 3942 u8 reserved_at_20[0x10];
e281682b
SM		 3943 u8 op_mod[0x10];
3944
b4ff3a36 3945 u8 reserved_at_40[0x18];
e281682b
SM		 3946 u8 eq_number[0x8];
3947
b4ff3a36 3948 u8 reserved_at_60[0x20];
e281682b
SM		 3949};
3950
3951struct mlx5_ifc_query_dct_out_bits {
3952 u8 status[0x8];
b4ff3a36 3953 u8 reserved_at_8[0x18];
e281682b
SM		 3954
3955 u8 syndrome[0x20];
3956
b4ff3a36 3957 u8 reserved_at_40[0x40];
e281682b
SM		 3958
3959 struct mlx5_ifc_dctc_bits dct_context_entry;
3960
b4ff3a36 3961 u8 reserved_at_280[0x180];
e281682b
SM		 3962};
3963
3964struct mlx5_ifc_query_dct_in_bits {
3965 u8 opcode[0x10];
b4ff3a36 3966 u8 reserved_at_10[0x10];
e281682b 3967
b4ff3a36 3968 u8 reserved_at_20[0x10];
e281682b
SM		 3969 u8 op_mod[0x10];
3970
b4ff3a36 3971 u8 reserved_at_40[0x8];
e281682b
SM		 3972 u8 dctn[0x18];
3973
b4ff3a36 3974 u8 reserved_at_60[0x20];
e281682b
SM		 3975};
3976
3977struct mlx5_ifc_query_cq_out_bits {
3978 u8 status[0x8];
b4ff3a36 3979 u8 reserved_at_8[0x18];
e281682b
SM		 3980
3981 u8 syndrome[0x20];
3982
b4ff3a36 3983 u8 reserved_at_40[0x40];
e281682b
SM		 3984
3985 struct mlx5_ifc_cqc_bits cq_context;
3986
b4ff3a36 3987 u8 reserved_at_280[0x600];
e281682b
SM		 3988
3989 u8 pas[0][0x40];
3990};
3991
3992struct mlx5_ifc_query_cq_in_bits {
3993 u8 opcode[0x10];
b4ff3a36 3994 u8 reserved_at_10[0x10];
e281682b 3995
b4ff3a36 3996 u8 reserved_at_20[0x10];
e281682b
SM		 3997 u8 op_mod[0x10];
3998
b4ff3a36 3999 u8 reserved_at_40[0x8];
e281682b
SM		 4000 u8 cqn[0x18];
4001
b4ff3a36 4002 u8 reserved_at_60[0x20];
e281682b
SM		 4003};
4004
4005struct mlx5_ifc_query_cong_status_out_bits {
4006 u8 status[0x8];
b4ff3a36 4007 u8 reserved_at_8[0x18];
e281682b
SM		 4008
4009 u8 syndrome[0x20];
4010
b4ff3a36 4011 u8 reserved_at_40[0x20];
e281682b
SM		 4012
4013 u8 enable[0x1];
4014 u8 tag_enable[0x1];
b4ff3a36 4015 u8 reserved_at_62[0x1e];
e281682b
SM		 4016};
4017
4018struct mlx5_ifc_query_cong_status_in_bits {
4019 u8 opcode[0x10];
b4ff3a36 4020 u8 reserved_at_10[0x10];
e281682b 4021
b4ff3a36 4022 u8 reserved_at_20[0x10];
e281682b
SM		 4023 u8 op_mod[0x10];
4024
b4ff3a36 4025 u8 reserved_at_40[0x18];
e281682b
SM		 4026 u8 priority[0x4];
4027 u8 cong_protocol[0x4];
4028
b4ff3a36 4029 u8 reserved_at_60[0x20];
e281682b
SM		 4030};
4031
4032struct mlx5_ifc_query_cong_statistics_out_bits {
4033 u8 status[0x8];
b4ff3a36 4034 u8 reserved_at_8[0x18];
e281682b
SM		 4035
4036 u8 syndrome[0x20];
4037
b4ff3a36 4038 u8 reserved_at_40[0x40];
e281682b
SM		 4039
4040 u8 cur_flows[0x20];
4041
4042 u8 sum_flows[0x20];
4043
4044 u8 cnp_ignored_high[0x20];
4045
4046 u8 cnp_ignored_low[0x20];
4047
4048 u8 cnp_handled_high[0x20];
4049
4050 u8 cnp_handled_low[0x20];
4051
b4ff3a36 4052 u8 reserved_at_140[0x100];
e281682b
SM		 4053
4054 u8 time_stamp_high[0x20];
4055
4056 u8 time_stamp_low[0x20];
4057
4058 u8 accumulators_period[0x20];
4059
4060 u8 ecn_marked_roce_packets_high[0x20];
4061
4062 u8 ecn_marked_roce_packets_low[0x20];
4063
4064 u8 cnps_sent_high[0x20];
4065
4066 u8 cnps_sent_low[0x20];
4067
b4ff3a36 4068 u8 reserved_at_320[0x560];
e281682b
SM		 4069};
4070
4071struct mlx5_ifc_query_cong_statistics_in_bits {
4072 u8 opcode[0x10];
b4ff3a36 4073 u8 reserved_at_10[0x10];
e281682b 4074
b4ff3a36 4075 u8 reserved_at_20[0x10];
e281682b
SM		 4076 u8 op_mod[0x10];
4077
4078 u8 clear[0x1];
b4ff3a36 4079 u8 reserved_at_41[0x1f];
e281682b 4080
b4ff3a36 4081 u8 reserved_at_60[0x20];
e281682b
SM		 4082};
4083
4084struct mlx5_ifc_query_cong_params_out_bits {
4085 u8 status[0x8];
b4ff3a36 4086 u8 reserved_at_8[0x18];
e281682b
SM		 4087
4088 u8 syndrome[0x20];
4089
b4ff3a36 4090 u8 reserved_at_40[0x40];
e281682b
SM		 4091
4092 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4093};
4094
4095struct mlx5_ifc_query_cong_params_in_bits {
4096 u8 opcode[0x10];
b4ff3a36 4097 u8 reserved_at_10[0x10];
e281682b 4098
b4ff3a36 4099 u8 reserved_at_20[0x10];
e281682b
SM		 4100 u8 op_mod[0x10];
4101
b4ff3a36 4102 u8 reserved_at_40[0x1c];
e281682b
SM		 4103 u8 cong_protocol[0x4];
4104
b4ff3a36 4105 u8 reserved_at_60[0x20];
e281682b
SM		 4106};
4107
4108struct mlx5_ifc_query_adapter_out_bits {
4109 u8 status[0x8];
b4ff3a36 4110 u8 reserved_at_8[0x18];
e281682b
SM		 4111
4112 u8 syndrome[0x20];
4113
b4ff3a36 4114 u8 reserved_at_40[0x40];
e281682b
SM		 4115
4116 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4117};
4118
4119struct mlx5_ifc_query_adapter_in_bits {
4120 u8 opcode[0x10];
b4ff3a36 4121 u8 reserved_at_10[0x10];
e281682b 4122
b4ff3a36 4123 u8 reserved_at_20[0x10];
e281682b
SM		 4124 u8 op_mod[0x10];
4125
b4ff3a36 4126 u8 reserved_at_40[0x40];
e281682b
SM		 4127};
4128
4129struct mlx5_ifc_qp_2rst_out_bits {
4130 u8 status[0x8];
b4ff3a36 4131 u8 reserved_at_8[0x18];
e281682b
SM		 4132
4133 u8 syndrome[0x20];
4134
b4ff3a36 4135 u8 reserved_at_40[0x40];
e281682b
SM		 4136};
4137
4138struct mlx5_ifc_qp_2rst_in_bits {
4139 u8 opcode[0x10];
b4ff3a36 4140 u8 reserved_at_10[0x10];
e281682b 4141
b4ff3a36 4142 u8 reserved_at_20[0x10];
e281682b
SM		 4143 u8 op_mod[0x10];
4144
b4ff3a36 4145 u8 reserved_at_40[0x8];
e281682b
SM		 4146 u8 qpn[0x18];
4147
b4ff3a36 4148 u8 reserved_at_60[0x20];
e281682b
SM		 4149};
4150
4151struct mlx5_ifc_qp_2err_out_bits {
4152 u8 status[0x8];
b4ff3a36 4153 u8 reserved_at_8[0x18];
e281682b
SM		 4154
4155 u8 syndrome[0x20];
4156
b4ff3a36 4157 u8 reserved_at_40[0x40];
e281682b
SM		 4158};
4159
4160struct mlx5_ifc_qp_2err_in_bits {
4161 u8 opcode[0x10];
b4ff3a36 4162 u8 reserved_at_10[0x10];
e281682b 4163
b4ff3a36 4164 u8 reserved_at_20[0x10];
e281682b
SM		 4165 u8 op_mod[0x10];
4166
b4ff3a36 4167 u8 reserved_at_40[0x8];
e281682b
SM		 4168 u8 qpn[0x18];
4169
b4ff3a36 4170 u8 reserved_at_60[0x20];
e281682b
SM		 4171};
4172
4173struct mlx5_ifc_page_fault_resume_out_bits {
4174 u8 status[0x8];
b4ff3a36 4175 u8 reserved_at_8[0x18];
e281682b
SM		 4176
4177 u8 syndrome[0x20];
4178
b4ff3a36 4179 u8 reserved_at_40[0x40];
e281682b
SM		 4180};
4181
4182struct mlx5_ifc_page_fault_resume_in_bits {
4183 u8 opcode[0x10];
b4ff3a36 4184 u8 reserved_at_10[0x10];
e281682b 4185
b4ff3a36 4186 u8 reserved_at_20[0x10];
e281682b
SM		 4187 u8 op_mod[0x10];
4188
4189 u8 error[0x1];
b4ff3a36 4190 u8 reserved_at_41[0x4];
e281682b
SM		 4191 u8 rdma[0x1];
4192 u8 read_write[0x1];
4193 u8 req_res[0x1];
4194 u8 qpn[0x18];
4195
b4ff3a36 4196 u8 reserved_at_60[0x20];
e281682b
SM		 4197};
4198
4199struct mlx5_ifc_nop_out_bits {
4200 u8 status[0x8];
b4ff3a36 4201 u8 reserved_at_8[0x18];
e281682b
SM		 4202
4203 u8 syndrome[0x20];
4204
b4ff3a36 4205 u8 reserved_at_40[0x40];
e281682b
SM		 4206};
4207
4208struct mlx5_ifc_nop_in_bits {
4209 u8 opcode[0x10];
b4ff3a36 4210 u8 reserved_at_10[0x10];
e281682b 4211
b4ff3a36 4212 u8 reserved_at_20[0x10];
e281682b
SM		 4213 u8 op_mod[0x10];
4214
b4ff3a36 4215 u8 reserved_at_40[0x40];
e281682b
SM		 4216};
4217
4218struct mlx5_ifc_modify_vport_state_out_bits {
4219 u8 status[0x8];
b4ff3a36 4220 u8 reserved_at_8[0x18];
e281682b
SM		 4221
4222 u8 syndrome[0x20];
4223
b4ff3a36 4224 u8 reserved_at_40[0x40];
e281682b
SM		 4225};
4226
4227struct mlx5_ifc_modify_vport_state_in_bits {
4228 u8 opcode[0x10];
b4ff3a36 4229 u8 reserved_at_10[0x10];
e281682b 4230
b4ff3a36 4231 u8 reserved_at_20[0x10];
e281682b
SM		 4232 u8 op_mod[0x10];
4233
4234 u8 other_vport[0x1];
b4ff3a36 4235 u8 reserved_at_41[0xf];
e281682b
SM		 4236 u8 vport_number[0x10];
4237
b4ff3a36 4238 u8 reserved_at_60[0x18];
e281682b 4239 u8 admin_state[0x4];
b4ff3a36 4240 u8 reserved_at_7c[0x4];
e281682b
SM		 4241};
4242
4243struct mlx5_ifc_modify_tis_out_bits {
4244 u8 status[0x8];
b4ff3a36 4245 u8 reserved_at_8[0x18];
e281682b
SM		 4246
4247 u8 syndrome[0x20];
4248
b4ff3a36 4249 u8 reserved_at_40[0x40];
e281682b
SM		 4250};
4251
75850d0b 4252struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 4253 u8 reserved_at_0[0x20];
75850d0b 4254
b4ff3a36 4255 u8 reserved_at_20[0x1f];
75850d0b 4256 u8 prio[0x1];
4257};
4258
e281682b
SM		 4259struct mlx5_ifc_modify_tis_in_bits {
4260 u8 opcode[0x10];
b4ff3a36 4261 u8 reserved_at_10[0x10];
e281682b 4262
b4ff3a36 4263 u8 reserved_at_20[0x10];
e281682b
SM		 4264 u8 op_mod[0x10];
4265
b4ff3a36 4266 u8 reserved_at_40[0x8];
e281682b
SM		 4267 u8 tisn[0x18];
4268
b4ff3a36 4269 u8 reserved_at_60[0x20];
e281682b 4270
75850d0b 4271 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 4272
b4ff3a36 4273 u8 reserved_at_c0[0x40];
e281682b
SM		 4274
4275 struct mlx5_ifc_tisc_bits ctx;
4276};
4277
d9eea403 4278struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 4279 u8 reserved_at_0[0x20];
d9eea403 4280
b4ff3a36 4281 u8 reserved_at_20[0x1b];
66189961 4282 u8 self_lb_en[0x1];
b4ff3a36 4283 u8 reserved_at_3c[0x3];
d9eea403
AS		 4284 u8 lro[0x1];
4285};
4286
e281682b
SM		 4287struct mlx5_ifc_modify_tir_out_bits {
4288 u8 status[0x8];
b4ff3a36 4289 u8 reserved_at_8[0x18];
e281682b
SM		 4290
4291 u8 syndrome[0x20];
4292
b4ff3a36 4293 u8 reserved_at_40[0x40];
e281682b
SM		 4294};
4295
4296struct mlx5_ifc_modify_tir_in_bits {
4297 u8 opcode[0x10];
b4ff3a36 4298 u8 reserved_at_10[0x10];
e281682b 4299
b4ff3a36 4300 u8 reserved_at_20[0x10];
e281682b
SM		 4301 u8 op_mod[0x10];
4302
b4ff3a36 4303 u8 reserved_at_40[0x8];
e281682b
SM		 4304 u8 tirn[0x18];
4305
b4ff3a36 4306 u8 reserved_at_60[0x20];
e281682b 4307
d9eea403 4308 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 4309
b4ff3a36 4310 u8 reserved_at_c0[0x40];
e281682b
SM		 4311
4312 struct mlx5_ifc_tirc_bits ctx;
4313};
4314
4315struct mlx5_ifc_modify_sq_out_bits {
4316 u8 status[0x8];
b4ff3a36 4317 u8 reserved_at_8[0x18];
e281682b
SM		 4318
4319 u8 syndrome[0x20];
4320
b4ff3a36 4321 u8 reserved_at_40[0x40];
e281682b
SM		 4322};
4323
4324struct mlx5_ifc_modify_sq_in_bits {
4325 u8 opcode[0x10];
b4ff3a36 4326 u8 reserved_at_10[0x10];
e281682b 4327
b4ff3a36 4328 u8 reserved_at_20[0x10];
e281682b
SM		 4329 u8 op_mod[0x10];
4330
4331 u8 sq_state[0x4];
b4ff3a36 4332 u8 reserved_at_44[0x4];
e281682b
SM		 4333 u8 sqn[0x18];
4334
b4ff3a36 4335 u8 reserved_at_60[0x20];
e281682b
SM		 4336
4337 u8 modify_bitmask[0x40];
4338
b4ff3a36 4339 u8 reserved_at_c0[0x40];
e281682b
SM		 4340
4341 struct mlx5_ifc_sqc_bits ctx;
4342};
4343
4344struct mlx5_ifc_modify_rqt_out_bits {
4345 u8 status[0x8];
b4ff3a36 4346 u8 reserved_at_8[0x18];
e281682b
SM		 4347
4348 u8 syndrome[0x20];
4349
b4ff3a36 4350 u8 reserved_at_40[0x40];
e281682b
SM		 4351};
4352
5c50368f 4353struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 4354 u8 reserved_at_0[0x20];
5c50368f 4355
b4ff3a36 4356 u8 reserved_at_20[0x1f];
5c50368f
AS		 4357 u8 rqn_list[0x1];
4358};
4359
e281682b
SM		 4360struct mlx5_ifc_modify_rqt_in_bits {
4361 u8 opcode[0x10];
b4ff3a36 4362 u8 reserved_at_10[0x10];
e281682b 4363
b4ff3a36 4364 u8 reserved_at_20[0x10];
e281682b
SM		 4365 u8 op_mod[0x10];
4366
b4ff3a36 4367 u8 reserved_at_40[0x8];
e281682b
SM		 4368 u8 rqtn[0x18];
4369
b4ff3a36 4370 u8 reserved_at_60[0x20];
e281682b 4371
5c50368f 4372 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 4373
b4ff3a36 4374 u8 reserved_at_c0[0x40];
e281682b
SM		 4375
4376 struct mlx5_ifc_rqtc_bits ctx;
4377};
4378
4379struct mlx5_ifc_modify_rq_out_bits {
4380 u8 status[0x8];
b4ff3a36 4381 u8 reserved_at_8[0x18];
e281682b
SM		 4382
4383 u8 syndrome[0x20];
4384
b4ff3a36 4385 u8 reserved_at_40[0x40];
e281682b
SM		 4386};
4387
4388struct mlx5_ifc_modify_rq_in_bits {
4389 u8 opcode[0x10];
b4ff3a36 4390 u8 reserved_at_10[0x10];
e281682b 4391
b4ff3a36 4392 u8 reserved_at_20[0x10];
e281682b
SM		 4393 u8 op_mod[0x10];
4394
4395 u8 rq_state[0x4];
b4ff3a36 4396 u8 reserved_at_44[0x4];
e281682b
SM		 4397 u8 rqn[0x18];
4398
b4ff3a36 4399 u8 reserved_at_60[0x20];
e281682b
SM		 4400
4401 u8 modify_bitmask[0x40];
4402
b4ff3a36 4403 u8 reserved_at_c0[0x40];
e281682b
SM		 4404
4405 struct mlx5_ifc_rqc_bits ctx;
4406};
4407
4408struct mlx5_ifc_modify_rmp_out_bits {
4409 u8 status[0x8];
b4ff3a36 4410 u8 reserved_at_8[0x18];
e281682b
SM		 4411
4412 u8 syndrome[0x20];
4413
b4ff3a36 4414 u8 reserved_at_40[0x40];
e281682b
SM		 4415};
4416
01949d01 4417struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 4418 u8 reserved_at_0[0x20];
01949d01 4419
b4ff3a36 4420 u8 reserved_at_20[0x1f];
01949d01
HA		 4421 u8 lwm[0x1];
4422};
4423
e281682b
SM		 4424struct mlx5_ifc_modify_rmp_in_bits {
4425 u8 opcode[0x10];
b4ff3a36 4426 u8 reserved_at_10[0x10];
e281682b 4427
b4ff3a36 4428 u8 reserved_at_20[0x10];
e281682b
SM		 4429 u8 op_mod[0x10];
4430
4431 u8 rmp_state[0x4];
b4ff3a36 4432 u8 reserved_at_44[0x4];
e281682b
SM		 4433 u8 rmpn[0x18];
4434
b4ff3a36 4435 u8 reserved_at_60[0x20];
e281682b 4436
01949d01 4437 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 4438
b4ff3a36 4439 u8 reserved_at_c0[0x40];
e281682b
SM		 4440
4441 struct mlx5_ifc_rmpc_bits ctx;
4442};
4443
4444struct mlx5_ifc_modify_nic_vport_context_out_bits {
4445 u8 status[0x8];
b4ff3a36 4446 u8 reserved_at_8[0x18];
e281682b
SM		 4447
4448 u8 syndrome[0x20];
4449
b4ff3a36 4450 u8 reserved_at_40[0x40];
e281682b
SM		 4451};
4452
4453struct mlx5_ifc_modify_nic_vport_field_select_bits {
b4ff3a36 4454 u8 reserved_at_0[0x19];
d82b7318
SM		 4455 u8 mtu[0x1];
4456 u8 change_event[0x1];
4457 u8 promisc[0x1];
e281682b
SM		 4458 u8 permanent_address[0x1];
4459 u8 addresses_list[0x1];
4460 u8 roce_en[0x1];
b4ff3a36 4461 u8 reserved_at_1f[0x1];
e281682b
SM		 4462};
4463
4464struct mlx5_ifc_modify_nic_vport_context_in_bits {
4465 u8 opcode[0x10];
b4ff3a36 4466 u8 reserved_at_10[0x10];
e281682b 4467
b4ff3a36 4468 u8 reserved_at_20[0x10];
e281682b
SM		 4469 u8 op_mod[0x10];
4470
4471 u8 other_vport[0x1];
b4ff3a36 4472 u8 reserved_at_41[0xf];
e281682b
SM		 4473 u8 vport_number[0x10];
4474
4475 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4476
b4ff3a36 4477 u8 reserved_at_80[0x780];
e281682b
SM		 4478
4479 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4480};
4481
4482struct mlx5_ifc_modify_hca_vport_context_out_bits {
4483 u8 status[0x8];
b4ff3a36 4484 u8 reserved_at_8[0x18];
e281682b
SM		 4485
4486 u8 syndrome[0x20];
4487
b4ff3a36 4488 u8 reserved_at_40[0x40];
e281682b
SM		 4489};
4490
4491struct mlx5_ifc_modify_hca_vport_context_in_bits {
4492 u8 opcode[0x10];
b4ff3a36 4493 u8 reserved_at_10[0x10];
e281682b 4494
b4ff3a36 4495 u8 reserved_at_20[0x10];
e281682b
SM		 4496 u8 op_mod[0x10];
4497
4498 u8 other_vport[0x1];
b4ff3a36 4499 u8 reserved_at_41[0xb];
707c4602 4500 u8 port_num[0x4];
e281682b
SM		 4501 u8 vport_number[0x10];
4502
b4ff3a36 4503 u8 reserved_at_60[0x20];
e281682b
SM		 4504
4505 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4506};
4507
4508struct mlx5_ifc_modify_cq_out_bits {
4509 u8 status[0x8];
b4ff3a36 4510 u8 reserved_at_8[0x18];
e281682b
SM		 4511
4512 u8 syndrome[0x20];
4513
b4ff3a36 4514 u8 reserved_at_40[0x40];
e281682b
SM		 4515};
4516
4517enum {
4518 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4519 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4520};
4521
4522struct mlx5_ifc_modify_cq_in_bits {
4523 u8 opcode[0x10];
b4ff3a36 4524 u8 reserved_at_10[0x10];
e281682b 4525
b4ff3a36 4526 u8 reserved_at_20[0x10];
e281682b
SM		 4527 u8 op_mod[0x10];
4528
b4ff3a36 4529 u8 reserved_at_40[0x8];
e281682b
SM		 4530 u8 cqn[0x18];
4531
4532 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4533
4534 struct mlx5_ifc_cqc_bits cq_context;
4535
b4ff3a36 4536 u8 reserved_at_280[0x600];
e281682b
SM		 4537
4538 u8 pas[0][0x40];
4539};
4540
4541struct mlx5_ifc_modify_cong_status_out_bits {
4542 u8 status[0x8];
b4ff3a36 4543 u8 reserved_at_8[0x18];
e281682b
SM		 4544
4545 u8 syndrome[0x20];
4546
b4ff3a36 4547 u8 reserved_at_40[0x40];
e281682b
SM		 4548};
4549
4550struct mlx5_ifc_modify_cong_status_in_bits {
4551 u8 opcode[0x10];
b4ff3a36 4552 u8 reserved_at_10[0x10];
e281682b 4553
b4ff3a36 4554 u8 reserved_at_20[0x10];
e281682b
SM		 4555 u8 op_mod[0x10];
4556
b4ff3a36 4557 u8 reserved_at_40[0x18];
e281682b
SM		 4558 u8 priority[0x4];
4559 u8 cong_protocol[0x4];
4560
4561 u8 enable[0x1];
4562 u8 tag_enable[0x1];
b4ff3a36 4563 u8 reserved_at_62[0x1e];
e281682b
SM		 4564};
4565
4566struct mlx5_ifc_modify_cong_params_out_bits {
4567 u8 status[0x8];
b4ff3a36 4568 u8 reserved_at_8[0x18];
e281682b
SM		 4569
4570 u8 syndrome[0x20];
4571
b4ff3a36 4572 u8 reserved_at_40[0x40];
e281682b
SM		 4573};
4574
4575struct mlx5_ifc_modify_cong_params_in_bits {
4576 u8 opcode[0x10];
b4ff3a36 4577 u8 reserved_at_10[0x10];
e281682b 4578
b4ff3a36 4579 u8 reserved_at_20[0x10];
e281682b
SM		 4580 u8 op_mod[0x10];
4581
b4ff3a36 4582 u8 reserved_at_40[0x1c];
e281682b
SM		 4583 u8 cong_protocol[0x4];
4584
4585 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4586
b4ff3a36 4587 u8 reserved_at_80[0x80];
e281682b
SM		 4588
4589 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4590};
4591
4592struct mlx5_ifc_manage_pages_out_bits {
4593 u8 status[0x8];
b4ff3a36 4594 u8 reserved_at_8[0x18];
e281682b
SM		 4595
4596 u8 syndrome[0x20];
4597
4598 u8 output_num_entries[0x20];
4599
b4ff3a36 4600 u8 reserved_at_60[0x20];
e281682b
SM		 4601
4602 u8 pas[0][0x40];
4603};
4604
4605enum {
4606 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4607 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
4608 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
4609};
4610
4611struct mlx5_ifc_manage_pages_in_bits {
4612 u8 opcode[0x10];
b4ff3a36 4613 u8 reserved_at_10[0x10];
e281682b 4614
b4ff3a36 4615 u8 reserved_at_20[0x10];
e281682b
SM		 4616 u8 op_mod[0x10];
4617
b4ff3a36 4618 u8 reserved_at_40[0x10];
e281682b
SM		 4619 u8 function_id[0x10];
4620
4621 u8 input_num_entries[0x20];
4622
4623 u8 pas[0][0x40];
4624};
4625
4626struct mlx5_ifc_mad_ifc_out_bits {
4627 u8 status[0x8];
b4ff3a36 4628 u8 reserved_at_8[0x18];
e281682b
SM		 4629
4630 u8 syndrome[0x20];
4631
b4ff3a36 4632 u8 reserved_at_40[0x40];
e281682b
SM		 4633
4634 u8 response_mad_packet[256][0x8];
4635};
4636
4637struct mlx5_ifc_mad_ifc_in_bits {
4638 u8 opcode[0x10];
b4ff3a36 4639 u8 reserved_at_10[0x10];
e281682b 4640
b4ff3a36 4641 u8 reserved_at_20[0x10];
e281682b
SM		 4642 u8 op_mod[0x10];
4643
4644 u8 remote_lid[0x10];
b4ff3a36 4645 u8 reserved_at_50[0x8];
e281682b
SM		 4646 u8 port[0x8];
4647
b4ff3a36 4648 u8 reserved_at_60[0x20];
e281682b
SM		 4649
4650 u8 mad[256][0x8];
4651};
4652
4653struct mlx5_ifc_init_hca_out_bits {
4654 u8 status[0x8];
b4ff3a36 4655 u8 reserved_at_8[0x18];
e281682b
SM		 4656
4657 u8 syndrome[0x20];
4658
b4ff3a36 4659 u8 reserved_at_40[0x40];
e281682b
SM		 4660};
4661
4662struct mlx5_ifc_init_hca_in_bits {
4663 u8 opcode[0x10];
b4ff3a36 4664 u8 reserved_at_10[0x10];
e281682b 4665
b4ff3a36 4666 u8 reserved_at_20[0x10];
e281682b
SM		 4667 u8 op_mod[0x10];
4668
b4ff3a36 4669 u8 reserved_at_40[0x40];
e281682b
SM		 4670};
4671
4672struct mlx5_ifc_init2rtr_qp_out_bits {
4673 u8 status[0x8];
b4ff3a36 4674 u8 reserved_at_8[0x18];
e281682b
SM		 4675
4676 u8 syndrome[0x20];
4677
b4ff3a36 4678 u8 reserved_at_40[0x40];
e281682b
SM		 4679};
4680
4681struct mlx5_ifc_init2rtr_qp_in_bits {
4682 u8 opcode[0x10];
b4ff3a36 4683 u8 reserved_at_10[0x10];
e281682b 4684
b4ff3a36 4685 u8 reserved_at_20[0x10];
e281682b
SM		 4686 u8 op_mod[0x10];
4687
b4ff3a36 4688 u8 reserved_at_40[0x8];
e281682b
SM		 4689 u8 qpn[0x18];
4690
b4ff3a36 4691 u8 reserved_at_60[0x20];
e281682b
SM		 4692
4693 u8 opt_param_mask[0x20];
4694
b4ff3a36 4695 u8 reserved_at_a0[0x20];
e281682b
SM		 4696
4697 struct mlx5_ifc_qpc_bits qpc;
4698
b4ff3a36 4699 u8 reserved_at_800[0x80];
e281682b
SM		 4700};
4701
4702struct mlx5_ifc_init2init_qp_out_bits {
4703 u8 status[0x8];
b4ff3a36 4704 u8 reserved_at_8[0x18];
e281682b
SM		 4705
4706 u8 syndrome[0x20];
4707
b4ff3a36 4708 u8 reserved_at_40[0x40];
e281682b
SM		 4709};
4710
4711struct mlx5_ifc_init2init_qp_in_bits {
4712 u8 opcode[0x10];
b4ff3a36 4713 u8 reserved_at_10[0x10];
e281682b 4714
b4ff3a36 4715 u8 reserved_at_20[0x10];
e281682b
SM		 4716 u8 op_mod[0x10];
4717
b4ff3a36 4718 u8 reserved_at_40[0x8];
e281682b
SM		 4719 u8 qpn[0x18];
4720
b4ff3a36 4721 u8 reserved_at_60[0x20];
e281682b
SM		 4722
4723 u8 opt_param_mask[0x20];
4724
b4ff3a36 4725 u8 reserved_at_a0[0x20];
e281682b
SM		 4726
4727 struct mlx5_ifc_qpc_bits qpc;
4728
b4ff3a36 4729 u8 reserved_at_800[0x80];
e281682b
SM		 4730};
4731
4732struct mlx5_ifc_get_dropped_packet_log_out_bits {
4733 u8 status[0x8];
b4ff3a36 4734 u8 reserved_at_8[0x18];
e281682b
SM		 4735
4736 u8 syndrome[0x20];
4737
b4ff3a36 4738 u8 reserved_at_40[0x40];
e281682b
SM		 4739
4740 u8 packet_headers_log[128][0x8];
4741
4742 u8 packet_syndrome[64][0x8];
4743};
4744
4745struct mlx5_ifc_get_dropped_packet_log_in_bits {
4746 u8 opcode[0x10];
b4ff3a36 4747 u8 reserved_at_10[0x10];
e281682b 4748
b4ff3a36 4749 u8 reserved_at_20[0x10];
e281682b
SM		 4750 u8 op_mod[0x10];
4751
b4ff3a36 4752 u8 reserved_at_40[0x40];
e281682b
SM		 4753};
4754
4755struct mlx5_ifc_gen_eqe_in_bits {
4756 u8 opcode[0x10];
b4ff3a36 4757 u8 reserved_at_10[0x10];
e281682b 4758
b4ff3a36 4759 u8 reserved_at_20[0x10];
e281682b
SM		 4760 u8 op_mod[0x10];
4761
b4ff3a36 4762 u8 reserved_at_40[0x18];
e281682b
SM		 4763 u8 eq_number[0x8];
4764
b4ff3a36 4765 u8 reserved_at_60[0x20];
e281682b
SM		 4766
4767 u8 eqe[64][0x8];
4768};
4769
4770struct mlx5_ifc_gen_eq_out_bits {
4771 u8 status[0x8];
b4ff3a36 4772 u8 reserved_at_8[0x18];
e281682b
SM		 4773
4774 u8 syndrome[0x20];
4775
b4ff3a36 4776 u8 reserved_at_40[0x40];
e281682b
SM		 4777};
4778
4779struct mlx5_ifc_enable_hca_out_bits {
4780 u8 status[0x8];
b4ff3a36 4781 u8 reserved_at_8[0x18];
e281682b
SM		 4782
4783 u8 syndrome[0x20];
4784
b4ff3a36 4785 u8 reserved_at_40[0x20];
e281682b
SM		 4786};
4787
4788struct mlx5_ifc_enable_hca_in_bits {
4789 u8 opcode[0x10];
b4ff3a36 4790 u8 reserved_at_10[0x10];
e281682b 4791
b4ff3a36 4792 u8 reserved_at_20[0x10];
e281682b
SM		 4793 u8 op_mod[0x10];
4794
b4ff3a36 4795 u8 reserved_at_40[0x10];
e281682b
SM		 4796 u8 function_id[0x10];
4797
b4ff3a36 4798 u8 reserved_at_60[0x20];
e281682b
SM		 4799};
4800
4801struct mlx5_ifc_drain_dct_out_bits {
4802 u8 status[0x8];
b4ff3a36 4803 u8 reserved_at_8[0x18];
e281682b
SM		 4804
4805 u8 syndrome[0x20];
4806
b4ff3a36 4807 u8 reserved_at_40[0x40];
e281682b
SM		 4808};
4809
4810struct mlx5_ifc_drain_dct_in_bits {
4811 u8 opcode[0x10];
b4ff3a36 4812 u8 reserved_at_10[0x10];
e281682b 4813
b4ff3a36 4814 u8 reserved_at_20[0x10];
e281682b
SM		 4815 u8 op_mod[0x10];
4816
b4ff3a36 4817 u8 reserved_at_40[0x8];
e281682b
SM		 4818 u8 dctn[0x18];
4819
b4ff3a36 4820 u8 reserved_at_60[0x20];
e281682b
SM		 4821};
4822
4823struct mlx5_ifc_disable_hca_out_bits {
4824 u8 status[0x8];
b4ff3a36 4825 u8 reserved_at_8[0x18];
e281682b
SM		 4826
4827 u8 syndrome[0x20];
4828
b4ff3a36 4829 u8 reserved_at_40[0x20];
e281682b
SM		 4830};
4831
4832struct mlx5_ifc_disable_hca_in_bits {
4833 u8 opcode[0x10];
b4ff3a36 4834 u8 reserved_at_10[0x10];
e281682b 4835
b4ff3a36 4836 u8 reserved_at_20[0x10];
e281682b
SM		 4837 u8 op_mod[0x10];
4838
b4ff3a36 4839 u8 reserved_at_40[0x10];
e281682b
SM		 4840 u8 function_id[0x10];
4841
b4ff3a36 4842 u8 reserved_at_60[0x20];
e281682b
SM		 4843};
4844
4845struct mlx5_ifc_detach_from_mcg_out_bits {
4846 u8 status[0x8];
b4ff3a36 4847 u8 reserved_at_8[0x18];
e281682b
SM		 4848
4849 u8 syndrome[0x20];
4850
b4ff3a36 4851 u8 reserved_at_40[0x40];
e281682b
SM		 4852};
4853
4854struct mlx5_ifc_detach_from_mcg_in_bits {
4855 u8 opcode[0x10];
b4ff3a36 4856 u8 reserved_at_10[0x10];
e281682b 4857
b4ff3a36 4858 u8 reserved_at_20[0x10];
e281682b
SM		 4859 u8 op_mod[0x10];
4860
b4ff3a36 4861 u8 reserved_at_40[0x8];
e281682b
SM		 4862 u8 qpn[0x18];
4863
b4ff3a36 4864 u8 reserved_at_60[0x20];
e281682b
SM		 4865
4866 u8 multicast_gid[16][0x8];
4867};
4868
4869struct mlx5_ifc_destroy_xrc_srq_out_bits {
4870 u8 status[0x8];
b4ff3a36 4871 u8 reserved_at_8[0x18];
e281682b
SM		 4872
4873 u8 syndrome[0x20];
4874
b4ff3a36 4875 u8 reserved_at_40[0x40];
e281682b
SM		 4876};
4877
4878struct mlx5_ifc_destroy_xrc_srq_in_bits {
4879 u8 opcode[0x10];
b4ff3a36 4880 u8 reserved_at_10[0x10];
e281682b 4881
b4ff3a36 4882 u8 reserved_at_20[0x10];
e281682b
SM		 4883 u8 op_mod[0x10];
4884
b4ff3a36 4885 u8 reserved_at_40[0x8];
e281682b
SM		 4886 u8 xrc_srqn[0x18];
4887
b4ff3a36 4888 u8 reserved_at_60[0x20];
e281682b
SM		 4889};
4890
4891struct mlx5_ifc_destroy_tis_out_bits {
4892 u8 status[0x8];
b4ff3a36 4893 u8 reserved_at_8[0x18];
e281682b
SM		 4894
4895 u8 syndrome[0x20];
4896
b4ff3a36 4897 u8 reserved_at_40[0x40];
e281682b
SM		 4898};
4899
4900struct mlx5_ifc_destroy_tis_in_bits {
4901 u8 opcode[0x10];
b4ff3a36 4902 u8 reserved_at_10[0x10];
e281682b 4903
b4ff3a36 4904 u8 reserved_at_20[0x10];
e281682b
SM		 4905 u8 op_mod[0x10];
4906
b4ff3a36 4907 u8 reserved_at_40[0x8];
e281682b
SM		 4908 u8 tisn[0x18];
4909
b4ff3a36 4910 u8 reserved_at_60[0x20];
e281682b
SM		 4911};
4912
4913struct mlx5_ifc_destroy_tir_out_bits {
4914 u8 status[0x8];
b4ff3a36 4915 u8 reserved_at_8[0x18];
e281682b
SM		 4916
4917 u8 syndrome[0x20];
4918
b4ff3a36 4919 u8 reserved_at_40[0x40];
e281682b
SM		 4920};
4921
4922struct mlx5_ifc_destroy_tir_in_bits {
4923 u8 opcode[0x10];
b4ff3a36 4924 u8 reserved_at_10[0x10];
e281682b 4925
b4ff3a36 4926 u8 reserved_at_20[0x10];
e281682b
SM		 4927 u8 op_mod[0x10];
4928
b4ff3a36 4929 u8 reserved_at_40[0x8];
e281682b
SM		 4930 u8 tirn[0x18];
4931
b4ff3a36 4932 u8 reserved_at_60[0x20];
e281682b
SM		 4933};
4934
4935struct mlx5_ifc_destroy_srq_out_bits {
4936 u8 status[0x8];
b4ff3a36 4937 u8 reserved_at_8[0x18];
e281682b
SM		 4938
4939 u8 syndrome[0x20];
4940
b4ff3a36 4941 u8 reserved_at_40[0x40];
e281682b
SM		 4942};
4943
4944struct mlx5_ifc_destroy_srq_in_bits {
4945 u8 opcode[0x10];
b4ff3a36 4946 u8 reserved_at_10[0x10];
e281682b 4947
b4ff3a36 4948 u8 reserved_at_20[0x10];
e281682b
SM		 4949 u8 op_mod[0x10];
4950
b4ff3a36 4951 u8 reserved_at_40[0x8];
e281682b
SM		 4952 u8 srqn[0x18];
4953
b4ff3a36 4954 u8 reserved_at_60[0x20];
e281682b
SM		 4955};
4956
4957struct mlx5_ifc_destroy_sq_out_bits {
4958 u8 status[0x8];
b4ff3a36 4959 u8 reserved_at_8[0x18];
e281682b
SM		 4960
4961 u8 syndrome[0x20];
4962
b4ff3a36 4963 u8 reserved_at_40[0x40];
e281682b
SM		 4964};
4965
4966struct mlx5_ifc_destroy_sq_in_bits {
4967 u8 opcode[0x10];
b4ff3a36 4968 u8 reserved_at_10[0x10];
e281682b 4969
b4ff3a36 4970 u8 reserved_at_20[0x10];
e281682b
SM		 4971 u8 op_mod[0x10];
4972
b4ff3a36 4973 u8 reserved_at_40[0x8];
e281682b
SM		 4974 u8 sqn[0x18];
4975
b4ff3a36 4976 u8 reserved_at_60[0x20];
e281682b
SM		 4977};
4978
4979struct mlx5_ifc_destroy_rqt_out_bits {
4980 u8 status[0x8];
b4ff3a36 4981 u8 reserved_at_8[0x18];
e281682b
SM		 4982
4983 u8 syndrome[0x20];
4984
b4ff3a36 4985 u8 reserved_at_40[0x40];
e281682b
SM		 4986};
4987
4988struct mlx5_ifc_destroy_rqt_in_bits {
4989 u8 opcode[0x10];
b4ff3a36 4990 u8 reserved_at_10[0x10];
e281682b 4991
b4ff3a36 4992 u8 reserved_at_20[0x10];
e281682b
SM		 4993 u8 op_mod[0x10];
4994
b4ff3a36 4995 u8 reserved_at_40[0x8];
e281682b
SM		 4996 u8 rqtn[0x18];
4997
b4ff3a36 4998 u8 reserved_at_60[0x20];
e281682b
SM		 4999};
5000
5001struct mlx5_ifc_destroy_rq_out_bits {
5002 u8 status[0x8];
b4ff3a36 5003 u8 reserved_at_8[0x18];
e281682b
SM		 5004
5005 u8 syndrome[0x20];
5006
b4ff3a36 5007 u8 reserved_at_40[0x40];
e281682b
SM		 5008};
5009
5010struct mlx5_ifc_destroy_rq_in_bits {
5011 u8 opcode[0x10];
b4ff3a36 5012 u8 reserved_at_10[0x10];
e281682b 5013
b4ff3a36 5014 u8 reserved_at_20[0x10];
e281682b
SM		 5015 u8 op_mod[0x10];
5016
b4ff3a36 5017 u8 reserved_at_40[0x8];
e281682b
SM		 5018 u8 rqn[0x18];
5019
b4ff3a36 5020 u8 reserved_at_60[0x20];
e281682b
SM		 5021};
5022
5023struct mlx5_ifc_destroy_rmp_out_bits {
5024 u8 status[0x8];
b4ff3a36 5025 u8 reserved_at_8[0x18];
e281682b
SM		 5026
5027 u8 syndrome[0x20];
5028
b4ff3a36 5029 u8 reserved_at_40[0x40];
e281682b
SM		 5030};
5031
5032struct mlx5_ifc_destroy_rmp_in_bits {
5033 u8 opcode[0x10];
b4ff3a36 5034 u8 reserved_at_10[0x10];
e281682b 5035
b4ff3a36 5036 u8 reserved_at_20[0x10];
e281682b
SM		 5037 u8 op_mod[0x10];
5038
b4ff3a36 5039 u8 reserved_at_40[0x8];
e281682b
SM		 5040 u8 rmpn[0x18];
5041
b4ff3a36 5042 u8 reserved_at_60[0x20];
e281682b
SM		 5043};
5044
5045struct mlx5_ifc_destroy_qp_out_bits {
5046 u8 status[0x8];
b4ff3a36 5047 u8 reserved_at_8[0x18];
e281682b
SM		 5048
5049 u8 syndrome[0x20];
5050
b4ff3a36 5051 u8 reserved_at_40[0x40];
e281682b
SM		 5052};
5053
5054struct mlx5_ifc_destroy_qp_in_bits {
5055 u8 opcode[0x10];
b4ff3a36 5056 u8 reserved_at_10[0x10];
e281682b 5057
b4ff3a36 5058 u8 reserved_at_20[0x10];
e281682b
SM		 5059 u8 op_mod[0x10];
5060
b4ff3a36 5061 u8 reserved_at_40[0x8];
e281682b
SM		 5062 u8 qpn[0x18];
5063
b4ff3a36 5064 u8 reserved_at_60[0x20];
e281682b
SM		 5065};
5066
5067struct mlx5_ifc_destroy_psv_out_bits {
5068 u8 status[0x8];
b4ff3a36 5069 u8 reserved_at_8[0x18];
e281682b
SM		 5070
5071 u8 syndrome[0x20];
5072
b4ff3a36 5073 u8 reserved_at_40[0x40];
e281682b
SM		 5074};
5075
5076struct mlx5_ifc_destroy_psv_in_bits {
5077 u8 opcode[0x10];
b4ff3a36 5078 u8 reserved_at_10[0x10];
e281682b 5079
b4ff3a36 5080 u8 reserved_at_20[0x10];
e281682b
SM		 5081 u8 op_mod[0x10];
5082
b4ff3a36 5083 u8 reserved_at_40[0x8];
e281682b
SM		 5084 u8 psvn[0x18];
5085
b4ff3a36 5086 u8 reserved_at_60[0x20];
e281682b
SM		 5087};
5088
5089struct mlx5_ifc_destroy_mkey_out_bits {
5090 u8 status[0x8];
b4ff3a36 5091 u8 reserved_at_8[0x18];
e281682b
SM		 5092
5093 u8 syndrome[0x20];
5094
b4ff3a36 5095 u8 reserved_at_40[0x40];
e281682b
SM		 5096};
5097
5098struct mlx5_ifc_destroy_mkey_in_bits {
5099 u8 opcode[0x10];
b4ff3a36 5100 u8 reserved_at_10[0x10];
e281682b 5101
b4ff3a36 5102 u8 reserved_at_20[0x10];
e281682b
SM		 5103 u8 op_mod[0x10];
5104
b4ff3a36 5105 u8 reserved_at_40[0x8];
e281682b
SM		 5106 u8 mkey_index[0x18];
5107
b4ff3a36 5108 u8 reserved_at_60[0x20];
e281682b
SM		 5109};
5110
5111struct mlx5_ifc_destroy_flow_table_out_bits {
5112 u8 status[0x8];
b4ff3a36 5113 u8 reserved_at_8[0x18];
e281682b
SM		 5114
5115 u8 syndrome[0x20];
5116
b4ff3a36 5117 u8 reserved_at_40[0x40];
e281682b
SM		 5118};
5119
5120struct mlx5_ifc_destroy_flow_table_in_bits {
5121 u8 opcode[0x10];
b4ff3a36 5122 u8 reserved_at_10[0x10];
e281682b 5123
b4ff3a36 5124 u8 reserved_at_20[0x10];
e281682b
SM		 5125 u8 op_mod[0x10];
5126
b4ff3a36 5127 u8 reserved_at_40[0x40];
e281682b
SM		 5128
5129 u8 table_type[0x8];
b4ff3a36 5130 u8 reserved_at_88[0x18];
e281682b 5131
b4ff3a36 5132 u8 reserved_at_a0[0x8];
e281682b
SM		 5133 u8 table_id[0x18];
5134
b4ff3a36 5135 u8 reserved_at_c0[0x140];
e281682b
SM		 5136};
5137
5138struct mlx5_ifc_destroy_flow_group_out_bits {
5139 u8 status[0x8];
b4ff3a36 5140 u8 reserved_at_8[0x18];
e281682b
SM		 5141
5142 u8 syndrome[0x20];
5143
b4ff3a36 5144 u8 reserved_at_40[0x40];
e281682b
SM		 5145};
5146
5147struct mlx5_ifc_destroy_flow_group_in_bits {
5148 u8 opcode[0x10];
b4ff3a36 5149 u8 reserved_at_10[0x10];
e281682b 5150
b4ff3a36 5151 u8 reserved_at_20[0x10];
e281682b
SM		 5152 u8 op_mod[0x10];
5153
b4ff3a36 5154 u8 reserved_at_40[0x40];
e281682b
SM		 5155
5156 u8 table_type[0x8];
b4ff3a36 5157 u8 reserved_at_88[0x18];
e281682b 5158
b4ff3a36 5159 u8 reserved_at_a0[0x8];
e281682b
SM		 5160 u8 table_id[0x18];
5161
5162 u8 group_id[0x20];
5163
b4ff3a36 5164 u8 reserved_at_e0[0x120];
e281682b
SM		 5165};
5166
5167struct mlx5_ifc_destroy_eq_out_bits {
5168 u8 status[0x8];
b4ff3a36 5169 u8 reserved_at_8[0x18];
e281682b
SM		 5170
5171 u8 syndrome[0x20];
5172
b4ff3a36 5173 u8 reserved_at_40[0x40];
e281682b
SM		 5174};
5175
5176struct mlx5_ifc_destroy_eq_in_bits {
5177 u8 opcode[0x10];
b4ff3a36 5178 u8 reserved_at_10[0x10];
e281682b 5179
b4ff3a36 5180 u8 reserved_at_20[0x10];
e281682b
SM		 5181 u8 op_mod[0x10];
5182
b4ff3a36 5183 u8 reserved_at_40[0x18];
e281682b
SM		 5184 u8 eq_number[0x8];
5185
b4ff3a36 5186 u8 reserved_at_60[0x20];
e281682b
SM		 5187};
5188
5189struct mlx5_ifc_destroy_dct_out_bits {
5190 u8 status[0x8];
b4ff3a36 5191 u8 reserved_at_8[0x18];
e281682b
SM		 5192
5193 u8 syndrome[0x20];
5194
b4ff3a36 5195 u8 reserved_at_40[0x40];
e281682b
SM		 5196};
5197
5198struct mlx5_ifc_destroy_dct_in_bits {
5199 u8 opcode[0x10];
b4ff3a36 5200 u8 reserved_at_10[0x10];
e281682b 5201
b4ff3a36 5202 u8 reserved_at_20[0x10];
e281682b
SM		 5203 u8 op_mod[0x10];
5204
b4ff3a36 5205 u8 reserved_at_40[0x8];
e281682b
SM		 5206 u8 dctn[0x18];
5207
b4ff3a36 5208 u8 reserved_at_60[0x20];
e281682b
SM		 5209};
5210
5211struct mlx5_ifc_destroy_cq_out_bits {
5212 u8 status[0x8];
b4ff3a36 5213 u8 reserved_at_8[0x18];
e281682b
SM		 5214
5215 u8 syndrome[0x20];
5216
b4ff3a36 5217 u8 reserved_at_40[0x40];
e281682b
SM		 5218};
5219
5220struct mlx5_ifc_destroy_cq_in_bits {
5221 u8 opcode[0x10];
b4ff3a36 5222 u8 reserved_at_10[0x10];
e281682b 5223
b4ff3a36 5224 u8 reserved_at_20[0x10];
e281682b
SM		 5225 u8 op_mod[0x10];
5226
b4ff3a36 5227 u8 reserved_at_40[0x8];
e281682b
SM		 5228 u8 cqn[0x18];
5229
b4ff3a36 5230 u8 reserved_at_60[0x20];
e281682b
SM		 5231};
5232
5233struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5234 u8 status[0x8];
b4ff3a36 5235 u8 reserved_at_8[0x18];
e281682b
SM		 5236
5237 u8 syndrome[0x20];
5238
b4ff3a36 5239 u8 reserved_at_40[0x40];
e281682b
SM		 5240};
5241
5242struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5243 u8 opcode[0x10];
b4ff3a36 5244 u8 reserved_at_10[0x10];
e281682b 5245
b4ff3a36 5246 u8 reserved_at_20[0x10];
e281682b
SM		 5247 u8 op_mod[0x10];
5248
b4ff3a36 5249 u8 reserved_at_40[0x20];
e281682b 5250
b4ff3a36 5251 u8 reserved_at_60[0x10];
e281682b
SM		 5252 u8 vxlan_udp_port[0x10];
5253};
5254
5255struct mlx5_ifc_delete_l2_table_entry_out_bits {
5256 u8 status[0x8];
b4ff3a36 5257 u8 reserved_at_8[0x18];
e281682b
SM		 5258
5259 u8 syndrome[0x20];
5260
b4ff3a36 5261 u8 reserved_at_40[0x40];
e281682b
SM		 5262};
5263
5264struct mlx5_ifc_delete_l2_table_entry_in_bits {
5265 u8 opcode[0x10];
b4ff3a36 5266 u8 reserved_at_10[0x10];
e281682b 5267
b4ff3a36 5268 u8 reserved_at_20[0x10];
e281682b
SM		 5269 u8 op_mod[0x10];
5270
b4ff3a36 5271 u8 reserved_at_40[0x60];
e281682b 5272
b4ff3a36 5273 u8 reserved_at_a0[0x8];
e281682b
SM		 5274 u8 table_index[0x18];
5275
b4ff3a36 5276 u8 reserved_at_c0[0x140];
e281682b
SM		 5277};
5278
5279struct mlx5_ifc_delete_fte_out_bits {
5280 u8 status[0x8];
b4ff3a36 5281 u8 reserved_at_8[0x18];
e281682b
SM		 5282
5283 u8 syndrome[0x20];
5284
b4ff3a36 5285 u8 reserved_at_40[0x40];
e281682b
SM		 5286};
5287
5288struct mlx5_ifc_delete_fte_in_bits {
5289 u8 opcode[0x10];
b4ff3a36 5290 u8 reserved_at_10[0x10];
e281682b 5291
b4ff3a36 5292 u8 reserved_at_20[0x10];
e281682b
SM		 5293 u8 op_mod[0x10];
5294
b4ff3a36 5295 u8 reserved_at_40[0x40];
e281682b
SM		 5296
5297 u8 table_type[0x8];
b4ff3a36 5298 u8 reserved_at_88[0x18];
e281682b 5299
b4ff3a36 5300 u8 reserved_at_a0[0x8];
e281682b
SM		 5301 u8 table_id[0x18];
5302
b4ff3a36 5303 u8 reserved_at_c0[0x40];
e281682b
SM		 5304
5305 u8 flow_index[0x20];
5306
b4ff3a36 5307 u8 reserved_at_120[0xe0];
e281682b
SM		 5308};
5309
5310struct mlx5_ifc_dealloc_xrcd_out_bits {
5311 u8 status[0x8];
b4ff3a36 5312 u8 reserved_at_8[0x18];
e281682b
SM		 5313
5314 u8 syndrome[0x20];
5315
b4ff3a36 5316 u8 reserved_at_40[0x40];
e281682b
SM		 5317};
5318
5319struct mlx5_ifc_dealloc_xrcd_in_bits {
5320 u8 opcode[0x10];
b4ff3a36 5321 u8 reserved_at_10[0x10];
e281682b 5322
b4ff3a36 5323 u8 reserved_at_20[0x10];
e281682b
SM		 5324 u8 op_mod[0x10];
5325
b4ff3a36 5326 u8 reserved_at_40[0x8];
e281682b
SM		 5327 u8 xrcd[0x18];
5328
b4ff3a36 5329 u8 reserved_at_60[0x20];
e281682b
SM		 5330};
5331
5332struct mlx5_ifc_dealloc_uar_out_bits {
5333 u8 status[0x8];
b4ff3a36 5334 u8 reserved_at_8[0x18];
e281682b
SM		 5335
5336 u8 syndrome[0x20];
5337
b4ff3a36 5338 u8 reserved_at_40[0x40];
e281682b
SM		 5339};
5340
5341struct mlx5_ifc_dealloc_uar_in_bits {
5342 u8 opcode[0x10];
b4ff3a36 5343 u8 reserved_at_10[0x10];
e281682b 5344
b4ff3a36 5345 u8 reserved_at_20[0x10];
e281682b
SM		 5346 u8 op_mod[0x10];
5347
b4ff3a36 5348 u8 reserved_at_40[0x8];
e281682b
SM		 5349 u8 uar[0x18];
5350
b4ff3a36 5351 u8 reserved_at_60[0x20];
e281682b
SM		 5352};
5353
5354struct mlx5_ifc_dealloc_transport_domain_out_bits {
5355 u8 status[0x8];
b4ff3a36 5356 u8 reserved_at_8[0x18];
e281682b
SM		 5357
5358 u8 syndrome[0x20];
5359
b4ff3a36 5360 u8 reserved_at_40[0x40];
e281682b
SM		 5361};
5362
5363struct mlx5_ifc_dealloc_transport_domain_in_bits {
5364 u8 opcode[0x10];
b4ff3a36 5365 u8 reserved_at_10[0x10];
e281682b 5366
b4ff3a36 5367 u8 reserved_at_20[0x10];
e281682b
SM		 5368 u8 op_mod[0x10];
5369
b4ff3a36 5370 u8 reserved_at_40[0x8];
e281682b
SM		 5371 u8 transport_domain[0x18];
5372
b4ff3a36 5373 u8 reserved_at_60[0x20];
e281682b
SM		 5374};
5375
5376struct mlx5_ifc_dealloc_q_counter_out_bits {
5377 u8 status[0x8];
b4ff3a36 5378 u8 reserved_at_8[0x18];
e281682b
SM		 5379
5380 u8 syndrome[0x20];
5381
b4ff3a36 5382 u8 reserved_at_40[0x40];
e281682b
SM		 5383};
5384
5385struct mlx5_ifc_dealloc_q_counter_in_bits {
5386 u8 opcode[0x10];
b4ff3a36 5387 u8 reserved_at_10[0x10];
e281682b 5388
b4ff3a36 5389 u8 reserved_at_20[0x10];
e281682b
SM		 5390 u8 op_mod[0x10];
5391
b4ff3a36 5392 u8 reserved_at_40[0x18];
e281682b
SM		 5393 u8 counter_set_id[0x8];
5394
b4ff3a36 5395 u8 reserved_at_60[0x20];
e281682b
SM		 5396};
5397
5398struct mlx5_ifc_dealloc_pd_out_bits {
5399 u8 status[0x8];
b4ff3a36 5400 u8 reserved_at_8[0x18];
e281682b
SM		 5401
5402 u8 syndrome[0x20];
5403
b4ff3a36 5404 u8 reserved_at_40[0x40];
e281682b
SM		 5405};
5406
5407struct mlx5_ifc_dealloc_pd_in_bits {
5408 u8 opcode[0x10];
b4ff3a36 5409 u8 reserved_at_10[0x10];
e281682b 5410
b4ff3a36 5411 u8 reserved_at_20[0x10];
e281682b
SM		 5412 u8 op_mod[0x10];
5413
b4ff3a36 5414 u8 reserved_at_40[0x8];
e281682b
SM		 5415 u8 pd[0x18];
5416
b4ff3a36 5417 u8 reserved_at_60[0x20];
e281682b
SM		 5418};
5419
5420struct mlx5_ifc_create_xrc_srq_out_bits {
5421 u8 status[0x8];
b4ff3a36 5422 u8 reserved_at_8[0x18];
e281682b
SM		 5423
5424 u8 syndrome[0x20];
5425
b4ff3a36 5426 u8 reserved_at_40[0x8];
e281682b
SM		 5427 u8 xrc_srqn[0x18];
5428
b4ff3a36 5429 u8 reserved_at_60[0x20];
e281682b
SM		 5430};
5431
5432struct mlx5_ifc_create_xrc_srq_in_bits {
5433 u8 opcode[0x10];
b4ff3a36 5434 u8 reserved_at_10[0x10];
e281682b 5435
b4ff3a36 5436 u8 reserved_at_20[0x10];
e281682b
SM		 5437 u8 op_mod[0x10];
5438
b4ff3a36 5439 u8 reserved_at_40[0x40];
e281682b
SM		 5440
5441 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5442
b4ff3a36 5443 u8 reserved_at_280[0x600];
e281682b
SM		 5444
5445 u8 pas[0][0x40];
5446};
5447
5448struct mlx5_ifc_create_tis_out_bits {
5449 u8 status[0x8];
b4ff3a36 5450 u8 reserved_at_8[0x18];
e281682b
SM		 5451
5452 u8 syndrome[0x20];
5453
b4ff3a36 5454 u8 reserved_at_40[0x8];
e281682b
SM		 5455 u8 tisn[0x18];
5456
b4ff3a36 5457 u8 reserved_at_60[0x20];
e281682b
SM		 5458};
5459
5460struct mlx5_ifc_create_tis_in_bits {
5461 u8 opcode[0x10];
b4ff3a36 5462 u8 reserved_at_10[0x10];
e281682b 5463
b4ff3a36 5464 u8 reserved_at_20[0x10];
e281682b
SM		 5465 u8 op_mod[0x10];
5466
b4ff3a36 5467 u8 reserved_at_40[0xc0];
e281682b
SM		 5468
5469 struct mlx5_ifc_tisc_bits ctx;
5470};
5471
5472struct mlx5_ifc_create_tir_out_bits {
5473 u8 status[0x8];
b4ff3a36 5474 u8 reserved_at_8[0x18];
e281682b
SM		 5475
5476 u8 syndrome[0x20];
5477
b4ff3a36 5478 u8 reserved_at_40[0x8];
e281682b
SM		 5479 u8 tirn[0x18];
5480
b4ff3a36 5481 u8 reserved_at_60[0x20];
e281682b
SM		 5482};
5483
5484struct mlx5_ifc_create_tir_in_bits {
5485 u8 opcode[0x10];
b4ff3a36 5486 u8 reserved_at_10[0x10];
e281682b 5487
b4ff3a36 5488 u8 reserved_at_20[0x10];
e281682b
SM		 5489 u8 op_mod[0x10];
5490
b4ff3a36 5491 u8 reserved_at_40[0xc0];
e281682b
SM		 5492
5493 struct mlx5_ifc_tirc_bits ctx;
5494};
5495
5496struct mlx5_ifc_create_srq_out_bits {
5497 u8 status[0x8];
b4ff3a36 5498 u8 reserved_at_8[0x18];
e281682b
SM		 5499
5500 u8 syndrome[0x20];
5501
b4ff3a36 5502 u8 reserved_at_40[0x8];
e281682b
SM		 5503 u8 srqn[0x18];
5504
b4ff3a36 5505 u8 reserved_at_60[0x20];
e281682b
SM		 5506};
5507
5508struct mlx5_ifc_create_srq_in_bits {
5509 u8 opcode[0x10];
b4ff3a36 5510 u8 reserved_at_10[0x10];
e281682b 5511
b4ff3a36 5512 u8 reserved_at_20[0x10];
e281682b
SM		 5513 u8 op_mod[0x10];
5514
b4ff3a36 5515 u8 reserved_at_40[0x40];
e281682b
SM		 5516
5517 struct mlx5_ifc_srqc_bits srq_context_entry;
5518
b4ff3a36 5519 u8 reserved_at_280[0x600];
e281682b
SM		 5520
5521 u8 pas[0][0x40];
5522};
5523
5524struct mlx5_ifc_create_sq_out_bits {
5525 u8 status[0x8];
b4ff3a36 5526 u8 reserved_at_8[0x18];
e281682b
SM		 5527
5528 u8 syndrome[0x20];
5529
b4ff3a36 5530 u8 reserved_at_40[0x8];
e281682b
SM		 5531 u8 sqn[0x18];
5532
b4ff3a36 5533 u8 reserved_at_60[0x20];
e281682b
SM		 5534};
5535
5536struct mlx5_ifc_create_sq_in_bits {
5537 u8 opcode[0x10];
b4ff3a36 5538 u8 reserved_at_10[0x10];
e281682b 5539
b4ff3a36 5540 u8 reserved_at_20[0x10];
e281682b
SM		 5541 u8 op_mod[0x10];
5542
b4ff3a36 5543 u8 reserved_at_40[0xc0];
e281682b
SM		 5544
5545 struct mlx5_ifc_sqc_bits ctx;
5546};
5547
5548struct mlx5_ifc_create_rqt_out_bits {
5549 u8 status[0x8];
b4ff3a36 5550 u8 reserved_at_8[0x18];
e281682b
SM		 5551
5552 u8 syndrome[0x20];
5553
b4ff3a36 5554 u8 reserved_at_40[0x8];
e281682b
SM		 5555 u8 rqtn[0x18];
5556
b4ff3a36 5557 u8 reserved_at_60[0x20];
e281682b
SM		 5558};
5559
5560struct mlx5_ifc_create_rqt_in_bits {
5561 u8 opcode[0x10];
b4ff3a36 5562 u8 reserved_at_10[0x10];
e281682b 5563
b4ff3a36 5564 u8 reserved_at_20[0x10];
e281682b
SM		 5565 u8 op_mod[0x10];
5566
b4ff3a36 5567 u8 reserved_at_40[0xc0];
e281682b
SM		 5568
5569 struct mlx5_ifc_rqtc_bits rqt_context;
5570};
5571
5572struct mlx5_ifc_create_rq_out_bits {
5573 u8 status[0x8];
b4ff3a36 5574 u8 reserved_at_8[0x18];
e281682b
SM		 5575
5576 u8 syndrome[0x20];
5577
b4ff3a36 5578 u8 reserved_at_40[0x8];
e281682b
SM		 5579 u8 rqn[0x18];
5580
b4ff3a36 5581 u8 reserved_at_60[0x20];
e281682b
SM		 5582};
5583
5584struct mlx5_ifc_create_rq_in_bits {
5585 u8 opcode[0x10];
b4ff3a36 5586 u8 reserved_at_10[0x10];
e281682b 5587
b4ff3a36 5588 u8 reserved_at_20[0x10];
e281682b
SM		 5589 u8 op_mod[0x10];
5590
b4ff3a36 5591 u8 reserved_at_40[0xc0];
e281682b
SM		 5592
5593 struct mlx5_ifc_rqc_bits ctx;
5594};
5595
5596struct mlx5_ifc_create_rmp_out_bits {
5597 u8 status[0x8];
b4ff3a36 5598 u8 reserved_at_8[0x18];
e281682b
SM		 5599
5600 u8 syndrome[0x20];
5601
b4ff3a36 5602 u8 reserved_at_40[0x8];
e281682b
SM		 5603 u8 rmpn[0x18];
5604
b4ff3a36 5605 u8 reserved_at_60[0x20];
e281682b
SM		 5606};
5607
5608struct mlx5_ifc_create_rmp_in_bits {
5609 u8 opcode[0x10];
b4ff3a36 5610 u8 reserved_at_10[0x10];
e281682b 5611
b4ff3a36 5612 u8 reserved_at_20[0x10];
e281682b
SM		 5613 u8 op_mod[0x10];
5614
b4ff3a36 5615 u8 reserved_at_40[0xc0];
e281682b
SM		 5616
5617 struct mlx5_ifc_rmpc_bits ctx;
5618};
5619
5620struct mlx5_ifc_create_qp_out_bits {
5621 u8 status[0x8];
b4ff3a36 5622 u8 reserved_at_8[0x18];
e281682b
SM		 5623
5624 u8 syndrome[0x20];
5625
b4ff3a36 5626 u8 reserved_at_40[0x8];
e281682b
SM		 5627 u8 qpn[0x18];
5628
b4ff3a36 5629 u8 reserved_at_60[0x20];
e281682b
SM		 5630};
5631
5632struct mlx5_ifc_create_qp_in_bits {
5633 u8 opcode[0x10];
b4ff3a36 5634 u8 reserved_at_10[0x10];
e281682b 5635
b4ff3a36 5636 u8 reserved_at_20[0x10];
e281682b
SM		 5637 u8 op_mod[0x10];
5638
b4ff3a36 5639 u8 reserved_at_40[0x40];
e281682b
SM		 5640
5641 u8 opt_param_mask[0x20];
5642
b4ff3a36 5643 u8 reserved_at_a0[0x20];
e281682b
SM		 5644
5645 struct mlx5_ifc_qpc_bits qpc;
5646
b4ff3a36 5647 u8 reserved_at_800[0x80];
e281682b
SM		 5648
5649 u8 pas[0][0x40];
5650};
5651
5652struct mlx5_ifc_create_psv_out_bits {
5653 u8 status[0x8];
b4ff3a36 5654 u8 reserved_at_8[0x18];
e281682b
SM		 5655
5656 u8 syndrome[0x20];
5657
b4ff3a36 5658 u8 reserved_at_40[0x40];
e281682b 5659
b4ff3a36 5660 u8 reserved_at_80[0x8];
e281682b
SM		 5661 u8 psv0_index[0x18];
5662
b4ff3a36 5663 u8 reserved_at_a0[0x8];
e281682b
SM		 5664 u8 psv1_index[0x18];
5665
b4ff3a36 5666 u8 reserved_at_c0[0x8];
e281682b
SM		 5667 u8 psv2_index[0x18];
5668
b4ff3a36 5669 u8 reserved_at_e0[0x8];
e281682b
SM		 5670 u8 psv3_index[0x18];
5671};
5672
5673struct mlx5_ifc_create_psv_in_bits {
5674 u8 opcode[0x10];
b4ff3a36 5675 u8 reserved_at_10[0x10];
e281682b 5676
b4ff3a36 5677 u8 reserved_at_20[0x10];
e281682b
SM		 5678 u8 op_mod[0x10];
5679
5680 u8 num_psv[0x4];
b4ff3a36 5681 u8 reserved_at_44[0x4];
e281682b
SM		 5682 u8 pd[0x18];
5683
b4ff3a36 5684 u8 reserved_at_60[0x20];
e281682b
SM		 5685};
5686
5687struct mlx5_ifc_create_mkey_out_bits {
5688 u8 status[0x8];
b4ff3a36 5689 u8 reserved_at_8[0x18];
e281682b
SM		 5690
5691 u8 syndrome[0x20];
5692
b4ff3a36 5693 u8 reserved_at_40[0x8];
e281682b
SM		 5694 u8 mkey_index[0x18];
5695
b4ff3a36 5696 u8 reserved_at_60[0x20];
e281682b
SM		 5697};
5698
5699struct mlx5_ifc_create_mkey_in_bits {
5700 u8 opcode[0x10];
b4ff3a36 5701 u8 reserved_at_10[0x10];
e281682b 5702
b4ff3a36 5703 u8 reserved_at_20[0x10];
e281682b
SM		 5704 u8 op_mod[0x10];
5705
b4ff3a36 5706 u8 reserved_at_40[0x20];
e281682b
SM		 5707
5708 u8 pg_access[0x1];
b4ff3a36 5709 u8 reserved_at_61[0x1f];
e281682b
SM		 5710
5711 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5712
b4ff3a36 5713 u8 reserved_at_280[0x80];
e281682b
SM		 5714
5715 u8 translations_octword_actual_size[0x20];
5716
b4ff3a36 5717 u8 reserved_at_320[0x560];
e281682b
SM		 5718
5719 u8 klm_pas_mtt[0][0x20];
5720};
5721
5722struct mlx5_ifc_create_flow_table_out_bits {
5723 u8 status[0x8];
b4ff3a36 5724 u8 reserved_at_8[0x18];
e281682b
SM		 5725
5726 u8 syndrome[0x20];
5727
b4ff3a36 5728 u8 reserved_at_40[0x8];
e281682b
SM		 5729 u8 table_id[0x18];
5730
b4ff3a36 5731 u8 reserved_at_60[0x20];
e281682b
SM		 5732};
5733
5734struct mlx5_ifc_create_flow_table_in_bits {
5735 u8 opcode[0x10];
b4ff3a36 5736 u8 reserved_at_10[0x10];
e281682b 5737
b4ff3a36 5738 u8 reserved_at_20[0x10];
e281682b
SM		 5739 u8 op_mod[0x10];
5740
b4ff3a36 5741 u8 reserved_at_40[0x40];
e281682b
SM		 5742
5743 u8 table_type[0x8];
b4ff3a36 5744 u8 reserved_at_88[0x18];
e281682b 5745
b4ff3a36 5746 u8 reserved_at_a0[0x20];
e281682b 5747
b4ff3a36 5748 u8 reserved_at_c0[0x4];
34a40e68 5749 u8 table_miss_mode[0x4];
e281682b 5750 u8 level[0x8];
b4ff3a36 5751 u8 reserved_at_d0[0x8];
e281682b
SM		 5752 u8 log_size[0x8];
5753
b4ff3a36 5754 u8 reserved_at_e0[0x8];
34a40e68
MG		 5755 u8 table_miss_id[0x18];
5756
b4ff3a36 5757 u8 reserved_at_100[0x100];
e281682b
SM		 5758};
5759
5760struct mlx5_ifc_create_flow_group_out_bits {
5761 u8 status[0x8];
b4ff3a36 5762 u8 reserved_at_8[0x18];
e281682b
SM		 5763
5764 u8 syndrome[0x20];
5765
b4ff3a36 5766 u8 reserved_at_40[0x8];
e281682b
SM		 5767 u8 group_id[0x18];
5768
b4ff3a36 5769 u8 reserved_at_60[0x20];
e281682b
SM		 5770};
5771
5772enum {
5773 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5774 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5775 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5776};
5777
5778struct mlx5_ifc_create_flow_group_in_bits {
5779 u8 opcode[0x10];
b4ff3a36 5780 u8 reserved_at_10[0x10];
e281682b 5781
b4ff3a36 5782 u8 reserved_at_20[0x10];
e281682b
SM		 5783 u8 op_mod[0x10];
5784
b4ff3a36 5785 u8 reserved_at_40[0x40];
e281682b
SM		 5786
5787 u8 table_type[0x8];
b4ff3a36 5788 u8 reserved_at_88[0x18];
e281682b 5789
b4ff3a36 5790 u8 reserved_at_a0[0x8];
e281682b
SM		 5791 u8 table_id[0x18];
5792
b4ff3a36 5793 u8 reserved_at_c0[0x20];
e281682b
SM		 5794
5795 u8 start_flow_index[0x20];
5796
b4ff3a36 5797 u8 reserved_at_100[0x20];
e281682b
SM		 5798
5799 u8 end_flow_index[0x20];
5800
b4ff3a36 5801 u8 reserved_at_140[0xa0];
e281682b 5802
b4ff3a36 5803 u8 reserved_at_1e0[0x18];
e281682b
SM		 5804 u8 match_criteria_enable[0x8];
5805
5806 struct mlx5_ifc_fte_match_param_bits match_criteria;
5807
b4ff3a36 5808 u8 reserved_at_1200[0xe00];
e281682b
SM		 5809};
5810
5811struct mlx5_ifc_create_eq_out_bits {
5812 u8 status[0x8];
b4ff3a36 5813 u8 reserved_at_8[0x18];
e281682b
SM		 5814
5815 u8 syndrome[0x20];
5816
b4ff3a36 5817 u8 reserved_at_40[0x18];
e281682b
SM		 5818 u8 eq_number[0x8];
5819
b4ff3a36 5820 u8 reserved_at_60[0x20];
e281682b
SM		 5821};
5822
5823struct mlx5_ifc_create_eq_in_bits {
5824 u8 opcode[0x10];
b4ff3a36 5825 u8 reserved_at_10[0x10];
e281682b 5826
b4ff3a36 5827 u8 reserved_at_20[0x10];
e281682b
SM		 5828 u8 op_mod[0x10];
5829
b4ff3a36 5830 u8 reserved_at_40[0x40];
e281682b
SM		 5831
5832 struct mlx5_ifc_eqc_bits eq_context_entry;
5833
b4ff3a36 5834 u8 reserved_at_280[0x40];
e281682b
SM		 5835
5836 u8 event_bitmask[0x40];
5837
b4ff3a36 5838 u8 reserved_at_300[0x580];
e281682b
SM		 5839
5840 u8 pas[0][0x40];
5841};
5842
5843struct mlx5_ifc_create_dct_out_bits {
5844 u8 status[0x8];
b4ff3a36 5845 u8 reserved_at_8[0x18];
e281682b
SM		 5846
5847 u8 syndrome[0x20];
5848
b4ff3a36 5849 u8 reserved_at_40[0x8];
e281682b
SM		 5850 u8 dctn[0x18];
5851
b4ff3a36 5852 u8 reserved_at_60[0x20];
e281682b
SM		 5853};
5854
5855struct mlx5_ifc_create_dct_in_bits {
5856 u8 opcode[0x10];
b4ff3a36 5857 u8 reserved_at_10[0x10];
e281682b 5858
b4ff3a36 5859 u8 reserved_at_20[0x10];
e281682b
SM		 5860 u8 op_mod[0x10];
5861
b4ff3a36 5862 u8 reserved_at_40[0x40];
e281682b
SM		 5863
5864 struct mlx5_ifc_dctc_bits dct_context_entry;
5865
b4ff3a36 5866 u8 reserved_at_280[0x180];
e281682b
SM		 5867};
5868
5869struct mlx5_ifc_create_cq_out_bits {
5870 u8 status[0x8];
b4ff3a36 5871 u8 reserved_at_8[0x18];
e281682b
SM		 5872
5873 u8 syndrome[0x20];
5874
b4ff3a36 5875 u8 reserved_at_40[0x8];
e281682b
SM		 5876 u8 cqn[0x18];
5877
b4ff3a36 5878 u8 reserved_at_60[0x20];
e281682b
SM		 5879};
5880
5881struct mlx5_ifc_create_cq_in_bits {
5882 u8 opcode[0x10];
b4ff3a36 5883 u8 reserved_at_10[0x10];
e281682b 5884
b4ff3a36 5885 u8 reserved_at_20[0x10];
e281682b
SM		 5886 u8 op_mod[0x10];
5887
b4ff3a36 5888 u8 reserved_at_40[0x40];
e281682b
SM		 5889
5890 struct mlx5_ifc_cqc_bits cq_context;
5891
b4ff3a36 5892 u8 reserved_at_280[0x600];
e281682b
SM		 5893
5894 u8 pas[0][0x40];
5895};
5896
5897struct mlx5_ifc_config_int_moderation_out_bits {
5898 u8 status[0x8];
b4ff3a36 5899 u8 reserved_at_8[0x18];
e281682b
SM		 5900
5901 u8 syndrome[0x20];
5902
b4ff3a36 5903 u8 reserved_at_40[0x4];
e281682b
SM		 5904 u8 min_delay[0xc];
5905 u8 int_vector[0x10];
5906
b4ff3a36 5907 u8 reserved_at_60[0x20];
e281682b
SM		 5908};
5909
5910enum {
5911 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
5912 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
5913};
5914
5915struct mlx5_ifc_config_int_moderation_in_bits {
5916 u8 opcode[0x10];
b4ff3a36 5917 u8 reserved_at_10[0x10];
e281682b 5918
b4ff3a36 5919 u8 reserved_at_20[0x10];
e281682b
SM		 5920 u8 op_mod[0x10];
5921
b4ff3a36 5922 u8 reserved_at_40[0x4];
e281682b
SM		 5923 u8 min_delay[0xc];
5924 u8 int_vector[0x10];
5925
b4ff3a36 5926 u8 reserved_at_60[0x20];
e281682b
SM		 5927};
5928
5929struct mlx5_ifc_attach_to_mcg_out_bits {
5930 u8 status[0x8];
b4ff3a36 5931 u8 reserved_at_8[0x18];
e281682b
SM		 5932
5933 u8 syndrome[0x20];
5934
b4ff3a36 5935 u8 reserved_at_40[0x40];
e281682b
SM		 5936};
5937
5938struct mlx5_ifc_attach_to_mcg_in_bits {
5939 u8 opcode[0x10];
b4ff3a36 5940 u8 reserved_at_10[0x10];
e281682b 5941
b4ff3a36 5942 u8 reserved_at_20[0x10];
e281682b
SM		 5943 u8 op_mod[0x10];
5944
b4ff3a36 5945 u8 reserved_at_40[0x8];
e281682b
SM		 5946 u8 qpn[0x18];
5947
b4ff3a36 5948 u8 reserved_at_60[0x20];
e281682b
SM		 5949
5950 u8 multicast_gid[16][0x8];
5951};
5952
5953struct mlx5_ifc_arm_xrc_srq_out_bits {
5954 u8 status[0x8];
b4ff3a36 5955 u8 reserved_at_8[0x18];
e281682b
SM		 5956
5957 u8 syndrome[0x20];
5958
b4ff3a36 5959 u8 reserved_at_40[0x40];
e281682b
SM		 5960};
5961
5962enum {
5963 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
5964};
5965
5966struct mlx5_ifc_arm_xrc_srq_in_bits {
5967 u8 opcode[0x10];
b4ff3a36 5968 u8 reserved_at_10[0x10];
e281682b 5969
b4ff3a36 5970 u8 reserved_at_20[0x10];
e281682b
SM		 5971 u8 op_mod[0x10];
5972
b4ff3a36 5973 u8 reserved_at_40[0x8];
e281682b
SM		 5974 u8 xrc_srqn[0x18];
5975
b4ff3a36 5976 u8 reserved_at_60[0x10];
e281682b
SM		 5977 u8 lwm[0x10];
5978};
5979
5980struct mlx5_ifc_arm_rq_out_bits {
5981 u8 status[0x8];
b4ff3a36 5982 u8 reserved_at_8[0x18];
e281682b
SM		 5983
5984 u8 syndrome[0x20];
5985
b4ff3a36 5986 u8 reserved_at_40[0x40];
e281682b
SM		 5987};
5988
5989enum {
5990 MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1,
5991};
5992
5993struct mlx5_ifc_arm_rq_in_bits {
5994 u8 opcode[0x10];
b4ff3a36 5995 u8 reserved_at_10[0x10];
e281682b 5996
b4ff3a36 5997 u8 reserved_at_20[0x10];
e281682b
SM		 5998 u8 op_mod[0x10];
5999
b4ff3a36 6000 u8 reserved_at_40[0x8];
e281682b
SM		 6001 u8 srq_number[0x18];
6002
b4ff3a36 6003 u8 reserved_at_60[0x10];
e281682b
SM		 6004 u8 lwm[0x10];
6005};
6006
6007struct mlx5_ifc_arm_dct_out_bits {
6008 u8 status[0x8];
b4ff3a36 6009 u8 reserved_at_8[0x18];
e281682b
SM		 6010
6011 u8 syndrome[0x20];
6012
b4ff3a36 6013 u8 reserved_at_40[0x40];
e281682b
SM		 6014};
6015
6016struct mlx5_ifc_arm_dct_in_bits {
6017 u8 opcode[0x10];
b4ff3a36 6018 u8 reserved_at_10[0x10];
e281682b 6019
b4ff3a36 6020 u8 reserved_at_20[0x10];
e281682b
SM		 6021 u8 op_mod[0x10];
6022
b4ff3a36 6023 u8 reserved_at_40[0x8];
e281682b
SM		 6024 u8 dct_number[0x18];
6025
b4ff3a36 6026 u8 reserved_at_60[0x20];
e281682b
SM		 6027};
6028
6029struct mlx5_ifc_alloc_xrcd_out_bits {
6030 u8 status[0x8];
b4ff3a36 6031 u8 reserved_at_8[0x18];
e281682b
SM		 6032
6033 u8 syndrome[0x20];
6034
b4ff3a36 6035 u8 reserved_at_40[0x8];
e281682b
SM		 6036 u8 xrcd[0x18];
6037
b4ff3a36 6038 u8 reserved_at_60[0x20];
e281682b
SM		 6039};
6040
6041struct mlx5_ifc_alloc_xrcd_in_bits {
6042 u8 opcode[0x10];
b4ff3a36 6043 u8 reserved_at_10[0x10];
e281682b 6044
b4ff3a36 6045 u8 reserved_at_20[0x10];
e281682b
SM		 6046 u8 op_mod[0x10];
6047
b4ff3a36 6048 u8 reserved_at_40[0x40];
e281682b
SM		 6049};
6050
6051struct mlx5_ifc_alloc_uar_out_bits {
6052 u8 status[0x8];
b4ff3a36 6053 u8 reserved_at_8[0x18];
e281682b
SM		 6054
6055 u8 syndrome[0x20];
6056
b4ff3a36 6057 u8 reserved_at_40[0x8];
e281682b
SM		 6058 u8 uar[0x18];
6059
b4ff3a36 6060 u8 reserved_at_60[0x20];
e281682b
SM		 6061};
6062
6063struct mlx5_ifc_alloc_uar_in_bits {
6064 u8 opcode[0x10];
b4ff3a36 6065 u8 reserved_at_10[0x10];
e281682b 6066
b4ff3a36 6067 u8 reserved_at_20[0x10];
e281682b
SM		 6068 u8 op_mod[0x10];
6069
b4ff3a36 6070 u8 reserved_at_40[0x40];
e281682b
SM		 6071};
6072
6073struct mlx5_ifc_alloc_transport_domain_out_bits {
6074 u8 status[0x8];
b4ff3a36 6075 u8 reserved_at_8[0x18];
e281682b
SM		 6076
6077 u8 syndrome[0x20];
6078
b4ff3a36 6079 u8 reserved_at_40[0x8];
e281682b
SM		 6080 u8 transport_domain[0x18];
6081
b4ff3a36 6082 u8 reserved_at_60[0x20];
e281682b
SM		 6083};
6084
6085struct mlx5_ifc_alloc_transport_domain_in_bits {
6086 u8 opcode[0x10];
b4ff3a36 6087 u8 reserved_at_10[0x10];
e281682b 6088
b4ff3a36 6089 u8 reserved_at_20[0x10];
e281682b
SM		 6090 u8 op_mod[0x10];
6091
b4ff3a36 6092 u8 reserved_at_40[0x40];
e281682b
SM		 6093};
6094
6095struct mlx5_ifc_alloc_q_counter_out_bits {
6096 u8 status[0x8];
b4ff3a36 6097 u8 reserved_at_8[0x18];
e281682b
SM		 6098
6099 u8 syndrome[0x20];
6100
b4ff3a36 6101 u8 reserved_at_40[0x18];
e281682b
SM		 6102 u8 counter_set_id[0x8];
6103
b4ff3a36 6104 u8 reserved_at_60[0x20];
e281682b
SM		 6105};
6106
6107struct mlx5_ifc_alloc_q_counter_in_bits {
6108 u8 opcode[0x10];
b4ff3a36 6109 u8 reserved_at_10[0x10];
e281682b 6110
b4ff3a36 6111 u8 reserved_at_20[0x10];
e281682b
SM		 6112 u8 op_mod[0x10];
6113
b4ff3a36 6114 u8 reserved_at_40[0x40];
e281682b
SM		 6115};
6116
6117struct mlx5_ifc_alloc_pd_out_bits {
6118 u8 status[0x8];
b4ff3a36 6119 u8 reserved_at_8[0x18];
e281682b
SM		 6120
6121 u8 syndrome[0x20];
6122
b4ff3a36 6123 u8 reserved_at_40[0x8];
e281682b
SM		 6124 u8 pd[0x18];
6125
b4ff3a36 6126 u8 reserved_at_60[0x20];
e281682b
SM		 6127};
6128
6129struct mlx5_ifc_alloc_pd_in_bits {
6130 u8 opcode[0x10];
b4ff3a36 6131 u8 reserved_at_10[0x10];
e281682b 6132
b4ff3a36 6133 u8 reserved_at_20[0x10];
e281682b
SM		 6134 u8 op_mod[0x10];
6135
b4ff3a36 6136 u8 reserved_at_40[0x40];
e281682b
SM		 6137};
6138
6139struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6140 u8 status[0x8];
b4ff3a36 6141 u8 reserved_at_8[0x18];
e281682b
SM		 6142
6143 u8 syndrome[0x20];
6144
b4ff3a36 6145 u8 reserved_at_40[0x40];
e281682b
SM		 6146};
6147
6148struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6149 u8 opcode[0x10];
b4ff3a36 6150 u8 reserved_at_10[0x10];
e281682b 6151
b4ff3a36 6152 u8 reserved_at_20[0x10];
e281682b
SM		 6153 u8 op_mod[0x10];
6154
b4ff3a36 6155 u8 reserved_at_40[0x20];
e281682b 6156
b4ff3a36 6157 u8 reserved_at_60[0x10];
e281682b
SM		 6158 u8 vxlan_udp_port[0x10];
6159};
6160
6161struct mlx5_ifc_access_register_out_bits {
6162 u8 status[0x8];
b4ff3a36 6163 u8 reserved_at_8[0x18];
e281682b
SM		 6164
6165 u8 syndrome[0x20];
6166
b4ff3a36 6167 u8 reserved_at_40[0x40];
e281682b
SM		 6168
6169 u8 register_data[0][0x20];
6170};
6171
6172enum {
6173 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
6174 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
6175};
6176
6177struct mlx5_ifc_access_register_in_bits {
6178 u8 opcode[0x10];
b4ff3a36 6179 u8 reserved_at_10[0x10];
e281682b 6180
b4ff3a36 6181 u8 reserved_at_20[0x10];
e281682b
SM		 6182 u8 op_mod[0x10];
6183
b4ff3a36 6184 u8 reserved_at_40[0x10];
e281682b
SM		 6185 u8 register_id[0x10];
6186
6187 u8 argument[0x20];
6188
6189 u8 register_data[0][0x20];
6190};
6191
6192struct mlx5_ifc_sltp_reg_bits {
6193 u8 status[0x4];
6194 u8 version[0x4];
6195 u8 local_port[0x8];
6196 u8 pnat[0x2];
b4ff3a36 6197 u8 reserved_at_12[0x2];
e281682b 6198 u8 lane[0x4];
b4ff3a36 6199 u8 reserved_at_18[0x8];
e281682b 6200
b4ff3a36 6201 u8 reserved_at_20[0x20];
e281682b 6202
b4ff3a36 6203 u8 reserved_at_40[0x7];
e281682b
SM		 6204 u8 polarity[0x1];
6205 u8 ob_tap0[0x8];
6206 u8 ob_tap1[0x8];
6207 u8 ob_tap2[0x8];
6208
b4ff3a36 6209 u8 reserved_at_60[0xc];
e281682b
SM		 6210 u8 ob_preemp_mode[0x4];
6211 u8 ob_reg[0x8];
6212 u8 ob_bias[0x8];
6213
b4ff3a36 6214 u8 reserved_at_80[0x20];
e281682b
SM		 6215};
6216
6217struct mlx5_ifc_slrg_reg_bits {
6218 u8 status[0x4];
6219 u8 version[0x4];
6220 u8 local_port[0x8];
6221 u8 pnat[0x2];
b4ff3a36 6222 u8 reserved_at_12[0x2];
e281682b 6223 u8 lane[0x4];
b4ff3a36 6224 u8 reserved_at_18[0x8];
e281682b
SM		 6225
6226 u8 time_to_link_up[0x10];
b4ff3a36 6227 u8 reserved_at_30[0xc];
e281682b
SM		 6228 u8 grade_lane_speed[0x4];
6229
6230 u8 grade_version[0x8];
6231 u8 grade[0x18];
6232
b4ff3a36 6233 u8 reserved_at_60[0x4];
e281682b
SM		 6234 u8 height_grade_type[0x4];
6235 u8 height_grade[0x18];
6236
6237 u8 height_dz[0x10];
6238 u8 height_dv[0x10];
6239
b4ff3a36 6240 u8 reserved_at_a0[0x10];
e281682b
SM		 6241 u8 height_sigma[0x10];
6242
b4ff3a36 6243 u8 reserved_at_c0[0x20];
e281682b 6244
b4ff3a36 6245 u8 reserved_at_e0[0x4];
e281682b
SM		 6246 u8 phase_grade_type[0x4];
6247 u8 phase_grade[0x18];
6248
b4ff3a36 6249 u8 reserved_at_100[0x8];
e281682b 6250 u8 phase_eo_pos[0x8];
b4ff3a36 6251 u8 reserved_at_110[0x8];
e281682b
SM		 6252 u8 phase_eo_neg[0x8];
6253
6254 u8 ffe_set_tested[0x10];
6255 u8 test_errors_per_lane[0x10];
6256};
6257
6258struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 6259 u8 reserved_at_0[0x8];
e281682b 6260 u8 local_port[0x8];
b4ff3a36 6261 u8 reserved_at_10[0x10];
e281682b 6262
b4ff3a36 6263 u8 reserved_at_20[0x1c];
e281682b
SM		 6264 u8 vl_hw_cap[0x4];
6265
b4ff3a36 6266 u8 reserved_at_40[0x1c];
e281682b
SM		 6267 u8 vl_admin[0x4];
6268
b4ff3a36 6269 u8 reserved_at_60[0x1c];
e281682b
SM		 6270 u8 vl_operational[0x4];
6271};
6272
6273struct mlx5_ifc_pude_reg_bits {
6274 u8 swid[0x8];
6275 u8 local_port[0x8];
b4ff3a36 6276 u8 reserved_at_10[0x4];
e281682b 6277 u8 admin_status[0x4];
b4ff3a36 6278 u8 reserved_at_18[0x4];
e281682b
SM		 6279 u8 oper_status[0x4];
6280
b4ff3a36 6281 u8 reserved_at_20[0x60];
e281682b
SM		 6282};
6283
6284struct mlx5_ifc_ptys_reg_bits {
b4ff3a36 6285 u8 reserved_at_0[0x8];
e281682b 6286 u8 local_port[0x8];
b4ff3a36 6287 u8 reserved_at_10[0xd];
e281682b
SM		 6288 u8 proto_mask[0x3];
6289
b4ff3a36 6290 u8 reserved_at_20[0x40];
e281682b
SM		 6291
6292 u8 eth_proto_capability[0x20];
6293
6294 u8 ib_link_width_capability[0x10];
6295 u8 ib_proto_capability[0x10];
6296
b4ff3a36 6297 u8 reserved_at_a0[0x20];
e281682b
SM		 6298
6299 u8 eth_proto_admin[0x20];
6300
6301 u8 ib_link_width_admin[0x10];
6302 u8 ib_proto_admin[0x10];
6303
b4ff3a36 6304 u8 reserved_at_100[0x20];
e281682b
SM		 6305
6306 u8 eth_proto_oper[0x20];
6307
6308 u8 ib_link_width_oper[0x10];
6309 u8 ib_proto_oper[0x10];
6310
b4ff3a36 6311 u8 reserved_at_160[0x20];
e281682b
SM		 6312
6313 u8 eth_proto_lp_advertise[0x20];
6314
b4ff3a36 6315 u8 reserved_at_1a0[0x60];
e281682b
SM		 6316};
6317
6318struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 6319 u8 reserved_at_0[0x20];
e281682b
SM		 6320
6321 u8 algorithm_options[0x10];
b4ff3a36 6322 u8 reserved_at_30[0x4];
e281682b
SM		 6323 u8 repetitions_mode[0x4];
6324 u8 num_of_repetitions[0x8];
6325
6326 u8 grade_version[0x8];
6327 u8 height_grade_type[0x4];
6328 u8 phase_grade_type[0x4];
6329 u8 height_grade_weight[0x8];
6330 u8 phase_grade_weight[0x8];
6331
6332 u8 gisim_measure_bits[0x10];
6333 u8 adaptive_tap_measure_bits[0x10];
6334
6335 u8 ber_bath_high_error_threshold[0x10];
6336 u8 ber_bath_mid_error_threshold[0x10];
6337
6338 u8 ber_bath_low_error_threshold[0x10];
6339 u8 one_ratio_high_threshold[0x10];
6340
6341 u8 one_ratio_high_mid_threshold[0x10];
6342 u8 one_ratio_low_mid_threshold[0x10];
6343
6344 u8 one_ratio_low_threshold[0x10];
6345 u8 ndeo_error_threshold[0x10];
6346
6347 u8 mixer_offset_step_size[0x10];
b4ff3a36 6348 u8 reserved_at_110[0x8];
e281682b
SM		 6349 u8 mix90_phase_for_voltage_bath[0x8];
6350
6351 u8 mixer_offset_start[0x10];
6352 u8 mixer_offset_end[0x10];
6353
b4ff3a36 6354 u8 reserved_at_140[0x15];
e281682b
SM		 6355 u8 ber_test_time[0xb];
6356};
6357
6358struct mlx5_ifc_pspa_reg_bits {
6359 u8 swid[0x8];
6360 u8 local_port[0x8];
6361 u8 sub_port[0x8];
b4ff3a36 6362 u8 reserved_at_18[0x8];
e281682b 6363
b4ff3a36 6364 u8 reserved_at_20[0x20];
e281682b
SM		 6365};
6366
6367struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 6368 u8 reserved_at_0[0x8];
e281682b 6369 u8 local_port[0x8];
b4ff3a36 6370 u8 reserved_at_10[0x5];
e281682b 6371 u8 prio[0x3];
b4ff3a36 6372 u8 reserved_at_18[0x6];
e281682b
SM		 6373 u8 mode[0x2];
6374
b4ff3a36 6375 u8 reserved_at_20[0x20];
e281682b 6376
b4ff3a36 6377 u8 reserved_at_40[0x10];
e281682b
SM		 6378 u8 min_threshold[0x10];
6379
b4ff3a36 6380 u8 reserved_at_60[0x10];
e281682b
SM		 6381 u8 max_threshold[0x10];
6382
b4ff3a36 6383 u8 reserved_at_80[0x10];
e281682b
SM		 6384 u8 mark_probability_denominator[0x10];
6385
b4ff3a36 6386 u8 reserved_at_a0[0x60];
e281682b
SM		 6387};
6388
6389struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 6390 u8 reserved_at_0[0x8];
e281682b 6391 u8 local_port[0x8];
b4ff3a36 6392 u8 reserved_at_10[0x10];
e281682b 6393
b4ff3a36 6394 u8 reserved_at_20[0x60];
e281682b 6395
b4ff3a36 6396 u8 reserved_at_80[0x1c];
e281682b
SM		 6397 u8 wrps_admin[0x4];
6398
b4ff3a36 6399 u8 reserved_at_a0[0x1c];
e281682b
SM		 6400 u8 wrps_status[0x4];
6401
b4ff3a36 6402 u8 reserved_at_c0[0x8];
e281682b 6403 u8 up_threshold[0x8];
b4ff3a36 6404 u8 reserved_at_d0[0x8];
e281682b
SM		 6405 u8 down_threshold[0x8];
6406
b4ff3a36 6407 u8 reserved_at_e0[0x20];
e281682b 6408
b4ff3a36 6409 u8 reserved_at_100[0x1c];
e281682b
SM		 6410 u8 srps_admin[0x4];
6411
b4ff3a36 6412 u8 reserved_at_120[0x1c];
e281682b
SM		 6413 u8 srps_status[0x4];
6414
b4ff3a36 6415 u8 reserved_at_140[0x40];
e281682b
SM		 6416};
6417
6418struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 6419 u8 reserved_at_0[0x8];
e281682b 6420 u8 local_port[0x8];
b4ff3a36 6421 u8 reserved_at_10[0x10];
e281682b 6422
b4ff3a36 6423 u8 reserved_at_20[0x8];
e281682b 6424 u8 lb_cap[0x8];
b4ff3a36 6425 u8 reserved_at_30[0x8];
e281682b
SM		 6426 u8 lb_en[0x8];
6427};
6428
6429struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 6430 u8 reserved_at_0[0x8];
e281682b 6431 u8 local_port[0x8];
b4ff3a36 6432 u8 reserved_at_10[0x10];
e281682b 6433
b4ff3a36 6434 u8 reserved_at_20[0x20];
e281682b
SM		 6435
6436 u8 port_profile_mode[0x8];
6437 u8 static_port_profile[0x8];
6438 u8 active_port_profile[0x8];
b4ff3a36 6439 u8 reserved_at_58[0x8];
e281682b
SM		 6440
6441 u8 retransmission_active[0x8];
6442 u8 fec_mode_active[0x18];
6443
b4ff3a36 6444 u8 reserved_at_80[0x20];
e281682b
SM		 6445};
6446
6447struct mlx5_ifc_ppcnt_reg_bits {
6448 u8 swid[0x8];
6449 u8 local_port[0x8];
6450 u8 pnat[0x2];
b4ff3a36 6451 u8 reserved_at_12[0x8];
e281682b
SM		 6452 u8 grp[0x6];
6453
6454 u8 clr[0x1];
b4ff3a36 6455 u8 reserved_at_21[0x1c];
e281682b
SM		 6456 u8 prio_tc[0x3];
6457
6458 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6459};
6460
6461struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 6462 u8 reserved_at_0[0x3];
e281682b 6463 u8 single_mac[0x1];
b4ff3a36 6464 u8 reserved_at_4[0x4];
e281682b
SM		 6465 u8 local_port[0x8];
6466 u8 mac_47_32[0x10];
6467
6468 u8 mac_31_0[0x20];
6469
b4ff3a36 6470 u8 reserved_at_40[0x40];
e281682b
SM		 6471};
6472
6473struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 6474 u8 reserved_at_0[0x8];
e281682b 6475 u8 local_port[0x8];
b4ff3a36 6476 u8 reserved_at_10[0x10];
e281682b
SM		 6477
6478 u8 max_mtu[0x10];
b4ff3a36 6479 u8 reserved_at_30[0x10];
e281682b
SM		 6480
6481 u8 admin_mtu[0x10];
b4ff3a36 6482 u8 reserved_at_50[0x10];
e281682b
SM		 6483
6484 u8 oper_mtu[0x10];
b4ff3a36 6485 u8 reserved_at_70[0x10];
e281682b
SM		 6486};
6487
6488struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 6489 u8 reserved_at_0[0x8];
e281682b 6490 u8 module[0x8];
b4ff3a36 6491 u8 reserved_at_10[0x10];
e281682b 6492
b4ff3a36 6493 u8 reserved_at_20[0x18];
e281682b
SM		 6494 u8 attenuation_5g[0x8];
6495
b4ff3a36 6496 u8 reserved_at_40[0x18];
e281682b
SM		 6497 u8 attenuation_7g[0x8];
6498
b4ff3a36 6499 u8 reserved_at_60[0x18];
e281682b
SM		 6500 u8 attenuation_12g[0x8];
6501};
6502
6503struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 6504 u8 reserved_at_0[0x8];
e281682b 6505 u8 module[0x8];
b4ff3a36 6506 u8 reserved_at_10[0xc];
e281682b
SM		 6507 u8 module_status[0x4];
6508
b4ff3a36 6509 u8 reserved_at_20[0x60];
e281682b
SM		 6510};
6511
6512struct mlx5_ifc_pmpc_reg_bits {
6513 u8 module_state_updated[32][0x8];
6514};
6515
6516struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 6517 u8 reserved_at_0[0x4];
e281682b
SM		 6518 u8 mlpn_status[0x4];
6519 u8 local_port[0x8];
b4ff3a36 6520 u8 reserved_at_10[0x10];
e281682b
SM		 6521
6522 u8 e[0x1];
b4ff3a36 6523 u8 reserved_at_21[0x1f];
e281682b
SM		 6524};
6525
6526struct mlx5_ifc_pmlp_reg_bits {
6527 u8 rxtx[0x1];
b4ff3a36 6528 u8 reserved_at_1[0x7];
e281682b 6529 u8 local_port[0x8];
b4ff3a36 6530 u8 reserved_at_10[0x8];
e281682b
SM		 6531 u8 width[0x8];
6532
6533 u8 lane0_module_mapping[0x20];
6534
6535 u8 lane1_module_mapping[0x20];
6536
6537 u8 lane2_module_mapping[0x20];
6538
6539 u8 lane3_module_mapping[0x20];
6540
b4ff3a36 6541 u8 reserved_at_a0[0x160];
e281682b
SM		 6542};
6543
6544struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 6545 u8 reserved_at_0[0x8];
e281682b 6546 u8 module[0x8];
b4ff3a36 6547 u8 reserved_at_10[0x4];
e281682b 6548 u8 admin_status[0x4];
b4ff3a36 6549 u8 reserved_at_18[0x4];
e281682b
SM		 6550 u8 oper_status[0x4];
6551
6552 u8 ase[0x1];
6553 u8 ee[0x1];
b4ff3a36 6554 u8 reserved_at_22[0x1c];
e281682b
SM		 6555 u8 e[0x2];
6556
b4ff3a36 6557 u8 reserved_at_40[0x40];
e281682b
SM		 6558};
6559
6560struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 6561 u8 reserved_at_0[0x4];
e281682b 6562 u8 profile_id[0xc];
b4ff3a36 6563 u8 reserved_at_10[0x4];
e281682b 6564 u8 proto_mask[0x4];
b4ff3a36 6565 u8 reserved_at_18[0x8];
e281682b 6566
b4ff3a36 6567 u8 reserved_at_20[0x10];
e281682b
SM		 6568 u8 lane_speed[0x10];
6569
b4ff3a36 6570 u8 reserved_at_40[0x17];
e281682b
SM		 6571 u8 lpbf[0x1];
6572 u8 fec_mode_policy[0x8];
6573
6574 u8 retransmission_capability[0x8];
6575 u8 fec_mode_capability[0x18];
6576
6577 u8 retransmission_support_admin[0x8];
6578 u8 fec_mode_support_admin[0x18];
6579
6580 u8 retransmission_request_admin[0x8];
6581 u8 fec_mode_request_admin[0x18];
6582
b4ff3a36 6583 u8 reserved_at_c0[0x80];
e281682b
SM		 6584};
6585
6586struct mlx5_ifc_plib_reg_bits {
b4ff3a36 6587 u8 reserved_at_0[0x8];
e281682b 6588 u8 local_port[0x8];
b4ff3a36 6589 u8 reserved_at_10[0x8];
e281682b
SM		 6590 u8 ib_port[0x8];
6591
b4ff3a36 6592 u8 reserved_at_20[0x60];
e281682b
SM		 6593};
6594
6595struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 6596 u8 reserved_at_0[0x8];
e281682b 6597 u8 local_port[0x8];
b4ff3a36 6598 u8 reserved_at_10[0xd];
e281682b
SM		 6599 u8 lbf_mode[0x3];
6600
b4ff3a36 6601 u8 reserved_at_20[0x20];
e281682b
SM		 6602};
6603
6604struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 6605 u8 reserved_at_0[0x8];
e281682b 6606 u8 local_port[0x8];
b4ff3a36 6607 u8 reserved_at_10[0x10];
e281682b
SM		 6608
6609 u8 dic[0x1];
b4ff3a36 6610 u8 reserved_at_21[0x19];
e281682b 6611 u8 ipg[0x4];
b4ff3a36 6612 u8 reserved_at_3e[0x2];
e281682b
SM		 6613};
6614
6615struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 6616 u8 reserved_at_0[0x8];
e281682b 6617 u8 local_port[0x8];
b4ff3a36 6618 u8 reserved_at_10[0x10];
e281682b 6619
b4ff3a36 6620 u8 reserved_at_20[0xe0];
e281682b
SM		 6621
6622 u8 port_filter[8][0x20];
6623
6624 u8 port_filter_update_en[8][0x20];
6625};
6626
6627struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 6628 u8 reserved_at_0[0x8];
e281682b 6629 u8 local_port[0x8];
b4ff3a36 6630 u8 reserved_at_10[0x10];
e281682b
SM		 6631
6632 u8 ppan[0x4];
b4ff3a36 6633 u8 reserved_at_24[0x4];
e281682b 6634 u8 prio_mask_tx[0x8];
b4ff3a36 6635 u8 reserved_at_30[0x8];
e281682b
SM		 6636 u8 prio_mask_rx[0x8];
6637
6638 u8 pptx[0x1];
6639 u8 aptx[0x1];
b4ff3a36 6640 u8 reserved_at_42[0x6];
e281682b 6641 u8 pfctx[0x8];
b4ff3a36 6642 u8 reserved_at_50[0x10];
e281682b
SM		 6643
6644 u8 pprx[0x1];
6645 u8 aprx[0x1];
b4ff3a36 6646 u8 reserved_at_62[0x6];
e281682b 6647 u8 pfcrx[0x8];
b4ff3a36 6648 u8 reserved_at_70[0x10];
e281682b 6649
b4ff3a36 6650 u8 reserved_at_80[0x80];
e281682b
SM		 6651};
6652
6653struct mlx5_ifc_pelc_reg_bits {
6654 u8 op[0x4];
b4ff3a36 6655 u8 reserved_at_4[0x4];
e281682b 6656 u8 local_port[0x8];
b4ff3a36 6657 u8 reserved_at_10[0x10];
e281682b
SM		 6658
6659 u8 op_admin[0x8];
6660 u8 op_capability[0x8];
6661 u8 op_request[0x8];
6662 u8 op_active[0x8];
6663
6664 u8 admin[0x40];
6665
6666 u8 capability[0x40];
6667
6668 u8 request[0x40];
6669
6670 u8 active[0x40];
6671
b4ff3a36 6672 u8 reserved_at_140[0x80];
e281682b
SM		 6673};
6674
6675struct mlx5_ifc_peir_reg_bits {
b4ff3a36 6676 u8 reserved_at_0[0x8];
e281682b 6677 u8 local_port[0x8];
b4ff3a36 6678 u8 reserved_at_10[0x10];
e281682b 6679
b4ff3a36 6680 u8 reserved_at_20[0xc];
e281682b 6681 u8 error_count[0x4];
b4ff3a36 6682 u8 reserved_at_30[0x10];
e281682b 6683
b4ff3a36 6684 u8 reserved_at_40[0xc];
e281682b 6685 u8 lane[0x4];
b4ff3a36 6686 u8 reserved_at_50[0x8];
e281682b
SM		 6687 u8 error_type[0x8];
6688};
6689
6690struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 6691 u8 reserved_at_0[0x8];
e281682b 6692 u8 local_port[0x8];
b4ff3a36 6693 u8 reserved_at_10[0x10];
e281682b
SM		 6694
6695 u8 port_capability_mask[4][0x20];
6696};
6697
6698struct mlx5_ifc_paos_reg_bits {
6699 u8 swid[0x8];
6700 u8 local_port[0x8];
b4ff3a36 6701 u8 reserved_at_10[0x4];
e281682b 6702 u8 admin_status[0x4];
b4ff3a36 6703 u8 reserved_at_18[0x4];
e281682b
SM		 6704 u8 oper_status[0x4];
6705
6706 u8 ase[0x1];
6707 u8 ee[0x1];
b4ff3a36 6708 u8 reserved_at_22[0x1c];
e281682b
SM		 6709 u8 e[0x2];
6710
b4ff3a36 6711 u8 reserved_at_40[0x40];
e281682b
SM		 6712};
6713
6714struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 6715 u8 reserved_at_0[0x8];
e281682b 6716 u8 opamp_group[0x8];
b4ff3a36 6717 u8 reserved_at_10[0xc];
e281682b
SM		 6718 u8 opamp_group_type[0x4];
6719
6720 u8 start_index[0x10];
b4ff3a36 6721 u8 reserved_at_30[0x4];
e281682b
SM		 6722 u8 num_of_indices[0xc];
6723
6724 u8 index_data[18][0x10];
6725};
6726
6727struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 6728 u8 reserved_at_0[0x6];
e281682b 6729 u8 rx_lane[0x2];
b4ff3a36 6730 u8 reserved_at_8[0x6];
e281682b 6731 u8 tx_lane[0x2];
b4ff3a36 6732 u8 reserved_at_10[0x8];
e281682b
SM		 6733 u8 module[0x8];
6734};
6735
6736struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 6737 u8 reserved_at_0[0x6];
e281682b
SM		 6738 u8 lossy[0x1];
6739 u8 epsb[0x1];
b4ff3a36 6740 u8 reserved_at_8[0xc];
e281682b
SM		 6741 u8 size[0xc];
6742
6743 u8 xoff_threshold[0x10];
6744 u8 xon_threshold[0x10];
6745};
6746
6747struct mlx5_ifc_set_node_in_bits {
6748 u8 node_description[64][0x8];
6749};
6750
6751struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 6752 u8 reserved_at_0[0x18];
e281682b
SM		 6753 u8 power_settings_level[0x8];
6754
b4ff3a36 6755 u8 reserved_at_20[0x60];
e281682b
SM		 6756};
6757
6758struct mlx5_ifc_register_host_endianness_bits {
6759 u8 he[0x1];
b4ff3a36 6760 u8 reserved_at_1[0x1f];
e281682b 6761
b4ff3a36 6762 u8 reserved_at_20[0x60];
e281682b
SM		 6763};
6764
6765struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 6766 u8 reserved_at_0[0x20];
e281682b
SM		 6767
6768 u8 mkey[0x20];
6769
6770 u8 addressh_63_32[0x20];
6771
6772 u8 addressl_31_0[0x20];
6773};
6774
6775struct mlx5_ifc_ud_adrs_vector_bits {
6776 u8 dc_key[0x40];
6777
6778 u8 ext[0x1];
b4ff3a36 6779 u8 reserved_at_41[0x7];
e281682b
SM		 6780 u8 destination_qp_dct[0x18];
6781
6782 u8 static_rate[0x4];
6783 u8 sl_eth_prio[0x4];
6784 u8 fl[0x1];
6785 u8 mlid[0x7];
6786 u8 rlid_udp_sport[0x10];
6787
b4ff3a36 6788 u8 reserved_at_80[0x20];
e281682b
SM		 6789
6790 u8 rmac_47_16[0x20];
6791
6792 u8 rmac_15_0[0x10];
6793 u8 tclass[0x8];
6794 u8 hop_limit[0x8];
6795
b4ff3a36 6796 u8 reserved_at_e0[0x1];
e281682b 6797 u8 grh[0x1];
b4ff3a36 6798 u8 reserved_at_e2[0x2];
e281682b
SM		 6799 u8 src_addr_index[0x8];
6800 u8 flow_label[0x14];
6801
6802 u8 rgid_rip[16][0x8];
6803};
6804
6805struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 6806 u8 reserved_at_0[0x10];
e281682b
SM		 6807 u8 function_id[0x10];
6808
6809 u8 num_pages[0x20];
6810
b4ff3a36 6811 u8 reserved_at_40[0xa0];
e281682b
SM		 6812};
6813
6814struct mlx5_ifc_eqe_bits {
b4ff3a36 6815 u8 reserved_at_0[0x8];
e281682b 6816 u8 event_type[0x8];
b4ff3a36 6817 u8 reserved_at_10[0x8];
e281682b
SM		 6818 u8 event_sub_type[0x8];
6819
b4ff3a36 6820 u8 reserved_at_20[0xe0];
e281682b
SM		 6821
6822 union mlx5_ifc_event_auto_bits event_data;
6823
b4ff3a36 6824 u8 reserved_at_1e0[0x10];
e281682b 6825 u8 signature[0x8];
b4ff3a36 6826 u8 reserved_at_1f8[0x7];
e281682b
SM		 6827 u8 owner[0x1];
6828};
6829
6830enum {
6831 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
6832};
6833
6834struct mlx5_ifc_cmd_queue_entry_bits {
6835 u8 type[0x8];
b4ff3a36 6836 u8 reserved_at_8[0x18];
e281682b
SM		 6837
6838 u8 input_length[0x20];
6839
6840 u8 input_mailbox_pointer_63_32[0x20];
6841
6842 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 6843 u8 reserved_at_77[0x9];
e281682b
SM		 6844
6845 u8 command_input_inline_data[16][0x8];
6846
6847 u8 command_output_inline_data[16][0x8];
6848
6849 u8 output_mailbox_pointer_63_32[0x20];
6850
6851 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 6852 u8 reserved_at_1b7[0x9];
e281682b
SM		 6853
6854 u8 output_length[0x20];
6855
6856 u8 token[0x8];
6857 u8 signature[0x8];
b4ff3a36 6858 u8 reserved_at_1f0[0x8];
e281682b
SM		 6859 u8 status[0x7];
6860 u8 ownership[0x1];
6861};
6862
6863struct mlx5_ifc_cmd_out_bits {
6864 u8 status[0x8];
b4ff3a36 6865 u8 reserved_at_8[0x18];
e281682b
SM		 6866
6867 u8 syndrome[0x20];
6868
6869 u8 command_output[0x20];
6870};
6871
6872struct mlx5_ifc_cmd_in_bits {
6873 u8 opcode[0x10];
b4ff3a36 6874 u8 reserved_at_10[0x10];
e281682b 6875
b4ff3a36 6876 u8 reserved_at_20[0x10];
e281682b
SM		 6877 u8 op_mod[0x10];
6878
6879 u8 command[0][0x20];
6880};
6881
6882struct mlx5_ifc_cmd_if_box_bits {
6883 u8 mailbox_data[512][0x8];
6884
b4ff3a36 6885 u8 reserved_at_1000[0x180];
e281682b
SM		 6886
6887 u8 next_pointer_63_32[0x20];
6888
6889 u8 next_pointer_31_10[0x16];
b4ff3a36 6890 u8 reserved_at_11b6[0xa];
e281682b
SM		 6891
6892 u8 block_number[0x20];
6893
b4ff3a36 6894 u8 reserved_at_11e0[0x8];
e281682b
SM		 6895 u8 token[0x8];
6896 u8 ctrl_signature[0x8];
6897 u8 signature[0x8];
6898};
6899
6900struct mlx5_ifc_mtt_bits {
6901 u8 ptag_63_32[0x20];
6902
6903 u8 ptag_31_8[0x18];
b4ff3a36 6904 u8 reserved_at_38[0x6];
e281682b
SM		 6905 u8 wr_en[0x1];
6906 u8 rd_en[0x1];
6907};
6908
6909enum {
6910 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
6911 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
6912 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
6913};
6914
6915enum {
6916 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
6917 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
6918 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
6919};
6920
6921enum {
6922 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
6923 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
6924 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
6925 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
6926 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
6927 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
6928 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
6929 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
6930 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
6931 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
6932 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
6933};
6934
6935struct mlx5_ifc_initial_seg_bits {
6936 u8 fw_rev_minor[0x10];
6937 u8 fw_rev_major[0x10];
6938
6939 u8 cmd_interface_rev[0x10];
6940 u8 fw_rev_subminor[0x10];
6941
b4ff3a36 6942 u8 reserved_at_40[0x40];
e281682b
SM		 6943
6944 u8 cmdq_phy_addr_63_32[0x20];
6945
6946 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 6947 u8 reserved_at_b4[0x2];
e281682b
SM		 6948 u8 nic_interface[0x2];
6949 u8 log_cmdq_size[0x4];
6950 u8 log_cmdq_stride[0x4];
6951
6952 u8 command_doorbell_vector[0x20];
6953
b4ff3a36 6954 u8 reserved_at_e0[0xf00];
e281682b
SM		 6955
6956 u8 initializing[0x1];
b4ff3a36 6957 u8 reserved_at_fe1[0x4];
e281682b 6958 u8 nic_interface_supported[0x3];
b4ff3a36 6959 u8 reserved_at_fe8[0x18];
e281682b
SM		 6960
6961 struct mlx5_ifc_health_buffer_bits health_buffer;
6962
6963 u8 no_dram_nic_offset[0x20];
6964
b4ff3a36 6965 u8 reserved_at_1220[0x6e40];
e281682b 6966
b4ff3a36 6967 u8 reserved_at_8060[0x1f];
e281682b
SM		 6968 u8 clear_int[0x1];
6969
6970 u8 health_syndrome[0x8];
6971 u8 health_counter[0x18];
6972
b4ff3a36 6973 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 6974};
6975
6976union mlx5_ifc_ports_control_registers_document_bits {
6977 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
6978 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
6979 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
6980 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
6981 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
6982 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
6983 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
6984 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
6985 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
6986 struct mlx5_ifc_pamp_reg_bits pamp_reg;
6987 struct mlx5_ifc_paos_reg_bits paos_reg;
6988 struct mlx5_ifc_pcap_reg_bits pcap_reg;
6989 struct mlx5_ifc_peir_reg_bits peir_reg;
6990 struct mlx5_ifc_pelc_reg_bits pelc_reg;
6991 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 6992 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 6993 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
6994 struct mlx5_ifc_pifr_reg_bits pifr_reg;
6995 struct mlx5_ifc_pipg_reg_bits pipg_reg;
6996 struct mlx5_ifc_plbf_reg_bits plbf_reg;
6997 struct mlx5_ifc_plib_reg_bits plib_reg;
6998 struct mlx5_ifc_plpc_reg_bits plpc_reg;
6999 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7000 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7001 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7002 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7003 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7004 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7005 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7006 struct mlx5_ifc_ppad_reg_bits ppad_reg;
7007 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7008 struct mlx5_ifc_pplm_reg_bits pplm_reg;
7009 struct mlx5_ifc_pplr_reg_bits pplr_reg;
7010 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7011 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7012 struct mlx5_ifc_pspa_reg_bits pspa_reg;
7013 struct mlx5_ifc_ptas_reg_bits ptas_reg;
7014 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7015 struct mlx5_ifc_pude_reg_bits pude_reg;
7016 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7017 struct mlx5_ifc_slrg_reg_bits slrg_reg;
7018 struct mlx5_ifc_sltp_reg_bits sltp_reg;
b4ff3a36 7019 u8 reserved_at_0[0x60e0];
e281682b
SM		 7020};
7021
7022union mlx5_ifc_debug_enhancements_document_bits {
7023 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 7024 u8 reserved_at_0[0x200];
e281682b
SM		 7025};
7026
7027union mlx5_ifc_uplink_pci_interface_document_bits {
7028 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 7029 u8 reserved_at_0[0x20060];
b775516b
EC		 7030};
7031
2cc43b49
MG		 7032struct mlx5_ifc_set_flow_table_root_out_bits {
7033 u8 status[0x8];
b4ff3a36 7034 u8 reserved_at_8[0x18];
2cc43b49
MG		 7035
7036 u8 syndrome[0x20];
7037
b4ff3a36 7038 u8 reserved_at_40[0x40];
2cc43b49
MG		 7039};
7040
7041struct mlx5_ifc_set_flow_table_root_in_bits {
7042 u8 opcode[0x10];
b4ff3a36 7043 u8 reserved_at_10[0x10];
2cc43b49 7044
b4ff3a36 7045 u8 reserved_at_20[0x10];
2cc43b49
MG		 7046 u8 op_mod[0x10];
7047
b4ff3a36 7048 u8 reserved_at_40[0x40];
2cc43b49
MG		 7049
7050 u8 table_type[0x8];
b4ff3a36 7051 u8 reserved_at_88[0x18];
2cc43b49 7052
b4ff3a36 7053 u8 reserved_at_a0[0x8];
2cc43b49
MG		 7054 u8 table_id[0x18];
7055
b4ff3a36 7056 u8 reserved_at_c0[0x140];
2cc43b49
MG		 7057};
7058
34a40e68
MG		 7059enum {
7060 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
7061};
7062
7063struct mlx5_ifc_modify_flow_table_out_bits {
7064 u8 status[0x8];
b4ff3a36 7065 u8 reserved_at_8[0x18];
34a40e68
MG		 7066
7067 u8 syndrome[0x20];
7068
b4ff3a36 7069 u8 reserved_at_40[0x40];
34a40e68
MG		 7070};
7071
7072struct mlx5_ifc_modify_flow_table_in_bits {
7073 u8 opcode[0x10];
b4ff3a36 7074 u8 reserved_at_10[0x10];
34a40e68 7075
b4ff3a36 7076 u8 reserved_at_20[0x10];
34a40e68
MG		 7077 u8 op_mod[0x10];
7078
b4ff3a36 7079 u8 reserved_at_40[0x20];
34a40e68 7080
b4ff3a36 7081 u8 reserved_at_60[0x10];
34a40e68
MG		 7082 u8 modify_field_select[0x10];
7083
7084 u8 table_type[0x8];
b4ff3a36 7085 u8 reserved_at_88[0x18];
34a40e68 7086
b4ff3a36 7087 u8 reserved_at_a0[0x8];
34a40e68
MG		 7088 u8 table_id[0x18];
7089
b4ff3a36 7090 u8 reserved_at_c0[0x4];
34a40e68 7091 u8 table_miss_mode[0x4];
b4ff3a36 7092 u8 reserved_at_c8[0x18];
34a40e68 7093
b4ff3a36 7094 u8 reserved_at_e0[0x8];
34a40e68
MG		 7095 u8 table_miss_id[0x18];
7096
b4ff3a36 7097 u8 reserved_at_100[0x100];
34a40e68
MG		 7098};
7099
d29b796a 7100#endif /* MLX5_IFC_H */
Linux 6.x block layer and io_uring tree(s)