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net/mlx5e: Add ethtool support for interface identify (LED blinking)
[linux-2.6-block.git] / include / linux / mlx5 / driver.h
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e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DRIVER_H
34#define MLX5_DRIVER_H
35
36#include <linux/kernel.h>
37#include <linux/completion.h>
38#include <linux/pci.h>
39#include <linux/spinlock_types.h>
40#include <linux/semaphore.h>
6ecde51d 41#include <linux/slab.h>
e126ba97
EC		 42#include <linux/vmalloc.h>
43#include <linux/radix-tree.h>
6ecde51d 44
e126ba97
EC		 45#include <linux/mlx5/device.h>
46#include <linux/mlx5/doorbell.h>
47
48enum {
49 MLX5_BOARD_ID_LEN = 64,
50 MLX5_MAX_NAME_LEN = 16,
51};
52
53enum {
54 /* one minute for the sake of bringup. Generally, commands must always
55 * complete and we may need to increase this timeout value
56 */
6b6c07bd 57 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000,
e126ba97
EC		 58 MLX5_CMD_WQ_MAX_NAME = 32,
59};
60
61enum {
62 CMD_OWNER_SW = 0x0,
63 CMD_OWNER_HW = 0x1,
64 CMD_STATUS_SUCCESS = 0,
65};
66
67enum mlx5_sqp_t {
68 MLX5_SQP_SMI = 0,
69 MLX5_SQP_GSI = 1,
70 MLX5_SQP_IEEE_1588 = 2,
71 MLX5_SQP_SNIFFER = 3,
72 MLX5_SQP_SYNC_UMR = 4,
73};
74
75enum {
76 MLX5_MAX_PORTS = 2,
77};
78
79enum {
80 MLX5_EQ_VEC_PAGES = 0,
81 MLX5_EQ_VEC_CMD = 1,
82 MLX5_EQ_VEC_ASYNC = 2,
83 MLX5_EQ_VEC_COMP_BASE,
84};
85
86enum {
db058a18 87 MLX5_MAX_IRQ_NAME = 32
e126ba97
EC		 88};
89
90enum {
91 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
92 MLX5_ATOMIC_MODE_CX = 2 << 16,
93 MLX5_ATOMIC_MODE_8B = 3 << 16,
94 MLX5_ATOMIC_MODE_16B = 4 << 16,
95 MLX5_ATOMIC_MODE_32B = 5 << 16,
96 MLX5_ATOMIC_MODE_64B = 6 << 16,
97 MLX5_ATOMIC_MODE_128B = 7 << 16,
98 MLX5_ATOMIC_MODE_256B = 8 << 16,
99};
100
e126ba97 101enum {
4f3961ee
SM		 102 MLX5_REG_QETCR = 0x4005,
103 MLX5_REG_QTCT = 0x400a,
e126ba97
EC		 104 MLX5_REG_PCAP = 0x5001,
105 MLX5_REG_PMTU = 0x5003,
106 MLX5_REG_PTYS = 0x5004,
107 MLX5_REG_PAOS = 0x5006,
3c2d18ef 108 MLX5_REG_PFCC = 0x5007,
efea389d 109 MLX5_REG_PPCNT = 0x5008,
e126ba97
EC		 110 MLX5_REG_PMAOS = 0x5012,
111 MLX5_REG_PUDE = 0x5009,
112 MLX5_REG_PMPE = 0x5010,
113 MLX5_REG_PELC = 0x500e,
a124d13e 114 MLX5_REG_PVLC = 0x500f,
94cb1ebb 115 MLX5_REG_PCMR = 0x5041,
e126ba97
EC		 116 MLX5_REG_PMLP = 0, /* TBD */
117 MLX5_REG_NODE_DESC = 0x6001,
118 MLX5_REG_HOST_ENDIANNESS = 0x7004,
da54d24e 119 MLX5_REG_MLCR = 0x902b,
e126ba97
EC		 120};
121
da7525d2
EBE		 122enum {
123 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
124 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
125};
126
e420f0c0
HE		 127enum mlx5_page_fault_resume_flags {
128 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
129 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
130 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
131 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
132};
133
e126ba97
EC		 134enum dbg_rsc_type {
135 MLX5_DBG_RSC_QP,
136 MLX5_DBG_RSC_EQ,
137 MLX5_DBG_RSC_CQ,
138};
139
140struct mlx5_field_desc {
141 struct dentry *dent;
142 int i;
143};
144
145struct mlx5_rsc_debug {
146 struct mlx5_core_dev *dev;
147 void *object;
148 enum dbg_rsc_type type;
149 struct dentry *root;
150 struct mlx5_field_desc fields[0];
151};
152
153enum mlx5_dev_event {
154 MLX5_DEV_EVENT_SYS_ERROR,
155 MLX5_DEV_EVENT_PORT_UP,
156 MLX5_DEV_EVENT_PORT_DOWN,
157 MLX5_DEV_EVENT_PORT_INITIALIZED,
158 MLX5_DEV_EVENT_LID_CHANGE,
159 MLX5_DEV_EVENT_PKEY_CHANGE,
160 MLX5_DEV_EVENT_GUID_CHANGE,
161 MLX5_DEV_EVENT_CLIENT_REREG,
162};
163
4c916a79 164enum mlx5_port_status {
6fa1bcab
AS		 165 MLX5_PORT_UP = 1,
166 MLX5_PORT_DOWN = 2,
4c916a79
RS		 167};
168
e126ba97
EC		 169struct mlx5_uuar_info {
170 struct mlx5_uar *uars;
171 int num_uars;
172 int num_low_latency_uuars;
173 unsigned long *bitmap;
174 unsigned int *count;
175 struct mlx5_bf *bfs;
176
177 /*
178 * protect uuar allocation data structs
179 */
180 struct mutex lock;
78c0f98c 181 u32 ver;
e126ba97
EC		 182};
183
184struct mlx5_bf {
185 void __iomem *reg;
186 void __iomem *regreg;
187 int buf_size;
188 struct mlx5_uar *uar;
189 unsigned long offset;
190 int need_lock;
191 /* protect blue flame buffer selection when needed
192 */
193 spinlock_t lock;
194
195 /* serialize 64 bit writes when done as two 32 bit accesses
196 */
197 spinlock_t lock32;
198 int uuarn;
199};
200
201struct mlx5_cmd_first {
202 __be32 data[4];
203};
204
205struct mlx5_cmd_msg {
206 struct list_head list;
207 struct cache_ent *cache;
208 u32 len;
209 struct mlx5_cmd_first first;
210 struct mlx5_cmd_mailbox *next;
211};
212
213struct mlx5_cmd_debug {
214 struct dentry *dbg_root;
215 struct dentry *dbg_in;
216 struct dentry *dbg_out;
217 struct dentry *dbg_outlen;
218 struct dentry *dbg_status;
219 struct dentry *dbg_run;
220 void *in_msg;
221 void *out_msg;
222 u8 status;
223 u16 inlen;
224 u16 outlen;
225};
226
227struct cache_ent {
228 /* protect block chain allocations
229 */
230 spinlock_t lock;
231 struct list_head head;
232};
233
234struct cmd_msg_cache {
235 struct cache_ent large;
236 struct cache_ent med;
237
238};
239
240struct mlx5_cmd_stats {
241 u64 sum;
242 u64 n;
243 struct dentry *root;
244 struct dentry *avg;
245 struct dentry *count;
246 /* protect command average calculations */
247 spinlock_t lock;
248};
249
250struct mlx5_cmd {
64599cca
EC		 251 void *cmd_alloc_buf;
252 dma_addr_t alloc_dma;
253 int alloc_size;
e126ba97
EC		 254 void *cmd_buf;
255 dma_addr_t dma;
256 u16 cmdif_rev;
257 u8 log_sz;
258 u8 log_stride;
259 int max_reg_cmds;
260 int events;
261 u32 __iomem *vector;
262
263 /* protect command queue allocations
264 */
265 spinlock_t alloc_lock;
266
267 /* protect token allocations
268 */
269 spinlock_t token_lock;
270 u8 token;
271 unsigned long bitmask;
272 char wq_name[MLX5_CMD_WQ_MAX_NAME];
273 struct workqueue_struct *wq;
274 struct semaphore sem;
275 struct semaphore pages_sem;
276 int mode;
277 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
278 struct pci_pool *pool;
279 struct mlx5_cmd_debug dbg;
280 struct cmd_msg_cache cache;
281 int checksum_disabled;
282 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
283};
284
285struct mlx5_port_caps {
286 int gid_table_len;
287 int pkey_table_len;
938fe83c 288 u8 ext_port_cap;
e126ba97
EC		 289};
290
291struct mlx5_cmd_mailbox {
292 void *buf;
293 dma_addr_t dma;
294 struct mlx5_cmd_mailbox *next;
295};
296
297struct mlx5_buf_list {
298 void *buf;
299 dma_addr_t map;
300};
301
302struct mlx5_buf {
303 struct mlx5_buf_list direct;
e126ba97 304 int npages;
e126ba97 305 int size;
f241e749 306 u8 page_shift;
e126ba97
EC		 307};
308
309struct mlx5_eq {
310 struct mlx5_core_dev *dev;
311 __be32 __iomem *doorbell;
312 u32 cons_index;
313 struct mlx5_buf buf;
314 int size;
0b6e26ce 315 unsigned int irqn;
e126ba97
EC		 316 u8 eqn;
317 int nent;
318 u64 mask;
e126ba97
EC		 319 struct list_head list;
320 int index;
321 struct mlx5_rsc_debug *dbg;
322};
323
3121e3c4
SG		 324struct mlx5_core_psv {
325 u32 psv_idx;
326 struct psv_layout {
327 u32 pd;
328 u16 syndrome;
329 u16 reserved;
330 u16 bg;
331 u16 app_tag;
332 u32 ref_tag;
333 } psv;
334};
335
336struct mlx5_core_sig_ctx {
337 struct mlx5_core_psv psv_memory;
338 struct mlx5_core_psv psv_wire;
d5436ba0
SG		 339 struct ib_sig_err err_item;
340 bool sig_status_checked;
341 bool sig_err_exists;
342 u32 sigerr_count;
3121e3c4 343};
e126ba97 344
a606b0f6 345struct mlx5_core_mkey {
e126ba97
EC		 346 u64 iova;
347 u64 size;
348 u32 key;
349 u32 pd;
e126ba97
EC		 350};
351
5903325a 352enum mlx5_res_type {
e2013b21 353 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
354 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
355 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
356 MLX5_RES_SRQ = 3,
357 MLX5_RES_XSRQ = 4,
5903325a
EC		 358};
359
360struct mlx5_core_rsc_common {
361 enum mlx5_res_type res;
362 atomic_t refcount;
363 struct completion free;
364};
365
e126ba97 366struct mlx5_core_srq {
01949d01 367 struct mlx5_core_rsc_common common; /* must be first */
e126ba97
EC		 368 u32 srqn;
369 int max;
370 int max_gs;
371 int max_avail_gather;
372 int wqe_shift;
373 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
374
375 atomic_t refcount;
376 struct completion free;
377};
378
379struct mlx5_eq_table {
380 void __iomem *update_ci;
381 void __iomem *update_arm_ci;
233d05d2 382 struct list_head comp_eqs_list;
e126ba97
EC		 383 struct mlx5_eq pages_eq;
384 struct mlx5_eq async_eq;
385 struct mlx5_eq cmd_eq;
e126ba97
EC		 386 int num_comp_vectors;
387 /* protect EQs list
388 */
389 spinlock_t lock;
390};
391
392struct mlx5_uar {
393 u32 index;
394 struct list_head bf_list;
395 unsigned free_bf_bmap;
88a85f99 396 void __iomem *bf_map;
e126ba97
EC		 397 void __iomem *map;
398};
399
400
401struct mlx5_core_health {
402 struct health_buffer __iomem *health;
403 __be32 __iomem *health_counter;
404 struct timer_list timer;
e126ba97
EC		 405 u32 prev;
406 int miss_counter;
fd76ee4d 407 bool sick;
ac6ea6e8
EC		 408 struct workqueue_struct *wq;
409 struct work_struct work;
e126ba97
EC		 410};
411
412struct mlx5_cq_table {
413 /* protect radix tree
414 */
415 spinlock_t lock;
416 struct radix_tree_root tree;
417};
418
419struct mlx5_qp_table {
420 /* protect radix tree
421 */
422 spinlock_t lock;
423 struct radix_tree_root tree;
424};
425
426struct mlx5_srq_table {
427 /* protect radix tree
428 */
429 spinlock_t lock;
430 struct radix_tree_root tree;
431};
432
a606b0f6 433struct mlx5_mkey_table {
3bcdb17a
SG		 434 /* protect radix tree
435 */
436 rwlock_t lock;
437 struct radix_tree_root tree;
438};
439
fc50db98
EC		 440struct mlx5_vf_context {
441 int enabled;
442};
443
444struct mlx5_core_sriov {
445 struct mlx5_vf_context *vfs_ctx;
446 int num_vfs;
447 int enabled_vfs;
448};
449
db058a18
SM		 450struct mlx5_irq_info {
451 cpumask_var_t mask;
452 char name[MLX5_MAX_IRQ_NAME];
453};
454
073bb189
SM		 455struct mlx5_eswitch;
456
e126ba97
EC		 457struct mlx5_priv {
458 char name[MLX5_MAX_NAME_LEN];
459 struct mlx5_eq_table eq_table;
db058a18
SM		 460 struct msix_entry *msix_arr;
461 struct mlx5_irq_info *irq_info;
e126ba97
EC		 462 struct mlx5_uuar_info uuari;
463 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
464
465 /* pages stuff */
466 struct workqueue_struct *pg_wq;
467 struct rb_root page_root;
468 int fw_pages;
6aec21f6 469 atomic_t reg_pages;
bf0bf77f 470 struct list_head free_list;
fc50db98 471 int vfs_pages;
e126ba97
EC		 472
473 struct mlx5_core_health health;
474
475 struct mlx5_srq_table srq_table;
476
477 /* start: qp staff */
478 struct mlx5_qp_table qp_table;
479 struct dentry *qp_debugfs;
480 struct dentry *eq_debugfs;
481 struct dentry *cq_debugfs;
482 struct dentry *cmdif_debugfs;
483 /* end: qp staff */
484
485 /* start: cq staff */
486 struct mlx5_cq_table cq_table;
487 /* end: cq staff */
488
a606b0f6
MB		 489 /* start: mkey staff */
490 struct mlx5_mkey_table mkey_table;
491 /* end: mkey staff */
3bcdb17a 492
e126ba97 493 /* start: alloc staff */
311c7c71
SM		 494 /* protect buffer alocation according to numa node */
495 struct mutex alloc_mutex;
496 int numa_node;
497
e126ba97
EC		 498 struct mutex pgdir_mutex;
499 struct list_head pgdir_list;
500 /* end: alloc staff */
501 struct dentry *dbg_root;
502
503 /* protect mkey key part */
504 spinlock_t mkey_lock;
505 u8 mkey_key;
9603b61d
JM		 506
507 struct list_head dev_list;
508 struct list_head ctx_list;
509 spinlock_t ctx_lock;
073bb189
SM		 510
511 struct mlx5_eswitch *eswitch;
fc50db98
EC		 512 struct mlx5_core_sriov sriov;
513 unsigned long pci_dev_data;
25302363
MG		 514 struct mlx5_flow_root_namespace *root_ns;
515 struct mlx5_flow_root_namespace *fdb_root_ns;
e126ba97
EC		 516};
517
89d44f0a
MD		 518enum mlx5_device_state {
519 MLX5_DEVICE_STATE_UP,
520 MLX5_DEVICE_STATE_INTERNAL_ERROR,
521};
522
523enum mlx5_interface_state {
524 MLX5_INTERFACE_STATE_DOWN,
525 MLX5_INTERFACE_STATE_UP,
526};
527
528enum mlx5_pci_status {
529 MLX5_PCI_STATUS_DISABLED,
530 MLX5_PCI_STATUS_ENABLED,
531};
532
e126ba97
EC		 533struct mlx5_core_dev {
534 struct pci_dev *pdev;
89d44f0a
MD		 535 /* sync pci state */
536 struct mutex pci_status_mutex;
537 enum mlx5_pci_status pci_status;
e126ba97
EC		 538 u8 rev_id;
539 char board_id[MLX5_BOARD_ID_LEN];
540 struct mlx5_cmd cmd;
938fe83c
SM		 541 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
542 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
543 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
e126ba97
EC		 544 phys_addr_t iseg_base;
545 struct mlx5_init_seg __iomem *iseg;
89d44f0a
MD		 546 enum mlx5_device_state state;
547 /* sync interface state */
548 struct mutex intf_state_mutex;
549 enum mlx5_interface_state interface_state;
e126ba97
EC		 550 void (*event) (struct mlx5_core_dev *dev,
551 enum mlx5_dev_event event,
4d2f9bbb 552 unsigned long param);
e126ba97
EC		 553 struct mlx5_priv priv;
554 struct mlx5_profile *profile;
555 atomic_t num_qps;
f62b8bb8 556 u32 issi;
e126ba97
EC		 557};
558
559struct mlx5_db {
560 __be32 *db;
561 union {
562 struct mlx5_db_pgdir *pgdir;
563 struct mlx5_ib_user_db_page *user_page;
564 } u;
565 dma_addr_t dma;
566 int index;
567};
568
569enum {
570 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES,
571};
572
573enum {
574 MLX5_COMP_EQ_SIZE = 1024,
575};
576
adb0c954
SM		 577enum {
578 MLX5_PTYS_IB = 1 << 0,
579 MLX5_PTYS_EN = 1 << 2,
580};
581
e126ba97
EC		 582struct mlx5_db_pgdir {
583 struct list_head list;
584 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
585 __be32 *db_page;
586 dma_addr_t db_dma;
587};
588
589typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
590
591struct mlx5_cmd_work_ent {
592 struct mlx5_cmd_msg *in;
593 struct mlx5_cmd_msg *out;
746b5583
EC		 594 void *uout;
595 int uout_size;
e126ba97
EC		 596 mlx5_cmd_cbk_t callback;
597 void *context;
746b5583 598 int idx;
e126ba97
EC		 599 struct completion done;
600 struct mlx5_cmd *cmd;
601 struct work_struct work;
602 struct mlx5_cmd_layout *lay;
603 int ret;
604 int page_queue;
605 u8 status;
606 u8 token;
14a70046
TG		 607 u64 ts1;
608 u64 ts2;
746b5583 609 u16 op;
e126ba97
EC		 610};
611
612struct mlx5_pas {
613 u64 pa;
614 u8 log_sz;
615};
616
707c4602 617enum port_state_policy {
eff901d3
EC		 618 MLX5_POLICY_DOWN = 0,
619 MLX5_POLICY_UP = 1,
620 MLX5_POLICY_FOLLOW = 2,
621 MLX5_POLICY_INVALID = 0xffffffff
707c4602
MD		 622};
623
624enum phy_port_state {
625 MLX5_AAA_111
626};
627
628struct mlx5_hca_vport_context {
629 u32 field_select;
630 bool sm_virt_aware;
631 bool has_smi;
632 bool has_raw;
633 enum port_state_policy policy;
634 enum phy_port_state phys_state;
635 enum ib_port_state vport_state;
636 u8 port_physical_state;
637 u64 sys_image_guid;
638 u64 port_guid;
639 u64 node_guid;
640 u32 cap_mask1;
641 u32 cap_mask1_perm;
642 u32 cap_mask2;
643 u32 cap_mask2_perm;
644 u16 lid;
645 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
646 u8 lmc;
647 u8 subnet_timeout;
648 u16 sm_lid;
649 u8 sm_sl;
650 u16 qkey_violation_counter;
651 u16 pkey_violation_counter;
652 bool grh_required;
653};
654
e126ba97
EC		 655static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
656{
e126ba97 657 return buf->direct.buf + offset;
e126ba97
EC		 658}
659
660extern struct workqueue_struct *mlx5_core_wq;
661
662#define STRUCT_FIELD(header, field) \
663 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
664 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
665
e126ba97
EC		 666static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
667{
668 return pci_get_drvdata(pdev);
669}
670
671extern struct dentry *mlx5_debugfs_root;
672
673static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
674{
675 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
676}
677
678static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
679{
680 return ioread32be(&dev->iseg->fw_rev) >> 16;
681}
682
683static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
684{
685 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
686}
687
688static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
689{
690 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
691}
692
693static inline void *mlx5_vzalloc(unsigned long size)
694{
695 void *rtn;
696
697 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
698 if (!rtn)
699 rtn = vzalloc(size);
700 return rtn;
701}
702
3bcdb17a
SG		 703static inline u32 mlx5_base_mkey(const u32 key)
704{
705 return key & 0xffffff00u;
706}
707
e126ba97
EC		 708int mlx5_cmd_init(struct mlx5_core_dev *dev);
709void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
710void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
711void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
712int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
b775516b 713int mlx5_cmd_status_to_err_v2(void *ptr);
b06e7de8 714int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
e126ba97
EC		 715int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
716 int out_size);
746b5583
EC		 717int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
718 void *out, int out_size, mlx5_cmd_cbk_t callback,
719 void *context);
e126ba97
EC		 720int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
721int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
722int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
723int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
0ba42241
ML		 724int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar,
725 bool map_wc);
e281682b 726void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
ac6ea6e8
EC		 727void mlx5_health_cleanup(struct mlx5_core_dev *dev);
728int mlx5_health_init(struct mlx5_core_dev *dev);
e126ba97
EC		 729void mlx5_start_health_poll(struct mlx5_core_dev *dev);
730void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
311c7c71
SM		 731int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
732 struct mlx5_buf *buf, int node);
64ffaa21 733int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
e126ba97
EC		 734void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
735struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
736 gfp_t flags, int npages);
737void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
738 struct mlx5_cmd_mailbox *head);
739int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
01949d01
HA		 740 struct mlx5_create_srq_mbox_in *in, int inlen,
741 int is_xrc);
e126ba97
EC		 742int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
743int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
744 struct mlx5_query_srq_mbox_out *out);
745int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
746 u16 lwm, int is_srq);
a606b0f6
MB		 747void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
748void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
749int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
750 struct mlx5_core_mkey *mkey,
746b5583
EC		 751 struct mlx5_create_mkey_mbox_in *in, int inlen,
752 mlx5_cmd_cbk_t callback, void *context,
753 struct mlx5_create_mkey_mbox_out *out);
a606b0f6
MB		 754int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
755 struct mlx5_core_mkey *mkey);
756int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
e126ba97 757 struct mlx5_query_mkey_mbox_out *out, int outlen);
a606b0f6 758int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey,
e126ba97
EC		 759 u32 *mkey);
760int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
761int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
a97e2d86 762int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
f241e749 763 u16 opmod, u8 port);
e126ba97
EC		 764void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
765void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
766int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
767void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
fc50db98
EC		 768int mlx5_sriov_init(struct mlx5_core_dev *dev);
769int mlx5_sriov_cleanup(struct mlx5_core_dev *dev);
e126ba97 770void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
0a324f31 771 s32 npages);
cd23b14b 772int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
e126ba97
EC		 773int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
774void mlx5_register_debugfs(void);
775void mlx5_unregister_debugfs(void);
776int mlx5_eq_init(struct mlx5_core_dev *dev);
777void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
778void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
779void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
5903325a 780void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
e420f0c0
HE		 781#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
782void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
783#endif
e126ba97
EC		 784void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
785struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
020446e0 786void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec);
e126ba97
EC		 787void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
788int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
789 int nent, u64 mask, const char *name, struct mlx5_uar *uar);
790int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
791int mlx5_start_eqs(struct mlx5_core_dev *dev);
792int mlx5_stop_eqs(struct mlx5_core_dev *dev);
0b6e26ce
DT		 793int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
794 unsigned int *irqn);
e126ba97
EC		 795int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
796int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
797
798int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
799void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
800int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
801 int size_in, void *data_out, int size_out,
802 u16 reg_num, int arg, int write);
adb0c954 803
e126ba97
EC		 804int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
805void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
806int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
807 struct mlx5_query_eq_mbox_out *out, int outlen);
808int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
809void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
810int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
811void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
812int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
311c7c71
SM		 813int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
814 int node);
e126ba97
EC		 815void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
816
e126ba97
EC		 817const char *mlx5_command_str(int command);
818int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
819void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
3121e3c4
SG		 820int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
821 int npsvs, u32 *sig_index);
822int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
5903325a 823void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
e420f0c0
HE		 824int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
825 struct mlx5_odp_caps *odp_caps);
1c64bf6f
MY		 826int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
827 u8 port_num, void *out, size_t sz);
e126ba97 828
e3297246
EC		 829static inline int fw_initializing(struct mlx5_core_dev *dev)
830{
831 return ioread32be(&dev->iseg->initializing) >> 31;
832}
833
e126ba97
EC		 834static inline u32 mlx5_mkey_to_idx(u32 mkey)
835{
836 return mkey >> 8;
837}
838
839static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
840{
841 return mkey_idx << 8;
842}
843
746b5583
EC		 844static inline u8 mlx5_mkey_variant(u32 mkey)
845{
846 return mkey & 0xff;
847}
848
e126ba97
EC		 849enum {
850 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
c1868b82 851 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
e126ba97
EC		 852};
853
854enum {
855 MAX_MR_CACHE_ENTRIES = 16,
856};
857
64613d94
SM		 858enum {
859 MLX5_INTERFACE_PROTOCOL_IB = 0,
860 MLX5_INTERFACE_PROTOCOL_ETH = 1,
861};
862
9603b61d
JM		 863struct mlx5_interface {
864 void * (*add)(struct mlx5_core_dev *dev);
865 void (*remove)(struct mlx5_core_dev *dev, void *context);
866 void (*event)(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 867 enum mlx5_dev_event event, unsigned long param);
64613d94
SM		 868 void * (*get_dev)(void *context);
869 int protocol;
9603b61d
JM		 870 struct list_head list;
871};
872
64613d94 873void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
9603b61d
JM		 874int mlx5_register_interface(struct mlx5_interface *intf);
875void mlx5_unregister_interface(struct mlx5_interface *intf);
211e6c80 876int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
9603b61d 877
e126ba97
EC		 878struct mlx5_profile {
879 u64 mask;
f241e749 880 u8 log_max_qp;
e126ba97
EC		 881 struct {
882 int size;
883 int limit;
884 } mr_cache[MAX_MR_CACHE_ENTRIES];
885};
886
fc50db98
EC		 887enum {
888 MLX5_PCI_DEV_IS_VF = 1 << 0,
889};
890
891static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
892{
893 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
894}
895
707c4602
MD		 896static inline int mlx5_get_gid_table_len(u16 param)
897{
898 if (param > 4) {
899 pr_warn("gid table length is zero\n");
900 return 0;
901 }
902
903 return 8 * (1 << param);
904}
905
020446e0
EC		 906enum {
907 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
908};
909
e126ba97 910#endif /* MLX5_DRIVER_H */
Linux 6.x block layer and io_uring tree(s)