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net/mlx5e: HW LRO changes/fixes
[linux-2.6-block.git] / include / linux / mlx5 / driver.h
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DRIVER_H
34#define MLX5_DRIVER_H
35
36#include <linux/kernel.h>
37#include <linux/completion.h>
38#include <linux/pci.h>
39#include <linux/spinlock_types.h>
40#include <linux/semaphore.h>
6ecde51d 41#include <linux/slab.h>
e126ba97
EC		 42#include <linux/vmalloc.h>
43#include <linux/radix-tree.h>
6ecde51d 44
e126ba97
EC		 45#include <linux/mlx5/device.h>
46#include <linux/mlx5/doorbell.h>
47
48enum {
49 MLX5_BOARD_ID_LEN = 64,
50 MLX5_MAX_NAME_LEN = 16,
51};
52
53enum {
54 /* one minute for the sake of bringup. Generally, commands must always
55 * complete and we may need to increase this timeout value
56 */
57 MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000,
58 MLX5_CMD_WQ_MAX_NAME = 32,
59};
60
61enum {
62 CMD_OWNER_SW = 0x0,
63 CMD_OWNER_HW = 0x1,
64 CMD_STATUS_SUCCESS = 0,
65};
66
67enum mlx5_sqp_t {
68 MLX5_SQP_SMI = 0,
69 MLX5_SQP_GSI = 1,
70 MLX5_SQP_IEEE_1588 = 2,
71 MLX5_SQP_SNIFFER = 3,
72 MLX5_SQP_SYNC_UMR = 4,
73};
74
75enum {
76 MLX5_MAX_PORTS = 2,
77};
78
79enum {
80 MLX5_EQ_VEC_PAGES = 0,
81 MLX5_EQ_VEC_CMD = 1,
82 MLX5_EQ_VEC_ASYNC = 2,
83 MLX5_EQ_VEC_COMP_BASE,
84};
85
86enum {
db058a18 87 MLX5_MAX_IRQ_NAME = 32
e126ba97
EC		 88};
89
90enum {
91 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
92 MLX5_ATOMIC_MODE_CX = 2 << 16,
93 MLX5_ATOMIC_MODE_8B = 3 << 16,
94 MLX5_ATOMIC_MODE_16B = 4 << 16,
95 MLX5_ATOMIC_MODE_32B = 5 << 16,
96 MLX5_ATOMIC_MODE_64B = 6 << 16,
97 MLX5_ATOMIC_MODE_128B = 7 << 16,
98 MLX5_ATOMIC_MODE_256B = 8 << 16,
99};
100
e126ba97
EC		 101enum {
102 MLX5_REG_PCAP = 0x5001,
103 MLX5_REG_PMTU = 0x5003,
104 MLX5_REG_PTYS = 0x5004,
105 MLX5_REG_PAOS = 0x5006,
efea389d 106 MLX5_REG_PPCNT = 0x5008,
e126ba97
EC		 107 MLX5_REG_PMAOS = 0x5012,
108 MLX5_REG_PUDE = 0x5009,
109 MLX5_REG_PMPE = 0x5010,
110 MLX5_REG_PELC = 0x500e,
a124d13e 111 MLX5_REG_PVLC = 0x500f,
e126ba97
EC		 112 MLX5_REG_PMLP = 0, /* TBD */
113 MLX5_REG_NODE_DESC = 0x6001,
114 MLX5_REG_HOST_ENDIANNESS = 0x7004,
115};
116
e420f0c0
HE		 117enum mlx5_page_fault_resume_flags {
118 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
119 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
120 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
121 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
122};
123
e126ba97
EC		 124enum dbg_rsc_type {
125 MLX5_DBG_RSC_QP,
126 MLX5_DBG_RSC_EQ,
127 MLX5_DBG_RSC_CQ,
128};
129
130struct mlx5_field_desc {
131 struct dentry *dent;
132 int i;
133};
134
135struct mlx5_rsc_debug {
136 struct mlx5_core_dev *dev;
137 void *object;
138 enum dbg_rsc_type type;
139 struct dentry *root;
140 struct mlx5_field_desc fields[0];
141};
142
143enum mlx5_dev_event {
144 MLX5_DEV_EVENT_SYS_ERROR,
145 MLX5_DEV_EVENT_PORT_UP,
146 MLX5_DEV_EVENT_PORT_DOWN,
147 MLX5_DEV_EVENT_PORT_INITIALIZED,
148 MLX5_DEV_EVENT_LID_CHANGE,
149 MLX5_DEV_EVENT_PKEY_CHANGE,
150 MLX5_DEV_EVENT_GUID_CHANGE,
151 MLX5_DEV_EVENT_CLIENT_REREG,
152};
153
4c916a79
RS		 154enum mlx5_port_status {
155 MLX5_PORT_UP = 1 << 1,
156 MLX5_PORT_DOWN = 1 << 2,
157};
158
e126ba97
EC		 159struct mlx5_uuar_info {
160 struct mlx5_uar *uars;
161 int num_uars;
162 int num_low_latency_uuars;
163 unsigned long *bitmap;
164 unsigned int *count;
165 struct mlx5_bf *bfs;
166
167 /*
168 * protect uuar allocation data structs
169 */
170 struct mutex lock;
78c0f98c 171 u32 ver;
e126ba97
EC		 172};
173
174struct mlx5_bf {
175 void __iomem *reg;
176 void __iomem *regreg;
177 int buf_size;
178 struct mlx5_uar *uar;
179 unsigned long offset;
180 int need_lock;
181 /* protect blue flame buffer selection when needed
182 */
183 spinlock_t lock;
184
185 /* serialize 64 bit writes when done as two 32 bit accesses
186 */
187 spinlock_t lock32;
188 int uuarn;
189};
190
191struct mlx5_cmd_first {
192 __be32 data[4];
193};
194
195struct mlx5_cmd_msg {
196 struct list_head list;
197 struct cache_ent *cache;
198 u32 len;
199 struct mlx5_cmd_first first;
200 struct mlx5_cmd_mailbox *next;
201};
202
203struct mlx5_cmd_debug {
204 struct dentry *dbg_root;
205 struct dentry *dbg_in;
206 struct dentry *dbg_out;
207 struct dentry *dbg_outlen;
208 struct dentry *dbg_status;
209 struct dentry *dbg_run;
210 void *in_msg;
211 void *out_msg;
212 u8 status;
213 u16 inlen;
214 u16 outlen;
215};
216
217struct cache_ent {
218 /* protect block chain allocations
219 */
220 spinlock_t lock;
221 struct list_head head;
222};
223
224struct cmd_msg_cache {
225 struct cache_ent large;
226 struct cache_ent med;
227
228};
229
230struct mlx5_cmd_stats {
231 u64 sum;
232 u64 n;
233 struct dentry *root;
234 struct dentry *avg;
235 struct dentry *count;
236 /* protect command average calculations */
237 spinlock_t lock;
238};
239
240struct mlx5_cmd {
64599cca
EC		 241 void *cmd_alloc_buf;
242 dma_addr_t alloc_dma;
243 int alloc_size;
e126ba97
EC		 244 void *cmd_buf;
245 dma_addr_t dma;
246 u16 cmdif_rev;
247 u8 log_sz;
248 u8 log_stride;
249 int max_reg_cmds;
250 int events;
251 u32 __iomem *vector;
252
253 /* protect command queue allocations
254 */
255 spinlock_t alloc_lock;
256
257 /* protect token allocations
258 */
259 spinlock_t token_lock;
260 u8 token;
261 unsigned long bitmask;
262 char wq_name[MLX5_CMD_WQ_MAX_NAME];
263 struct workqueue_struct *wq;
264 struct semaphore sem;
265 struct semaphore pages_sem;
266 int mode;
267 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
268 struct pci_pool *pool;
269 struct mlx5_cmd_debug dbg;
270 struct cmd_msg_cache cache;
271 int checksum_disabled;
272 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
273};
274
275struct mlx5_port_caps {
276 int gid_table_len;
277 int pkey_table_len;
938fe83c 278 u8 ext_port_cap;
e126ba97
EC		 279};
280
281struct mlx5_cmd_mailbox {
282 void *buf;
283 dma_addr_t dma;
284 struct mlx5_cmd_mailbox *next;
285};
286
287struct mlx5_buf_list {
288 void *buf;
289 dma_addr_t map;
290};
291
292struct mlx5_buf {
293 struct mlx5_buf_list direct;
e126ba97 294 int npages;
e126ba97 295 int size;
f241e749 296 u8 page_shift;
e126ba97
EC		 297};
298
299struct mlx5_eq {
300 struct mlx5_core_dev *dev;
301 __be32 __iomem *doorbell;
302 u32 cons_index;
303 struct mlx5_buf buf;
304 int size;
305 u8 irqn;
306 u8 eqn;
307 int nent;
308 u64 mask;
e126ba97
EC		 309 struct list_head list;
310 int index;
311 struct mlx5_rsc_debug *dbg;
312};
313
3121e3c4
SG		 314struct mlx5_core_psv {
315 u32 psv_idx;
316 struct psv_layout {
317 u32 pd;
318 u16 syndrome;
319 u16 reserved;
320 u16 bg;
321 u16 app_tag;
322 u32 ref_tag;
323 } psv;
324};
325
326struct mlx5_core_sig_ctx {
327 struct mlx5_core_psv psv_memory;
328 struct mlx5_core_psv psv_wire;
d5436ba0
SG		 329 struct ib_sig_err err_item;
330 bool sig_status_checked;
331 bool sig_err_exists;
332 u32 sigerr_count;
3121e3c4 333};
e126ba97
EC		 334
335struct mlx5_core_mr {
336 u64 iova;
337 u64 size;
338 u32 key;
339 u32 pd;
e126ba97
EC		 340};
341
5903325a
EC		 342enum mlx5_res_type {
343 MLX5_RES_QP,
01949d01
HA		 344 MLX5_RES_SRQ,
345 MLX5_RES_XSRQ,
5903325a
EC		 346};
347
348struct mlx5_core_rsc_common {
349 enum mlx5_res_type res;
350 atomic_t refcount;
351 struct completion free;
352};
353
e126ba97 354struct mlx5_core_srq {
01949d01 355 struct mlx5_core_rsc_common common; /* must be first */
e126ba97
EC		 356 u32 srqn;
357 int max;
358 int max_gs;
359 int max_avail_gather;
360 int wqe_shift;
361 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
362
363 atomic_t refcount;
364 struct completion free;
365};
366
367struct mlx5_eq_table {
368 void __iomem *update_ci;
369 void __iomem *update_arm_ci;
233d05d2 370 struct list_head comp_eqs_list;
e126ba97
EC		 371 struct mlx5_eq pages_eq;
372 struct mlx5_eq async_eq;
373 struct mlx5_eq cmd_eq;
e126ba97
EC		 374 int num_comp_vectors;
375 /* protect EQs list
376 */
377 spinlock_t lock;
378};
379
380struct mlx5_uar {
381 u32 index;
382 struct list_head bf_list;
383 unsigned free_bf_bmap;
88a85f99 384 void __iomem *bf_map;
e126ba97
EC		 385 void __iomem *map;
386};
387
388
389struct mlx5_core_health {
390 struct health_buffer __iomem *health;
391 __be32 __iomem *health_counter;
392 struct timer_list timer;
393 struct list_head list;
394 u32 prev;
395 int miss_counter;
396};
397
398struct mlx5_cq_table {
399 /* protect radix tree
400 */
401 spinlock_t lock;
402 struct radix_tree_root tree;
403};
404
405struct mlx5_qp_table {
406 /* protect radix tree
407 */
408 spinlock_t lock;
409 struct radix_tree_root tree;
410};
411
412struct mlx5_srq_table {
413 /* protect radix tree
414 */
415 spinlock_t lock;
416 struct radix_tree_root tree;
417};
418
3bcdb17a
SG		 419struct mlx5_mr_table {
420 /* protect radix tree
421 */
422 rwlock_t lock;
423 struct radix_tree_root tree;
424};
425
db058a18
SM		 426struct mlx5_irq_info {
427 cpumask_var_t mask;
428 char name[MLX5_MAX_IRQ_NAME];
429};
430
e126ba97
EC		 431struct mlx5_priv {
432 char name[MLX5_MAX_NAME_LEN];
433 struct mlx5_eq_table eq_table;
db058a18
SM		 434 struct msix_entry *msix_arr;
435 struct mlx5_irq_info *irq_info;
e126ba97
EC		 436 struct mlx5_uuar_info uuari;
437 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
438
88a85f99
AS		 439 struct io_mapping *bf_mapping;
440
e126ba97
EC		 441 /* pages stuff */
442 struct workqueue_struct *pg_wq;
443 struct rb_root page_root;
444 int fw_pages;
6aec21f6 445 atomic_t reg_pages;
bf0bf77f 446 struct list_head free_list;
e126ba97
EC		 447
448 struct mlx5_core_health health;
449
450 struct mlx5_srq_table srq_table;
451
452 /* start: qp staff */
453 struct mlx5_qp_table qp_table;
454 struct dentry *qp_debugfs;
455 struct dentry *eq_debugfs;
456 struct dentry *cq_debugfs;
457 struct dentry *cmdif_debugfs;
458 /* end: qp staff */
459
460 /* start: cq staff */
461 struct mlx5_cq_table cq_table;
462 /* end: cq staff */
463
3bcdb17a
SG		 464 /* start: mr staff */
465 struct mlx5_mr_table mr_table;
466 /* end: mr staff */
467
e126ba97 468 /* start: alloc staff */
311c7c71
SM		 469 /* protect buffer alocation according to numa node */
470 struct mutex alloc_mutex;
471 int numa_node;
472
e126ba97
EC		 473 struct mutex pgdir_mutex;
474 struct list_head pgdir_list;
475 /* end: alloc staff */
476 struct dentry *dbg_root;
477
478 /* protect mkey key part */
479 spinlock_t mkey_lock;
480 u8 mkey_key;
9603b61d
JM		 481
482 struct list_head dev_list;
483 struct list_head ctx_list;
484 spinlock_t ctx_lock;
e126ba97
EC		 485};
486
487struct mlx5_core_dev {
488 struct pci_dev *pdev;
489 u8 rev_id;
490 char board_id[MLX5_BOARD_ID_LEN];
491 struct mlx5_cmd cmd;
938fe83c
SM		 492 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
493 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
494 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
e126ba97
EC		 495 phys_addr_t iseg_base;
496 struct mlx5_init_seg __iomem *iseg;
497 void (*event) (struct mlx5_core_dev *dev,
498 enum mlx5_dev_event event,
4d2f9bbb 499 unsigned long param);
e126ba97
EC		 500 struct mlx5_priv priv;
501 struct mlx5_profile *profile;
502 atomic_t num_qps;
f62b8bb8 503 u32 issi;
e126ba97
EC		 504};
505
506struct mlx5_db {
507 __be32 *db;
508 union {
509 struct mlx5_db_pgdir *pgdir;
510 struct mlx5_ib_user_db_page *user_page;
511 } u;
512 dma_addr_t dma;
513 int index;
514};
515
516enum {
517 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES,
518};
519
520enum {
521 MLX5_COMP_EQ_SIZE = 1024,
522};
523
adb0c954
SM		 524enum {
525 MLX5_PTYS_IB = 1 << 0,
526 MLX5_PTYS_EN = 1 << 2,
527};
528
e126ba97
EC		 529struct mlx5_db_pgdir {
530 struct list_head list;
531 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
532 __be32 *db_page;
533 dma_addr_t db_dma;
534};
535
536typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
537
538struct mlx5_cmd_work_ent {
539 struct mlx5_cmd_msg *in;
540 struct mlx5_cmd_msg *out;
746b5583
EC		 541 void *uout;
542 int uout_size;
e126ba97
EC		 543 mlx5_cmd_cbk_t callback;
544 void *context;
746b5583 545 int idx;
e126ba97
EC		 546 struct completion done;
547 struct mlx5_cmd *cmd;
548 struct work_struct work;
549 struct mlx5_cmd_layout *lay;
550 int ret;
551 int page_queue;
552 u8 status;
553 u8 token;
14a70046
TG		 554 u64 ts1;
555 u64 ts2;
746b5583 556 u16 op;
e126ba97
EC		 557};
558
559struct mlx5_pas {
560 u64 pa;
561 u8 log_sz;
562};
563
707c4602
MD		 564enum port_state_policy {
565 MLX5_AAA_000
566};
567
568enum phy_port_state {
569 MLX5_AAA_111
570};
571
572struct mlx5_hca_vport_context {
573 u32 field_select;
574 bool sm_virt_aware;
575 bool has_smi;
576 bool has_raw;
577 enum port_state_policy policy;
578 enum phy_port_state phys_state;
579 enum ib_port_state vport_state;
580 u8 port_physical_state;
581 u64 sys_image_guid;
582 u64 port_guid;
583 u64 node_guid;
584 u32 cap_mask1;
585 u32 cap_mask1_perm;
586 u32 cap_mask2;
587 u32 cap_mask2_perm;
588 u16 lid;
589 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
590 u8 lmc;
591 u8 subnet_timeout;
592 u16 sm_lid;
593 u8 sm_sl;
594 u16 qkey_violation_counter;
595 u16 pkey_violation_counter;
596 bool grh_required;
597};
598
e126ba97
EC		 599static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
600{
e126ba97 601 return buf->direct.buf + offset;
e126ba97
EC		 602}
603
604extern struct workqueue_struct *mlx5_core_wq;
605
606#define STRUCT_FIELD(header, field) \
607 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
608 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
609
610struct ib_field {
611 size_t struct_offset_bytes;
612 size_t struct_size_bytes;
613 int offset_bits;
614 int size_bits;
615};
616
617static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
618{
619 return pci_get_drvdata(pdev);
620}
621
622extern struct dentry *mlx5_debugfs_root;
623
624static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
625{
626 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
627}
628
629static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
630{
631 return ioread32be(&dev->iseg->fw_rev) >> 16;
632}
633
634static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
635{
636 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
637}
638
639static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
640{
641 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
642}
643
644static inline void *mlx5_vzalloc(unsigned long size)
645{
646 void *rtn;
647
648 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
649 if (!rtn)
650 rtn = vzalloc(size);
651 return rtn;
652}
653
3bcdb17a
SG		 654static inline u32 mlx5_base_mkey(const u32 key)
655{
656 return key & 0xffffff00u;
657}
658
e126ba97
EC		 659int mlx5_cmd_init(struct mlx5_core_dev *dev);
660void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
661void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
662void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
663int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
b775516b 664int mlx5_cmd_status_to_err_v2(void *ptr);
938fe83c
SM		 665int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
666 enum mlx5_cap_mode cap_mode);
e126ba97
EC		 667int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
668 int out_size);
746b5583
EC		 669int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
670 void *out, int out_size, mlx5_cmd_cbk_t callback,
671 void *context);
e126ba97
EC		 672int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
673int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
674int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
675int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
e281682b
SM		 676int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
677void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
e126ba97
EC		 678void mlx5_health_cleanup(void);
679void __init mlx5_health_init(void);
680void mlx5_start_health_poll(struct mlx5_core_dev *dev);
681void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
311c7c71
SM		 682int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
683 struct mlx5_buf *buf, int node);
64ffaa21 684int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
e126ba97
EC		 685void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
686struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
687 gfp_t flags, int npages);
688void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
689 struct mlx5_cmd_mailbox *head);
690int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
01949d01
HA		 691 struct mlx5_create_srq_mbox_in *in, int inlen,
692 int is_xrc);
e126ba97
EC		 693int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
694int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
695 struct mlx5_query_srq_mbox_out *out);
696int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
697 u16 lwm, int is_srq);
3bcdb17a
SG		 698void mlx5_init_mr_table(struct mlx5_core_dev *dev);
699void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
e126ba97 700int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
746b5583
EC		 701 struct mlx5_create_mkey_mbox_in *in, int inlen,
702 mlx5_cmd_cbk_t callback, void *context,
703 struct mlx5_create_mkey_mbox_out *out);
e126ba97
EC		 704int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr);
705int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
706 struct mlx5_query_mkey_mbox_out *out, int outlen);
707int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
708 u32 *mkey);
709int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
710int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
a97e2d86 711int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
f241e749 712 u16 opmod, u8 port);
e126ba97
EC		 713void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
714void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
715int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
716void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
717void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
0a324f31 718 s32 npages);
cd23b14b 719int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
e126ba97
EC		 720int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
721void mlx5_register_debugfs(void);
722void mlx5_unregister_debugfs(void);
723int mlx5_eq_init(struct mlx5_core_dev *dev);
724void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
725void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
726void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
5903325a 727void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
e420f0c0
HE		 728#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
729void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
730#endif
e126ba97
EC		 731void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
732struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
733void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector);
734void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
735int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
736 int nent, u64 mask, const char *name, struct mlx5_uar *uar);
737int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
738int mlx5_start_eqs(struct mlx5_core_dev *dev);
739int mlx5_stop_eqs(struct mlx5_core_dev *dev);
233d05d2 740int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
e126ba97
EC		 741int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
742int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
743
744int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
745void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
746int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
747 int size_in, void *data_out, int size_out,
748 u16 reg_num, int arg, int write);
adb0c954 749
f241e749 750int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
adb0c954 751int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
a05bdefa 752 int ptys_size, int proto_mask, u8 local_port);
adb0c954
SM		 753int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
754 u32 *proto_cap, int proto_mask);
755int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
756 u32 *proto_admin, int proto_mask);
a124d13e
MD		 757int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
758 u8 *link_width_oper, u8 local_port);
759int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev,
760 u8 *proto_oper, int proto_mask,
761 u8 local_port);
adb0c954
SM		 762int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
763 int proto_mask);
4c916a79
RS		 764int mlx5_set_port_status(struct mlx5_core_dev *dev,
765 enum mlx5_port_status status);
766int mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status);
e126ba97 767
facc9699
SM		 768int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu, u8 port);
769void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu, u8 port);
770void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu,
771 u8 port);
772
a124d13e
MD		 773int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
774 u8 *vl_hw_cap, u8 local_port);
e126ba97
EC		 775
776int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
777void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
778int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
779 struct mlx5_query_eq_mbox_out *out, int outlen);
780int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
781void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
782int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
783void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
784int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
311c7c71
SM		 785int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
786 int node);
e126ba97
EC		 787void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
788
e126ba97
EC		 789const char *mlx5_command_str(int command);
790int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
791void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
3121e3c4
SG		 792int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
793 int npsvs, u32 *sig_index);
794int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
5903325a 795void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
e420f0c0
HE		 796int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
797 struct mlx5_odp_caps *odp_caps);
e126ba97
EC		 798
799static inline u32 mlx5_mkey_to_idx(u32 mkey)
800{
801 return mkey >> 8;
802}
803
804static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
805{
806 return mkey_idx << 8;
807}
808
746b5583
EC		 809static inline u8 mlx5_mkey_variant(u32 mkey)
810{
811 return mkey & 0xff;
812}
813
e126ba97
EC		 814enum {
815 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
c1868b82 816 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
e126ba97
EC		 817};
818
819enum {
820 MAX_MR_CACHE_ENTRIES = 16,
821};
822
64613d94
SM		 823enum {
824 MLX5_INTERFACE_PROTOCOL_IB = 0,
825 MLX5_INTERFACE_PROTOCOL_ETH = 1,
826};
827
9603b61d
JM		 828struct mlx5_interface {
829 void * (*add)(struct mlx5_core_dev *dev);
830 void (*remove)(struct mlx5_core_dev *dev, void *context);
831 void (*event)(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 832 enum mlx5_dev_event event, unsigned long param);
64613d94
SM		 833 void * (*get_dev)(void *context);
834 int protocol;
9603b61d
JM		 835 struct list_head list;
836};
837
64613d94 838void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
9603b61d
JM		 839int mlx5_register_interface(struct mlx5_interface *intf);
840void mlx5_unregister_interface(struct mlx5_interface *intf);
211e6c80 841int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
9603b61d 842
e126ba97
EC		 843struct mlx5_profile {
844 u64 mask;
f241e749 845 u8 log_max_qp;
e126ba97
EC		 846 struct {
847 int size;
848 int limit;
849 } mr_cache[MAX_MR_CACHE_ENTRIES];
850};
851
707c4602
MD		 852static inline int mlx5_get_gid_table_len(u16 param)
853{
854 if (param > 4) {
855 pr_warn("gid table length is zero\n");
856 return 0;
857 }
858
859 return 8 * (1 << param);
860}
861
e126ba97 862#endif /* MLX5_DRIVER_H */
Linux 6.x block layer and io_uring tree(s)