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net/mlx5_core: use set/get macros in device caps
[linux-2.6-block.git] / include / linux / mlx5 / driver.h
CommitLineData
e126ba97
EC		 1/*
2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DRIVER_H
34#define MLX5_DRIVER_H
35
36#include <linux/kernel.h>
37#include <linux/completion.h>
38#include <linux/pci.h>
39#include <linux/spinlock_types.h>
40#include <linux/semaphore.h>
6ecde51d 41#include <linux/slab.h>
e126ba97
EC		 42#include <linux/vmalloc.h>
43#include <linux/radix-tree.h>
6ecde51d 44
e126ba97
EC		 45#include <linux/mlx5/device.h>
46#include <linux/mlx5/doorbell.h>
d29b796a 47#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 48
49enum {
50 MLX5_BOARD_ID_LEN = 64,
51 MLX5_MAX_NAME_LEN = 16,
52};
53
54enum {
55 /* one minute for the sake of bringup. Generally, commands must always
56 * complete and we may need to increase this timeout value
57 */
58 MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000,
59 MLX5_CMD_WQ_MAX_NAME = 32,
60};
61
62enum {
63 CMD_OWNER_SW = 0x0,
64 CMD_OWNER_HW = 0x1,
65 CMD_STATUS_SUCCESS = 0,
66};
67
68enum mlx5_sqp_t {
69 MLX5_SQP_SMI = 0,
70 MLX5_SQP_GSI = 1,
71 MLX5_SQP_IEEE_1588 = 2,
72 MLX5_SQP_SNIFFER = 3,
73 MLX5_SQP_SYNC_UMR = 4,
74};
75
76enum {
77 MLX5_MAX_PORTS = 2,
78};
79
80enum {
81 MLX5_EQ_VEC_PAGES = 0,
82 MLX5_EQ_VEC_CMD = 1,
83 MLX5_EQ_VEC_ASYNC = 2,
84 MLX5_EQ_VEC_COMP_BASE,
85};
86
87enum {
ada9f5d0 88 MLX5_MAX_EQ_NAME = 32
e126ba97
EC		 89};
90
91enum {
92 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
93 MLX5_ATOMIC_MODE_CX = 2 << 16,
94 MLX5_ATOMIC_MODE_8B = 3 << 16,
95 MLX5_ATOMIC_MODE_16B = 4 << 16,
96 MLX5_ATOMIC_MODE_32B = 5 << 16,
97 MLX5_ATOMIC_MODE_64B = 6 << 16,
98 MLX5_ATOMIC_MODE_128B = 7 << 16,
99 MLX5_ATOMIC_MODE_256B = 8 << 16,
100};
101
e126ba97
EC		 102enum {
103 MLX5_REG_PCAP = 0x5001,
104 MLX5_REG_PMTU = 0x5003,
105 MLX5_REG_PTYS = 0x5004,
106 MLX5_REG_PAOS = 0x5006,
107 MLX5_REG_PMAOS = 0x5012,
108 MLX5_REG_PUDE = 0x5009,
109 MLX5_REG_PMPE = 0x5010,
110 MLX5_REG_PELC = 0x500e,
111 MLX5_REG_PMLP = 0, /* TBD */
112 MLX5_REG_NODE_DESC = 0x6001,
113 MLX5_REG_HOST_ENDIANNESS = 0x7004,
114};
115
116enum dbg_rsc_type {
117 MLX5_DBG_RSC_QP,
118 MLX5_DBG_RSC_EQ,
119 MLX5_DBG_RSC_CQ,
120};
121
122struct mlx5_field_desc {
123 struct dentry *dent;
124 int i;
125};
126
127struct mlx5_rsc_debug {
128 struct mlx5_core_dev *dev;
129 void *object;
130 enum dbg_rsc_type type;
131 struct dentry *root;
132 struct mlx5_field_desc fields[0];
133};
134
135enum mlx5_dev_event {
136 MLX5_DEV_EVENT_SYS_ERROR,
137 MLX5_DEV_EVENT_PORT_UP,
138 MLX5_DEV_EVENT_PORT_DOWN,
139 MLX5_DEV_EVENT_PORT_INITIALIZED,
140 MLX5_DEV_EVENT_LID_CHANGE,
141 MLX5_DEV_EVENT_PKEY_CHANGE,
142 MLX5_DEV_EVENT_GUID_CHANGE,
143 MLX5_DEV_EVENT_CLIENT_REREG,
144};
145
146struct mlx5_uuar_info {
147 struct mlx5_uar *uars;
148 int num_uars;
149 int num_low_latency_uuars;
150 unsigned long *bitmap;
151 unsigned int *count;
152 struct mlx5_bf *bfs;
153
154 /*
155 * protect uuar allocation data structs
156 */
157 struct mutex lock;
78c0f98c 158 u32 ver;
e126ba97
EC		 159};
160
161struct mlx5_bf {
162 void __iomem *reg;
163 void __iomem *regreg;
164 int buf_size;
165 struct mlx5_uar *uar;
166 unsigned long offset;
167 int need_lock;
168 /* protect blue flame buffer selection when needed
169 */
170 spinlock_t lock;
171
172 /* serialize 64 bit writes when done as two 32 bit accesses
173 */
174 spinlock_t lock32;
175 int uuarn;
176};
177
178struct mlx5_cmd_first {
179 __be32 data[4];
180};
181
182struct mlx5_cmd_msg {
183 struct list_head list;
184 struct cache_ent *cache;
185 u32 len;
186 struct mlx5_cmd_first first;
187 struct mlx5_cmd_mailbox *next;
188};
189
190struct mlx5_cmd_debug {
191 struct dentry *dbg_root;
192 struct dentry *dbg_in;
193 struct dentry *dbg_out;
194 struct dentry *dbg_outlen;
195 struct dentry *dbg_status;
196 struct dentry *dbg_run;
197 void *in_msg;
198 void *out_msg;
199 u8 status;
200 u16 inlen;
201 u16 outlen;
202};
203
204struct cache_ent {
205 /* protect block chain allocations
206 */
207 spinlock_t lock;
208 struct list_head head;
209};
210
211struct cmd_msg_cache {
212 struct cache_ent large;
213 struct cache_ent med;
214
215};
216
217struct mlx5_cmd_stats {
218 u64 sum;
219 u64 n;
220 struct dentry *root;
221 struct dentry *avg;
222 struct dentry *count;
223 /* protect command average calculations */
224 spinlock_t lock;
225};
226
227struct mlx5_cmd {
228 void *cmd_buf;
229 dma_addr_t dma;
230 u16 cmdif_rev;
231 u8 log_sz;
232 u8 log_stride;
233 int max_reg_cmds;
234 int events;
235 u32 __iomem *vector;
236
237 /* protect command queue allocations
238 */
239 spinlock_t alloc_lock;
240
241 /* protect token allocations
242 */
243 spinlock_t token_lock;
244 u8 token;
245 unsigned long bitmask;
246 char wq_name[MLX5_CMD_WQ_MAX_NAME];
247 struct workqueue_struct *wq;
248 struct semaphore sem;
249 struct semaphore pages_sem;
250 int mode;
251 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
252 struct pci_pool *pool;
253 struct mlx5_cmd_debug dbg;
254 struct cmd_msg_cache cache;
255 int checksum_disabled;
256 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
257};
258
259struct mlx5_port_caps {
260 int gid_table_len;
261 int pkey_table_len;
262};
263
c7a08ac7 264struct mlx5_general_caps {
e126ba97
EC		 265 u8 log_max_eq;
266 u8 log_max_cq;
267 u8 log_max_qp;
268 u8 log_max_mkey;
269 u8 log_max_pd;
270 u8 log_max_srq;
c7a08ac7
EC		 271 u8 log_max_strq;
272 u8 log_max_mrw_sz;
273 u8 log_max_bsf_list_size;
274 u8 log_max_klm_list_size;
e126ba97
EC		 275 u32 max_cqes;
276 int max_wqes;
c7a08ac7
EC		 277 u32 max_eqes;
278 u32 max_indirection;
e126ba97
EC		 279 int max_sq_desc_sz;
280 int max_rq_desc_sz;
c7a08ac7 281 int max_dc_sq_desc_sz;
e126ba97
EC		 282 u64 flags;
283 u16 stat_rate_support;
284 int log_max_msg;
285 int num_ports;
c7a08ac7
EC		 286 u8 log_max_ra_res_qp;
287 u8 log_max_ra_req_qp;
e126ba97
EC		 288 int max_srq_wqes;
289 int bf_reg_size;
290 int bf_regs_per_page;
291 struct mlx5_port_caps port[MLX5_MAX_PORTS];
292 u8 ext_port_cap[MLX5_MAX_PORTS];
293 int max_vf;
294 u32 reserved_lkey;
295 u8 local_ca_ack_delay;
296 u8 log_max_mcg;
0a324f31 297 u32 max_qp_mcg;
e126ba97 298 int min_page_sz;
c7a08ac7
EC		 299 int pd_cap;
300 u32 max_qp_counters;
301 u32 pkey_table_size;
302 u8 log_max_ra_req_dc;
303 u8 log_max_ra_res_dc;
304 u32 uar_sz;
305 u8 min_log_pg_sz;
306 u8 log_max_xrcd;
307 u16 log_uar_page_sz;
308};
309
310struct mlx5_caps {
311 struct mlx5_general_caps gen;
e126ba97
EC		 312};
313
314struct mlx5_cmd_mailbox {
315 void *buf;
316 dma_addr_t dma;
317 struct mlx5_cmd_mailbox *next;
318};
319
320struct mlx5_buf_list {
321 void *buf;
322 dma_addr_t map;
323};
324
325struct mlx5_buf {
326 struct mlx5_buf_list direct;
327 struct mlx5_buf_list *page_list;
328 int nbufs;
329 int npages;
e126ba97 330 int size;
f241e749 331 u8 page_shift;
e126ba97
EC		 332};
333
334struct mlx5_eq {
335 struct mlx5_core_dev *dev;
336 __be32 __iomem *doorbell;
337 u32 cons_index;
338 struct mlx5_buf buf;
339 int size;
340 u8 irqn;
341 u8 eqn;
342 int nent;
343 u64 mask;
344 char name[MLX5_MAX_EQ_NAME];
345 struct list_head list;
346 int index;
347 struct mlx5_rsc_debug *dbg;
348};
349
3121e3c4
SG		 350struct mlx5_core_psv {
351 u32 psv_idx;
352 struct psv_layout {
353 u32 pd;
354 u16 syndrome;
355 u16 reserved;
356 u16 bg;
357 u16 app_tag;
358 u32 ref_tag;
359 } psv;
360};
361
362struct mlx5_core_sig_ctx {
363 struct mlx5_core_psv psv_memory;
364 struct mlx5_core_psv psv_wire;
d5436ba0
SG		 365 struct ib_sig_err err_item;
366 bool sig_status_checked;
367 bool sig_err_exists;
368 u32 sigerr_count;
3121e3c4 369};
e126ba97
EC		 370
371struct mlx5_core_mr {
372 u64 iova;
373 u64 size;
374 u32 key;
375 u32 pd;
e126ba97
EC		 376};
377
378struct mlx5_core_srq {
379 u32 srqn;
380 int max;
381 int max_gs;
382 int max_avail_gather;
383 int wqe_shift;
384 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
385
386 atomic_t refcount;
387 struct completion free;
388};
389
390struct mlx5_eq_table {
391 void __iomem *update_ci;
392 void __iomem *update_arm_ci;
393 struct list_head *comp_eq_head;
394 struct mlx5_eq pages_eq;
395 struct mlx5_eq async_eq;
396 struct mlx5_eq cmd_eq;
397 struct msix_entry *msix_arr;
398 int num_comp_vectors;
399 /* protect EQs list
400 */
401 spinlock_t lock;
402};
403
404struct mlx5_uar {
405 u32 index;
406 struct list_head bf_list;
407 unsigned free_bf_bmap;
408 void __iomem *wc_map;
409 void __iomem *map;
410};
411
412
413struct mlx5_core_health {
414 struct health_buffer __iomem *health;
415 __be32 __iomem *health_counter;
416 struct timer_list timer;
417 struct list_head list;
418 u32 prev;
419 int miss_counter;
420};
421
422struct mlx5_cq_table {
423 /* protect radix tree
424 */
425 spinlock_t lock;
426 struct radix_tree_root tree;
427};
428
429struct mlx5_qp_table {
430 /* protect radix tree
431 */
432 spinlock_t lock;
433 struct radix_tree_root tree;
434};
435
436struct mlx5_srq_table {
437 /* protect radix tree
438 */
439 spinlock_t lock;
440 struct radix_tree_root tree;
441};
442
3bcdb17a
SG		 443struct mlx5_mr_table {
444 /* protect radix tree
445 */
446 rwlock_t lock;
447 struct radix_tree_root tree;
448};
449
e126ba97
EC		 450struct mlx5_priv {
451 char name[MLX5_MAX_NAME_LEN];
452 struct mlx5_eq_table eq_table;
453 struct mlx5_uuar_info uuari;
454 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
455
456 /* pages stuff */
457 struct workqueue_struct *pg_wq;
458 struct rb_root page_root;
459 int fw_pages;
460 int reg_pages;
bf0bf77f 461 struct list_head free_list;
e126ba97
EC		 462
463 struct mlx5_core_health health;
464
465 struct mlx5_srq_table srq_table;
466
467 /* start: qp staff */
468 struct mlx5_qp_table qp_table;
469 struct dentry *qp_debugfs;
470 struct dentry *eq_debugfs;
471 struct dentry *cq_debugfs;
472 struct dentry *cmdif_debugfs;
473 /* end: qp staff */
474
475 /* start: cq staff */
476 struct mlx5_cq_table cq_table;
477 /* end: cq staff */
478
3bcdb17a
SG		 479 /* start: mr staff */
480 struct mlx5_mr_table mr_table;
481 /* end: mr staff */
482
e126ba97
EC		 483 /* start: alloc staff */
484 struct mutex pgdir_mutex;
485 struct list_head pgdir_list;
486 /* end: alloc staff */
487 struct dentry *dbg_root;
488
489 /* protect mkey key part */
490 spinlock_t mkey_lock;
491 u8 mkey_key;
9603b61d
JM		 492
493 struct list_head dev_list;
494 struct list_head ctx_list;
495 spinlock_t ctx_lock;
e126ba97
EC		 496};
497
498struct mlx5_core_dev {
499 struct pci_dev *pdev;
500 u8 rev_id;
501 char board_id[MLX5_BOARD_ID_LEN];
502 struct mlx5_cmd cmd;
503 struct mlx5_caps caps;
504 phys_addr_t iseg_base;
505 struct mlx5_init_seg __iomem *iseg;
506 void (*event) (struct mlx5_core_dev *dev,
507 enum mlx5_dev_event event,
4d2f9bbb 508 unsigned long param);
e126ba97
EC		 509 struct mlx5_priv priv;
510 struct mlx5_profile *profile;
511 atomic_t num_qps;
512};
513
514struct mlx5_db {
515 __be32 *db;
516 union {
517 struct mlx5_db_pgdir *pgdir;
518 struct mlx5_ib_user_db_page *user_page;
519 } u;
520 dma_addr_t dma;
521 int index;
522};
523
524enum {
525 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES,
526};
527
528enum {
529 MLX5_COMP_EQ_SIZE = 1024,
530};
531
532struct mlx5_db_pgdir {
533 struct list_head list;
534 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
535 __be32 *db_page;
536 dma_addr_t db_dma;
537};
538
539typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
540
541struct mlx5_cmd_work_ent {
542 struct mlx5_cmd_msg *in;
543 struct mlx5_cmd_msg *out;
746b5583
EC		 544 void *uout;
545 int uout_size;
e126ba97
EC		 546 mlx5_cmd_cbk_t callback;
547 void *context;
746b5583 548 int idx;
e126ba97
EC		 549 struct completion done;
550 struct mlx5_cmd *cmd;
551 struct work_struct work;
552 struct mlx5_cmd_layout *lay;
553 int ret;
554 int page_queue;
555 u8 status;
556 u8 token;
14a70046
TG		 557 u64 ts1;
558 u64 ts2;
746b5583 559 u16 op;
e126ba97
EC		 560};
561
562struct mlx5_pas {
563 u64 pa;
564 u8 log_sz;
565};
566
567static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
568{
569 if (likely(BITS_PER_LONG == 64 || buf->nbufs == 1))
570 return buf->direct.buf + offset;
571 else
572 return buf->page_list[offset >> PAGE_SHIFT].buf +
573 (offset & (PAGE_SIZE - 1));
574}
575
576extern struct workqueue_struct *mlx5_core_wq;
577
578#define STRUCT_FIELD(header, field) \
579 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
580 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
581
582struct ib_field {
583 size_t struct_offset_bytes;
584 size_t struct_size_bytes;
585 int offset_bits;
586 int size_bits;
587};
588
589static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
590{
591 return pci_get_drvdata(pdev);
592}
593
594extern struct dentry *mlx5_debugfs_root;
595
596static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
597{
598 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
599}
600
601static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
602{
603 return ioread32be(&dev->iseg->fw_rev) >> 16;
604}
605
606static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
607{
608 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
609}
610
611static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
612{
613 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
614}
615
616static inline void *mlx5_vzalloc(unsigned long size)
617{
618 void *rtn;
619
620 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
621 if (!rtn)
622 rtn = vzalloc(size);
623 return rtn;
624}
625
626static inline void mlx5_vfree(const void *addr)
627{
628 if (addr && is_vmalloc_addr(addr))
629 vfree(addr);
630 else
631 kfree(addr);
632}
633
3bcdb17a
SG		 634static inline u32 mlx5_base_mkey(const u32 key)
635{
636 return key & 0xffffff00u;
637}
638
e126ba97
EC		 639int mlx5_cmd_init(struct mlx5_core_dev *dev);
640void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
641void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
642void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
643int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
b775516b 644int mlx5_cmd_status_to_err_v2(void *ptr);
c7a08ac7
EC		 645int mlx5_core_get_caps(struct mlx5_core_dev *dev, struct mlx5_caps *caps,
646 u16 opmod);
e126ba97
EC		 647int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
648 int out_size);
746b5583
EC		 649int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
650 void *out, int out_size, mlx5_cmd_cbk_t callback,
651 void *context);
e126ba97
EC		 652int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
653int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
654int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
655int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
656void mlx5_health_cleanup(void);
657void __init mlx5_health_init(void);
658void mlx5_start_health_poll(struct mlx5_core_dev *dev);
659void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
660int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct,
661 struct mlx5_buf *buf);
662void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
663struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
664 gfp_t flags, int npages);
665void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
666 struct mlx5_cmd_mailbox *head);
667int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
668 struct mlx5_create_srq_mbox_in *in, int inlen);
669int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
670int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
671 struct mlx5_query_srq_mbox_out *out);
672int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
673 u16 lwm, int is_srq);
3bcdb17a
SG		 674void mlx5_init_mr_table(struct mlx5_core_dev *dev);
675void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
e126ba97 676int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
746b5583
EC		 677 struct mlx5_create_mkey_mbox_in *in, int inlen,
678 mlx5_cmd_cbk_t callback, void *context,
679 struct mlx5_create_mkey_mbox_out *out);
e126ba97
EC		 680int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr);
681int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
682 struct mlx5_query_mkey_mbox_out *out, int outlen);
683int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
684 u32 *mkey);
685int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
686int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
687int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, void *inb, void *outb,
f241e749 688 u16 opmod, u8 port);
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EC		 689void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
690void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
691int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
692void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
693void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
0a324f31 694 s32 npages);
cd23b14b 695int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
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EC		 696int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
697void mlx5_register_debugfs(void);
698void mlx5_unregister_debugfs(void);
699int mlx5_eq_init(struct mlx5_core_dev *dev);
700void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
701void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
702void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
703void mlx5_qp_event(struct mlx5_core_dev *dev, u32 qpn, int event_type);
704void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
705struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
706void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector);
707void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
708int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
709 int nent, u64 mask, const char *name, struct mlx5_uar *uar);
710int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
711int mlx5_start_eqs(struct mlx5_core_dev *dev);
712int mlx5_stop_eqs(struct mlx5_core_dev *dev);
713int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
714int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
715
716int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
717void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
718int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
719 int size_in, void *data_out, int size_out,
720 u16 reg_num, int arg, int write);
f241e749 721int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
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EC		 722
723int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
724void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
725int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
726 struct mlx5_query_eq_mbox_out *out, int outlen);
727int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
728void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
729int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
730void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
731int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
732void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
733
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EC		 734const char *mlx5_command_str(int command);
735int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
736void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
3121e3c4
SG		 737int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
738 int npsvs, u32 *sig_index);
739int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
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EC		 740
741static inline u32 mlx5_mkey_to_idx(u32 mkey)
742{
743 return mkey >> 8;
744}
745
746static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
747{
748 return mkey_idx << 8;
749}
750
746b5583
EC		 751static inline u8 mlx5_mkey_variant(u32 mkey)
752{
753 return mkey & 0xff;
754}
755
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EC		 756enum {
757 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
c1868b82 758 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
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EC		 759};
760
761enum {
762 MAX_MR_CACHE_ENTRIES = 16,
763};
764
9603b61d
JM		 765struct mlx5_interface {
766 void * (*add)(struct mlx5_core_dev *dev);
767 void (*remove)(struct mlx5_core_dev *dev, void *context);
768 void (*event)(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 769 enum mlx5_dev_event event, unsigned long param);
9603b61d
JM		 770 struct list_head list;
771};
772
773int mlx5_register_interface(struct mlx5_interface *intf);
774void mlx5_unregister_interface(struct mlx5_interface *intf);
775
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EC		 776struct mlx5_profile {
777 u64 mask;
f241e749 778 u8 log_max_qp;
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EC		 779 struct {
780 int size;
781 int limit;
782 } mr_cache[MAX_MR_CACHE_ENTRIES];
783};
784
785#endif /* MLX5_DRIVER_H */
Linux 6.x block layer and io_uring tree(s)