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net/mlx5e: Write vlan list into vport context
[linux-2.6-block.git] / include / linux / mlx5 / driver.h
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DRIVER_H
34#define MLX5_DRIVER_H
35
36#include <linux/kernel.h>
37#include <linux/completion.h>
38#include <linux/pci.h>
39#include <linux/spinlock_types.h>
40#include <linux/semaphore.h>
6ecde51d 41#include <linux/slab.h>
e126ba97
EC		 42#include <linux/vmalloc.h>
43#include <linux/radix-tree.h>
6ecde51d 44
e126ba97
EC		 45#include <linux/mlx5/device.h>
46#include <linux/mlx5/doorbell.h>
47
48enum {
49 MLX5_BOARD_ID_LEN = 64,
50 MLX5_MAX_NAME_LEN = 16,
51};
52
53enum {
54 /* one minute for the sake of bringup. Generally, commands must always
55 * complete and we may need to increase this timeout value
56 */
57 MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000,
58 MLX5_CMD_WQ_MAX_NAME = 32,
59};
60
61enum {
62 CMD_OWNER_SW = 0x0,
63 CMD_OWNER_HW = 0x1,
64 CMD_STATUS_SUCCESS = 0,
65};
66
67enum mlx5_sqp_t {
68 MLX5_SQP_SMI = 0,
69 MLX5_SQP_GSI = 1,
70 MLX5_SQP_IEEE_1588 = 2,
71 MLX5_SQP_SNIFFER = 3,
72 MLX5_SQP_SYNC_UMR = 4,
73};
74
75enum {
76 MLX5_MAX_PORTS = 2,
77};
78
79enum {
80 MLX5_EQ_VEC_PAGES = 0,
81 MLX5_EQ_VEC_CMD = 1,
82 MLX5_EQ_VEC_ASYNC = 2,
83 MLX5_EQ_VEC_COMP_BASE,
84};
85
86enum {
db058a18 87 MLX5_MAX_IRQ_NAME = 32
e126ba97
EC		 88};
89
90enum {
91 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
92 MLX5_ATOMIC_MODE_CX = 2 << 16,
93 MLX5_ATOMIC_MODE_8B = 3 << 16,
94 MLX5_ATOMIC_MODE_16B = 4 << 16,
95 MLX5_ATOMIC_MODE_32B = 5 << 16,
96 MLX5_ATOMIC_MODE_64B = 6 << 16,
97 MLX5_ATOMIC_MODE_128B = 7 << 16,
98 MLX5_ATOMIC_MODE_256B = 8 << 16,
99};
100
e126ba97
EC		 101enum {
102 MLX5_REG_PCAP = 0x5001,
103 MLX5_REG_PMTU = 0x5003,
104 MLX5_REG_PTYS = 0x5004,
105 MLX5_REG_PAOS = 0x5006,
3c2d18ef 106 MLX5_REG_PFCC = 0x5007,
efea389d 107 MLX5_REG_PPCNT = 0x5008,
e126ba97
EC		 108 MLX5_REG_PMAOS = 0x5012,
109 MLX5_REG_PUDE = 0x5009,
110 MLX5_REG_PMPE = 0x5010,
111 MLX5_REG_PELC = 0x500e,
a124d13e 112 MLX5_REG_PVLC = 0x500f,
e126ba97
EC		 113 MLX5_REG_PMLP = 0, /* TBD */
114 MLX5_REG_NODE_DESC = 0x6001,
115 MLX5_REG_HOST_ENDIANNESS = 0x7004,
116};
117
e420f0c0
HE		 118enum mlx5_page_fault_resume_flags {
119 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
120 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
121 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
122 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
123};
124
e126ba97
EC		 125enum dbg_rsc_type {
126 MLX5_DBG_RSC_QP,
127 MLX5_DBG_RSC_EQ,
128 MLX5_DBG_RSC_CQ,
129};
130
131struct mlx5_field_desc {
132 struct dentry *dent;
133 int i;
134};
135
136struct mlx5_rsc_debug {
137 struct mlx5_core_dev *dev;
138 void *object;
139 enum dbg_rsc_type type;
140 struct dentry *root;
141 struct mlx5_field_desc fields[0];
142};
143
144enum mlx5_dev_event {
145 MLX5_DEV_EVENT_SYS_ERROR,
146 MLX5_DEV_EVENT_PORT_UP,
147 MLX5_DEV_EVENT_PORT_DOWN,
148 MLX5_DEV_EVENT_PORT_INITIALIZED,
149 MLX5_DEV_EVENT_LID_CHANGE,
150 MLX5_DEV_EVENT_PKEY_CHANGE,
151 MLX5_DEV_EVENT_GUID_CHANGE,
152 MLX5_DEV_EVENT_CLIENT_REREG,
153};
154
4c916a79 155enum mlx5_port_status {
6fa1bcab
AS		 156 MLX5_PORT_UP = 1,
157 MLX5_PORT_DOWN = 2,
4c916a79
RS		 158};
159
e126ba97
EC		 160struct mlx5_uuar_info {
161 struct mlx5_uar *uars;
162 int num_uars;
163 int num_low_latency_uuars;
164 unsigned long *bitmap;
165 unsigned int *count;
166 struct mlx5_bf *bfs;
167
168 /*
169 * protect uuar allocation data structs
170 */
171 struct mutex lock;
78c0f98c 172 u32 ver;
e126ba97
EC		 173};
174
175struct mlx5_bf {
176 void __iomem *reg;
177 void __iomem *regreg;
178 int buf_size;
179 struct mlx5_uar *uar;
180 unsigned long offset;
181 int need_lock;
182 /* protect blue flame buffer selection when needed
183 */
184 spinlock_t lock;
185
186 /* serialize 64 bit writes when done as two 32 bit accesses
187 */
188 spinlock_t lock32;
189 int uuarn;
190};
191
192struct mlx5_cmd_first {
193 __be32 data[4];
194};
195
196struct mlx5_cmd_msg {
197 struct list_head list;
198 struct cache_ent *cache;
199 u32 len;
200 struct mlx5_cmd_first first;
201 struct mlx5_cmd_mailbox *next;
202};
203
204struct mlx5_cmd_debug {
205 struct dentry *dbg_root;
206 struct dentry *dbg_in;
207 struct dentry *dbg_out;
208 struct dentry *dbg_outlen;
209 struct dentry *dbg_status;
210 struct dentry *dbg_run;
211 void *in_msg;
212 void *out_msg;
213 u8 status;
214 u16 inlen;
215 u16 outlen;
216};
217
218struct cache_ent {
219 /* protect block chain allocations
220 */
221 spinlock_t lock;
222 struct list_head head;
223};
224
225struct cmd_msg_cache {
226 struct cache_ent large;
227 struct cache_ent med;
228
229};
230
231struct mlx5_cmd_stats {
232 u64 sum;
233 u64 n;
234 struct dentry *root;
235 struct dentry *avg;
236 struct dentry *count;
237 /* protect command average calculations */
238 spinlock_t lock;
239};
240
241struct mlx5_cmd {
64599cca
EC		 242 void *cmd_alloc_buf;
243 dma_addr_t alloc_dma;
244 int alloc_size;
e126ba97
EC		 245 void *cmd_buf;
246 dma_addr_t dma;
247 u16 cmdif_rev;
248 u8 log_sz;
249 u8 log_stride;
250 int max_reg_cmds;
251 int events;
252 u32 __iomem *vector;
253
254 /* protect command queue allocations
255 */
256 spinlock_t alloc_lock;
257
258 /* protect token allocations
259 */
260 spinlock_t token_lock;
261 u8 token;
262 unsigned long bitmask;
263 char wq_name[MLX5_CMD_WQ_MAX_NAME];
264 struct workqueue_struct *wq;
265 struct semaphore sem;
266 struct semaphore pages_sem;
267 int mode;
268 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
269 struct pci_pool *pool;
270 struct mlx5_cmd_debug dbg;
271 struct cmd_msg_cache cache;
272 int checksum_disabled;
273 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
274};
275
276struct mlx5_port_caps {
277 int gid_table_len;
278 int pkey_table_len;
938fe83c 279 u8 ext_port_cap;
e126ba97
EC		 280};
281
282struct mlx5_cmd_mailbox {
283 void *buf;
284 dma_addr_t dma;
285 struct mlx5_cmd_mailbox *next;
286};
287
288struct mlx5_buf_list {
289 void *buf;
290 dma_addr_t map;
291};
292
293struct mlx5_buf {
294 struct mlx5_buf_list direct;
e126ba97 295 int npages;
e126ba97 296 int size;
f241e749 297 u8 page_shift;
e126ba97
EC		 298};
299
300struct mlx5_eq {
301 struct mlx5_core_dev *dev;
302 __be32 __iomem *doorbell;
303 u32 cons_index;
304 struct mlx5_buf buf;
305 int size;
306 u8 irqn;
307 u8 eqn;
308 int nent;
309 u64 mask;
e126ba97
EC		 310 struct list_head list;
311 int index;
312 struct mlx5_rsc_debug *dbg;
313};
314
3121e3c4
SG		 315struct mlx5_core_psv {
316 u32 psv_idx;
317 struct psv_layout {
318 u32 pd;
319 u16 syndrome;
320 u16 reserved;
321 u16 bg;
322 u16 app_tag;
323 u32 ref_tag;
324 } psv;
325};
326
327struct mlx5_core_sig_ctx {
328 struct mlx5_core_psv psv_memory;
329 struct mlx5_core_psv psv_wire;
d5436ba0
SG		 330 struct ib_sig_err err_item;
331 bool sig_status_checked;
332 bool sig_err_exists;
333 u32 sigerr_count;
3121e3c4 334};
e126ba97
EC		 335
336struct mlx5_core_mr {
337 u64 iova;
338 u64 size;
339 u32 key;
340 u32 pd;
e126ba97
EC		 341};
342
5903325a
EC		 343enum mlx5_res_type {
344 MLX5_RES_QP,
01949d01
HA		 345 MLX5_RES_SRQ,
346 MLX5_RES_XSRQ,
5903325a
EC		 347};
348
349struct mlx5_core_rsc_common {
350 enum mlx5_res_type res;
351 atomic_t refcount;
352 struct completion free;
353};
354
e126ba97 355struct mlx5_core_srq {
01949d01 356 struct mlx5_core_rsc_common common; /* must be first */
e126ba97
EC		 357 u32 srqn;
358 int max;
359 int max_gs;
360 int max_avail_gather;
361 int wqe_shift;
362 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
363
364 atomic_t refcount;
365 struct completion free;
366};
367
368struct mlx5_eq_table {
369 void __iomem *update_ci;
370 void __iomem *update_arm_ci;
233d05d2 371 struct list_head comp_eqs_list;
e126ba97
EC		 372 struct mlx5_eq pages_eq;
373 struct mlx5_eq async_eq;
374 struct mlx5_eq cmd_eq;
e126ba97
EC		 375 int num_comp_vectors;
376 /* protect EQs list
377 */
378 spinlock_t lock;
379};
380
381struct mlx5_uar {
382 u32 index;
383 struct list_head bf_list;
384 unsigned free_bf_bmap;
88a85f99 385 void __iomem *bf_map;
e126ba97
EC		 386 void __iomem *map;
387};
388
389
390struct mlx5_core_health {
391 struct health_buffer __iomem *health;
392 __be32 __iomem *health_counter;
393 struct timer_list timer;
e126ba97
EC		 394 u32 prev;
395 int miss_counter;
fd76ee4d 396 bool sick;
ac6ea6e8
EC		 397 struct workqueue_struct *wq;
398 struct work_struct work;
e126ba97
EC		 399};
400
401struct mlx5_cq_table {
402 /* protect radix tree
403 */
404 spinlock_t lock;
405 struct radix_tree_root tree;
406};
407
408struct mlx5_qp_table {
409 /* protect radix tree
410 */
411 spinlock_t lock;
412 struct radix_tree_root tree;
413};
414
415struct mlx5_srq_table {
416 /* protect radix tree
417 */
418 spinlock_t lock;
419 struct radix_tree_root tree;
420};
421
3bcdb17a
SG		 422struct mlx5_mr_table {
423 /* protect radix tree
424 */
425 rwlock_t lock;
426 struct radix_tree_root tree;
427};
428
fc50db98
EC		 429struct mlx5_vf_context {
430 int enabled;
431};
432
433struct mlx5_core_sriov {
434 struct mlx5_vf_context *vfs_ctx;
435 int num_vfs;
436 int enabled_vfs;
437};
438
db058a18
SM		 439struct mlx5_irq_info {
440 cpumask_var_t mask;
441 char name[MLX5_MAX_IRQ_NAME];
442};
443
e126ba97
EC		 444struct mlx5_priv {
445 char name[MLX5_MAX_NAME_LEN];
446 struct mlx5_eq_table eq_table;
db058a18
SM		 447 struct msix_entry *msix_arr;
448 struct mlx5_irq_info *irq_info;
e126ba97
EC		 449 struct mlx5_uuar_info uuari;
450 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
451
88a85f99
AS		 452 struct io_mapping *bf_mapping;
453
e126ba97
EC		 454 /* pages stuff */
455 struct workqueue_struct *pg_wq;
456 struct rb_root page_root;
457 int fw_pages;
6aec21f6 458 atomic_t reg_pages;
bf0bf77f 459 struct list_head free_list;
fc50db98 460 int vfs_pages;
e126ba97
EC		 461
462 struct mlx5_core_health health;
463
464 struct mlx5_srq_table srq_table;
465
466 /* start: qp staff */
467 struct mlx5_qp_table qp_table;
468 struct dentry *qp_debugfs;
469 struct dentry *eq_debugfs;
470 struct dentry *cq_debugfs;
471 struct dentry *cmdif_debugfs;
472 /* end: qp staff */
473
474 /* start: cq staff */
475 struct mlx5_cq_table cq_table;
476 /* end: cq staff */
477
3bcdb17a
SG		 478 /* start: mr staff */
479 struct mlx5_mr_table mr_table;
480 /* end: mr staff */
481
e126ba97 482 /* start: alloc staff */
311c7c71
SM		 483 /* protect buffer alocation according to numa node */
484 struct mutex alloc_mutex;
485 int numa_node;
486
e126ba97
EC		 487 struct mutex pgdir_mutex;
488 struct list_head pgdir_list;
489 /* end: alloc staff */
490 struct dentry *dbg_root;
491
492 /* protect mkey key part */
493 spinlock_t mkey_lock;
494 u8 mkey_key;
9603b61d
JM		 495
496 struct list_head dev_list;
497 struct list_head ctx_list;
498 spinlock_t ctx_lock;
fc50db98
EC		 499 struct mlx5_core_sriov sriov;
500 unsigned long pci_dev_data;
e126ba97
EC		 501};
502
89d44f0a
MD		 503enum mlx5_device_state {
504 MLX5_DEVICE_STATE_UP,
505 MLX5_DEVICE_STATE_INTERNAL_ERROR,
506};
507
508enum mlx5_interface_state {
509 MLX5_INTERFACE_STATE_DOWN,
510 MLX5_INTERFACE_STATE_UP,
511};
512
513enum mlx5_pci_status {
514 MLX5_PCI_STATUS_DISABLED,
515 MLX5_PCI_STATUS_ENABLED,
516};
517
e126ba97
EC		 518struct mlx5_core_dev {
519 struct pci_dev *pdev;
89d44f0a
MD		 520 /* sync pci state */
521 struct mutex pci_status_mutex;
522 enum mlx5_pci_status pci_status;
e126ba97
EC		 523 u8 rev_id;
524 char board_id[MLX5_BOARD_ID_LEN];
525 struct mlx5_cmd cmd;
938fe83c
SM		 526 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
527 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
528 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
e126ba97
EC		 529 phys_addr_t iseg_base;
530 struct mlx5_init_seg __iomem *iseg;
89d44f0a
MD		 531 enum mlx5_device_state state;
532 /* sync interface state */
533 struct mutex intf_state_mutex;
534 enum mlx5_interface_state interface_state;
e126ba97
EC		 535 void (*event) (struct mlx5_core_dev *dev,
536 enum mlx5_dev_event event,
4d2f9bbb 537 unsigned long param);
e126ba97
EC		 538 struct mlx5_priv priv;
539 struct mlx5_profile *profile;
540 atomic_t num_qps;
f62b8bb8 541 u32 issi;
e126ba97
EC		 542};
543
544struct mlx5_db {
545 __be32 *db;
546 union {
547 struct mlx5_db_pgdir *pgdir;
548 struct mlx5_ib_user_db_page *user_page;
549 } u;
550 dma_addr_t dma;
551 int index;
552};
553
554enum {
555 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES,
556};
557
558enum {
559 MLX5_COMP_EQ_SIZE = 1024,
560};
561
adb0c954
SM		 562enum {
563 MLX5_PTYS_IB = 1 << 0,
564 MLX5_PTYS_EN = 1 << 2,
565};
566
e126ba97
EC		 567struct mlx5_db_pgdir {
568 struct list_head list;
569 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
570 __be32 *db_page;
571 dma_addr_t db_dma;
572};
573
574typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
575
576struct mlx5_cmd_work_ent {
577 struct mlx5_cmd_msg *in;
578 struct mlx5_cmd_msg *out;
746b5583
EC		 579 void *uout;
580 int uout_size;
e126ba97
EC		 581 mlx5_cmd_cbk_t callback;
582 void *context;
746b5583 583 int idx;
e126ba97
EC		 584 struct completion done;
585 struct mlx5_cmd *cmd;
586 struct work_struct work;
587 struct mlx5_cmd_layout *lay;
588 int ret;
589 int page_queue;
590 u8 status;
591 u8 token;
14a70046
TG		 592 u64 ts1;
593 u64 ts2;
746b5583 594 u16 op;
e126ba97
EC		 595};
596
597struct mlx5_pas {
598 u64 pa;
599 u8 log_sz;
600};
601
707c4602
MD		 602enum port_state_policy {
603 MLX5_AAA_000
604};
605
606enum phy_port_state {
607 MLX5_AAA_111
608};
609
610struct mlx5_hca_vport_context {
611 u32 field_select;
612 bool sm_virt_aware;
613 bool has_smi;
614 bool has_raw;
615 enum port_state_policy policy;
616 enum phy_port_state phys_state;
617 enum ib_port_state vport_state;
618 u8 port_physical_state;
619 u64 sys_image_guid;
620 u64 port_guid;
621 u64 node_guid;
622 u32 cap_mask1;
623 u32 cap_mask1_perm;
624 u32 cap_mask2;
625 u32 cap_mask2_perm;
626 u16 lid;
627 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
628 u8 lmc;
629 u8 subnet_timeout;
630 u16 sm_lid;
631 u8 sm_sl;
632 u16 qkey_violation_counter;
633 u16 pkey_violation_counter;
634 bool grh_required;
635};
636
e126ba97
EC		 637static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
638{
e126ba97 639 return buf->direct.buf + offset;
e126ba97
EC		 640}
641
642extern struct workqueue_struct *mlx5_core_wq;
643
644#define STRUCT_FIELD(header, field) \
645 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
646 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
647
648struct ib_field {
649 size_t struct_offset_bytes;
650 size_t struct_size_bytes;
651 int offset_bits;
652 int size_bits;
653};
654
655static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
656{
657 return pci_get_drvdata(pdev);
658}
659
660extern struct dentry *mlx5_debugfs_root;
661
662static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
663{
664 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
665}
666
667static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
668{
669 return ioread32be(&dev->iseg->fw_rev) >> 16;
670}
671
672static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
673{
674 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
675}
676
677static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
678{
679 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
680}
681
682static inline void *mlx5_vzalloc(unsigned long size)
683{
684 void *rtn;
685
686 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
687 if (!rtn)
688 rtn = vzalloc(size);
689 return rtn;
690}
691
3bcdb17a
SG		 692static inline u32 mlx5_base_mkey(const u32 key)
693{
694 return key & 0xffffff00u;
695}
696
e126ba97
EC		 697int mlx5_cmd_init(struct mlx5_core_dev *dev);
698void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
699void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
700void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
701int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
b775516b 702int mlx5_cmd_status_to_err_v2(void *ptr);
938fe83c
SM		 703int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
704 enum mlx5_cap_mode cap_mode);
e126ba97
EC		 705int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
706 int out_size);
746b5583
EC		 707int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
708 void *out, int out_size, mlx5_cmd_cbk_t callback,
709 void *context);
e126ba97
EC		 710int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
711int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
712int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
713int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
e281682b
SM		 714int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
715void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
ac6ea6e8
EC		 716void mlx5_health_cleanup(struct mlx5_core_dev *dev);
717int mlx5_health_init(struct mlx5_core_dev *dev);
e126ba97
EC		 718void mlx5_start_health_poll(struct mlx5_core_dev *dev);
719void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
311c7c71
SM		 720int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
721 struct mlx5_buf *buf, int node);
64ffaa21 722int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
e126ba97
EC		 723void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
724struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
725 gfp_t flags, int npages);
726void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
727 struct mlx5_cmd_mailbox *head);
728int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
01949d01
HA		 729 struct mlx5_create_srq_mbox_in *in, int inlen,
730 int is_xrc);
e126ba97
EC		 731int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
732int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
733 struct mlx5_query_srq_mbox_out *out);
734int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
735 u16 lwm, int is_srq);
3bcdb17a
SG		 736void mlx5_init_mr_table(struct mlx5_core_dev *dev);
737void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
e126ba97 738int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
746b5583
EC		 739 struct mlx5_create_mkey_mbox_in *in, int inlen,
740 mlx5_cmd_cbk_t callback, void *context,
741 struct mlx5_create_mkey_mbox_out *out);
e126ba97
EC		 742int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr);
743int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
744 struct mlx5_query_mkey_mbox_out *out, int outlen);
745int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
746 u32 *mkey);
747int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
748int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
a97e2d86 749int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
f241e749 750 u16 opmod, u8 port);
e126ba97
EC		 751void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
752void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
753int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
754void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
fc50db98
EC		 755int mlx5_sriov_init(struct mlx5_core_dev *dev);
756int mlx5_sriov_cleanup(struct mlx5_core_dev *dev);
e126ba97 757void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
0a324f31 758 s32 npages);
cd23b14b 759int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
e126ba97
EC		 760int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
761void mlx5_register_debugfs(void);
762void mlx5_unregister_debugfs(void);
763int mlx5_eq_init(struct mlx5_core_dev *dev);
764void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
765void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
766void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
5903325a 767void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
e420f0c0
HE		 768#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
769void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
770#endif
e126ba97
EC		 771void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
772struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
020446e0 773void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec);
e126ba97
EC		 774void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
775int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
776 int nent, u64 mask, const char *name, struct mlx5_uar *uar);
777int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
778int mlx5_start_eqs(struct mlx5_core_dev *dev);
779int mlx5_stop_eqs(struct mlx5_core_dev *dev);
233d05d2 780int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
e126ba97
EC		 781int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
782int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
783
784int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
785void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
786int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
787 int size_in, void *data_out, int size_out,
788 u16 reg_num, int arg, int write);
adb0c954 789
f241e749 790int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
adb0c954 791int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
a05bdefa 792 int ptys_size, int proto_mask, u8 local_port);
adb0c954
SM		 793int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
794 u32 *proto_cap, int proto_mask);
795int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
796 u32 *proto_admin, int proto_mask);
a124d13e
MD		 797int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
798 u8 *link_width_oper, u8 local_port);
799int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev,
800 u8 *proto_oper, int proto_mask,
801 u8 local_port);
adb0c954
SM		 802int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
803 int proto_mask);
6fa1bcab
AS		 804int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
805 enum mlx5_port_status status);
806int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
807 enum mlx5_port_status *status);
e126ba97 808
facc9699
SM		 809int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu, u8 port);
810void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu, u8 port);
811void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu,
812 u8 port);
813
a124d13e
MD		 814int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
815 u8 *vl_hw_cap, u8 local_port);
e126ba97 816
3c2d18ef
AS		 817int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause);
818int mlx5_query_port_pause(struct mlx5_core_dev *dev,
819 u32 *rx_pause, u32 *tx_pause);
820
e126ba97
EC		 821int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
822void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
823int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
824 struct mlx5_query_eq_mbox_out *out, int outlen);
825int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
826void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
827int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
828void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
829int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
311c7c71
SM		 830int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
831 int node);
e126ba97
EC		 832void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
833
e126ba97
EC		 834const char *mlx5_command_str(int command);
835int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
836void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
3121e3c4
SG		 837int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
838 int npsvs, u32 *sig_index);
839int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
5903325a 840void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
e420f0c0
HE		 841int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
842 struct mlx5_odp_caps *odp_caps);
e126ba97 843
e3297246
EC		 844static inline int fw_initializing(struct mlx5_core_dev *dev)
845{
846 return ioread32be(&dev->iseg->initializing) >> 31;
847}
848
e126ba97
EC		 849static inline u32 mlx5_mkey_to_idx(u32 mkey)
850{
851 return mkey >> 8;
852}
853
854static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
855{
856 return mkey_idx << 8;
857}
858
746b5583
EC		 859static inline u8 mlx5_mkey_variant(u32 mkey)
860{
861 return mkey & 0xff;
862}
863
e126ba97
EC		 864enum {
865 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
c1868b82 866 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
e126ba97
EC		 867};
868
869enum {
870 MAX_MR_CACHE_ENTRIES = 16,
871};
872
64613d94
SM		 873enum {
874 MLX5_INTERFACE_PROTOCOL_IB = 0,
875 MLX5_INTERFACE_PROTOCOL_ETH = 1,
876};
877
9603b61d
JM		 878struct mlx5_interface {
879 void * (*add)(struct mlx5_core_dev *dev);
880 void (*remove)(struct mlx5_core_dev *dev, void *context);
881 void (*event)(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 882 enum mlx5_dev_event event, unsigned long param);
64613d94
SM		 883 void * (*get_dev)(void *context);
884 int protocol;
9603b61d
JM		 885 struct list_head list;
886};
887
64613d94 888void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
9603b61d
JM		 889int mlx5_register_interface(struct mlx5_interface *intf);
890void mlx5_unregister_interface(struct mlx5_interface *intf);
211e6c80 891int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
9603b61d 892
e126ba97
EC		 893struct mlx5_profile {
894 u64 mask;
f241e749 895 u8 log_max_qp;
e126ba97
EC		 896 struct {
897 int size;
898 int limit;
899 } mr_cache[MAX_MR_CACHE_ENTRIES];
900};
901
fc50db98
EC		 902enum {
903 MLX5_PCI_DEV_IS_VF = 1 << 0,
904};
905
906static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
907{
908 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
909}
910
707c4602
MD		 911static inline int mlx5_get_gid_table_len(u16 param)
912{
913 if (param > 4) {
914 pr_warn("gid table length is zero\n");
915 return 0;
916 }
917
918 return 8 * (1 << param);
919}
920
020446e0
EC		 921enum {
922 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
923};
924
e126ba97 925#endif /* MLX5_DRIVER_H */
Linux 6.x block layer and io_uring tree(s)