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net/mlx5e: Take advantage of the light-weight netdev open/stop
[linux-2.6-block.git] / include / linux / mlx5 / driver.h
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DRIVER_H
34#define MLX5_DRIVER_H
35
36#include <linux/kernel.h>
37#include <linux/completion.h>
38#include <linux/pci.h>
39#include <linux/spinlock_types.h>
40#include <linux/semaphore.h>
6ecde51d 41#include <linux/slab.h>
e126ba97
EC		 42#include <linux/vmalloc.h>
43#include <linux/radix-tree.h>
6ecde51d 44
e126ba97
EC		 45#include <linux/mlx5/device.h>
46#include <linux/mlx5/doorbell.h>
47
48enum {
49 MLX5_BOARD_ID_LEN = 64,
50 MLX5_MAX_NAME_LEN = 16,
51};
52
53enum {
54 /* one minute for the sake of bringup. Generally, commands must always
55 * complete and we may need to increase this timeout value
56 */
57 MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000,
58 MLX5_CMD_WQ_MAX_NAME = 32,
59};
60
61enum {
62 CMD_OWNER_SW = 0x0,
63 CMD_OWNER_HW = 0x1,
64 CMD_STATUS_SUCCESS = 0,
65};
66
67enum mlx5_sqp_t {
68 MLX5_SQP_SMI = 0,
69 MLX5_SQP_GSI = 1,
70 MLX5_SQP_IEEE_1588 = 2,
71 MLX5_SQP_SNIFFER = 3,
72 MLX5_SQP_SYNC_UMR = 4,
73};
74
75enum {
76 MLX5_MAX_PORTS = 2,
77};
78
79enum {
80 MLX5_EQ_VEC_PAGES = 0,
81 MLX5_EQ_VEC_CMD = 1,
82 MLX5_EQ_VEC_ASYNC = 2,
83 MLX5_EQ_VEC_COMP_BASE,
84};
85
86enum {
db058a18 87 MLX5_MAX_IRQ_NAME = 32
e126ba97
EC		 88};
89
90enum {
91 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
92 MLX5_ATOMIC_MODE_CX = 2 << 16,
93 MLX5_ATOMIC_MODE_8B = 3 << 16,
94 MLX5_ATOMIC_MODE_16B = 4 << 16,
95 MLX5_ATOMIC_MODE_32B = 5 << 16,
96 MLX5_ATOMIC_MODE_64B = 6 << 16,
97 MLX5_ATOMIC_MODE_128B = 7 << 16,
98 MLX5_ATOMIC_MODE_256B = 8 << 16,
99};
100
e126ba97
EC		 101enum {
102 MLX5_REG_PCAP = 0x5001,
103 MLX5_REG_PMTU = 0x5003,
104 MLX5_REG_PTYS = 0x5004,
105 MLX5_REG_PAOS = 0x5006,
106 MLX5_REG_PMAOS = 0x5012,
107 MLX5_REG_PUDE = 0x5009,
108 MLX5_REG_PMPE = 0x5010,
109 MLX5_REG_PELC = 0x500e,
a124d13e 110 MLX5_REG_PVLC = 0x500f,
e126ba97
EC		 111 MLX5_REG_PMLP = 0, /* TBD */
112 MLX5_REG_NODE_DESC = 0x6001,
113 MLX5_REG_HOST_ENDIANNESS = 0x7004,
114};
115
e420f0c0
HE		 116enum mlx5_page_fault_resume_flags {
117 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
118 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
119 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
120 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
121};
122
e126ba97
EC		 123enum dbg_rsc_type {
124 MLX5_DBG_RSC_QP,
125 MLX5_DBG_RSC_EQ,
126 MLX5_DBG_RSC_CQ,
127};
128
129struct mlx5_field_desc {
130 struct dentry *dent;
131 int i;
132};
133
134struct mlx5_rsc_debug {
135 struct mlx5_core_dev *dev;
136 void *object;
137 enum dbg_rsc_type type;
138 struct dentry *root;
139 struct mlx5_field_desc fields[0];
140};
141
142enum mlx5_dev_event {
143 MLX5_DEV_EVENT_SYS_ERROR,
144 MLX5_DEV_EVENT_PORT_UP,
145 MLX5_DEV_EVENT_PORT_DOWN,
146 MLX5_DEV_EVENT_PORT_INITIALIZED,
147 MLX5_DEV_EVENT_LID_CHANGE,
148 MLX5_DEV_EVENT_PKEY_CHANGE,
149 MLX5_DEV_EVENT_GUID_CHANGE,
150 MLX5_DEV_EVENT_CLIENT_REREG,
151};
152
4c916a79
RS		 153enum mlx5_port_status {
154 MLX5_PORT_UP = 1 << 1,
155 MLX5_PORT_DOWN = 1 << 2,
156};
157
e126ba97
EC		 158struct mlx5_uuar_info {
159 struct mlx5_uar *uars;
160 int num_uars;
161 int num_low_latency_uuars;
162 unsigned long *bitmap;
163 unsigned int *count;
164 struct mlx5_bf *bfs;
165
166 /*
167 * protect uuar allocation data structs
168 */
169 struct mutex lock;
78c0f98c 170 u32 ver;
e126ba97
EC		 171};
172
173struct mlx5_bf {
174 void __iomem *reg;
175 void __iomem *regreg;
176 int buf_size;
177 struct mlx5_uar *uar;
178 unsigned long offset;
179 int need_lock;
180 /* protect blue flame buffer selection when needed
181 */
182 spinlock_t lock;
183
184 /* serialize 64 bit writes when done as two 32 bit accesses
185 */
186 spinlock_t lock32;
187 int uuarn;
188};
189
190struct mlx5_cmd_first {
191 __be32 data[4];
192};
193
194struct mlx5_cmd_msg {
195 struct list_head list;
196 struct cache_ent *cache;
197 u32 len;
198 struct mlx5_cmd_first first;
199 struct mlx5_cmd_mailbox *next;
200};
201
202struct mlx5_cmd_debug {
203 struct dentry *dbg_root;
204 struct dentry *dbg_in;
205 struct dentry *dbg_out;
206 struct dentry *dbg_outlen;
207 struct dentry *dbg_status;
208 struct dentry *dbg_run;
209 void *in_msg;
210 void *out_msg;
211 u8 status;
212 u16 inlen;
213 u16 outlen;
214};
215
216struct cache_ent {
217 /* protect block chain allocations
218 */
219 spinlock_t lock;
220 struct list_head head;
221};
222
223struct cmd_msg_cache {
224 struct cache_ent large;
225 struct cache_ent med;
226
227};
228
229struct mlx5_cmd_stats {
230 u64 sum;
231 u64 n;
232 struct dentry *root;
233 struct dentry *avg;
234 struct dentry *count;
235 /* protect command average calculations */
236 spinlock_t lock;
237};
238
239struct mlx5_cmd {
64599cca
EC		 240 void *cmd_alloc_buf;
241 dma_addr_t alloc_dma;
242 int alloc_size;
e126ba97
EC		 243 void *cmd_buf;
244 dma_addr_t dma;
245 u16 cmdif_rev;
246 u8 log_sz;
247 u8 log_stride;
248 int max_reg_cmds;
249 int events;
250 u32 __iomem *vector;
251
252 /* protect command queue allocations
253 */
254 spinlock_t alloc_lock;
255
256 /* protect token allocations
257 */
258 spinlock_t token_lock;
259 u8 token;
260 unsigned long bitmask;
261 char wq_name[MLX5_CMD_WQ_MAX_NAME];
262 struct workqueue_struct *wq;
263 struct semaphore sem;
264 struct semaphore pages_sem;
265 int mode;
266 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
267 struct pci_pool *pool;
268 struct mlx5_cmd_debug dbg;
269 struct cmd_msg_cache cache;
270 int checksum_disabled;
271 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
272};
273
274struct mlx5_port_caps {
275 int gid_table_len;
276 int pkey_table_len;
938fe83c 277 u8 ext_port_cap;
e126ba97
EC		 278};
279
280struct mlx5_cmd_mailbox {
281 void *buf;
282 dma_addr_t dma;
283 struct mlx5_cmd_mailbox *next;
284};
285
286struct mlx5_buf_list {
287 void *buf;
288 dma_addr_t map;
289};
290
291struct mlx5_buf {
292 struct mlx5_buf_list direct;
e126ba97 293 int npages;
e126ba97 294 int size;
f241e749 295 u8 page_shift;
e126ba97
EC		 296};
297
298struct mlx5_eq {
299 struct mlx5_core_dev *dev;
300 __be32 __iomem *doorbell;
301 u32 cons_index;
302 struct mlx5_buf buf;
303 int size;
304 u8 irqn;
305 u8 eqn;
306 int nent;
307 u64 mask;
e126ba97
EC		 308 struct list_head list;
309 int index;
310 struct mlx5_rsc_debug *dbg;
311};
312
3121e3c4
SG		 313struct mlx5_core_psv {
314 u32 psv_idx;
315 struct psv_layout {
316 u32 pd;
317 u16 syndrome;
318 u16 reserved;
319 u16 bg;
320 u16 app_tag;
321 u32 ref_tag;
322 } psv;
323};
324
325struct mlx5_core_sig_ctx {
326 struct mlx5_core_psv psv_memory;
327 struct mlx5_core_psv psv_wire;
d5436ba0
SG		 328 struct ib_sig_err err_item;
329 bool sig_status_checked;
330 bool sig_err_exists;
331 u32 sigerr_count;
3121e3c4 332};
e126ba97
EC		 333
334struct mlx5_core_mr {
335 u64 iova;
336 u64 size;
337 u32 key;
338 u32 pd;
e126ba97
EC		 339};
340
5903325a
EC		 341enum mlx5_res_type {
342 MLX5_RES_QP,
01949d01
HA		 343 MLX5_RES_SRQ,
344 MLX5_RES_XSRQ,
5903325a
EC		 345};
346
347struct mlx5_core_rsc_common {
348 enum mlx5_res_type res;
349 atomic_t refcount;
350 struct completion free;
351};
352
e126ba97 353struct mlx5_core_srq {
01949d01 354 struct mlx5_core_rsc_common common; /* must be first */
e126ba97
EC		 355 u32 srqn;
356 int max;
357 int max_gs;
358 int max_avail_gather;
359 int wqe_shift;
360 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
361
362 atomic_t refcount;
363 struct completion free;
364};
365
366struct mlx5_eq_table {
367 void __iomem *update_ci;
368 void __iomem *update_arm_ci;
233d05d2 369 struct list_head comp_eqs_list;
e126ba97
EC		 370 struct mlx5_eq pages_eq;
371 struct mlx5_eq async_eq;
372 struct mlx5_eq cmd_eq;
e126ba97
EC		 373 int num_comp_vectors;
374 /* protect EQs list
375 */
376 spinlock_t lock;
377};
378
379struct mlx5_uar {
380 u32 index;
381 struct list_head bf_list;
382 unsigned free_bf_bmap;
88a85f99 383 void __iomem *bf_map;
e126ba97
EC		 384 void __iomem *map;
385};
386
387
388struct mlx5_core_health {
389 struct health_buffer __iomem *health;
390 __be32 __iomem *health_counter;
391 struct timer_list timer;
392 struct list_head list;
393 u32 prev;
394 int miss_counter;
395};
396
397struct mlx5_cq_table {
398 /* protect radix tree
399 */
400 spinlock_t lock;
401 struct radix_tree_root tree;
402};
403
404struct mlx5_qp_table {
405 /* protect radix tree
406 */
407 spinlock_t lock;
408 struct radix_tree_root tree;
409};
410
411struct mlx5_srq_table {
412 /* protect radix tree
413 */
414 spinlock_t lock;
415 struct radix_tree_root tree;
416};
417
3bcdb17a
SG		 418struct mlx5_mr_table {
419 /* protect radix tree
420 */
421 rwlock_t lock;
422 struct radix_tree_root tree;
423};
424
db058a18
SM		 425struct mlx5_irq_info {
426 cpumask_var_t mask;
427 char name[MLX5_MAX_IRQ_NAME];
428};
429
e126ba97
EC		 430struct mlx5_priv {
431 char name[MLX5_MAX_NAME_LEN];
432 struct mlx5_eq_table eq_table;
db058a18
SM		 433 struct msix_entry *msix_arr;
434 struct mlx5_irq_info *irq_info;
e126ba97
EC		 435 struct mlx5_uuar_info uuari;
436 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
437
88a85f99
AS		 438 struct io_mapping *bf_mapping;
439
e126ba97
EC		 440 /* pages stuff */
441 struct workqueue_struct *pg_wq;
442 struct rb_root page_root;
443 int fw_pages;
6aec21f6 444 atomic_t reg_pages;
bf0bf77f 445 struct list_head free_list;
e126ba97
EC		 446
447 struct mlx5_core_health health;
448
449 struct mlx5_srq_table srq_table;
450
451 /* start: qp staff */
452 struct mlx5_qp_table qp_table;
453 struct dentry *qp_debugfs;
454 struct dentry *eq_debugfs;
455 struct dentry *cq_debugfs;
456 struct dentry *cmdif_debugfs;
457 /* end: qp staff */
458
459 /* start: cq staff */
460 struct mlx5_cq_table cq_table;
461 /* end: cq staff */
462
3bcdb17a
SG		 463 /* start: mr staff */
464 struct mlx5_mr_table mr_table;
465 /* end: mr staff */
466
e126ba97 467 /* start: alloc staff */
311c7c71
SM		 468 /* protect buffer alocation according to numa node */
469 struct mutex alloc_mutex;
470 int numa_node;
471
e126ba97
EC		 472 struct mutex pgdir_mutex;
473 struct list_head pgdir_list;
474 /* end: alloc staff */
475 struct dentry *dbg_root;
476
477 /* protect mkey key part */
478 spinlock_t mkey_lock;
479 u8 mkey_key;
9603b61d
JM		 480
481 struct list_head dev_list;
482 struct list_head ctx_list;
483 spinlock_t ctx_lock;
e126ba97
EC		 484};
485
486struct mlx5_core_dev {
487 struct pci_dev *pdev;
488 u8 rev_id;
489 char board_id[MLX5_BOARD_ID_LEN];
490 struct mlx5_cmd cmd;
938fe83c
SM		 491 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
492 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
493 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
e126ba97
EC		 494 phys_addr_t iseg_base;
495 struct mlx5_init_seg __iomem *iseg;
496 void (*event) (struct mlx5_core_dev *dev,
497 enum mlx5_dev_event event,
4d2f9bbb 498 unsigned long param);
e126ba97
EC		 499 struct mlx5_priv priv;
500 struct mlx5_profile *profile;
501 atomic_t num_qps;
f62b8bb8 502 u32 issi;
e126ba97
EC		 503};
504
505struct mlx5_db {
506 __be32 *db;
507 union {
508 struct mlx5_db_pgdir *pgdir;
509 struct mlx5_ib_user_db_page *user_page;
510 } u;
511 dma_addr_t dma;
512 int index;
513};
514
515enum {
516 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES,
517};
518
519enum {
520 MLX5_COMP_EQ_SIZE = 1024,
521};
522
adb0c954
SM		 523enum {
524 MLX5_PTYS_IB = 1 << 0,
525 MLX5_PTYS_EN = 1 << 2,
526};
527
e126ba97
EC		 528struct mlx5_db_pgdir {
529 struct list_head list;
530 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
531 __be32 *db_page;
532 dma_addr_t db_dma;
533};
534
535typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
536
537struct mlx5_cmd_work_ent {
538 struct mlx5_cmd_msg *in;
539 struct mlx5_cmd_msg *out;
746b5583
EC		 540 void *uout;
541 int uout_size;
e126ba97
EC		 542 mlx5_cmd_cbk_t callback;
543 void *context;
746b5583 544 int idx;
e126ba97
EC		 545 struct completion done;
546 struct mlx5_cmd *cmd;
547 struct work_struct work;
548 struct mlx5_cmd_layout *lay;
549 int ret;
550 int page_queue;
551 u8 status;
552 u8 token;
14a70046
TG		 553 u64 ts1;
554 u64 ts2;
746b5583 555 u16 op;
e126ba97
EC		 556};
557
558struct mlx5_pas {
559 u64 pa;
560 u8 log_sz;
561};
562
707c4602
MD		 563enum port_state_policy {
564 MLX5_AAA_000
565};
566
567enum phy_port_state {
568 MLX5_AAA_111
569};
570
571struct mlx5_hca_vport_context {
572 u32 field_select;
573 bool sm_virt_aware;
574 bool has_smi;
575 bool has_raw;
576 enum port_state_policy policy;
577 enum phy_port_state phys_state;
578 enum ib_port_state vport_state;
579 u8 port_physical_state;
580 u64 sys_image_guid;
581 u64 port_guid;
582 u64 node_guid;
583 u32 cap_mask1;
584 u32 cap_mask1_perm;
585 u32 cap_mask2;
586 u32 cap_mask2_perm;
587 u16 lid;
588 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
589 u8 lmc;
590 u8 subnet_timeout;
591 u16 sm_lid;
592 u8 sm_sl;
593 u16 qkey_violation_counter;
594 u16 pkey_violation_counter;
595 bool grh_required;
596};
597
e126ba97
EC		 598static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
599{
e126ba97 600 return buf->direct.buf + offset;
e126ba97
EC		 601}
602
603extern struct workqueue_struct *mlx5_core_wq;
604
605#define STRUCT_FIELD(header, field) \
606 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
607 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
608
609struct ib_field {
610 size_t struct_offset_bytes;
611 size_t struct_size_bytes;
612 int offset_bits;
613 int size_bits;
614};
615
616static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
617{
618 return pci_get_drvdata(pdev);
619}
620
621extern struct dentry *mlx5_debugfs_root;
622
623static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
624{
625 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
626}
627
628static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
629{
630 return ioread32be(&dev->iseg->fw_rev) >> 16;
631}
632
633static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
634{
635 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
636}
637
638static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
639{
640 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
641}
642
643static inline void *mlx5_vzalloc(unsigned long size)
644{
645 void *rtn;
646
647 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
648 if (!rtn)
649 rtn = vzalloc(size);
650 return rtn;
651}
652
3bcdb17a
SG		 653static inline u32 mlx5_base_mkey(const u32 key)
654{
655 return key & 0xffffff00u;
656}
657
e126ba97
EC		 658int mlx5_cmd_init(struct mlx5_core_dev *dev);
659void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
660void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
661void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
662int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
b775516b 663int mlx5_cmd_status_to_err_v2(void *ptr);
938fe83c
SM		 664int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
665 enum mlx5_cap_mode cap_mode);
e126ba97
EC		 666int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
667 int out_size);
746b5583
EC		 668int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
669 void *out, int out_size, mlx5_cmd_cbk_t callback,
670 void *context);
e126ba97
EC		 671int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
672int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
673int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
674int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
e281682b
SM		 675int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
676void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
e126ba97
EC		 677void mlx5_health_cleanup(void);
678void __init mlx5_health_init(void);
679void mlx5_start_health_poll(struct mlx5_core_dev *dev);
680void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
311c7c71
SM		 681int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
682 struct mlx5_buf *buf, int node);
64ffaa21 683int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
e126ba97
EC		 684void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
685struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
686 gfp_t flags, int npages);
687void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
688 struct mlx5_cmd_mailbox *head);
689int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
01949d01
HA		 690 struct mlx5_create_srq_mbox_in *in, int inlen,
691 int is_xrc);
e126ba97
EC		 692int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
693int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
694 struct mlx5_query_srq_mbox_out *out);
695int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
696 u16 lwm, int is_srq);
3bcdb17a
SG		 697void mlx5_init_mr_table(struct mlx5_core_dev *dev);
698void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
e126ba97 699int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
746b5583
EC		 700 struct mlx5_create_mkey_mbox_in *in, int inlen,
701 mlx5_cmd_cbk_t callback, void *context,
702 struct mlx5_create_mkey_mbox_out *out);
e126ba97
EC		 703int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr);
704int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
705 struct mlx5_query_mkey_mbox_out *out, int outlen);
706int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
707 u32 *mkey);
708int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
709int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
a97e2d86 710int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
f241e749 711 u16 opmod, u8 port);
e126ba97
EC		 712void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
713void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
714int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
715void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
716void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
0a324f31 717 s32 npages);
cd23b14b 718int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
e126ba97
EC		 719int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
720void mlx5_register_debugfs(void);
721void mlx5_unregister_debugfs(void);
722int mlx5_eq_init(struct mlx5_core_dev *dev);
723void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
724void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
725void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
5903325a 726void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
e420f0c0
HE		 727#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
728void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
729#endif
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EC		 730void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
731struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
732void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector);
733void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
734int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
735 int nent, u64 mask, const char *name, struct mlx5_uar *uar);
736int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
737int mlx5_start_eqs(struct mlx5_core_dev *dev);
738int mlx5_stop_eqs(struct mlx5_core_dev *dev);
233d05d2 739int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
e126ba97
EC		 740int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
741int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
742
743int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
744void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
745int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
746 int size_in, void *data_out, int size_out,
747 u16 reg_num, int arg, int write);
adb0c954 748
f241e749 749int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
adb0c954 750int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
a05bdefa 751 int ptys_size, int proto_mask, u8 local_port);
adb0c954
SM		 752int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
753 u32 *proto_cap, int proto_mask);
754int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
755 u32 *proto_admin, int proto_mask);
a124d13e
MD		 756int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
757 u8 *link_width_oper, u8 local_port);
758int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev,
759 u8 *proto_oper, int proto_mask,
760 u8 local_port);
adb0c954
SM		 761int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
762 int proto_mask);
4c916a79
RS		 763int mlx5_set_port_status(struct mlx5_core_dev *dev,
764 enum mlx5_port_status status);
765int mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status);
e126ba97 766
facc9699
SM		 767int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu, u8 port);
768void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu, u8 port);
769void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu,
770 u8 port);
771
a124d13e
MD		 772int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
773 u8 *vl_hw_cap, u8 local_port);
e126ba97
EC		 774
775int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
776void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
777int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
778 struct mlx5_query_eq_mbox_out *out, int outlen);
779int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
780void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
781int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
782void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
783int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
311c7c71
SM		 784int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
785 int node);
e126ba97
EC		 786void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
787
e126ba97
EC		 788const char *mlx5_command_str(int command);
789int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
790void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
3121e3c4
SG		 791int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
792 int npsvs, u32 *sig_index);
793int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
5903325a 794void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
e420f0c0
HE		 795int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
796 struct mlx5_odp_caps *odp_caps);
e126ba97
EC		 797
798static inline u32 mlx5_mkey_to_idx(u32 mkey)
799{
800 return mkey >> 8;
801}
802
803static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
804{
805 return mkey_idx << 8;
806}
807
746b5583
EC		 808static inline u8 mlx5_mkey_variant(u32 mkey)
809{
810 return mkey & 0xff;
811}
812
e126ba97
EC		 813enum {
814 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
c1868b82 815 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
e126ba97
EC		 816};
817
818enum {
819 MAX_MR_CACHE_ENTRIES = 16,
820};
821
64613d94
SM		 822enum {
823 MLX5_INTERFACE_PROTOCOL_IB = 0,
824 MLX5_INTERFACE_PROTOCOL_ETH = 1,
825};
826
9603b61d
JM		 827struct mlx5_interface {
828 void * (*add)(struct mlx5_core_dev *dev);
829 void (*remove)(struct mlx5_core_dev *dev, void *context);
830 void (*event)(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 831 enum mlx5_dev_event event, unsigned long param);
64613d94
SM		 832 void * (*get_dev)(void *context);
833 int protocol;
9603b61d
JM		 834 struct list_head list;
835};
836
64613d94 837void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
9603b61d
JM		 838int mlx5_register_interface(struct mlx5_interface *intf);
839void mlx5_unregister_interface(struct mlx5_interface *intf);
211e6c80 840int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
9603b61d 841
e126ba97
EC		 842struct mlx5_profile {
843 u64 mask;
f241e749 844 u8 log_max_qp;
e126ba97
EC		 845 struct {
846 int size;
847 int limit;
848 } mr_cache[MAX_MR_CACHE_ENTRIES];
849};
850
707c4602
MD		 851static inline int mlx5_get_gid_table_len(u16 param)
852{
853 if (param > 4) {
854 pr_warn("gid table length is zero\n");
855 return 0;
856 }
857
858 return 8 * (1 << param);
859}
860
e126ba97 861#endif /* MLX5_DRIVER_H */
Linux 6.x block layer and io_uring tree(s)