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net/mlx5_core: New device capabilities handling
[linux-2.6-block.git] / include / linux / mlx5 / driver.h
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DRIVER_H
34#define MLX5_DRIVER_H
35
36#include <linux/kernel.h>
37#include <linux/completion.h>
38#include <linux/pci.h>
39#include <linux/spinlock_types.h>
40#include <linux/semaphore.h>
6ecde51d 41#include <linux/slab.h>
e126ba97
EC		 42#include <linux/vmalloc.h>
43#include <linux/radix-tree.h>
6ecde51d 44
e126ba97
EC		 45#include <linux/mlx5/device.h>
46#include <linux/mlx5/doorbell.h>
47
48enum {
49 MLX5_BOARD_ID_LEN = 64,
50 MLX5_MAX_NAME_LEN = 16,
51};
52
53enum {
54 /* one minute for the sake of bringup. Generally, commands must always
55 * complete and we may need to increase this timeout value
56 */
57 MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000,
58 MLX5_CMD_WQ_MAX_NAME = 32,
59};
60
61enum {
62 CMD_OWNER_SW = 0x0,
63 CMD_OWNER_HW = 0x1,
64 CMD_STATUS_SUCCESS = 0,
65};
66
67enum mlx5_sqp_t {
68 MLX5_SQP_SMI = 0,
69 MLX5_SQP_GSI = 1,
70 MLX5_SQP_IEEE_1588 = 2,
71 MLX5_SQP_SNIFFER = 3,
72 MLX5_SQP_SYNC_UMR = 4,
73};
74
75enum {
76 MLX5_MAX_PORTS = 2,
77};
78
79enum {
80 MLX5_EQ_VEC_PAGES = 0,
81 MLX5_EQ_VEC_CMD = 1,
82 MLX5_EQ_VEC_ASYNC = 2,
83 MLX5_EQ_VEC_COMP_BASE,
84};
85
86enum {
db058a18 87 MLX5_MAX_IRQ_NAME = 32
e126ba97
EC		 88};
89
90enum {
91 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
92 MLX5_ATOMIC_MODE_CX = 2 << 16,
93 MLX5_ATOMIC_MODE_8B = 3 << 16,
94 MLX5_ATOMIC_MODE_16B = 4 << 16,
95 MLX5_ATOMIC_MODE_32B = 5 << 16,
96 MLX5_ATOMIC_MODE_64B = 6 << 16,
97 MLX5_ATOMIC_MODE_128B = 7 << 16,
98 MLX5_ATOMIC_MODE_256B = 8 << 16,
99};
100
e126ba97
EC		 101enum {
102 MLX5_REG_PCAP = 0x5001,
103 MLX5_REG_PMTU = 0x5003,
104 MLX5_REG_PTYS = 0x5004,
105 MLX5_REG_PAOS = 0x5006,
106 MLX5_REG_PMAOS = 0x5012,
107 MLX5_REG_PUDE = 0x5009,
108 MLX5_REG_PMPE = 0x5010,
109 MLX5_REG_PELC = 0x500e,
110 MLX5_REG_PMLP = 0, /* TBD */
111 MLX5_REG_NODE_DESC = 0x6001,
112 MLX5_REG_HOST_ENDIANNESS = 0x7004,
113};
114
e420f0c0
HE		 115enum mlx5_page_fault_resume_flags {
116 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
117 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
118 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
119 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
120};
121
e126ba97
EC		 122enum dbg_rsc_type {
123 MLX5_DBG_RSC_QP,
124 MLX5_DBG_RSC_EQ,
125 MLX5_DBG_RSC_CQ,
126};
127
128struct mlx5_field_desc {
129 struct dentry *dent;
130 int i;
131};
132
133struct mlx5_rsc_debug {
134 struct mlx5_core_dev *dev;
135 void *object;
136 enum dbg_rsc_type type;
137 struct dentry *root;
138 struct mlx5_field_desc fields[0];
139};
140
141enum mlx5_dev_event {
142 MLX5_DEV_EVENT_SYS_ERROR,
143 MLX5_DEV_EVENT_PORT_UP,
144 MLX5_DEV_EVENT_PORT_DOWN,
145 MLX5_DEV_EVENT_PORT_INITIALIZED,
146 MLX5_DEV_EVENT_LID_CHANGE,
147 MLX5_DEV_EVENT_PKEY_CHANGE,
148 MLX5_DEV_EVENT_GUID_CHANGE,
149 MLX5_DEV_EVENT_CLIENT_REREG,
150};
151
152struct mlx5_uuar_info {
153 struct mlx5_uar *uars;
154 int num_uars;
155 int num_low_latency_uuars;
156 unsigned long *bitmap;
157 unsigned int *count;
158 struct mlx5_bf *bfs;
159
160 /*
161 * protect uuar allocation data structs
162 */
163 struct mutex lock;
78c0f98c 164 u32 ver;
e126ba97
EC		 165};
166
167struct mlx5_bf {
168 void __iomem *reg;
169 void __iomem *regreg;
170 int buf_size;
171 struct mlx5_uar *uar;
172 unsigned long offset;
173 int need_lock;
174 /* protect blue flame buffer selection when needed
175 */
176 spinlock_t lock;
177
178 /* serialize 64 bit writes when done as two 32 bit accesses
179 */
180 spinlock_t lock32;
181 int uuarn;
182};
183
184struct mlx5_cmd_first {
185 __be32 data[4];
186};
187
188struct mlx5_cmd_msg {
189 struct list_head list;
190 struct cache_ent *cache;
191 u32 len;
192 struct mlx5_cmd_first first;
193 struct mlx5_cmd_mailbox *next;
194};
195
196struct mlx5_cmd_debug {
197 struct dentry *dbg_root;
198 struct dentry *dbg_in;
199 struct dentry *dbg_out;
200 struct dentry *dbg_outlen;
201 struct dentry *dbg_status;
202 struct dentry *dbg_run;
203 void *in_msg;
204 void *out_msg;
205 u8 status;
206 u16 inlen;
207 u16 outlen;
208};
209
210struct cache_ent {
211 /* protect block chain allocations
212 */
213 spinlock_t lock;
214 struct list_head head;
215};
216
217struct cmd_msg_cache {
218 struct cache_ent large;
219 struct cache_ent med;
220
221};
222
223struct mlx5_cmd_stats {
224 u64 sum;
225 u64 n;
226 struct dentry *root;
227 struct dentry *avg;
228 struct dentry *count;
229 /* protect command average calculations */
230 spinlock_t lock;
231};
232
233struct mlx5_cmd {
64599cca
EC		 234 void *cmd_alloc_buf;
235 dma_addr_t alloc_dma;
236 int alloc_size;
e126ba97
EC		 237 void *cmd_buf;
238 dma_addr_t dma;
239 u16 cmdif_rev;
240 u8 log_sz;
241 u8 log_stride;
242 int max_reg_cmds;
243 int events;
244 u32 __iomem *vector;
245
246 /* protect command queue allocations
247 */
248 spinlock_t alloc_lock;
249
250 /* protect token allocations
251 */
252 spinlock_t token_lock;
253 u8 token;
254 unsigned long bitmask;
255 char wq_name[MLX5_CMD_WQ_MAX_NAME];
256 struct workqueue_struct *wq;
257 struct semaphore sem;
258 struct semaphore pages_sem;
259 int mode;
260 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
261 struct pci_pool *pool;
262 struct mlx5_cmd_debug dbg;
263 struct cmd_msg_cache cache;
264 int checksum_disabled;
265 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
266};
267
268struct mlx5_port_caps {
269 int gid_table_len;
270 int pkey_table_len;
938fe83c 271 u8 ext_port_cap;
e126ba97
EC		 272};
273
274struct mlx5_cmd_mailbox {
275 void *buf;
276 dma_addr_t dma;
277 struct mlx5_cmd_mailbox *next;
278};
279
280struct mlx5_buf_list {
281 void *buf;
282 dma_addr_t map;
283};
284
285struct mlx5_buf {
286 struct mlx5_buf_list direct;
e126ba97 287 int npages;
e126ba97 288 int size;
f241e749 289 u8 page_shift;
e126ba97
EC		 290};
291
292struct mlx5_eq {
293 struct mlx5_core_dev *dev;
294 __be32 __iomem *doorbell;
295 u32 cons_index;
296 struct mlx5_buf buf;
297 int size;
298 u8 irqn;
299 u8 eqn;
300 int nent;
301 u64 mask;
e126ba97
EC		 302 struct list_head list;
303 int index;
304 struct mlx5_rsc_debug *dbg;
305};
306
3121e3c4
SG		 307struct mlx5_core_psv {
308 u32 psv_idx;
309 struct psv_layout {
310 u32 pd;
311 u16 syndrome;
312 u16 reserved;
313 u16 bg;
314 u16 app_tag;
315 u32 ref_tag;
316 } psv;
317};
318
319struct mlx5_core_sig_ctx {
320 struct mlx5_core_psv psv_memory;
321 struct mlx5_core_psv psv_wire;
d5436ba0
SG		 322 struct ib_sig_err err_item;
323 bool sig_status_checked;
324 bool sig_err_exists;
325 u32 sigerr_count;
3121e3c4 326};
e126ba97
EC		 327
328struct mlx5_core_mr {
329 u64 iova;
330 u64 size;
331 u32 key;
332 u32 pd;
e126ba97
EC		 333};
334
5903325a
EC		 335enum mlx5_res_type {
336 MLX5_RES_QP,
337};
338
339struct mlx5_core_rsc_common {
340 enum mlx5_res_type res;
341 atomic_t refcount;
342 struct completion free;
343};
344
e126ba97
EC		 345struct mlx5_core_srq {
346 u32 srqn;
347 int max;
348 int max_gs;
349 int max_avail_gather;
350 int wqe_shift;
351 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
352
353 atomic_t refcount;
354 struct completion free;
355};
356
357struct mlx5_eq_table {
358 void __iomem *update_ci;
359 void __iomem *update_arm_ci;
233d05d2 360 struct list_head comp_eqs_list;
e126ba97
EC		 361 struct mlx5_eq pages_eq;
362 struct mlx5_eq async_eq;
363 struct mlx5_eq cmd_eq;
e126ba97
EC		 364 int num_comp_vectors;
365 /* protect EQs list
366 */
367 spinlock_t lock;
368};
369
370struct mlx5_uar {
371 u32 index;
372 struct list_head bf_list;
373 unsigned free_bf_bmap;
374 void __iomem *wc_map;
375 void __iomem *map;
376};
377
378
379struct mlx5_core_health {
380 struct health_buffer __iomem *health;
381 __be32 __iomem *health_counter;
382 struct timer_list timer;
383 struct list_head list;
384 u32 prev;
385 int miss_counter;
386};
387
388struct mlx5_cq_table {
389 /* protect radix tree
390 */
391 spinlock_t lock;
392 struct radix_tree_root tree;
393};
394
395struct mlx5_qp_table {
396 /* protect radix tree
397 */
398 spinlock_t lock;
399 struct radix_tree_root tree;
400};
401
402struct mlx5_srq_table {
403 /* protect radix tree
404 */
405 spinlock_t lock;
406 struct radix_tree_root tree;
407};
408
3bcdb17a
SG		 409struct mlx5_mr_table {
410 /* protect radix tree
411 */
412 rwlock_t lock;
413 struct radix_tree_root tree;
414};
415
db058a18
SM		 416struct mlx5_irq_info {
417 cpumask_var_t mask;
418 char name[MLX5_MAX_IRQ_NAME];
419};
420
e126ba97
EC		 421struct mlx5_priv {
422 char name[MLX5_MAX_NAME_LEN];
423 struct mlx5_eq_table eq_table;
db058a18
SM		 424 struct msix_entry *msix_arr;
425 struct mlx5_irq_info *irq_info;
e126ba97
EC		 426 struct mlx5_uuar_info uuari;
427 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
428
429 /* pages stuff */
430 struct workqueue_struct *pg_wq;
431 struct rb_root page_root;
432 int fw_pages;
6aec21f6 433 atomic_t reg_pages;
bf0bf77f 434 struct list_head free_list;
e126ba97
EC		 435
436 struct mlx5_core_health health;
437
438 struct mlx5_srq_table srq_table;
439
440 /* start: qp staff */
441 struct mlx5_qp_table qp_table;
442 struct dentry *qp_debugfs;
443 struct dentry *eq_debugfs;
444 struct dentry *cq_debugfs;
445 struct dentry *cmdif_debugfs;
446 /* end: qp staff */
447
448 /* start: cq staff */
449 struct mlx5_cq_table cq_table;
450 /* end: cq staff */
451
3bcdb17a
SG		 452 /* start: mr staff */
453 struct mlx5_mr_table mr_table;
454 /* end: mr staff */
455
e126ba97
EC		 456 /* start: alloc staff */
457 struct mutex pgdir_mutex;
458 struct list_head pgdir_list;
459 /* end: alloc staff */
460 struct dentry *dbg_root;
461
462 /* protect mkey key part */
463 spinlock_t mkey_lock;
464 u8 mkey_key;
9603b61d
JM		 465
466 struct list_head dev_list;
467 struct list_head ctx_list;
468 spinlock_t ctx_lock;
e126ba97
EC		 469};
470
471struct mlx5_core_dev {
472 struct pci_dev *pdev;
473 u8 rev_id;
474 char board_id[MLX5_BOARD_ID_LEN];
475 struct mlx5_cmd cmd;
938fe83c
SM		 476 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
477 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
478 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
e126ba97
EC		 479 phys_addr_t iseg_base;
480 struct mlx5_init_seg __iomem *iseg;
481 void (*event) (struct mlx5_core_dev *dev,
482 enum mlx5_dev_event event,
4d2f9bbb 483 unsigned long param);
e126ba97
EC		 484 struct mlx5_priv priv;
485 struct mlx5_profile *profile;
486 atomic_t num_qps;
487};
488
489struct mlx5_db {
490 __be32 *db;
491 union {
492 struct mlx5_db_pgdir *pgdir;
493 struct mlx5_ib_user_db_page *user_page;
494 } u;
495 dma_addr_t dma;
496 int index;
497};
498
499enum {
500 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES,
501};
502
503enum {
504 MLX5_COMP_EQ_SIZE = 1024,
505};
506
507struct mlx5_db_pgdir {
508 struct list_head list;
509 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
510 __be32 *db_page;
511 dma_addr_t db_dma;
512};
513
514typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
515
516struct mlx5_cmd_work_ent {
517 struct mlx5_cmd_msg *in;
518 struct mlx5_cmd_msg *out;
746b5583
EC		 519 void *uout;
520 int uout_size;
e126ba97
EC		 521 mlx5_cmd_cbk_t callback;
522 void *context;
746b5583 523 int idx;
e126ba97
EC		 524 struct completion done;
525 struct mlx5_cmd *cmd;
526 struct work_struct work;
527 struct mlx5_cmd_layout *lay;
528 int ret;
529 int page_queue;
530 u8 status;
531 u8 token;
14a70046
TG		 532 u64 ts1;
533 u64 ts2;
746b5583 534 u16 op;
e126ba97
EC		 535};
536
537struct mlx5_pas {
538 u64 pa;
539 u8 log_sz;
540};
541
542static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
543{
e126ba97 544 return buf->direct.buf + offset;
e126ba97
EC		 545}
546
547extern struct workqueue_struct *mlx5_core_wq;
548
549#define STRUCT_FIELD(header, field) \
550 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
551 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
552
553struct ib_field {
554 size_t struct_offset_bytes;
555 size_t struct_size_bytes;
556 int offset_bits;
557 int size_bits;
558};
559
560static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
561{
562 return pci_get_drvdata(pdev);
563}
564
565extern struct dentry *mlx5_debugfs_root;
566
567static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
568{
569 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
570}
571
572static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
573{
574 return ioread32be(&dev->iseg->fw_rev) >> 16;
575}
576
577static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
578{
579 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
580}
581
582static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
583{
584 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
585}
586
587static inline void *mlx5_vzalloc(unsigned long size)
588{
589 void *rtn;
590
591 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
592 if (!rtn)
593 rtn = vzalloc(size);
594 return rtn;
595}
596
3bcdb17a
SG		 597static inline u32 mlx5_base_mkey(const u32 key)
598{
599 return key & 0xffffff00u;
600}
601
e126ba97
EC		 602int mlx5_cmd_init(struct mlx5_core_dev *dev);
603void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
604void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
605void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
606int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
b775516b 607int mlx5_cmd_status_to_err_v2(void *ptr);
938fe83c
SM		 608int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
609 enum mlx5_cap_mode cap_mode);
e126ba97
EC		 610int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
611 int out_size);
746b5583
EC		 612int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
613 void *out, int out_size, mlx5_cmd_cbk_t callback,
614 void *context);
e126ba97
EC		 615int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
616int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
617int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
618int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
e281682b
SM		 619int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
620void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
e126ba97
EC		 621void mlx5_health_cleanup(void);
622void __init mlx5_health_init(void);
623void mlx5_start_health_poll(struct mlx5_core_dev *dev);
624void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
64ffaa21 625int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
e126ba97
EC		 626void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
627struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
628 gfp_t flags, int npages);
629void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
630 struct mlx5_cmd_mailbox *head);
631int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
632 struct mlx5_create_srq_mbox_in *in, int inlen);
633int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
634int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
635 struct mlx5_query_srq_mbox_out *out);
636int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
637 u16 lwm, int is_srq);
3bcdb17a
SG		 638void mlx5_init_mr_table(struct mlx5_core_dev *dev);
639void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
e126ba97 640int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
746b5583
EC		 641 struct mlx5_create_mkey_mbox_in *in, int inlen,
642 mlx5_cmd_cbk_t callback, void *context,
643 struct mlx5_create_mkey_mbox_out *out);
e126ba97
EC		 644int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr);
645int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
646 struct mlx5_query_mkey_mbox_out *out, int outlen);
647int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
648 u32 *mkey);
649int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
650int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
651int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, void *inb, void *outb,
f241e749 652 u16 opmod, u8 port);
e126ba97
EC		 653void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
654void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
655int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
656void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
657void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
0a324f31 658 s32 npages);
cd23b14b 659int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
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EC		 660int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
661void mlx5_register_debugfs(void);
662void mlx5_unregister_debugfs(void);
663int mlx5_eq_init(struct mlx5_core_dev *dev);
664void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
665void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
666void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
5903325a 667void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
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HE		 668#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
669void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
670#endif
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EC		 671void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
672struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
673void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector);
674void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
675int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
676 int nent, u64 mask, const char *name, struct mlx5_uar *uar);
677int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
678int mlx5_start_eqs(struct mlx5_core_dev *dev);
679int mlx5_stop_eqs(struct mlx5_core_dev *dev);
233d05d2 680int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
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EC		 681int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
682int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
683
684int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
685void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
686int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
687 int size_in, void *data_out, int size_out,
688 u16 reg_num, int arg, int write);
f241e749 689int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
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EC		 690
691int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
692void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
693int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
694 struct mlx5_query_eq_mbox_out *out, int outlen);
695int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
696void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
697int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
698void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
699int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
700void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
701
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EC		 702const char *mlx5_command_str(int command);
703int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
704void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
3121e3c4
SG		 705int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
706 int npsvs, u32 *sig_index);
707int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
5903325a 708void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
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HE		 709int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
710 struct mlx5_odp_caps *odp_caps);
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EC		 711
712static inline u32 mlx5_mkey_to_idx(u32 mkey)
713{
714 return mkey >> 8;
715}
716
717static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
718{
719 return mkey_idx << 8;
720}
721
746b5583
EC		 722static inline u8 mlx5_mkey_variant(u32 mkey)
723{
724 return mkey & 0xff;
725}
726
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EC		 727enum {
728 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
c1868b82 729 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
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EC		 730};
731
732enum {
733 MAX_MR_CACHE_ENTRIES = 16,
734};
735
64613d94
SM		 736enum {
737 MLX5_INTERFACE_PROTOCOL_IB = 0,
738 MLX5_INTERFACE_PROTOCOL_ETH = 1,
739};
740
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JM		 741struct mlx5_interface {
742 void * (*add)(struct mlx5_core_dev *dev);
743 void (*remove)(struct mlx5_core_dev *dev, void *context);
744 void (*event)(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 745 enum mlx5_dev_event event, unsigned long param);
64613d94
SM		 746 void * (*get_dev)(void *context);
747 int protocol;
9603b61d
JM		 748 struct list_head list;
749};
750
64613d94 751void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
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JM		 752int mlx5_register_interface(struct mlx5_interface *intf);
753void mlx5_unregister_interface(struct mlx5_interface *intf);
754
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EC		 755struct mlx5_profile {
756 u64 mask;
f241e749 757 u8 log_max_qp;
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EC		 758 struct {
759 int size;
760 int limit;
761 } mr_cache[MAX_MR_CACHE_ENTRIES];
762};
763
764#endif /* MLX5_DRIVER_H */
Linux 6.x block layer and io_uring tree(s)