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net/mlx5_core: Add new query HCA vport commands
[linux-2.6-block.git] / include / linux / mlx5 / driver.h
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DRIVER_H
34#define MLX5_DRIVER_H
35
36#include <linux/kernel.h>
37#include <linux/completion.h>
38#include <linux/pci.h>
39#include <linux/spinlock_types.h>
40#include <linux/semaphore.h>
6ecde51d 41#include <linux/slab.h>
e126ba97
EC		 42#include <linux/vmalloc.h>
43#include <linux/radix-tree.h>
6ecde51d 44
e126ba97
EC		 45#include <linux/mlx5/device.h>
46#include <linux/mlx5/doorbell.h>
47
48enum {
49 MLX5_BOARD_ID_LEN = 64,
50 MLX5_MAX_NAME_LEN = 16,
51};
52
53enum {
54 /* one minute for the sake of bringup. Generally, commands must always
55 * complete and we may need to increase this timeout value
56 */
57 MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000,
58 MLX5_CMD_WQ_MAX_NAME = 32,
59};
60
61enum {
62 CMD_OWNER_SW = 0x0,
63 CMD_OWNER_HW = 0x1,
64 CMD_STATUS_SUCCESS = 0,
65};
66
67enum mlx5_sqp_t {
68 MLX5_SQP_SMI = 0,
69 MLX5_SQP_GSI = 1,
70 MLX5_SQP_IEEE_1588 = 2,
71 MLX5_SQP_SNIFFER = 3,
72 MLX5_SQP_SYNC_UMR = 4,
73};
74
75enum {
76 MLX5_MAX_PORTS = 2,
77};
78
79enum {
80 MLX5_EQ_VEC_PAGES = 0,
81 MLX5_EQ_VEC_CMD = 1,
82 MLX5_EQ_VEC_ASYNC = 2,
83 MLX5_EQ_VEC_COMP_BASE,
84};
85
86enum {
db058a18 87 MLX5_MAX_IRQ_NAME = 32
e126ba97
EC		 88};
89
90enum {
91 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
92 MLX5_ATOMIC_MODE_CX = 2 << 16,
93 MLX5_ATOMIC_MODE_8B = 3 << 16,
94 MLX5_ATOMIC_MODE_16B = 4 << 16,
95 MLX5_ATOMIC_MODE_32B = 5 << 16,
96 MLX5_ATOMIC_MODE_64B = 6 << 16,
97 MLX5_ATOMIC_MODE_128B = 7 << 16,
98 MLX5_ATOMIC_MODE_256B = 8 << 16,
99};
100
e126ba97
EC		 101enum {
102 MLX5_REG_PCAP = 0x5001,
103 MLX5_REG_PMTU = 0x5003,
104 MLX5_REG_PTYS = 0x5004,
105 MLX5_REG_PAOS = 0x5006,
106 MLX5_REG_PMAOS = 0x5012,
107 MLX5_REG_PUDE = 0x5009,
108 MLX5_REG_PMPE = 0x5010,
109 MLX5_REG_PELC = 0x500e,
110 MLX5_REG_PMLP = 0, /* TBD */
111 MLX5_REG_NODE_DESC = 0x6001,
112 MLX5_REG_HOST_ENDIANNESS = 0x7004,
113};
114
e420f0c0
HE		 115enum mlx5_page_fault_resume_flags {
116 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
117 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
118 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
119 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
120};
121
e126ba97
EC		 122enum dbg_rsc_type {
123 MLX5_DBG_RSC_QP,
124 MLX5_DBG_RSC_EQ,
125 MLX5_DBG_RSC_CQ,
126};
127
128struct mlx5_field_desc {
129 struct dentry *dent;
130 int i;
131};
132
133struct mlx5_rsc_debug {
134 struct mlx5_core_dev *dev;
135 void *object;
136 enum dbg_rsc_type type;
137 struct dentry *root;
138 struct mlx5_field_desc fields[0];
139};
140
141enum mlx5_dev_event {
142 MLX5_DEV_EVENT_SYS_ERROR,
143 MLX5_DEV_EVENT_PORT_UP,
144 MLX5_DEV_EVENT_PORT_DOWN,
145 MLX5_DEV_EVENT_PORT_INITIALIZED,
146 MLX5_DEV_EVENT_LID_CHANGE,
147 MLX5_DEV_EVENT_PKEY_CHANGE,
148 MLX5_DEV_EVENT_GUID_CHANGE,
149 MLX5_DEV_EVENT_CLIENT_REREG,
150};
151
4c916a79
RS		 152enum mlx5_port_status {
153 MLX5_PORT_UP = 1 << 1,
154 MLX5_PORT_DOWN = 1 << 2,
155};
156
e126ba97
EC		 157struct mlx5_uuar_info {
158 struct mlx5_uar *uars;
159 int num_uars;
160 int num_low_latency_uuars;
161 unsigned long *bitmap;
162 unsigned int *count;
163 struct mlx5_bf *bfs;
164
165 /*
166 * protect uuar allocation data structs
167 */
168 struct mutex lock;
78c0f98c 169 u32 ver;
e126ba97
EC		 170};
171
172struct mlx5_bf {
173 void __iomem *reg;
174 void __iomem *regreg;
175 int buf_size;
176 struct mlx5_uar *uar;
177 unsigned long offset;
178 int need_lock;
179 /* protect blue flame buffer selection when needed
180 */
181 spinlock_t lock;
182
183 /* serialize 64 bit writes when done as two 32 bit accesses
184 */
185 spinlock_t lock32;
186 int uuarn;
187};
188
189struct mlx5_cmd_first {
190 __be32 data[4];
191};
192
193struct mlx5_cmd_msg {
194 struct list_head list;
195 struct cache_ent *cache;
196 u32 len;
197 struct mlx5_cmd_first first;
198 struct mlx5_cmd_mailbox *next;
199};
200
201struct mlx5_cmd_debug {
202 struct dentry *dbg_root;
203 struct dentry *dbg_in;
204 struct dentry *dbg_out;
205 struct dentry *dbg_outlen;
206 struct dentry *dbg_status;
207 struct dentry *dbg_run;
208 void *in_msg;
209 void *out_msg;
210 u8 status;
211 u16 inlen;
212 u16 outlen;
213};
214
215struct cache_ent {
216 /* protect block chain allocations
217 */
218 spinlock_t lock;
219 struct list_head head;
220};
221
222struct cmd_msg_cache {
223 struct cache_ent large;
224 struct cache_ent med;
225
226};
227
228struct mlx5_cmd_stats {
229 u64 sum;
230 u64 n;
231 struct dentry *root;
232 struct dentry *avg;
233 struct dentry *count;
234 /* protect command average calculations */
235 spinlock_t lock;
236};
237
238struct mlx5_cmd {
64599cca
EC		 239 void *cmd_alloc_buf;
240 dma_addr_t alloc_dma;
241 int alloc_size;
e126ba97
EC		 242 void *cmd_buf;
243 dma_addr_t dma;
244 u16 cmdif_rev;
245 u8 log_sz;
246 u8 log_stride;
247 int max_reg_cmds;
248 int events;
249 u32 __iomem *vector;
250
251 /* protect command queue allocations
252 */
253 spinlock_t alloc_lock;
254
255 /* protect token allocations
256 */
257 spinlock_t token_lock;
258 u8 token;
259 unsigned long bitmask;
260 char wq_name[MLX5_CMD_WQ_MAX_NAME];
261 struct workqueue_struct *wq;
262 struct semaphore sem;
263 struct semaphore pages_sem;
264 int mode;
265 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
266 struct pci_pool *pool;
267 struct mlx5_cmd_debug dbg;
268 struct cmd_msg_cache cache;
269 int checksum_disabled;
270 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
271};
272
273struct mlx5_port_caps {
274 int gid_table_len;
275 int pkey_table_len;
938fe83c 276 u8 ext_port_cap;
e126ba97
EC		 277};
278
279struct mlx5_cmd_mailbox {
280 void *buf;
281 dma_addr_t dma;
282 struct mlx5_cmd_mailbox *next;
283};
284
285struct mlx5_buf_list {
286 void *buf;
287 dma_addr_t map;
288};
289
290struct mlx5_buf {
291 struct mlx5_buf_list direct;
e126ba97 292 int npages;
e126ba97 293 int size;
f241e749 294 u8 page_shift;
e126ba97
EC		 295};
296
297struct mlx5_eq {
298 struct mlx5_core_dev *dev;
299 __be32 __iomem *doorbell;
300 u32 cons_index;
301 struct mlx5_buf buf;
302 int size;
303 u8 irqn;
304 u8 eqn;
305 int nent;
306 u64 mask;
e126ba97
EC		 307 struct list_head list;
308 int index;
309 struct mlx5_rsc_debug *dbg;
310};
311
3121e3c4
SG		 312struct mlx5_core_psv {
313 u32 psv_idx;
314 struct psv_layout {
315 u32 pd;
316 u16 syndrome;
317 u16 reserved;
318 u16 bg;
319 u16 app_tag;
320 u32 ref_tag;
321 } psv;
322};
323
324struct mlx5_core_sig_ctx {
325 struct mlx5_core_psv psv_memory;
326 struct mlx5_core_psv psv_wire;
d5436ba0
SG		 327 struct ib_sig_err err_item;
328 bool sig_status_checked;
329 bool sig_err_exists;
330 u32 sigerr_count;
3121e3c4 331};
e126ba97
EC		 332
333struct mlx5_core_mr {
334 u64 iova;
335 u64 size;
336 u32 key;
337 u32 pd;
e126ba97
EC		 338};
339
5903325a
EC		 340enum mlx5_res_type {
341 MLX5_RES_QP,
01949d01
HA		 342 MLX5_RES_SRQ,
343 MLX5_RES_XSRQ,
5903325a
EC		 344};
345
346struct mlx5_core_rsc_common {
347 enum mlx5_res_type res;
348 atomic_t refcount;
349 struct completion free;
350};
351
e126ba97 352struct mlx5_core_srq {
01949d01 353 struct mlx5_core_rsc_common common; /* must be first */
e126ba97
EC		 354 u32 srqn;
355 int max;
356 int max_gs;
357 int max_avail_gather;
358 int wqe_shift;
359 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
360
361 atomic_t refcount;
362 struct completion free;
363};
364
365struct mlx5_eq_table {
366 void __iomem *update_ci;
367 void __iomem *update_arm_ci;
233d05d2 368 struct list_head comp_eqs_list;
e126ba97
EC		 369 struct mlx5_eq pages_eq;
370 struct mlx5_eq async_eq;
371 struct mlx5_eq cmd_eq;
e126ba97
EC		 372 int num_comp_vectors;
373 /* protect EQs list
374 */
375 spinlock_t lock;
376};
377
378struct mlx5_uar {
379 u32 index;
380 struct list_head bf_list;
381 unsigned free_bf_bmap;
382 void __iomem *wc_map;
383 void __iomem *map;
384};
385
386
387struct mlx5_core_health {
388 struct health_buffer __iomem *health;
389 __be32 __iomem *health_counter;
390 struct timer_list timer;
391 struct list_head list;
392 u32 prev;
393 int miss_counter;
394};
395
396struct mlx5_cq_table {
397 /* protect radix tree
398 */
399 spinlock_t lock;
400 struct radix_tree_root tree;
401};
402
403struct mlx5_qp_table {
404 /* protect radix tree
405 */
406 spinlock_t lock;
407 struct radix_tree_root tree;
408};
409
410struct mlx5_srq_table {
411 /* protect radix tree
412 */
413 spinlock_t lock;
414 struct radix_tree_root tree;
415};
416
3bcdb17a
SG		 417struct mlx5_mr_table {
418 /* protect radix tree
419 */
420 rwlock_t lock;
421 struct radix_tree_root tree;
422};
423
db058a18
SM		 424struct mlx5_irq_info {
425 cpumask_var_t mask;
426 char name[MLX5_MAX_IRQ_NAME];
427};
428
e126ba97
EC		 429struct mlx5_priv {
430 char name[MLX5_MAX_NAME_LEN];
431 struct mlx5_eq_table eq_table;
db058a18
SM		 432 struct msix_entry *msix_arr;
433 struct mlx5_irq_info *irq_info;
e126ba97
EC		 434 struct mlx5_uuar_info uuari;
435 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
436
437 /* pages stuff */
438 struct workqueue_struct *pg_wq;
439 struct rb_root page_root;
440 int fw_pages;
6aec21f6 441 atomic_t reg_pages;
bf0bf77f 442 struct list_head free_list;
e126ba97
EC		 443
444 struct mlx5_core_health health;
445
446 struct mlx5_srq_table srq_table;
447
448 /* start: qp staff */
449 struct mlx5_qp_table qp_table;
450 struct dentry *qp_debugfs;
451 struct dentry *eq_debugfs;
452 struct dentry *cq_debugfs;
453 struct dentry *cmdif_debugfs;
454 /* end: qp staff */
455
456 /* start: cq staff */
457 struct mlx5_cq_table cq_table;
458 /* end: cq staff */
459
3bcdb17a
SG		 460 /* start: mr staff */
461 struct mlx5_mr_table mr_table;
462 /* end: mr staff */
463
e126ba97
EC		 464 /* start: alloc staff */
465 struct mutex pgdir_mutex;
466 struct list_head pgdir_list;
467 /* end: alloc staff */
468 struct dentry *dbg_root;
469
470 /* protect mkey key part */
471 spinlock_t mkey_lock;
472 u8 mkey_key;
9603b61d
JM		 473
474 struct list_head dev_list;
475 struct list_head ctx_list;
476 spinlock_t ctx_lock;
e126ba97
EC		 477};
478
479struct mlx5_core_dev {
480 struct pci_dev *pdev;
481 u8 rev_id;
482 char board_id[MLX5_BOARD_ID_LEN];
483 struct mlx5_cmd cmd;
938fe83c
SM		 484 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
485 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
486 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
e126ba97
EC		 487 phys_addr_t iseg_base;
488 struct mlx5_init_seg __iomem *iseg;
489 void (*event) (struct mlx5_core_dev *dev,
490 enum mlx5_dev_event event,
4d2f9bbb 491 unsigned long param);
e126ba97
EC		 492 struct mlx5_priv priv;
493 struct mlx5_profile *profile;
494 atomic_t num_qps;
f62b8bb8 495 u32 issi;
e126ba97
EC		 496};
497
498struct mlx5_db {
499 __be32 *db;
500 union {
501 struct mlx5_db_pgdir *pgdir;
502 struct mlx5_ib_user_db_page *user_page;
503 } u;
504 dma_addr_t dma;
505 int index;
506};
507
508enum {
509 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES,
510};
511
512enum {
513 MLX5_COMP_EQ_SIZE = 1024,
514};
515
adb0c954
SM		 516enum {
517 MLX5_PTYS_IB = 1 << 0,
518 MLX5_PTYS_EN = 1 << 2,
519};
520
e126ba97
EC		 521struct mlx5_db_pgdir {
522 struct list_head list;
523 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
524 __be32 *db_page;
525 dma_addr_t db_dma;
526};
527
528typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
529
530struct mlx5_cmd_work_ent {
531 struct mlx5_cmd_msg *in;
532 struct mlx5_cmd_msg *out;
746b5583
EC		 533 void *uout;
534 int uout_size;
e126ba97
EC		 535 mlx5_cmd_cbk_t callback;
536 void *context;
746b5583 537 int idx;
e126ba97
EC		 538 struct completion done;
539 struct mlx5_cmd *cmd;
540 struct work_struct work;
541 struct mlx5_cmd_layout *lay;
542 int ret;
543 int page_queue;
544 u8 status;
545 u8 token;
14a70046
TG		 546 u64 ts1;
547 u64 ts2;
746b5583 548 u16 op;
e126ba97
EC		 549};
550
551struct mlx5_pas {
552 u64 pa;
553 u8 log_sz;
554};
555
707c4602
MD		 556enum port_state_policy {
557 MLX5_AAA_000
558};
559
560enum phy_port_state {
561 MLX5_AAA_111
562};
563
564struct mlx5_hca_vport_context {
565 u32 field_select;
566 bool sm_virt_aware;
567 bool has_smi;
568 bool has_raw;
569 enum port_state_policy policy;
570 enum phy_port_state phys_state;
571 enum ib_port_state vport_state;
572 u8 port_physical_state;
573 u64 sys_image_guid;
574 u64 port_guid;
575 u64 node_guid;
576 u32 cap_mask1;
577 u32 cap_mask1_perm;
578 u32 cap_mask2;
579 u32 cap_mask2_perm;
580 u16 lid;
581 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
582 u8 lmc;
583 u8 subnet_timeout;
584 u16 sm_lid;
585 u8 sm_sl;
586 u16 qkey_violation_counter;
587 u16 pkey_violation_counter;
588 bool grh_required;
589};
590
e126ba97
EC		 591static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
592{
e126ba97 593 return buf->direct.buf + offset;
e126ba97
EC		 594}
595
596extern struct workqueue_struct *mlx5_core_wq;
597
598#define STRUCT_FIELD(header, field) \
599 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
600 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
601
602struct ib_field {
603 size_t struct_offset_bytes;
604 size_t struct_size_bytes;
605 int offset_bits;
606 int size_bits;
607};
608
609static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
610{
611 return pci_get_drvdata(pdev);
612}
613
614extern struct dentry *mlx5_debugfs_root;
615
616static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
617{
618 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
619}
620
621static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
622{
623 return ioread32be(&dev->iseg->fw_rev) >> 16;
624}
625
626static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
627{
628 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
629}
630
631static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
632{
633 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
634}
635
636static inline void *mlx5_vzalloc(unsigned long size)
637{
638 void *rtn;
639
640 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
641 if (!rtn)
642 rtn = vzalloc(size);
643 return rtn;
644}
645
3bcdb17a
SG		 646static inline u32 mlx5_base_mkey(const u32 key)
647{
648 return key & 0xffffff00u;
649}
650
e126ba97
EC		 651int mlx5_cmd_init(struct mlx5_core_dev *dev);
652void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
653void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
654void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
655int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
b775516b 656int mlx5_cmd_status_to_err_v2(void *ptr);
938fe83c
SM		 657int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
658 enum mlx5_cap_mode cap_mode);
e126ba97
EC		 659int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
660 int out_size);
746b5583
EC		 661int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
662 void *out, int out_size, mlx5_cmd_cbk_t callback,
663 void *context);
e126ba97
EC		 664int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
665int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
666int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
667int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
e281682b
SM		 668int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
669void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
e126ba97
EC		 670void mlx5_health_cleanup(void);
671void __init mlx5_health_init(void);
672void mlx5_start_health_poll(struct mlx5_core_dev *dev);
673void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
64ffaa21 674int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
e126ba97
EC		 675void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
676struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
677 gfp_t flags, int npages);
678void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
679 struct mlx5_cmd_mailbox *head);
680int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
01949d01
HA		 681 struct mlx5_create_srq_mbox_in *in, int inlen,
682 int is_xrc);
e126ba97
EC		 683int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
684int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
685 struct mlx5_query_srq_mbox_out *out);
686int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
687 u16 lwm, int is_srq);
3bcdb17a
SG		 688void mlx5_init_mr_table(struct mlx5_core_dev *dev);
689void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
e126ba97 690int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
746b5583
EC		 691 struct mlx5_create_mkey_mbox_in *in, int inlen,
692 mlx5_cmd_cbk_t callback, void *context,
693 struct mlx5_create_mkey_mbox_out *out);
e126ba97
EC		 694int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr);
695int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
696 struct mlx5_query_mkey_mbox_out *out, int outlen);
697int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
698 u32 *mkey);
699int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
700int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
701int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, void *inb, void *outb,
f241e749 702 u16 opmod, u8 port);
e126ba97
EC		 703void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
704void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
705int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
706void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
707void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
0a324f31 708 s32 npages);
cd23b14b 709int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
e126ba97
EC		 710int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
711void mlx5_register_debugfs(void);
712void mlx5_unregister_debugfs(void);
713int mlx5_eq_init(struct mlx5_core_dev *dev);
714void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
715void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
716void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
5903325a 717void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
e420f0c0
HE		 718#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
719void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
720#endif
e126ba97
EC		 721void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
722struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
723void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector);
724void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
725int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
726 int nent, u64 mask, const char *name, struct mlx5_uar *uar);
727int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
728int mlx5_start_eqs(struct mlx5_core_dev *dev);
729int mlx5_stop_eqs(struct mlx5_core_dev *dev);
233d05d2 730int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
e126ba97
EC		 731int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
732int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
733
734int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
735void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
736int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
737 int size_in, void *data_out, int size_out,
738 u16 reg_num, int arg, int write);
adb0c954 739
f241e749 740int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
adb0c954
SM		 741int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
742 int ptys_size, int proto_mask);
743int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
744 u32 *proto_cap, int proto_mask);
745int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
746 u32 *proto_admin, int proto_mask);
747int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
748 int proto_mask);
4c916a79
RS		 749int mlx5_set_port_status(struct mlx5_core_dev *dev,
750 enum mlx5_port_status status);
751int mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status);
e126ba97 752
e725440e
SM		 753int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu);
754int mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu);
755int mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu);
756
e126ba97
EC		 757int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
758void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
759int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
760 struct mlx5_query_eq_mbox_out *out, int outlen);
761int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
762void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
763int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
764void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
765int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
766void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
767
e126ba97
EC		 768const char *mlx5_command_str(int command);
769int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
770void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
3121e3c4
SG		 771int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
772 int npsvs, u32 *sig_index);
773int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
5903325a 774void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
e420f0c0
HE		 775int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
776 struct mlx5_odp_caps *odp_caps);
e126ba97
EC		 777
778static inline u32 mlx5_mkey_to_idx(u32 mkey)
779{
780 return mkey >> 8;
781}
782
783static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
784{
785 return mkey_idx << 8;
786}
787
746b5583
EC		 788static inline u8 mlx5_mkey_variant(u32 mkey)
789{
790 return mkey & 0xff;
791}
792
e126ba97
EC		 793enum {
794 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
c1868b82 795 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
e126ba97
EC		 796};
797
798enum {
799 MAX_MR_CACHE_ENTRIES = 16,
800};
801
64613d94
SM		 802enum {
803 MLX5_INTERFACE_PROTOCOL_IB = 0,
804 MLX5_INTERFACE_PROTOCOL_ETH = 1,
805};
806
9603b61d
JM		 807struct mlx5_interface {
808 void * (*add)(struct mlx5_core_dev *dev);
809 void (*remove)(struct mlx5_core_dev *dev, void *context);
810 void (*event)(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 811 enum mlx5_dev_event event, unsigned long param);
64613d94
SM		 812 void * (*get_dev)(void *context);
813 int protocol;
9603b61d
JM		 814 struct list_head list;
815};
816
64613d94 817void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
9603b61d
JM		 818int mlx5_register_interface(struct mlx5_interface *intf);
819void mlx5_unregister_interface(struct mlx5_interface *intf);
820
e126ba97
EC		 821struct mlx5_profile {
822 u64 mask;
f241e749 823 u8 log_max_qp;
e126ba97
EC		 824 struct {
825 int size;
826 int limit;
827 } mr_cache[MAX_MR_CACHE_ENTRIES];
828};
829
707c4602
MD		 830static inline int mlx5_get_gid_table_len(u16 param)
831{
832 if (param > 4) {
833 pr_warn("gid table length is zero\n");
834 return 0;
835 }
836
837 return 8 * (1 << param);
838}
839
e126ba97 840#endif /* MLX5_DRIVER_H */
Linux 6.x block layer and io_uring tree(s)