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mlx5_core: Re-add MLX5_DEV_CAP_FLAG_ON_DMND_PG flag
[linux-2.6-block.git] / include / linux / mlx5 / driver.h
CommitLineData
e126ba97
EC		 1/*
2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DRIVER_H
34#define MLX5_DRIVER_H
35
36#include <linux/kernel.h>
37#include <linux/completion.h>
38#include <linux/pci.h>
39#include <linux/spinlock_types.h>
40#include <linux/semaphore.h>
6ecde51d 41#include <linux/slab.h>
e126ba97
EC		 42#include <linux/vmalloc.h>
43#include <linux/radix-tree.h>
6ecde51d 44
e126ba97
EC		 45#include <linux/mlx5/device.h>
46#include <linux/mlx5/doorbell.h>
d29b796a 47#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 48
49enum {
50 MLX5_BOARD_ID_LEN = 64,
51 MLX5_MAX_NAME_LEN = 16,
52};
53
54enum {
55 /* one minute for the sake of bringup. Generally, commands must always
56 * complete and we may need to increase this timeout value
57 */
58 MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000,
59 MLX5_CMD_WQ_MAX_NAME = 32,
60};
61
62enum {
63 CMD_OWNER_SW = 0x0,
64 CMD_OWNER_HW = 0x1,
65 CMD_STATUS_SUCCESS = 0,
66};
67
68enum mlx5_sqp_t {
69 MLX5_SQP_SMI = 0,
70 MLX5_SQP_GSI = 1,
71 MLX5_SQP_IEEE_1588 = 2,
72 MLX5_SQP_SNIFFER = 3,
73 MLX5_SQP_SYNC_UMR = 4,
74};
75
76enum {
77 MLX5_MAX_PORTS = 2,
78};
79
80enum {
81 MLX5_EQ_VEC_PAGES = 0,
82 MLX5_EQ_VEC_CMD = 1,
83 MLX5_EQ_VEC_ASYNC = 2,
84 MLX5_EQ_VEC_COMP_BASE,
85};
86
87enum {
ada9f5d0 88 MLX5_MAX_EQ_NAME = 32
e126ba97
EC		 89};
90
91enum {
92 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
93 MLX5_ATOMIC_MODE_CX = 2 << 16,
94 MLX5_ATOMIC_MODE_8B = 3 << 16,
95 MLX5_ATOMIC_MODE_16B = 4 << 16,
96 MLX5_ATOMIC_MODE_32B = 5 << 16,
97 MLX5_ATOMIC_MODE_64B = 6 << 16,
98 MLX5_ATOMIC_MODE_128B = 7 << 16,
99 MLX5_ATOMIC_MODE_256B = 8 << 16,
100};
101
e126ba97
EC		 102enum {
103 MLX5_REG_PCAP = 0x5001,
104 MLX5_REG_PMTU = 0x5003,
105 MLX5_REG_PTYS = 0x5004,
106 MLX5_REG_PAOS = 0x5006,
107 MLX5_REG_PMAOS = 0x5012,
108 MLX5_REG_PUDE = 0x5009,
109 MLX5_REG_PMPE = 0x5010,
110 MLX5_REG_PELC = 0x500e,
111 MLX5_REG_PMLP = 0, /* TBD */
112 MLX5_REG_NODE_DESC = 0x6001,
113 MLX5_REG_HOST_ENDIANNESS = 0x7004,
114};
115
116enum dbg_rsc_type {
117 MLX5_DBG_RSC_QP,
118 MLX5_DBG_RSC_EQ,
119 MLX5_DBG_RSC_CQ,
120};
121
122struct mlx5_field_desc {
123 struct dentry *dent;
124 int i;
125};
126
127struct mlx5_rsc_debug {
128 struct mlx5_core_dev *dev;
129 void *object;
130 enum dbg_rsc_type type;
131 struct dentry *root;
132 struct mlx5_field_desc fields[0];
133};
134
135enum mlx5_dev_event {
136 MLX5_DEV_EVENT_SYS_ERROR,
137 MLX5_DEV_EVENT_PORT_UP,
138 MLX5_DEV_EVENT_PORT_DOWN,
139 MLX5_DEV_EVENT_PORT_INITIALIZED,
140 MLX5_DEV_EVENT_LID_CHANGE,
141 MLX5_DEV_EVENT_PKEY_CHANGE,
142 MLX5_DEV_EVENT_GUID_CHANGE,
143 MLX5_DEV_EVENT_CLIENT_REREG,
144};
145
146struct mlx5_uuar_info {
147 struct mlx5_uar *uars;
148 int num_uars;
149 int num_low_latency_uuars;
150 unsigned long *bitmap;
151 unsigned int *count;
152 struct mlx5_bf *bfs;
153
154 /*
155 * protect uuar allocation data structs
156 */
157 struct mutex lock;
78c0f98c 158 u32 ver;
e126ba97
EC		 159};
160
161struct mlx5_bf {
162 void __iomem *reg;
163 void __iomem *regreg;
164 int buf_size;
165 struct mlx5_uar *uar;
166 unsigned long offset;
167 int need_lock;
168 /* protect blue flame buffer selection when needed
169 */
170 spinlock_t lock;
171
172 /* serialize 64 bit writes when done as two 32 bit accesses
173 */
174 spinlock_t lock32;
175 int uuarn;
176};
177
178struct mlx5_cmd_first {
179 __be32 data[4];
180};
181
182struct mlx5_cmd_msg {
183 struct list_head list;
184 struct cache_ent *cache;
185 u32 len;
186 struct mlx5_cmd_first first;
187 struct mlx5_cmd_mailbox *next;
188};
189
190struct mlx5_cmd_debug {
191 struct dentry *dbg_root;
192 struct dentry *dbg_in;
193 struct dentry *dbg_out;
194 struct dentry *dbg_outlen;
195 struct dentry *dbg_status;
196 struct dentry *dbg_run;
197 void *in_msg;
198 void *out_msg;
199 u8 status;
200 u16 inlen;
201 u16 outlen;
202};
203
204struct cache_ent {
205 /* protect block chain allocations
206 */
207 spinlock_t lock;
208 struct list_head head;
209};
210
211struct cmd_msg_cache {
212 struct cache_ent large;
213 struct cache_ent med;
214
215};
216
217struct mlx5_cmd_stats {
218 u64 sum;
219 u64 n;
220 struct dentry *root;
221 struct dentry *avg;
222 struct dentry *count;
223 /* protect command average calculations */
224 spinlock_t lock;
225};
226
227struct mlx5_cmd {
228 void *cmd_buf;
229 dma_addr_t dma;
230 u16 cmdif_rev;
231 u8 log_sz;
232 u8 log_stride;
233 int max_reg_cmds;
234 int events;
235 u32 __iomem *vector;
236
237 /* protect command queue allocations
238 */
239 spinlock_t alloc_lock;
240
241 /* protect token allocations
242 */
243 spinlock_t token_lock;
244 u8 token;
245 unsigned long bitmask;
246 char wq_name[MLX5_CMD_WQ_MAX_NAME];
247 struct workqueue_struct *wq;
248 struct semaphore sem;
249 struct semaphore pages_sem;
250 int mode;
251 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
252 struct pci_pool *pool;
253 struct mlx5_cmd_debug dbg;
254 struct cmd_msg_cache cache;
255 int checksum_disabled;
256 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
257};
258
259struct mlx5_port_caps {
260 int gid_table_len;
261 int pkey_table_len;
262};
263
c7a08ac7 264struct mlx5_general_caps {
e126ba97
EC		 265 u8 log_max_eq;
266 u8 log_max_cq;
267 u8 log_max_qp;
268 u8 log_max_mkey;
269 u8 log_max_pd;
270 u8 log_max_srq;
c7a08ac7
EC		 271 u8 log_max_strq;
272 u8 log_max_mrw_sz;
273 u8 log_max_bsf_list_size;
274 u8 log_max_klm_list_size;
e126ba97
EC		 275 u32 max_cqes;
276 int max_wqes;
c7a08ac7
EC		 277 u32 max_eqes;
278 u32 max_indirection;
e126ba97
EC		 279 int max_sq_desc_sz;
280 int max_rq_desc_sz;
c7a08ac7 281 int max_dc_sq_desc_sz;
e126ba97
EC		 282 u64 flags;
283 u16 stat_rate_support;
284 int log_max_msg;
285 int num_ports;
c7a08ac7
EC		 286 u8 log_max_ra_res_qp;
287 u8 log_max_ra_req_qp;
e126ba97
EC		 288 int max_srq_wqes;
289 int bf_reg_size;
290 int bf_regs_per_page;
291 struct mlx5_port_caps port[MLX5_MAX_PORTS];
292 u8 ext_port_cap[MLX5_MAX_PORTS];
293 int max_vf;
294 u32 reserved_lkey;
295 u8 local_ca_ack_delay;
296 u8 log_max_mcg;
0a324f31 297 u32 max_qp_mcg;
e126ba97 298 int min_page_sz;
c7a08ac7
EC		 299 int pd_cap;
300 u32 max_qp_counters;
301 u32 pkey_table_size;
302 u8 log_max_ra_req_dc;
303 u8 log_max_ra_res_dc;
304 u32 uar_sz;
305 u8 min_log_pg_sz;
306 u8 log_max_xrcd;
307 u16 log_uar_page_sz;
308};
309
310struct mlx5_caps {
311 struct mlx5_general_caps gen;
e126ba97
EC		 312};
313
314struct mlx5_cmd_mailbox {
315 void *buf;
316 dma_addr_t dma;
317 struct mlx5_cmd_mailbox *next;
318};
319
320struct mlx5_buf_list {
321 void *buf;
322 dma_addr_t map;
323};
324
325struct mlx5_buf {
326 struct mlx5_buf_list direct;
327 struct mlx5_buf_list *page_list;
328 int nbufs;
329 int npages;
e126ba97 330 int size;
f241e749 331 u8 page_shift;
e126ba97
EC		 332};
333
334struct mlx5_eq {
335 struct mlx5_core_dev *dev;
336 __be32 __iomem *doorbell;
337 u32 cons_index;
338 struct mlx5_buf buf;
339 int size;
340 u8 irqn;
341 u8 eqn;
342 int nent;
343 u64 mask;
344 char name[MLX5_MAX_EQ_NAME];
345 struct list_head list;
346 int index;
347 struct mlx5_rsc_debug *dbg;
348};
349
3121e3c4
SG		 350struct mlx5_core_psv {
351 u32 psv_idx;
352 struct psv_layout {
353 u32 pd;
354 u16 syndrome;
355 u16 reserved;
356 u16 bg;
357 u16 app_tag;
358 u32 ref_tag;
359 } psv;
360};
361
362struct mlx5_core_sig_ctx {
363 struct mlx5_core_psv psv_memory;
364 struct mlx5_core_psv psv_wire;
d5436ba0
SG		 365 struct ib_sig_err err_item;
366 bool sig_status_checked;
367 bool sig_err_exists;
368 u32 sigerr_count;
3121e3c4 369};
e126ba97
EC		 370
371struct mlx5_core_mr {
372 u64 iova;
373 u64 size;
374 u32 key;
375 u32 pd;
e126ba97
EC		 376};
377
5903325a
EC		 378enum mlx5_res_type {
379 MLX5_RES_QP,
380};
381
382struct mlx5_core_rsc_common {
383 enum mlx5_res_type res;
384 atomic_t refcount;
385 struct completion free;
386};
387
e126ba97
EC		 388struct mlx5_core_srq {
389 u32 srqn;
390 int max;
391 int max_gs;
392 int max_avail_gather;
393 int wqe_shift;
394 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
395
396 atomic_t refcount;
397 struct completion free;
398};
399
400struct mlx5_eq_table {
401 void __iomem *update_ci;
402 void __iomem *update_arm_ci;
403 struct list_head *comp_eq_head;
404 struct mlx5_eq pages_eq;
405 struct mlx5_eq async_eq;
406 struct mlx5_eq cmd_eq;
407 struct msix_entry *msix_arr;
408 int num_comp_vectors;
409 /* protect EQs list
410 */
411 spinlock_t lock;
412};
413
414struct mlx5_uar {
415 u32 index;
416 struct list_head bf_list;
417 unsigned free_bf_bmap;
418 void __iomem *wc_map;
419 void __iomem *map;
420};
421
422
423struct mlx5_core_health {
424 struct health_buffer __iomem *health;
425 __be32 __iomem *health_counter;
426 struct timer_list timer;
427 struct list_head list;
428 u32 prev;
429 int miss_counter;
430};
431
432struct mlx5_cq_table {
433 /* protect radix tree
434 */
435 spinlock_t lock;
436 struct radix_tree_root tree;
437};
438
439struct mlx5_qp_table {
440 /* protect radix tree
441 */
442 spinlock_t lock;
443 struct radix_tree_root tree;
444};
445
446struct mlx5_srq_table {
447 /* protect radix tree
448 */
449 spinlock_t lock;
450 struct radix_tree_root tree;
451};
452
3bcdb17a
SG		 453struct mlx5_mr_table {
454 /* protect radix tree
455 */
456 rwlock_t lock;
457 struct radix_tree_root tree;
458};
459
e126ba97
EC		 460struct mlx5_priv {
461 char name[MLX5_MAX_NAME_LEN];
462 struct mlx5_eq_table eq_table;
463 struct mlx5_uuar_info uuari;
464 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
465
466 /* pages stuff */
467 struct workqueue_struct *pg_wq;
468 struct rb_root page_root;
469 int fw_pages;
470 int reg_pages;
bf0bf77f 471 struct list_head free_list;
e126ba97
EC		 472
473 struct mlx5_core_health health;
474
475 struct mlx5_srq_table srq_table;
476
477 /* start: qp staff */
478 struct mlx5_qp_table qp_table;
479 struct dentry *qp_debugfs;
480 struct dentry *eq_debugfs;
481 struct dentry *cq_debugfs;
482 struct dentry *cmdif_debugfs;
483 /* end: qp staff */
484
485 /* start: cq staff */
486 struct mlx5_cq_table cq_table;
487 /* end: cq staff */
488
3bcdb17a
SG		 489 /* start: mr staff */
490 struct mlx5_mr_table mr_table;
491 /* end: mr staff */
492
e126ba97
EC		 493 /* start: alloc staff */
494 struct mutex pgdir_mutex;
495 struct list_head pgdir_list;
496 /* end: alloc staff */
497 struct dentry *dbg_root;
498
499 /* protect mkey key part */
500 spinlock_t mkey_lock;
501 u8 mkey_key;
9603b61d
JM		 502
503 struct list_head dev_list;
504 struct list_head ctx_list;
505 spinlock_t ctx_lock;
e126ba97
EC		 506};
507
508struct mlx5_core_dev {
509 struct pci_dev *pdev;
510 u8 rev_id;
511 char board_id[MLX5_BOARD_ID_LEN];
512 struct mlx5_cmd cmd;
513 struct mlx5_caps caps;
514 phys_addr_t iseg_base;
515 struct mlx5_init_seg __iomem *iseg;
516 void (*event) (struct mlx5_core_dev *dev,
517 enum mlx5_dev_event event,
4d2f9bbb 518 unsigned long param);
e126ba97
EC		 519 struct mlx5_priv priv;
520 struct mlx5_profile *profile;
521 atomic_t num_qps;
522};
523
524struct mlx5_db {
525 __be32 *db;
526 union {
527 struct mlx5_db_pgdir *pgdir;
528 struct mlx5_ib_user_db_page *user_page;
529 } u;
530 dma_addr_t dma;
531 int index;
532};
533
534enum {
535 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES,
536};
537
538enum {
539 MLX5_COMP_EQ_SIZE = 1024,
540};
541
542struct mlx5_db_pgdir {
543 struct list_head list;
544 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
545 __be32 *db_page;
546 dma_addr_t db_dma;
547};
548
549typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
550
551struct mlx5_cmd_work_ent {
552 struct mlx5_cmd_msg *in;
553 struct mlx5_cmd_msg *out;
746b5583
EC		 554 void *uout;
555 int uout_size;
e126ba97
EC		 556 mlx5_cmd_cbk_t callback;
557 void *context;
746b5583 558 int idx;
e126ba97
EC		 559 struct completion done;
560 struct mlx5_cmd *cmd;
561 struct work_struct work;
562 struct mlx5_cmd_layout *lay;
563 int ret;
564 int page_queue;
565 u8 status;
566 u8 token;
14a70046
TG		 567 u64 ts1;
568 u64 ts2;
746b5583 569 u16 op;
e126ba97
EC		 570};
571
572struct mlx5_pas {
573 u64 pa;
574 u8 log_sz;
575};
576
577static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
578{
579 if (likely(BITS_PER_LONG == 64 || buf->nbufs == 1))
580 return buf->direct.buf + offset;
581 else
582 return buf->page_list[offset >> PAGE_SHIFT].buf +
583 (offset & (PAGE_SIZE - 1));
584}
585
586extern struct workqueue_struct *mlx5_core_wq;
587
588#define STRUCT_FIELD(header, field) \
589 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
590 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
591
592struct ib_field {
593 size_t struct_offset_bytes;
594 size_t struct_size_bytes;
595 int offset_bits;
596 int size_bits;
597};
598
599static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
600{
601 return pci_get_drvdata(pdev);
602}
603
604extern struct dentry *mlx5_debugfs_root;
605
606static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
607{
608 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
609}
610
611static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
612{
613 return ioread32be(&dev->iseg->fw_rev) >> 16;
614}
615
616static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
617{
618 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
619}
620
621static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
622{
623 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
624}
625
626static inline void *mlx5_vzalloc(unsigned long size)
627{
628 void *rtn;
629
630 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
631 if (!rtn)
632 rtn = vzalloc(size);
633 return rtn;
634}
635
3bcdb17a
SG		 636static inline u32 mlx5_base_mkey(const u32 key)
637{
638 return key & 0xffffff00u;
639}
640
e126ba97
EC		 641int mlx5_cmd_init(struct mlx5_core_dev *dev);
642void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
643void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
644void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
645int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
b775516b 646int mlx5_cmd_status_to_err_v2(void *ptr);
c7a08ac7
EC		 647int mlx5_core_get_caps(struct mlx5_core_dev *dev, struct mlx5_caps *caps,
648 u16 opmod);
e126ba97
EC		 649int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
650 int out_size);
746b5583
EC		 651int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
652 void *out, int out_size, mlx5_cmd_cbk_t callback,
653 void *context);
e126ba97
EC		 654int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
655int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
656int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
657int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
658void mlx5_health_cleanup(void);
659void __init mlx5_health_init(void);
660void mlx5_start_health_poll(struct mlx5_core_dev *dev);
661void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
662int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct,
663 struct mlx5_buf *buf);
664void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
665struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
666 gfp_t flags, int npages);
667void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
668 struct mlx5_cmd_mailbox *head);
669int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
670 struct mlx5_create_srq_mbox_in *in, int inlen);
671int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
672int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
673 struct mlx5_query_srq_mbox_out *out);
674int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
675 u16 lwm, int is_srq);
3bcdb17a
SG		 676void mlx5_init_mr_table(struct mlx5_core_dev *dev);
677void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
e126ba97 678int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
746b5583
EC		 679 struct mlx5_create_mkey_mbox_in *in, int inlen,
680 mlx5_cmd_cbk_t callback, void *context,
681 struct mlx5_create_mkey_mbox_out *out);
e126ba97
EC		 682int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr);
683int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
684 struct mlx5_query_mkey_mbox_out *out, int outlen);
685int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
686 u32 *mkey);
687int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
688int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
689int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, void *inb, void *outb,
f241e749 690 u16 opmod, u8 port);
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EC		 691void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
692void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
693int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
694void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
695void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
0a324f31 696 s32 npages);
cd23b14b 697int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
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EC		 698int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
699void mlx5_register_debugfs(void);
700void mlx5_unregister_debugfs(void);
701int mlx5_eq_init(struct mlx5_core_dev *dev);
702void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
703void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
704void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
5903325a 705void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
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EC		 706void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
707struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
708void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector);
709void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
710int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
711 int nent, u64 mask, const char *name, struct mlx5_uar *uar);
712int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
713int mlx5_start_eqs(struct mlx5_core_dev *dev);
714int mlx5_stop_eqs(struct mlx5_core_dev *dev);
715int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
716int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
717
718int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
719void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
720int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
721 int size_in, void *data_out, int size_out,
722 u16 reg_num, int arg, int write);
f241e749 723int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
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EC		 724
725int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
726void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
727int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
728 struct mlx5_query_eq_mbox_out *out, int outlen);
729int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
730void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
731int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
732void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
733int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
734void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
735
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EC		 736const char *mlx5_command_str(int command);
737int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
738void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
3121e3c4
SG		 739int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
740 int npsvs, u32 *sig_index);
741int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
5903325a 742void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
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EC		 743
744static inline u32 mlx5_mkey_to_idx(u32 mkey)
745{
746 return mkey >> 8;
747}
748
749static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
750{
751 return mkey_idx << 8;
752}
753
746b5583
EC		 754static inline u8 mlx5_mkey_variant(u32 mkey)
755{
756 return mkey & 0xff;
757}
758
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EC		 759enum {
760 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
c1868b82 761 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
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EC		 762};
763
764enum {
765 MAX_MR_CACHE_ENTRIES = 16,
766};
767
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JM		 768struct mlx5_interface {
769 void * (*add)(struct mlx5_core_dev *dev);
770 void (*remove)(struct mlx5_core_dev *dev, void *context);
771 void (*event)(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 772 enum mlx5_dev_event event, unsigned long param);
9603b61d
JM		 773 struct list_head list;
774};
775
776int mlx5_register_interface(struct mlx5_interface *intf);
777void mlx5_unregister_interface(struct mlx5_interface *intf);
778
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EC		 779struct mlx5_profile {
780 u64 mask;
f241e749 781 u8 log_max_qp;
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EC		 782 struct {
783 int size;
784 int limit;
785 } mr_cache[MAX_MR_CACHE_ENTRIES];
786};
787
788#endif /* MLX5_DRIVER_H */
Linux 6.x block layer and io_uring tree(s)