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net/mlx5_core,mlx5_ib: Do not use vmap() on coherent memory
[linux-2.6-block.git] / include / linux / mlx5 / driver.h
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DRIVER_H
34#define MLX5_DRIVER_H
35
36#include <linux/kernel.h>
37#include <linux/completion.h>
38#include <linux/pci.h>
39#include <linux/spinlock_types.h>
40#include <linux/semaphore.h>
6ecde51d 41#include <linux/slab.h>
e126ba97
EC		 42#include <linux/vmalloc.h>
43#include <linux/radix-tree.h>
6ecde51d 44
e126ba97
EC		 45#include <linux/mlx5/device.h>
46#include <linux/mlx5/doorbell.h>
d29b796a 47#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 48
49enum {
50 MLX5_BOARD_ID_LEN = 64,
51 MLX5_MAX_NAME_LEN = 16,
52};
53
54enum {
55 /* one minute for the sake of bringup. Generally, commands must always
56 * complete and we may need to increase this timeout value
57 */
58 MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000,
59 MLX5_CMD_WQ_MAX_NAME = 32,
60};
61
62enum {
63 CMD_OWNER_SW = 0x0,
64 CMD_OWNER_HW = 0x1,
65 CMD_STATUS_SUCCESS = 0,
66};
67
68enum mlx5_sqp_t {
69 MLX5_SQP_SMI = 0,
70 MLX5_SQP_GSI = 1,
71 MLX5_SQP_IEEE_1588 = 2,
72 MLX5_SQP_SNIFFER = 3,
73 MLX5_SQP_SYNC_UMR = 4,
74};
75
76enum {
77 MLX5_MAX_PORTS = 2,
78};
79
80enum {
81 MLX5_EQ_VEC_PAGES = 0,
82 MLX5_EQ_VEC_CMD = 1,
83 MLX5_EQ_VEC_ASYNC = 2,
84 MLX5_EQ_VEC_COMP_BASE,
85};
86
87enum {
ada9f5d0 88 MLX5_MAX_EQ_NAME = 32
e126ba97
EC		 89};
90
91enum {
92 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
93 MLX5_ATOMIC_MODE_CX = 2 << 16,
94 MLX5_ATOMIC_MODE_8B = 3 << 16,
95 MLX5_ATOMIC_MODE_16B = 4 << 16,
96 MLX5_ATOMIC_MODE_32B = 5 << 16,
97 MLX5_ATOMIC_MODE_64B = 6 << 16,
98 MLX5_ATOMIC_MODE_128B = 7 << 16,
99 MLX5_ATOMIC_MODE_256B = 8 << 16,
100};
101
e126ba97
EC		 102enum {
103 MLX5_REG_PCAP = 0x5001,
104 MLX5_REG_PMTU = 0x5003,
105 MLX5_REG_PTYS = 0x5004,
106 MLX5_REG_PAOS = 0x5006,
107 MLX5_REG_PMAOS = 0x5012,
108 MLX5_REG_PUDE = 0x5009,
109 MLX5_REG_PMPE = 0x5010,
110 MLX5_REG_PELC = 0x500e,
111 MLX5_REG_PMLP = 0, /* TBD */
112 MLX5_REG_NODE_DESC = 0x6001,
113 MLX5_REG_HOST_ENDIANNESS = 0x7004,
114};
115
e420f0c0
HE		 116enum mlx5_page_fault_resume_flags {
117 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
118 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
119 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
120 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
121};
122
e126ba97
EC		 123enum dbg_rsc_type {
124 MLX5_DBG_RSC_QP,
125 MLX5_DBG_RSC_EQ,
126 MLX5_DBG_RSC_CQ,
127};
128
129struct mlx5_field_desc {
130 struct dentry *dent;
131 int i;
132};
133
134struct mlx5_rsc_debug {
135 struct mlx5_core_dev *dev;
136 void *object;
137 enum dbg_rsc_type type;
138 struct dentry *root;
139 struct mlx5_field_desc fields[0];
140};
141
142enum mlx5_dev_event {
143 MLX5_DEV_EVENT_SYS_ERROR,
144 MLX5_DEV_EVENT_PORT_UP,
145 MLX5_DEV_EVENT_PORT_DOWN,
146 MLX5_DEV_EVENT_PORT_INITIALIZED,
147 MLX5_DEV_EVENT_LID_CHANGE,
148 MLX5_DEV_EVENT_PKEY_CHANGE,
149 MLX5_DEV_EVENT_GUID_CHANGE,
150 MLX5_DEV_EVENT_CLIENT_REREG,
151};
152
153struct mlx5_uuar_info {
154 struct mlx5_uar *uars;
155 int num_uars;
156 int num_low_latency_uuars;
157 unsigned long *bitmap;
158 unsigned int *count;
159 struct mlx5_bf *bfs;
160
161 /*
162 * protect uuar allocation data structs
163 */
164 struct mutex lock;
78c0f98c 165 u32 ver;
e126ba97
EC		 166};
167
168struct mlx5_bf {
169 void __iomem *reg;
170 void __iomem *regreg;
171 int buf_size;
172 struct mlx5_uar *uar;
173 unsigned long offset;
174 int need_lock;
175 /* protect blue flame buffer selection when needed
176 */
177 spinlock_t lock;
178
179 /* serialize 64 bit writes when done as two 32 bit accesses
180 */
181 spinlock_t lock32;
182 int uuarn;
183};
184
185struct mlx5_cmd_first {
186 __be32 data[4];
187};
188
189struct mlx5_cmd_msg {
190 struct list_head list;
191 struct cache_ent *cache;
192 u32 len;
193 struct mlx5_cmd_first first;
194 struct mlx5_cmd_mailbox *next;
195};
196
197struct mlx5_cmd_debug {
198 struct dentry *dbg_root;
199 struct dentry *dbg_in;
200 struct dentry *dbg_out;
201 struct dentry *dbg_outlen;
202 struct dentry *dbg_status;
203 struct dentry *dbg_run;
204 void *in_msg;
205 void *out_msg;
206 u8 status;
207 u16 inlen;
208 u16 outlen;
209};
210
211struct cache_ent {
212 /* protect block chain allocations
213 */
214 spinlock_t lock;
215 struct list_head head;
216};
217
218struct cmd_msg_cache {
219 struct cache_ent large;
220 struct cache_ent med;
221
222};
223
224struct mlx5_cmd_stats {
225 u64 sum;
226 u64 n;
227 struct dentry *root;
228 struct dentry *avg;
229 struct dentry *count;
230 /* protect command average calculations */
231 spinlock_t lock;
232};
233
234struct mlx5_cmd {
64599cca
EC		 235 void *cmd_alloc_buf;
236 dma_addr_t alloc_dma;
237 int alloc_size;
e126ba97
EC		 238 void *cmd_buf;
239 dma_addr_t dma;
240 u16 cmdif_rev;
241 u8 log_sz;
242 u8 log_stride;
243 int max_reg_cmds;
244 int events;
245 u32 __iomem *vector;
246
247 /* protect command queue allocations
248 */
249 spinlock_t alloc_lock;
250
251 /* protect token allocations
252 */
253 spinlock_t token_lock;
254 u8 token;
255 unsigned long bitmask;
256 char wq_name[MLX5_CMD_WQ_MAX_NAME];
257 struct workqueue_struct *wq;
258 struct semaphore sem;
259 struct semaphore pages_sem;
260 int mode;
261 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
262 struct pci_pool *pool;
263 struct mlx5_cmd_debug dbg;
264 struct cmd_msg_cache cache;
265 int checksum_disabled;
266 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
267};
268
269struct mlx5_port_caps {
270 int gid_table_len;
271 int pkey_table_len;
272};
273
c7a08ac7 274struct mlx5_general_caps {
e126ba97
EC		 275 u8 log_max_eq;
276 u8 log_max_cq;
277 u8 log_max_qp;
278 u8 log_max_mkey;
279 u8 log_max_pd;
280 u8 log_max_srq;
c7a08ac7
EC		 281 u8 log_max_strq;
282 u8 log_max_mrw_sz;
283 u8 log_max_bsf_list_size;
284 u8 log_max_klm_list_size;
e126ba97
EC		 285 u32 max_cqes;
286 int max_wqes;
c7a08ac7
EC		 287 u32 max_eqes;
288 u32 max_indirection;
e126ba97
EC		 289 int max_sq_desc_sz;
290 int max_rq_desc_sz;
c7a08ac7 291 int max_dc_sq_desc_sz;
e126ba97
EC		 292 u64 flags;
293 u16 stat_rate_support;
294 int log_max_msg;
295 int num_ports;
c7a08ac7
EC		 296 u8 log_max_ra_res_qp;
297 u8 log_max_ra_req_qp;
e126ba97
EC		 298 int max_srq_wqes;
299 int bf_reg_size;
300 int bf_regs_per_page;
301 struct mlx5_port_caps port[MLX5_MAX_PORTS];
302 u8 ext_port_cap[MLX5_MAX_PORTS];
303 int max_vf;
304 u32 reserved_lkey;
305 u8 local_ca_ack_delay;
306 u8 log_max_mcg;
0a324f31 307 u32 max_qp_mcg;
e126ba97 308 int min_page_sz;
c7a08ac7
EC		 309 int pd_cap;
310 u32 max_qp_counters;
311 u32 pkey_table_size;
312 u8 log_max_ra_req_dc;
313 u8 log_max_ra_res_dc;
314 u32 uar_sz;
315 u8 min_log_pg_sz;
316 u8 log_max_xrcd;
317 u16 log_uar_page_sz;
318};
319
320struct mlx5_caps {
321 struct mlx5_general_caps gen;
e126ba97
EC		 322};
323
324struct mlx5_cmd_mailbox {
325 void *buf;
326 dma_addr_t dma;
327 struct mlx5_cmd_mailbox *next;
328};
329
330struct mlx5_buf_list {
331 void *buf;
332 dma_addr_t map;
333};
334
335struct mlx5_buf {
336 struct mlx5_buf_list direct;
e126ba97 337 int npages;
e126ba97 338 int size;
f241e749 339 u8 page_shift;
e126ba97
EC		 340};
341
342struct mlx5_eq {
343 struct mlx5_core_dev *dev;
344 __be32 __iomem *doorbell;
345 u32 cons_index;
346 struct mlx5_buf buf;
347 int size;
348 u8 irqn;
349 u8 eqn;
350 int nent;
351 u64 mask;
352 char name[MLX5_MAX_EQ_NAME];
353 struct list_head list;
354 int index;
355 struct mlx5_rsc_debug *dbg;
356};
357
3121e3c4
SG		 358struct mlx5_core_psv {
359 u32 psv_idx;
360 struct psv_layout {
361 u32 pd;
362 u16 syndrome;
363 u16 reserved;
364 u16 bg;
365 u16 app_tag;
366 u32 ref_tag;
367 } psv;
368};
369
370struct mlx5_core_sig_ctx {
371 struct mlx5_core_psv psv_memory;
372 struct mlx5_core_psv psv_wire;
d5436ba0
SG		 373 struct ib_sig_err err_item;
374 bool sig_status_checked;
375 bool sig_err_exists;
376 u32 sigerr_count;
3121e3c4 377};
e126ba97
EC		 378
379struct mlx5_core_mr {
380 u64 iova;
381 u64 size;
382 u32 key;
383 u32 pd;
e126ba97
EC		 384};
385
5903325a
EC		 386enum mlx5_res_type {
387 MLX5_RES_QP,
388};
389
390struct mlx5_core_rsc_common {
391 enum mlx5_res_type res;
392 atomic_t refcount;
393 struct completion free;
394};
395
e126ba97
EC		 396struct mlx5_core_srq {
397 u32 srqn;
398 int max;
399 int max_gs;
400 int max_avail_gather;
401 int wqe_shift;
402 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
403
404 atomic_t refcount;
405 struct completion free;
406};
407
408struct mlx5_eq_table {
409 void __iomem *update_ci;
410 void __iomem *update_arm_ci;
233d05d2 411 struct list_head comp_eqs_list;
e126ba97
EC		 412 struct mlx5_eq pages_eq;
413 struct mlx5_eq async_eq;
414 struct mlx5_eq cmd_eq;
415 struct msix_entry *msix_arr;
416 int num_comp_vectors;
417 /* protect EQs list
418 */
419 spinlock_t lock;
420};
421
422struct mlx5_uar {
423 u32 index;
424 struct list_head bf_list;
425 unsigned free_bf_bmap;
426 void __iomem *wc_map;
427 void __iomem *map;
428};
429
430
431struct mlx5_core_health {
432 struct health_buffer __iomem *health;
433 __be32 __iomem *health_counter;
434 struct timer_list timer;
435 struct list_head list;
436 u32 prev;
437 int miss_counter;
438};
439
440struct mlx5_cq_table {
441 /* protect radix tree
442 */
443 spinlock_t lock;
444 struct radix_tree_root tree;
445};
446
447struct mlx5_qp_table {
448 /* protect radix tree
449 */
450 spinlock_t lock;
451 struct radix_tree_root tree;
452};
453
454struct mlx5_srq_table {
455 /* protect radix tree
456 */
457 spinlock_t lock;
458 struct radix_tree_root tree;
459};
460
3bcdb17a
SG		 461struct mlx5_mr_table {
462 /* protect radix tree
463 */
464 rwlock_t lock;
465 struct radix_tree_root tree;
466};
467
e126ba97
EC		 468struct mlx5_priv {
469 char name[MLX5_MAX_NAME_LEN];
470 struct mlx5_eq_table eq_table;
471 struct mlx5_uuar_info uuari;
472 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
473
474 /* pages stuff */
475 struct workqueue_struct *pg_wq;
476 struct rb_root page_root;
477 int fw_pages;
6aec21f6 478 atomic_t reg_pages;
bf0bf77f 479 struct list_head free_list;
e126ba97
EC		 480
481 struct mlx5_core_health health;
482
483 struct mlx5_srq_table srq_table;
484
485 /* start: qp staff */
486 struct mlx5_qp_table qp_table;
487 struct dentry *qp_debugfs;
488 struct dentry *eq_debugfs;
489 struct dentry *cq_debugfs;
490 struct dentry *cmdif_debugfs;
491 /* end: qp staff */
492
493 /* start: cq staff */
494 struct mlx5_cq_table cq_table;
495 /* end: cq staff */
496
3bcdb17a
SG		 497 /* start: mr staff */
498 struct mlx5_mr_table mr_table;
499 /* end: mr staff */
500
e126ba97
EC		 501 /* start: alloc staff */
502 struct mutex pgdir_mutex;
503 struct list_head pgdir_list;
504 /* end: alloc staff */
505 struct dentry *dbg_root;
506
507 /* protect mkey key part */
508 spinlock_t mkey_lock;
509 u8 mkey_key;
9603b61d
JM		 510
511 struct list_head dev_list;
512 struct list_head ctx_list;
513 spinlock_t ctx_lock;
e126ba97
EC		 514};
515
516struct mlx5_core_dev {
517 struct pci_dev *pdev;
518 u8 rev_id;
519 char board_id[MLX5_BOARD_ID_LEN];
520 struct mlx5_cmd cmd;
521 struct mlx5_caps caps;
522 phys_addr_t iseg_base;
523 struct mlx5_init_seg __iomem *iseg;
524 void (*event) (struct mlx5_core_dev *dev,
525 enum mlx5_dev_event event,
4d2f9bbb 526 unsigned long param);
e126ba97
EC		 527 struct mlx5_priv priv;
528 struct mlx5_profile *profile;
529 atomic_t num_qps;
530};
531
532struct mlx5_db {
533 __be32 *db;
534 union {
535 struct mlx5_db_pgdir *pgdir;
536 struct mlx5_ib_user_db_page *user_page;
537 } u;
538 dma_addr_t dma;
539 int index;
540};
541
542enum {
543 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES,
544};
545
546enum {
547 MLX5_COMP_EQ_SIZE = 1024,
548};
549
550struct mlx5_db_pgdir {
551 struct list_head list;
552 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
553 __be32 *db_page;
554 dma_addr_t db_dma;
555};
556
557typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
558
559struct mlx5_cmd_work_ent {
560 struct mlx5_cmd_msg *in;
561 struct mlx5_cmd_msg *out;
746b5583
EC		 562 void *uout;
563 int uout_size;
e126ba97
EC		 564 mlx5_cmd_cbk_t callback;
565 void *context;
746b5583 566 int idx;
e126ba97
EC		 567 struct completion done;
568 struct mlx5_cmd *cmd;
569 struct work_struct work;
570 struct mlx5_cmd_layout *lay;
571 int ret;
572 int page_queue;
573 u8 status;
574 u8 token;
14a70046
TG		 575 u64 ts1;
576 u64 ts2;
746b5583 577 u16 op;
e126ba97
EC		 578};
579
580struct mlx5_pas {
581 u64 pa;
582 u8 log_sz;
583};
584
585static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
586{
e126ba97 587 return buf->direct.buf + offset;
e126ba97
EC		 588}
589
590extern struct workqueue_struct *mlx5_core_wq;
591
592#define STRUCT_FIELD(header, field) \
593 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
594 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
595
596struct ib_field {
597 size_t struct_offset_bytes;
598 size_t struct_size_bytes;
599 int offset_bits;
600 int size_bits;
601};
602
603static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
604{
605 return pci_get_drvdata(pdev);
606}
607
608extern struct dentry *mlx5_debugfs_root;
609
610static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
611{
612 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
613}
614
615static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
616{
617 return ioread32be(&dev->iseg->fw_rev) >> 16;
618}
619
620static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
621{
622 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
623}
624
625static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
626{
627 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
628}
629
630static inline void *mlx5_vzalloc(unsigned long size)
631{
632 void *rtn;
633
634 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
635 if (!rtn)
636 rtn = vzalloc(size);
637 return rtn;
638}
639
3bcdb17a
SG		 640static inline u32 mlx5_base_mkey(const u32 key)
641{
642 return key & 0xffffff00u;
643}
644
e126ba97
EC		 645int mlx5_cmd_init(struct mlx5_core_dev *dev);
646void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
647void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
648void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
649int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
b775516b 650int mlx5_cmd_status_to_err_v2(void *ptr);
c7a08ac7
EC		 651int mlx5_core_get_caps(struct mlx5_core_dev *dev, struct mlx5_caps *caps,
652 u16 opmod);
e126ba97
EC		 653int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
654 int out_size);
746b5583
EC		 655int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
656 void *out, int out_size, mlx5_cmd_cbk_t callback,
657 void *context);
e126ba97
EC		 658int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
659int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
660int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
661int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
662void mlx5_health_cleanup(void);
663void __init mlx5_health_init(void);
664void mlx5_start_health_poll(struct mlx5_core_dev *dev);
665void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
64ffaa21 666int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
e126ba97
EC		 667void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
668struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
669 gfp_t flags, int npages);
670void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
671 struct mlx5_cmd_mailbox *head);
672int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
673 struct mlx5_create_srq_mbox_in *in, int inlen);
674int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
675int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
676 struct mlx5_query_srq_mbox_out *out);
677int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
678 u16 lwm, int is_srq);
3bcdb17a
SG		 679void mlx5_init_mr_table(struct mlx5_core_dev *dev);
680void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
e126ba97 681int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
746b5583
EC		 682 struct mlx5_create_mkey_mbox_in *in, int inlen,
683 mlx5_cmd_cbk_t callback, void *context,
684 struct mlx5_create_mkey_mbox_out *out);
e126ba97
EC		 685int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr);
686int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
687 struct mlx5_query_mkey_mbox_out *out, int outlen);
688int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
689 u32 *mkey);
690int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
691int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
692int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, void *inb, void *outb,
f241e749 693 u16 opmod, u8 port);
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EC		 694void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
695void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
696int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
697void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
698void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
0a324f31 699 s32 npages);
cd23b14b 700int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
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EC		 701int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
702void mlx5_register_debugfs(void);
703void mlx5_unregister_debugfs(void);
704int mlx5_eq_init(struct mlx5_core_dev *dev);
705void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
706void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
707void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
5903325a 708void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
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HE		 709#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
710void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
711#endif
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EC		 712void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
713struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
714void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector);
715void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
716int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
717 int nent, u64 mask, const char *name, struct mlx5_uar *uar);
718int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
719int mlx5_start_eqs(struct mlx5_core_dev *dev);
720int mlx5_stop_eqs(struct mlx5_core_dev *dev);
233d05d2 721int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
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EC		 722int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
723int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
724
725int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
726void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
727int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
728 int size_in, void *data_out, int size_out,
729 u16 reg_num, int arg, int write);
f241e749 730int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
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EC		 731
732int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
733void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
734int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
735 struct mlx5_query_eq_mbox_out *out, int outlen);
736int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
737void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
738int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
739void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
740int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
741void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
742
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EC		 743const char *mlx5_command_str(int command);
744int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
745void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
3121e3c4
SG		 746int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
747 int npsvs, u32 *sig_index);
748int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
5903325a 749void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
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HE		 750int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
751 struct mlx5_odp_caps *odp_caps);
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EC		 752
753static inline u32 mlx5_mkey_to_idx(u32 mkey)
754{
755 return mkey >> 8;
756}
757
758static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
759{
760 return mkey_idx << 8;
761}
762
746b5583
EC		 763static inline u8 mlx5_mkey_variant(u32 mkey)
764{
765 return mkey & 0xff;
766}
767
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EC		 768enum {
769 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
c1868b82 770 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
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EC		 771};
772
773enum {
774 MAX_MR_CACHE_ENTRIES = 16,
775};
776
64613d94
SM		 777enum {
778 MLX5_INTERFACE_PROTOCOL_IB = 0,
779 MLX5_INTERFACE_PROTOCOL_ETH = 1,
780};
781
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JM		 782struct mlx5_interface {
783 void * (*add)(struct mlx5_core_dev *dev);
784 void (*remove)(struct mlx5_core_dev *dev, void *context);
785 void (*event)(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 786 enum mlx5_dev_event event, unsigned long param);
64613d94
SM		 787 void * (*get_dev)(void *context);
788 int protocol;
9603b61d
JM		 789 struct list_head list;
790};
791
64613d94 792void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
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JM		 793int mlx5_register_interface(struct mlx5_interface *intf);
794void mlx5_unregister_interface(struct mlx5_interface *intf);
795
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EC		 796struct mlx5_profile {
797 u64 mask;
f241e749 798 u8 log_max_qp;
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EC		 799 struct {
800 int size;
801 int limit;
802 } mr_cache[MAX_MR_CACHE_ENTRIES];
803};
804
805#endif /* MLX5_DRIVER_H */
Linux 6.x block layer and io_uring tree(s)