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e126ba97 EC |
1 | /* |
2 | * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DRIVER_H | |
34 | #define MLX5_DRIVER_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/pci.h> | |
39 | #include <linux/spinlock_types.h> | |
40 | #include <linux/semaphore.h> | |
41 | #include <linux/vmalloc.h> | |
42 | #include <linux/radix-tree.h> | |
43 | #include <linux/mlx5/device.h> | |
44 | #include <linux/mlx5/doorbell.h> | |
45 | ||
46 | enum { | |
47 | MLX5_BOARD_ID_LEN = 64, | |
48 | MLX5_MAX_NAME_LEN = 16, | |
49 | }; | |
50 | ||
51 | enum { | |
52 | /* one minute for the sake of bringup. Generally, commands must always | |
53 | * complete and we may need to increase this timeout value | |
54 | */ | |
55 | MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000, | |
56 | MLX5_CMD_WQ_MAX_NAME = 32, | |
57 | }; | |
58 | ||
59 | enum { | |
60 | CMD_OWNER_SW = 0x0, | |
61 | CMD_OWNER_HW = 0x1, | |
62 | CMD_STATUS_SUCCESS = 0, | |
63 | }; | |
64 | ||
65 | enum mlx5_sqp_t { | |
66 | MLX5_SQP_SMI = 0, | |
67 | MLX5_SQP_GSI = 1, | |
68 | MLX5_SQP_IEEE_1588 = 2, | |
69 | MLX5_SQP_SNIFFER = 3, | |
70 | MLX5_SQP_SYNC_UMR = 4, | |
71 | }; | |
72 | ||
73 | enum { | |
74 | MLX5_MAX_PORTS = 2, | |
75 | }; | |
76 | ||
77 | enum { | |
78 | MLX5_EQ_VEC_PAGES = 0, | |
79 | MLX5_EQ_VEC_CMD = 1, | |
80 | MLX5_EQ_VEC_ASYNC = 2, | |
81 | MLX5_EQ_VEC_COMP_BASE, | |
82 | }; | |
83 | ||
84 | enum { | |
ada9f5d0 | 85 | MLX5_MAX_EQ_NAME = 32 |
e126ba97 EC |
86 | }; |
87 | ||
88 | enum { | |
89 | MLX5_ATOMIC_MODE_IB_COMP = 1 << 16, | |
90 | MLX5_ATOMIC_MODE_CX = 2 << 16, | |
91 | MLX5_ATOMIC_MODE_8B = 3 << 16, | |
92 | MLX5_ATOMIC_MODE_16B = 4 << 16, | |
93 | MLX5_ATOMIC_MODE_32B = 5 << 16, | |
94 | MLX5_ATOMIC_MODE_64B = 6 << 16, | |
95 | MLX5_ATOMIC_MODE_128B = 7 << 16, | |
96 | MLX5_ATOMIC_MODE_256B = 8 << 16, | |
97 | }; | |
98 | ||
99 | enum { | |
100 | MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, | |
101 | MLX5_CMD_OP_QUERY_ADAPTER = 0x101, | |
102 | MLX5_CMD_OP_INIT_HCA = 0x102, | |
103 | MLX5_CMD_OP_TEARDOWN_HCA = 0x103, | |
cd23b14b EC |
104 | MLX5_CMD_OP_ENABLE_HCA = 0x104, |
105 | MLX5_CMD_OP_DISABLE_HCA = 0x105, | |
e126ba97 EC |
106 | MLX5_CMD_OP_QUERY_PAGES = 0x107, |
107 | MLX5_CMD_OP_MANAGE_PAGES = 0x108, | |
108 | MLX5_CMD_OP_SET_HCA_CAP = 0x109, | |
109 | ||
110 | MLX5_CMD_OP_CREATE_MKEY = 0x200, | |
111 | MLX5_CMD_OP_QUERY_MKEY = 0x201, | |
112 | MLX5_CMD_OP_DESTROY_MKEY = 0x202, | |
113 | MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, | |
114 | ||
115 | MLX5_CMD_OP_CREATE_EQ = 0x301, | |
116 | MLX5_CMD_OP_DESTROY_EQ = 0x302, | |
117 | MLX5_CMD_OP_QUERY_EQ = 0x303, | |
118 | ||
119 | MLX5_CMD_OP_CREATE_CQ = 0x400, | |
120 | MLX5_CMD_OP_DESTROY_CQ = 0x401, | |
121 | MLX5_CMD_OP_QUERY_CQ = 0x402, | |
122 | MLX5_CMD_OP_MODIFY_CQ = 0x403, | |
123 | ||
124 | MLX5_CMD_OP_CREATE_QP = 0x500, | |
125 | MLX5_CMD_OP_DESTROY_QP = 0x501, | |
126 | MLX5_CMD_OP_RST2INIT_QP = 0x502, | |
127 | MLX5_CMD_OP_INIT2RTR_QP = 0x503, | |
128 | MLX5_CMD_OP_RTR2RTS_QP = 0x504, | |
129 | MLX5_CMD_OP_RTS2RTS_QP = 0x505, | |
130 | MLX5_CMD_OP_SQERR2RTS_QP = 0x506, | |
131 | MLX5_CMD_OP_2ERR_QP = 0x507, | |
132 | MLX5_CMD_OP_RTS2SQD_QP = 0x508, | |
133 | MLX5_CMD_OP_SQD2RTS_QP = 0x509, | |
134 | MLX5_CMD_OP_2RST_QP = 0x50a, | |
135 | MLX5_CMD_OP_QUERY_QP = 0x50b, | |
136 | MLX5_CMD_OP_CONF_SQP = 0x50c, | |
137 | MLX5_CMD_OP_MAD_IFC = 0x50d, | |
138 | MLX5_CMD_OP_INIT2INIT_QP = 0x50e, | |
139 | MLX5_CMD_OP_SUSPEND_QP = 0x50f, | |
140 | MLX5_CMD_OP_UNSUSPEND_QP = 0x510, | |
141 | MLX5_CMD_OP_SQD2SQD_QP = 0x511, | |
142 | MLX5_CMD_OP_ALLOC_QP_COUNTER_SET = 0x512, | |
143 | MLX5_CMD_OP_DEALLOC_QP_COUNTER_SET = 0x513, | |
144 | MLX5_CMD_OP_QUERY_QP_COUNTER_SET = 0x514, | |
145 | ||
146 | MLX5_CMD_OP_CREATE_PSV = 0x600, | |
147 | MLX5_CMD_OP_DESTROY_PSV = 0x601, | |
148 | MLX5_CMD_OP_QUERY_PSV = 0x602, | |
149 | MLX5_CMD_OP_QUERY_SIG_RULE_TABLE = 0x603, | |
150 | MLX5_CMD_OP_QUERY_BLOCK_SIZE_TABLE = 0x604, | |
151 | ||
152 | MLX5_CMD_OP_CREATE_SRQ = 0x700, | |
153 | MLX5_CMD_OP_DESTROY_SRQ = 0x701, | |
154 | MLX5_CMD_OP_QUERY_SRQ = 0x702, | |
155 | MLX5_CMD_OP_ARM_RQ = 0x703, | |
156 | MLX5_CMD_OP_RESIZE_SRQ = 0x704, | |
157 | ||
158 | MLX5_CMD_OP_ALLOC_PD = 0x800, | |
159 | MLX5_CMD_OP_DEALLOC_PD = 0x801, | |
160 | MLX5_CMD_OP_ALLOC_UAR = 0x802, | |
161 | MLX5_CMD_OP_DEALLOC_UAR = 0x803, | |
162 | ||
163 | MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, | |
164 | MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, | |
165 | ||
166 | ||
167 | MLX5_CMD_OP_ALLOC_XRCD = 0x80e, | |
168 | MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, | |
169 | ||
170 | MLX5_CMD_OP_ACCESS_REG = 0x805, | |
171 | MLX5_CMD_OP_MAX = 0x810, | |
172 | }; | |
173 | ||
174 | enum { | |
175 | MLX5_REG_PCAP = 0x5001, | |
176 | MLX5_REG_PMTU = 0x5003, | |
177 | MLX5_REG_PTYS = 0x5004, | |
178 | MLX5_REG_PAOS = 0x5006, | |
179 | MLX5_REG_PMAOS = 0x5012, | |
180 | MLX5_REG_PUDE = 0x5009, | |
181 | MLX5_REG_PMPE = 0x5010, | |
182 | MLX5_REG_PELC = 0x500e, | |
183 | MLX5_REG_PMLP = 0, /* TBD */ | |
184 | MLX5_REG_NODE_DESC = 0x6001, | |
185 | MLX5_REG_HOST_ENDIANNESS = 0x7004, | |
186 | }; | |
187 | ||
188 | enum dbg_rsc_type { | |
189 | MLX5_DBG_RSC_QP, | |
190 | MLX5_DBG_RSC_EQ, | |
191 | MLX5_DBG_RSC_CQ, | |
192 | }; | |
193 | ||
194 | struct mlx5_field_desc { | |
195 | struct dentry *dent; | |
196 | int i; | |
197 | }; | |
198 | ||
199 | struct mlx5_rsc_debug { | |
200 | struct mlx5_core_dev *dev; | |
201 | void *object; | |
202 | enum dbg_rsc_type type; | |
203 | struct dentry *root; | |
204 | struct mlx5_field_desc fields[0]; | |
205 | }; | |
206 | ||
207 | enum mlx5_dev_event { | |
208 | MLX5_DEV_EVENT_SYS_ERROR, | |
209 | MLX5_DEV_EVENT_PORT_UP, | |
210 | MLX5_DEV_EVENT_PORT_DOWN, | |
211 | MLX5_DEV_EVENT_PORT_INITIALIZED, | |
212 | MLX5_DEV_EVENT_LID_CHANGE, | |
213 | MLX5_DEV_EVENT_PKEY_CHANGE, | |
214 | MLX5_DEV_EVENT_GUID_CHANGE, | |
215 | MLX5_DEV_EVENT_CLIENT_REREG, | |
216 | }; | |
217 | ||
218 | struct mlx5_uuar_info { | |
219 | struct mlx5_uar *uars; | |
220 | int num_uars; | |
221 | int num_low_latency_uuars; | |
222 | unsigned long *bitmap; | |
223 | unsigned int *count; | |
224 | struct mlx5_bf *bfs; | |
225 | ||
226 | /* | |
227 | * protect uuar allocation data structs | |
228 | */ | |
229 | struct mutex lock; | |
78c0f98c | 230 | u32 ver; |
e126ba97 EC |
231 | }; |
232 | ||
233 | struct mlx5_bf { | |
234 | void __iomem *reg; | |
235 | void __iomem *regreg; | |
236 | int buf_size; | |
237 | struct mlx5_uar *uar; | |
238 | unsigned long offset; | |
239 | int need_lock; | |
240 | /* protect blue flame buffer selection when needed | |
241 | */ | |
242 | spinlock_t lock; | |
243 | ||
244 | /* serialize 64 bit writes when done as two 32 bit accesses | |
245 | */ | |
246 | spinlock_t lock32; | |
247 | int uuarn; | |
248 | }; | |
249 | ||
250 | struct mlx5_cmd_first { | |
251 | __be32 data[4]; | |
252 | }; | |
253 | ||
254 | struct mlx5_cmd_msg { | |
255 | struct list_head list; | |
256 | struct cache_ent *cache; | |
257 | u32 len; | |
258 | struct mlx5_cmd_first first; | |
259 | struct mlx5_cmd_mailbox *next; | |
260 | }; | |
261 | ||
262 | struct mlx5_cmd_debug { | |
263 | struct dentry *dbg_root; | |
264 | struct dentry *dbg_in; | |
265 | struct dentry *dbg_out; | |
266 | struct dentry *dbg_outlen; | |
267 | struct dentry *dbg_status; | |
268 | struct dentry *dbg_run; | |
269 | void *in_msg; | |
270 | void *out_msg; | |
271 | u8 status; | |
272 | u16 inlen; | |
273 | u16 outlen; | |
274 | }; | |
275 | ||
276 | struct cache_ent { | |
277 | /* protect block chain allocations | |
278 | */ | |
279 | spinlock_t lock; | |
280 | struct list_head head; | |
281 | }; | |
282 | ||
283 | struct cmd_msg_cache { | |
284 | struct cache_ent large; | |
285 | struct cache_ent med; | |
286 | ||
287 | }; | |
288 | ||
289 | struct mlx5_cmd_stats { | |
290 | u64 sum; | |
291 | u64 n; | |
292 | struct dentry *root; | |
293 | struct dentry *avg; | |
294 | struct dentry *count; | |
295 | /* protect command average calculations */ | |
296 | spinlock_t lock; | |
297 | }; | |
298 | ||
299 | struct mlx5_cmd { | |
300 | void *cmd_buf; | |
301 | dma_addr_t dma; | |
302 | u16 cmdif_rev; | |
303 | u8 log_sz; | |
304 | u8 log_stride; | |
305 | int max_reg_cmds; | |
306 | int events; | |
307 | u32 __iomem *vector; | |
308 | ||
309 | /* protect command queue allocations | |
310 | */ | |
311 | spinlock_t alloc_lock; | |
312 | ||
313 | /* protect token allocations | |
314 | */ | |
315 | spinlock_t token_lock; | |
316 | u8 token; | |
317 | unsigned long bitmask; | |
318 | char wq_name[MLX5_CMD_WQ_MAX_NAME]; | |
319 | struct workqueue_struct *wq; | |
320 | struct semaphore sem; | |
321 | struct semaphore pages_sem; | |
322 | int mode; | |
323 | struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; | |
324 | struct pci_pool *pool; | |
325 | struct mlx5_cmd_debug dbg; | |
326 | struct cmd_msg_cache cache; | |
327 | int checksum_disabled; | |
328 | struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; | |
329 | }; | |
330 | ||
331 | struct mlx5_port_caps { | |
332 | int gid_table_len; | |
333 | int pkey_table_len; | |
334 | }; | |
335 | ||
336 | struct mlx5_caps { | |
337 | u8 log_max_eq; | |
338 | u8 log_max_cq; | |
339 | u8 log_max_qp; | |
340 | u8 log_max_mkey; | |
341 | u8 log_max_pd; | |
342 | u8 log_max_srq; | |
343 | u32 max_cqes; | |
344 | int max_wqes; | |
345 | int max_sq_desc_sz; | |
346 | int max_rq_desc_sz; | |
347 | u64 flags; | |
348 | u16 stat_rate_support; | |
349 | int log_max_msg; | |
350 | int num_ports; | |
351 | int max_ra_res_qp; | |
352 | int max_ra_req_qp; | |
353 | int max_srq_wqes; | |
354 | int bf_reg_size; | |
355 | int bf_regs_per_page; | |
356 | struct mlx5_port_caps port[MLX5_MAX_PORTS]; | |
357 | u8 ext_port_cap[MLX5_MAX_PORTS]; | |
358 | int max_vf; | |
359 | u32 reserved_lkey; | |
360 | u8 local_ca_ack_delay; | |
361 | u8 log_max_mcg; | |
0a324f31 | 362 | u32 max_qp_mcg; |
e126ba97 EC |
363 | int min_page_sz; |
364 | }; | |
365 | ||
366 | struct mlx5_cmd_mailbox { | |
367 | void *buf; | |
368 | dma_addr_t dma; | |
369 | struct mlx5_cmd_mailbox *next; | |
370 | }; | |
371 | ||
372 | struct mlx5_buf_list { | |
373 | void *buf; | |
374 | dma_addr_t map; | |
375 | }; | |
376 | ||
377 | struct mlx5_buf { | |
378 | struct mlx5_buf_list direct; | |
379 | struct mlx5_buf_list *page_list; | |
380 | int nbufs; | |
381 | int npages; | |
382 | int page_shift; | |
383 | int size; | |
384 | }; | |
385 | ||
386 | struct mlx5_eq { | |
387 | struct mlx5_core_dev *dev; | |
388 | __be32 __iomem *doorbell; | |
389 | u32 cons_index; | |
390 | struct mlx5_buf buf; | |
391 | int size; | |
392 | u8 irqn; | |
393 | u8 eqn; | |
394 | int nent; | |
395 | u64 mask; | |
396 | char name[MLX5_MAX_EQ_NAME]; | |
397 | struct list_head list; | |
398 | int index; | |
399 | struct mlx5_rsc_debug *dbg; | |
400 | }; | |
401 | ||
402 | ||
403 | struct mlx5_core_mr { | |
404 | u64 iova; | |
405 | u64 size; | |
406 | u32 key; | |
407 | u32 pd; | |
408 | u32 access; | |
409 | }; | |
410 | ||
411 | struct mlx5_core_srq { | |
412 | u32 srqn; | |
413 | int max; | |
414 | int max_gs; | |
415 | int max_avail_gather; | |
416 | int wqe_shift; | |
417 | void (*event) (struct mlx5_core_srq *, enum mlx5_event); | |
418 | ||
419 | atomic_t refcount; | |
420 | struct completion free; | |
421 | }; | |
422 | ||
423 | struct mlx5_eq_table { | |
424 | void __iomem *update_ci; | |
425 | void __iomem *update_arm_ci; | |
426 | struct list_head *comp_eq_head; | |
427 | struct mlx5_eq pages_eq; | |
428 | struct mlx5_eq async_eq; | |
429 | struct mlx5_eq cmd_eq; | |
430 | struct msix_entry *msix_arr; | |
431 | int num_comp_vectors; | |
432 | /* protect EQs list | |
433 | */ | |
434 | spinlock_t lock; | |
435 | }; | |
436 | ||
437 | struct mlx5_uar { | |
438 | u32 index; | |
439 | struct list_head bf_list; | |
440 | unsigned free_bf_bmap; | |
441 | void __iomem *wc_map; | |
442 | void __iomem *map; | |
443 | }; | |
444 | ||
445 | ||
446 | struct mlx5_core_health { | |
447 | struct health_buffer __iomem *health; | |
448 | __be32 __iomem *health_counter; | |
449 | struct timer_list timer; | |
450 | struct list_head list; | |
451 | u32 prev; | |
452 | int miss_counter; | |
453 | }; | |
454 | ||
455 | struct mlx5_cq_table { | |
456 | /* protect radix tree | |
457 | */ | |
458 | spinlock_t lock; | |
459 | struct radix_tree_root tree; | |
460 | }; | |
461 | ||
462 | struct mlx5_qp_table { | |
463 | /* protect radix tree | |
464 | */ | |
465 | spinlock_t lock; | |
466 | struct radix_tree_root tree; | |
467 | }; | |
468 | ||
469 | struct mlx5_srq_table { | |
470 | /* protect radix tree | |
471 | */ | |
472 | spinlock_t lock; | |
473 | struct radix_tree_root tree; | |
474 | }; | |
475 | ||
476 | struct mlx5_priv { | |
477 | char name[MLX5_MAX_NAME_LEN]; | |
478 | struct mlx5_eq_table eq_table; | |
479 | struct mlx5_uuar_info uuari; | |
480 | MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); | |
481 | ||
482 | /* pages stuff */ | |
483 | struct workqueue_struct *pg_wq; | |
484 | struct rb_root page_root; | |
485 | int fw_pages; | |
486 | int reg_pages; | |
bf0bf77f | 487 | struct list_head free_list; |
e126ba97 EC |
488 | |
489 | struct mlx5_core_health health; | |
490 | ||
491 | struct mlx5_srq_table srq_table; | |
492 | ||
493 | /* start: qp staff */ | |
494 | struct mlx5_qp_table qp_table; | |
495 | struct dentry *qp_debugfs; | |
496 | struct dentry *eq_debugfs; | |
497 | struct dentry *cq_debugfs; | |
498 | struct dentry *cmdif_debugfs; | |
499 | /* end: qp staff */ | |
500 | ||
501 | /* start: cq staff */ | |
502 | struct mlx5_cq_table cq_table; | |
503 | /* end: cq staff */ | |
504 | ||
505 | /* start: alloc staff */ | |
506 | struct mutex pgdir_mutex; | |
507 | struct list_head pgdir_list; | |
508 | /* end: alloc staff */ | |
509 | struct dentry *dbg_root; | |
510 | ||
511 | /* protect mkey key part */ | |
512 | spinlock_t mkey_lock; | |
513 | u8 mkey_key; | |
514 | }; | |
515 | ||
516 | struct mlx5_core_dev { | |
517 | struct pci_dev *pdev; | |
518 | u8 rev_id; | |
519 | char board_id[MLX5_BOARD_ID_LEN]; | |
520 | struct mlx5_cmd cmd; | |
521 | struct mlx5_caps caps; | |
522 | phys_addr_t iseg_base; | |
523 | struct mlx5_init_seg __iomem *iseg; | |
524 | void (*event) (struct mlx5_core_dev *dev, | |
525 | enum mlx5_dev_event event, | |
526 | void *data); | |
527 | struct mlx5_priv priv; | |
528 | struct mlx5_profile *profile; | |
529 | atomic_t num_qps; | |
530 | }; | |
531 | ||
532 | struct mlx5_db { | |
533 | __be32 *db; | |
534 | union { | |
535 | struct mlx5_db_pgdir *pgdir; | |
536 | struct mlx5_ib_user_db_page *user_page; | |
537 | } u; | |
538 | dma_addr_t dma; | |
539 | int index; | |
540 | }; | |
541 | ||
542 | enum { | |
543 | MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES, | |
544 | }; | |
545 | ||
546 | enum { | |
547 | MLX5_COMP_EQ_SIZE = 1024, | |
548 | }; | |
549 | ||
550 | struct mlx5_db_pgdir { | |
551 | struct list_head list; | |
552 | DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE); | |
553 | __be32 *db_page; | |
554 | dma_addr_t db_dma; | |
555 | }; | |
556 | ||
557 | typedef void (*mlx5_cmd_cbk_t)(int status, void *context); | |
558 | ||
559 | struct mlx5_cmd_work_ent { | |
560 | struct mlx5_cmd_msg *in; | |
561 | struct mlx5_cmd_msg *out; | |
746b5583 EC |
562 | void *uout; |
563 | int uout_size; | |
e126ba97 EC |
564 | mlx5_cmd_cbk_t callback; |
565 | void *context; | |
746b5583 | 566 | int idx; |
e126ba97 EC |
567 | struct completion done; |
568 | struct mlx5_cmd *cmd; | |
569 | struct work_struct work; | |
570 | struct mlx5_cmd_layout *lay; | |
571 | int ret; | |
572 | int page_queue; | |
573 | u8 status; | |
574 | u8 token; | |
575 | struct timespec ts1; | |
576 | struct timespec ts2; | |
746b5583 | 577 | u16 op; |
e126ba97 EC |
578 | }; |
579 | ||
580 | struct mlx5_pas { | |
581 | u64 pa; | |
582 | u8 log_sz; | |
583 | }; | |
584 | ||
585 | static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset) | |
586 | { | |
587 | if (likely(BITS_PER_LONG == 64 || buf->nbufs == 1)) | |
588 | return buf->direct.buf + offset; | |
589 | else | |
590 | return buf->page_list[offset >> PAGE_SHIFT].buf + | |
591 | (offset & (PAGE_SIZE - 1)); | |
592 | } | |
593 | ||
594 | extern struct workqueue_struct *mlx5_core_wq; | |
595 | ||
596 | #define STRUCT_FIELD(header, field) \ | |
597 | .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ | |
598 | .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field | |
599 | ||
600 | struct ib_field { | |
601 | size_t struct_offset_bytes; | |
602 | size_t struct_size_bytes; | |
603 | int offset_bits; | |
604 | int size_bits; | |
605 | }; | |
606 | ||
607 | static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) | |
608 | { | |
609 | return pci_get_drvdata(pdev); | |
610 | } | |
611 | ||
612 | extern struct dentry *mlx5_debugfs_root; | |
613 | ||
614 | static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) | |
615 | { | |
616 | return ioread32be(&dev->iseg->fw_rev) & 0xffff; | |
617 | } | |
618 | ||
619 | static inline u16 fw_rev_min(struct mlx5_core_dev *dev) | |
620 | { | |
621 | return ioread32be(&dev->iseg->fw_rev) >> 16; | |
622 | } | |
623 | ||
624 | static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) | |
625 | { | |
626 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; | |
627 | } | |
628 | ||
629 | static inline u16 cmdif_rev(struct mlx5_core_dev *dev) | |
630 | { | |
631 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; | |
632 | } | |
633 | ||
634 | static inline void *mlx5_vzalloc(unsigned long size) | |
635 | { | |
636 | void *rtn; | |
637 | ||
638 | rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); | |
639 | if (!rtn) | |
640 | rtn = vzalloc(size); | |
641 | return rtn; | |
642 | } | |
643 | ||
644 | static inline void mlx5_vfree(const void *addr) | |
645 | { | |
646 | if (addr && is_vmalloc_addr(addr)) | |
647 | vfree(addr); | |
648 | else | |
649 | kfree(addr); | |
650 | } | |
651 | ||
652 | int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev); | |
653 | void mlx5_dev_cleanup(struct mlx5_core_dev *dev); | |
654 | int mlx5_cmd_init(struct mlx5_core_dev *dev); | |
655 | void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); | |
656 | void mlx5_cmd_use_events(struct mlx5_core_dev *dev); | |
657 | void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); | |
658 | int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr); | |
659 | int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, | |
660 | int out_size); | |
746b5583 EC |
661 | int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, |
662 | void *out, int out_size, mlx5_cmd_cbk_t callback, | |
663 | void *context); | |
e126ba97 EC |
664 | int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); |
665 | int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); | |
666 | int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); | |
667 | int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); | |
668 | void mlx5_health_cleanup(void); | |
669 | void __init mlx5_health_init(void); | |
670 | void mlx5_start_health_poll(struct mlx5_core_dev *dev); | |
671 | void mlx5_stop_health_poll(struct mlx5_core_dev *dev); | |
672 | int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct, | |
673 | struct mlx5_buf *buf); | |
674 | void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); | |
675 | struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
676 | gfp_t flags, int npages); | |
677 | void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
678 | struct mlx5_cmd_mailbox *head); | |
679 | int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
680 | struct mlx5_create_srq_mbox_in *in, int inlen); | |
681 | int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); | |
682 | int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
683 | struct mlx5_query_srq_mbox_out *out); | |
684 | int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
685 | u16 lwm, int is_srq); | |
686 | int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, | |
746b5583 EC |
687 | struct mlx5_create_mkey_mbox_in *in, int inlen, |
688 | mlx5_cmd_cbk_t callback, void *context, | |
689 | struct mlx5_create_mkey_mbox_out *out); | |
e126ba97 EC |
690 | int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr); |
691 | int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, | |
692 | struct mlx5_query_mkey_mbox_out *out, int outlen); | |
693 | int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, | |
694 | u32 *mkey); | |
695 | int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); | |
696 | int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); | |
697 | int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, void *inb, void *outb, | |
698 | u16 opmod, int port); | |
699 | void mlx5_pagealloc_init(struct mlx5_core_dev *dev); | |
700 | void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); | |
701 | int mlx5_pagealloc_start(struct mlx5_core_dev *dev); | |
702 | void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); | |
703 | void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, | |
0a324f31 | 704 | s32 npages); |
cd23b14b | 705 | int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); |
e126ba97 EC |
706 | int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); |
707 | void mlx5_register_debugfs(void); | |
708 | void mlx5_unregister_debugfs(void); | |
709 | int mlx5_eq_init(struct mlx5_core_dev *dev); | |
710 | void mlx5_eq_cleanup(struct mlx5_core_dev *dev); | |
711 | void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); | |
712 | void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); | |
713 | void mlx5_qp_event(struct mlx5_core_dev *dev, u32 qpn, int event_type); | |
714 | void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); | |
715 | struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); | |
716 | void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector); | |
717 | void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); | |
718 | int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, | |
719 | int nent, u64 mask, const char *name, struct mlx5_uar *uar); | |
720 | int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); | |
721 | int mlx5_start_eqs(struct mlx5_core_dev *dev); | |
722 | int mlx5_stop_eqs(struct mlx5_core_dev *dev); | |
723 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); | |
724 | int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); | |
725 | ||
726 | int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); | |
727 | void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); | |
728 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, | |
729 | int size_in, void *data_out, int size_out, | |
730 | u16 reg_num, int arg, int write); | |
731 | int mlx5_set_port_caps(struct mlx5_core_dev *dev, int port_num, u32 caps); | |
732 | ||
733 | int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); | |
734 | void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); | |
735 | int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, | |
736 | struct mlx5_query_eq_mbox_out *out, int outlen); | |
737 | int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); | |
738 | void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); | |
739 | int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); | |
740 | void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); | |
741 | int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); | |
742 | void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); | |
743 | ||
e126ba97 EC |
744 | const char *mlx5_command_str(int command); |
745 | int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); | |
746 | void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); | |
747 | ||
748 | static inline u32 mlx5_mkey_to_idx(u32 mkey) | |
749 | { | |
750 | return mkey >> 8; | |
751 | } | |
752 | ||
753 | static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) | |
754 | { | |
755 | return mkey_idx << 8; | |
756 | } | |
757 | ||
746b5583 EC |
758 | static inline u8 mlx5_mkey_variant(u32 mkey) |
759 | { | |
760 | return mkey & 0xff; | |
761 | } | |
762 | ||
e126ba97 EC |
763 | enum { |
764 | MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, | |
c1868b82 | 765 | MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, |
e126ba97 EC |
766 | }; |
767 | ||
768 | enum { | |
769 | MAX_MR_CACHE_ENTRIES = 16, | |
770 | }; | |
771 | ||
772 | struct mlx5_profile { | |
773 | u64 mask; | |
774 | u32 log_max_qp; | |
e126ba97 EC |
775 | struct { |
776 | int size; | |
777 | int limit; | |
778 | } mr_cache[MAX_MR_CACHE_ENTRIES]; | |
779 | }; | |
780 | ||
781 | #endif /* MLX5_DRIVER_H */ |