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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DEVICE_H | |
34 | #define MLX5_DEVICE_H | |
35 | ||
36 | #include <linux/types.h> | |
37 | #include <rdma/ib_verbs.h> | |
e281682b | 38 | #include <linux/mlx5/mlx5_ifc.h> |
e126ba97 EC |
39 | |
40 | #if defined(__LITTLE_ENDIAN) | |
41 | #define MLX5_SET_HOST_ENDIANNESS 0 | |
42 | #elif defined(__BIG_ENDIAN) | |
43 | #define MLX5_SET_HOST_ENDIANNESS 0x80 | |
44 | #else | |
45 | #error Host endianness not defined | |
46 | #endif | |
47 | ||
d29b796a EC |
48 | /* helper macros */ |
49 | #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) | |
50 | #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) | |
51 | #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld))) | |
52 | #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) | |
53 | #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) | |
54 | #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) | |
55 | #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) | |
56 | #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) | |
57 | #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) | |
58 | ||
59 | #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) | |
60 | #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) | |
61 | #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) | |
938fe83c SM |
62 | #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) |
63 | #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) | |
d29b796a EC |
64 | #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) |
65 | #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) | |
66 | ||
67 | /* insert a value to a struct */ | |
68 | #define MLX5_SET(typ, p, fld, v) do { \ | |
69 | BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ | |
70 | *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ | |
71 | cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ | |
72 | (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ | |
73 | << __mlx5_dw_bit_off(typ, fld))); \ | |
74 | } while (0) | |
75 | ||
e281682b SM |
76 | #define MLX5_SET_TO_ONES(typ, p, fld) do { \ |
77 | BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ | |
78 | *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ | |
79 | cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ | |
80 | (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ | |
81 | << __mlx5_dw_bit_off(typ, fld))); \ | |
82 | } while (0) | |
83 | ||
d29b796a EC |
84 | #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ |
85 | __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ | |
86 | __mlx5_mask(typ, fld)) | |
87 | ||
88 | #define MLX5_GET_PR(typ, p, fld) ({ \ | |
89 | u32 ___t = MLX5_GET(typ, p, fld); \ | |
90 | pr_debug(#fld " = 0x%x\n", ___t); \ | |
91 | ___t; \ | |
92 | }) | |
93 | ||
94 | #define MLX5_SET64(typ, p, fld, v) do { \ | |
95 | BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ | |
96 | BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ | |
97 | *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ | |
98 | } while (0) | |
99 | ||
100 | #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) | |
101 | ||
707c4602 MD |
102 | #define MLX5_GET64_PR(typ, p, fld) ({ \ |
103 | u64 ___t = MLX5_GET64(typ, p, fld); \ | |
104 | pr_debug(#fld " = 0x%llx\n", ___t); \ | |
105 | ___t; \ | |
106 | }) | |
107 | ||
e126ba97 EC |
108 | enum { |
109 | MLX5_MAX_COMMANDS = 32, | |
110 | MLX5_CMD_DATA_BLOCK_SIZE = 512, | |
111 | MLX5_PCI_CMD_XPORT = 7, | |
3121e3c4 SG |
112 | MLX5_MKEY_BSF_OCTO_SIZE = 4, |
113 | MLX5_MAX_PSVS = 4, | |
e126ba97 EC |
114 | }; |
115 | ||
116 | enum { | |
117 | MLX5_EXTENDED_UD_AV = 0x80000000, | |
118 | }; | |
119 | ||
120 | enum { | |
121 | MLX5_CQ_STATE_ARMED = 9, | |
122 | MLX5_CQ_STATE_ALWAYS_ARMED = 0xb, | |
123 | MLX5_CQ_STATE_FIRED = 0xa, | |
124 | }; | |
125 | ||
126 | enum { | |
127 | MLX5_STAT_RATE_OFFSET = 5, | |
128 | }; | |
129 | ||
130 | enum { | |
131 | MLX5_INLINE_SEG = 0x80000000, | |
132 | }; | |
133 | ||
c7a08ac7 EC |
134 | enum { |
135 | MLX5_MIN_PKEY_TABLE_SIZE = 128, | |
136 | MLX5_MAX_LOG_PKEY_TABLE = 5, | |
137 | }; | |
138 | ||
e420f0c0 HE |
139 | enum { |
140 | MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 | |
141 | }; | |
142 | ||
143 | enum { | |
144 | MLX5_PFAULT_SUBTYPE_WQE = 0, | |
145 | MLX5_PFAULT_SUBTYPE_RDMA = 1, | |
146 | }; | |
147 | ||
e126ba97 EC |
148 | enum { |
149 | MLX5_PERM_LOCAL_READ = 1 << 2, | |
150 | MLX5_PERM_LOCAL_WRITE = 1 << 3, | |
151 | MLX5_PERM_REMOTE_READ = 1 << 4, | |
152 | MLX5_PERM_REMOTE_WRITE = 1 << 5, | |
153 | MLX5_PERM_ATOMIC = 1 << 6, | |
154 | MLX5_PERM_UMR_EN = 1 << 7, | |
155 | }; | |
156 | ||
157 | enum { | |
158 | MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, | |
159 | MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, | |
160 | MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, | |
161 | MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, | |
162 | MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, | |
163 | }; | |
164 | ||
165 | enum { | |
166 | MLX5_ACCESS_MODE_PA = 0, | |
167 | MLX5_ACCESS_MODE_MTT = 1, | |
168 | MLX5_ACCESS_MODE_KLM = 2 | |
169 | }; | |
170 | ||
171 | enum { | |
172 | MLX5_MKEY_REMOTE_INVAL = 1 << 24, | |
173 | MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, | |
174 | MLX5_MKEY_BSF_EN = 1 << 30, | |
175 | MLX5_MKEY_LEN64 = 1 << 31, | |
176 | }; | |
177 | ||
178 | enum { | |
179 | MLX5_EN_RD = (u64)1, | |
180 | MLX5_EN_WR = (u64)2 | |
181 | }; | |
182 | ||
183 | enum { | |
c1be5232 EC |
184 | MLX5_BF_REGS_PER_PAGE = 4, |
185 | MLX5_MAX_UAR_PAGES = 1 << 8, | |
186 | MLX5_NON_FP_BF_REGS_PER_PAGE = 2, | |
187 | MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE, | |
e126ba97 EC |
188 | }; |
189 | ||
190 | enum { | |
191 | MLX5_MKEY_MASK_LEN = 1ull << 0, | |
192 | MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, | |
193 | MLX5_MKEY_MASK_START_ADDR = 1ull << 6, | |
194 | MLX5_MKEY_MASK_PD = 1ull << 7, | |
195 | MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, | |
d5436ba0 | 196 | MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, |
e126ba97 EC |
197 | MLX5_MKEY_MASK_BSF_EN = 1ull << 12, |
198 | MLX5_MKEY_MASK_KEY = 1ull << 13, | |
199 | MLX5_MKEY_MASK_QPN = 1ull << 14, | |
200 | MLX5_MKEY_MASK_LR = 1ull << 17, | |
201 | MLX5_MKEY_MASK_LW = 1ull << 18, | |
202 | MLX5_MKEY_MASK_RR = 1ull << 19, | |
203 | MLX5_MKEY_MASK_RW = 1ull << 20, | |
204 | MLX5_MKEY_MASK_A = 1ull << 21, | |
205 | MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, | |
206 | MLX5_MKEY_MASK_FREE = 1ull << 29, | |
207 | }; | |
208 | ||
968e78dd HE |
209 | enum { |
210 | MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), | |
211 | ||
212 | MLX5_UMR_CHECK_NOT_FREE = (1 << 5), | |
213 | MLX5_UMR_CHECK_FREE = (2 << 5), | |
214 | ||
215 | MLX5_UMR_INLINE = (1 << 7), | |
216 | }; | |
217 | ||
cc149f75 HE |
218 | #define MLX5_UMR_MTT_ALIGNMENT 0x40 |
219 | #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) | |
832a6b06 | 220 | #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT |
cc149f75 | 221 | |
e126ba97 EC |
222 | enum mlx5_event { |
223 | MLX5_EVENT_TYPE_COMP = 0x0, | |
224 | ||
225 | MLX5_EVENT_TYPE_PATH_MIG = 0x01, | |
226 | MLX5_EVENT_TYPE_COMM_EST = 0x02, | |
227 | MLX5_EVENT_TYPE_SQ_DRAINED = 0x03, | |
228 | MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, | |
229 | MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, | |
230 | ||
231 | MLX5_EVENT_TYPE_CQ_ERROR = 0x04, | |
232 | MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, | |
233 | MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07, | |
234 | MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, | |
235 | MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, | |
236 | MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, | |
237 | ||
238 | MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08, | |
239 | MLX5_EVENT_TYPE_PORT_CHANGE = 0x09, | |
240 | MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, | |
241 | MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, | |
242 | ||
243 | MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, | |
244 | MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, | |
245 | ||
246 | MLX5_EVENT_TYPE_CMD = 0x0a, | |
247 | MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, | |
e420f0c0 HE |
248 | |
249 | MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, | |
e126ba97 EC |
250 | }; |
251 | ||
252 | enum { | |
253 | MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, | |
254 | MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, | |
255 | MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, | |
256 | MLX5_PORT_CHANGE_SUBTYPE_LID = 6, | |
257 | MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, | |
258 | MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, | |
259 | MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, | |
260 | }; | |
261 | ||
262 | enum { | |
e126ba97 | 263 | MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, |
e126ba97 EC |
264 | MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, |
265 | MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, | |
266 | MLX5_DEV_CAP_FLAG_APM = 1LL << 17, | |
267 | MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18, | |
f360d88a | 268 | MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, |
6cb7ff3d | 269 | MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24, |
3bdb31f6 | 270 | MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, |
bde51583 | 271 | MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, |
c7a08ac7 | 272 | MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, |
e126ba97 | 273 | MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, |
c1868b82 | 274 | MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, |
e126ba97 EC |
275 | }; |
276 | ||
277 | enum { | |
278 | MLX5_OPCODE_NOP = 0x00, | |
279 | MLX5_OPCODE_SEND_INVAL = 0x01, | |
280 | MLX5_OPCODE_RDMA_WRITE = 0x08, | |
281 | MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, | |
282 | MLX5_OPCODE_SEND = 0x0a, | |
283 | MLX5_OPCODE_SEND_IMM = 0x0b, | |
e281682b | 284 | MLX5_OPCODE_LSO = 0x0e, |
e126ba97 EC |
285 | MLX5_OPCODE_RDMA_READ = 0x10, |
286 | MLX5_OPCODE_ATOMIC_CS = 0x11, | |
287 | MLX5_OPCODE_ATOMIC_FA = 0x12, | |
288 | MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, | |
289 | MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, | |
290 | MLX5_OPCODE_BIND_MW = 0x18, | |
291 | MLX5_OPCODE_CONFIG_CMD = 0x1f, | |
292 | ||
293 | MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, | |
294 | MLX5_RECV_OPCODE_SEND = 0x01, | |
295 | MLX5_RECV_OPCODE_SEND_IMM = 0x02, | |
296 | MLX5_RECV_OPCODE_SEND_INVAL = 0x03, | |
297 | ||
298 | MLX5_CQE_OPCODE_ERROR = 0x1e, | |
299 | MLX5_CQE_OPCODE_RESIZE = 0x16, | |
300 | ||
301 | MLX5_OPCODE_SET_PSV = 0x20, | |
302 | MLX5_OPCODE_GET_PSV = 0x21, | |
303 | MLX5_OPCODE_CHECK_PSV = 0x22, | |
304 | MLX5_OPCODE_RGET_PSV = 0x26, | |
305 | MLX5_OPCODE_RCHECK_PSV = 0x27, | |
306 | ||
307 | MLX5_OPCODE_UMR = 0x25, | |
308 | ||
309 | }; | |
310 | ||
311 | enum { | |
312 | MLX5_SET_PORT_RESET_QKEY = 0, | |
313 | MLX5_SET_PORT_GUID0 = 16, | |
314 | MLX5_SET_PORT_NODE_GUID = 17, | |
315 | MLX5_SET_PORT_SYS_GUID = 18, | |
316 | MLX5_SET_PORT_GID_TABLE = 19, | |
317 | MLX5_SET_PORT_PKEY_TABLE = 20, | |
318 | }; | |
319 | ||
320 | enum { | |
321 | MLX5_MAX_PAGE_SHIFT = 31 | |
322 | }; | |
323 | ||
1b77d2bd | 324 | enum { |
05bdb2ab EC |
325 | MLX5_ADAPTER_PAGE_SHIFT = 12, |
326 | MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, | |
1b77d2bd EC |
327 | }; |
328 | ||
87b8de49 | 329 | enum { |
87b8de49 EC |
330 | MLX5_CAP_OFF_CMDIF_CSUM = 46, |
331 | }; | |
332 | ||
e126ba97 EC |
333 | struct mlx5_inbox_hdr { |
334 | __be16 opcode; | |
335 | u8 rsvd[4]; | |
336 | __be16 opmod; | |
337 | }; | |
338 | ||
339 | struct mlx5_outbox_hdr { | |
340 | u8 status; | |
341 | u8 rsvd[3]; | |
342 | __be32 syndrome; | |
343 | }; | |
344 | ||
345 | struct mlx5_cmd_query_adapter_mbox_in { | |
346 | struct mlx5_inbox_hdr hdr; | |
347 | u8 rsvd[8]; | |
348 | }; | |
349 | ||
350 | struct mlx5_cmd_query_adapter_mbox_out { | |
351 | struct mlx5_outbox_hdr hdr; | |
352 | u8 rsvd0[24]; | |
353 | u8 intapin; | |
354 | u8 rsvd1[13]; | |
355 | __be16 vsd_vendor_id; | |
356 | u8 vsd[208]; | |
357 | u8 vsd_psid[16]; | |
358 | }; | |
359 | ||
e420f0c0 HE |
360 | enum mlx5_odp_transport_cap_bits { |
361 | MLX5_ODP_SUPPORT_SEND = 1 << 31, | |
362 | MLX5_ODP_SUPPORT_RECV = 1 << 30, | |
363 | MLX5_ODP_SUPPORT_WRITE = 1 << 29, | |
364 | MLX5_ODP_SUPPORT_READ = 1 << 28, | |
365 | }; | |
366 | ||
367 | struct mlx5_odp_caps { | |
368 | char reserved[0x10]; | |
369 | struct { | |
370 | __be32 rc_odp_caps; | |
371 | __be32 uc_odp_caps; | |
372 | __be32 ud_odp_caps; | |
373 | } per_transport_caps; | |
374 | char reserved2[0xe4]; | |
375 | }; | |
376 | ||
e126ba97 EC |
377 | struct mlx5_cmd_init_hca_mbox_in { |
378 | struct mlx5_inbox_hdr hdr; | |
379 | u8 rsvd0[2]; | |
380 | __be16 profile; | |
381 | u8 rsvd1[4]; | |
382 | }; | |
383 | ||
384 | struct mlx5_cmd_init_hca_mbox_out { | |
385 | struct mlx5_outbox_hdr hdr; | |
386 | u8 rsvd[8]; | |
387 | }; | |
388 | ||
389 | struct mlx5_cmd_teardown_hca_mbox_in { | |
390 | struct mlx5_inbox_hdr hdr; | |
391 | u8 rsvd0[2]; | |
392 | __be16 profile; | |
393 | u8 rsvd1[4]; | |
394 | }; | |
395 | ||
396 | struct mlx5_cmd_teardown_hca_mbox_out { | |
397 | struct mlx5_outbox_hdr hdr; | |
398 | u8 rsvd[8]; | |
399 | }; | |
400 | ||
401 | struct mlx5_cmd_layout { | |
402 | u8 type; | |
403 | u8 rsvd0[3]; | |
404 | __be32 inlen; | |
405 | __be64 in_ptr; | |
406 | __be32 in[4]; | |
407 | __be32 out[4]; | |
408 | __be64 out_ptr; | |
409 | __be32 outlen; | |
410 | u8 token; | |
411 | u8 sig; | |
412 | u8 rsvd1; | |
413 | u8 status_own; | |
414 | }; | |
415 | ||
416 | ||
417 | struct health_buffer { | |
418 | __be32 assert_var[5]; | |
419 | __be32 rsvd0[3]; | |
420 | __be32 assert_exit_ptr; | |
421 | __be32 assert_callra; | |
422 | __be32 rsvd1[2]; | |
423 | __be32 fw_ver; | |
424 | __be32 hw_id; | |
425 | __be32 rsvd2; | |
426 | u8 irisc_index; | |
427 | u8 synd; | |
428 | __be16 ext_sync; | |
429 | }; | |
430 | ||
431 | struct mlx5_init_seg { | |
432 | __be32 fw_rev; | |
433 | __be32 cmdif_rev_fw_sub; | |
434 | __be32 rsvd0[2]; | |
435 | __be32 cmdq_addr_h; | |
436 | __be32 cmdq_addr_l_sz; | |
437 | __be32 cmd_dbell; | |
438 | __be32 rsvd1[121]; | |
439 | struct health_buffer health; | |
440 | __be32 rsvd2[884]; | |
441 | __be32 health_counter; | |
2f6daec1 | 442 | __be32 rsvd3[1019]; |
e126ba97 EC |
443 | __be64 ieee1588_clk; |
444 | __be32 ieee1588_clk_type; | |
445 | __be32 clr_intx; | |
446 | }; | |
447 | ||
448 | struct mlx5_eqe_comp { | |
449 | __be32 reserved[6]; | |
450 | __be32 cqn; | |
451 | }; | |
452 | ||
453 | struct mlx5_eqe_qp_srq { | |
454 | __be32 reserved[6]; | |
455 | __be32 qp_srq_n; | |
456 | }; | |
457 | ||
458 | struct mlx5_eqe_cq_err { | |
459 | __be32 cqn; | |
460 | u8 reserved1[7]; | |
461 | u8 syndrome; | |
462 | }; | |
463 | ||
e126ba97 EC |
464 | struct mlx5_eqe_port_state { |
465 | u8 reserved0[8]; | |
466 | u8 port; | |
467 | }; | |
468 | ||
469 | struct mlx5_eqe_gpio { | |
470 | __be32 reserved0[2]; | |
471 | __be64 gpio_event; | |
472 | }; | |
473 | ||
474 | struct mlx5_eqe_congestion { | |
475 | u8 type; | |
476 | u8 rsvd0; | |
477 | u8 congestion_level; | |
478 | }; | |
479 | ||
480 | struct mlx5_eqe_stall_vl { | |
481 | u8 rsvd0[3]; | |
482 | u8 port_vl; | |
483 | }; | |
484 | ||
485 | struct mlx5_eqe_cmd { | |
486 | __be32 vector; | |
487 | __be32 rsvd[6]; | |
488 | }; | |
489 | ||
490 | struct mlx5_eqe_page_req { | |
491 | u8 rsvd0[2]; | |
492 | __be16 func_id; | |
0a324f31 ML |
493 | __be32 num_pages; |
494 | __be32 rsvd1[5]; | |
e126ba97 EC |
495 | }; |
496 | ||
e420f0c0 HE |
497 | struct mlx5_eqe_page_fault { |
498 | __be32 bytes_committed; | |
499 | union { | |
500 | struct { | |
501 | u16 reserved1; | |
502 | __be16 wqe_index; | |
503 | u16 reserved2; | |
504 | __be16 packet_length; | |
505 | u8 reserved3[12]; | |
506 | } __packed wqe; | |
507 | struct { | |
508 | __be32 r_key; | |
509 | u16 reserved1; | |
510 | __be16 packet_length; | |
511 | __be32 rdma_op_len; | |
512 | __be64 rdma_va; | |
513 | } __packed rdma; | |
514 | } __packed; | |
515 | __be32 flags_qpn; | |
516 | } __packed; | |
517 | ||
e126ba97 EC |
518 | union ev_data { |
519 | __be32 raw[7]; | |
520 | struct mlx5_eqe_cmd cmd; | |
521 | struct mlx5_eqe_comp comp; | |
522 | struct mlx5_eqe_qp_srq qp_srq; | |
523 | struct mlx5_eqe_cq_err cq_err; | |
e126ba97 EC |
524 | struct mlx5_eqe_port_state port; |
525 | struct mlx5_eqe_gpio gpio; | |
526 | struct mlx5_eqe_congestion cong; | |
527 | struct mlx5_eqe_stall_vl stall_vl; | |
528 | struct mlx5_eqe_page_req req_pages; | |
e420f0c0 | 529 | struct mlx5_eqe_page_fault page_fault; |
e126ba97 EC |
530 | } __packed; |
531 | ||
532 | struct mlx5_eqe { | |
533 | u8 rsvd0; | |
534 | u8 type; | |
535 | u8 rsvd1; | |
536 | u8 sub_type; | |
537 | __be32 rsvd2[7]; | |
538 | union ev_data data; | |
539 | __be16 rsvd3; | |
540 | u8 signature; | |
541 | u8 owner; | |
542 | } __packed; | |
543 | ||
544 | struct mlx5_cmd_prot_block { | |
545 | u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; | |
546 | u8 rsvd0[48]; | |
547 | __be64 next; | |
548 | __be32 block_num; | |
549 | u8 rsvd1; | |
550 | u8 token; | |
551 | u8 ctrl_sig; | |
552 | u8 sig; | |
553 | }; | |
554 | ||
e281682b SM |
555 | enum { |
556 | MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, | |
557 | }; | |
558 | ||
e126ba97 EC |
559 | struct mlx5_err_cqe { |
560 | u8 rsvd0[32]; | |
561 | __be32 srqn; | |
562 | u8 rsvd1[18]; | |
563 | u8 vendor_err_synd; | |
564 | u8 syndrome; | |
565 | __be32 s_wqe_opcode_qpn; | |
566 | __be16 wqe_counter; | |
567 | u8 signature; | |
568 | u8 op_own; | |
569 | }; | |
570 | ||
571 | struct mlx5_cqe64 { | |
e281682b SM |
572 | u8 rsvd0[4]; |
573 | u8 lro_tcppsh_abort_dupack; | |
574 | u8 lro_min_ttl; | |
575 | __be16 lro_tcp_win; | |
576 | __be32 lro_ack_seq_num; | |
577 | __be32 rss_hash_result; | |
578 | u8 rss_hash_type; | |
e126ba97 | 579 | u8 ml_path; |
e281682b SM |
580 | u8 rsvd20[2]; |
581 | __be16 check_sum; | |
e126ba97 EC |
582 | __be16 slid; |
583 | __be32 flags_rqpn; | |
e281682b SM |
584 | u8 hds_ip_ext; |
585 | u8 l4_hdr_type_etc; | |
586 | __be16 vlan_info; | |
587 | __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ | |
e126ba97 EC |
588 | __be32 imm_inval_pkey; |
589 | u8 rsvd40[4]; | |
590 | __be32 byte_cnt; | |
591 | __be64 timestamp; | |
592 | __be32 sop_drop_qpn; | |
593 | __be16 wqe_counter; | |
594 | u8 signature; | |
595 | u8 op_own; | |
596 | }; | |
597 | ||
e281682b SM |
598 | static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) |
599 | { | |
600 | return (cqe->lro_tcppsh_abort_dupack >> 6) & 1; | |
601 | } | |
602 | ||
603 | static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) | |
604 | { | |
605 | return (cqe->l4_hdr_type_etc >> 4) & 0x7; | |
606 | } | |
607 | ||
608 | static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe) | |
609 | { | |
610 | return !!(cqe->l4_hdr_type_etc & 0x1); | |
611 | } | |
612 | ||
613 | enum { | |
614 | CQE_L4_HDR_TYPE_NONE = 0x0, | |
615 | CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, | |
616 | CQE_L4_HDR_TYPE_UDP = 0x2, | |
617 | CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, | |
618 | CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, | |
619 | }; | |
620 | ||
621 | enum { | |
622 | CQE_RSS_HTYPE_IP = 0x3 << 6, | |
623 | CQE_RSS_HTYPE_L4 = 0x3 << 2, | |
624 | }; | |
625 | ||
626 | enum { | |
627 | CQE_L2_OK = 1 << 0, | |
628 | CQE_L3_OK = 1 << 1, | |
629 | CQE_L4_OK = 1 << 2, | |
630 | }; | |
631 | ||
d5436ba0 SG |
632 | struct mlx5_sig_err_cqe { |
633 | u8 rsvd0[16]; | |
634 | __be32 expected_trans_sig; | |
635 | __be32 actual_trans_sig; | |
636 | __be32 expected_reftag; | |
637 | __be32 actual_reftag; | |
638 | __be16 syndrome; | |
639 | u8 rsvd22[2]; | |
640 | __be32 mkey; | |
641 | __be64 err_offset; | |
642 | u8 rsvd30[8]; | |
643 | __be32 qpn; | |
644 | u8 rsvd38[2]; | |
645 | u8 signature; | |
646 | u8 op_own; | |
647 | }; | |
648 | ||
e126ba97 EC |
649 | struct mlx5_wqe_srq_next_seg { |
650 | u8 rsvd0[2]; | |
651 | __be16 next_wqe_index; | |
652 | u8 signature; | |
653 | u8 rsvd1[11]; | |
654 | }; | |
655 | ||
656 | union mlx5_ext_cqe { | |
657 | struct ib_grh grh; | |
658 | u8 inl[64]; | |
659 | }; | |
660 | ||
661 | struct mlx5_cqe128 { | |
662 | union mlx5_ext_cqe inl_grh; | |
663 | struct mlx5_cqe64 cqe64; | |
664 | }; | |
665 | ||
666 | struct mlx5_srq_ctx { | |
667 | u8 state_log_sz; | |
668 | u8 rsvd0[3]; | |
669 | __be32 flags_xrcd; | |
670 | __be32 pgoff_cqn; | |
671 | u8 rsvd1[4]; | |
672 | u8 log_pg_sz; | |
673 | u8 rsvd2[7]; | |
674 | __be32 pd; | |
675 | __be16 lwm; | |
676 | __be16 wqe_cnt; | |
677 | u8 rsvd3[8]; | |
678 | __be64 db_record; | |
679 | }; | |
680 | ||
681 | struct mlx5_create_srq_mbox_in { | |
682 | struct mlx5_inbox_hdr hdr; | |
683 | __be32 input_srqn; | |
684 | u8 rsvd0[4]; | |
685 | struct mlx5_srq_ctx ctx; | |
686 | u8 rsvd1[208]; | |
687 | __be64 pas[0]; | |
688 | }; | |
689 | ||
690 | struct mlx5_create_srq_mbox_out { | |
691 | struct mlx5_outbox_hdr hdr; | |
692 | __be32 srqn; | |
693 | u8 rsvd[4]; | |
694 | }; | |
695 | ||
696 | struct mlx5_destroy_srq_mbox_in { | |
697 | struct mlx5_inbox_hdr hdr; | |
698 | __be32 srqn; | |
699 | u8 rsvd[4]; | |
700 | }; | |
701 | ||
702 | struct mlx5_destroy_srq_mbox_out { | |
703 | struct mlx5_outbox_hdr hdr; | |
704 | u8 rsvd[8]; | |
705 | }; | |
706 | ||
707 | struct mlx5_query_srq_mbox_in { | |
708 | struct mlx5_inbox_hdr hdr; | |
709 | __be32 srqn; | |
710 | u8 rsvd0[4]; | |
711 | }; | |
712 | ||
713 | struct mlx5_query_srq_mbox_out { | |
714 | struct mlx5_outbox_hdr hdr; | |
715 | u8 rsvd0[8]; | |
716 | struct mlx5_srq_ctx ctx; | |
717 | u8 rsvd1[32]; | |
718 | __be64 pas[0]; | |
719 | }; | |
720 | ||
721 | struct mlx5_arm_srq_mbox_in { | |
722 | struct mlx5_inbox_hdr hdr; | |
723 | __be32 srqn; | |
724 | __be16 rsvd; | |
725 | __be16 lwm; | |
726 | }; | |
727 | ||
728 | struct mlx5_arm_srq_mbox_out { | |
729 | struct mlx5_outbox_hdr hdr; | |
730 | u8 rsvd[8]; | |
731 | }; | |
732 | ||
733 | struct mlx5_cq_context { | |
734 | u8 status; | |
735 | u8 cqe_sz_flags; | |
736 | u8 st; | |
737 | u8 rsvd3; | |
738 | u8 rsvd4[6]; | |
739 | __be16 page_offset; | |
740 | __be32 log_sz_usr_page; | |
741 | __be16 cq_period; | |
742 | __be16 cq_max_count; | |
743 | __be16 rsvd20; | |
744 | __be16 c_eqn; | |
745 | u8 log_pg_sz; | |
746 | u8 rsvd25[7]; | |
747 | __be32 last_notified_index; | |
748 | __be32 solicit_producer_index; | |
749 | __be32 consumer_counter; | |
750 | __be32 producer_counter; | |
751 | u8 rsvd48[8]; | |
752 | __be64 db_record_addr; | |
753 | }; | |
754 | ||
755 | struct mlx5_create_cq_mbox_in { | |
756 | struct mlx5_inbox_hdr hdr; | |
757 | __be32 input_cqn; | |
758 | u8 rsvdx[4]; | |
759 | struct mlx5_cq_context ctx; | |
760 | u8 rsvd6[192]; | |
761 | __be64 pas[0]; | |
762 | }; | |
763 | ||
764 | struct mlx5_create_cq_mbox_out { | |
765 | struct mlx5_outbox_hdr hdr; | |
766 | __be32 cqn; | |
767 | u8 rsvd0[4]; | |
768 | }; | |
769 | ||
770 | struct mlx5_destroy_cq_mbox_in { | |
771 | struct mlx5_inbox_hdr hdr; | |
772 | __be32 cqn; | |
773 | u8 rsvd0[4]; | |
774 | }; | |
775 | ||
776 | struct mlx5_destroy_cq_mbox_out { | |
777 | struct mlx5_outbox_hdr hdr; | |
778 | u8 rsvd0[8]; | |
779 | }; | |
780 | ||
781 | struct mlx5_query_cq_mbox_in { | |
782 | struct mlx5_inbox_hdr hdr; | |
783 | __be32 cqn; | |
784 | u8 rsvd0[4]; | |
785 | }; | |
786 | ||
787 | struct mlx5_query_cq_mbox_out { | |
788 | struct mlx5_outbox_hdr hdr; | |
789 | u8 rsvd0[8]; | |
790 | struct mlx5_cq_context ctx; | |
791 | u8 rsvd6[16]; | |
792 | __be64 pas[0]; | |
793 | }; | |
794 | ||
3bdb31f6 EC |
795 | struct mlx5_modify_cq_mbox_in { |
796 | struct mlx5_inbox_hdr hdr; | |
797 | __be32 cqn; | |
798 | __be32 field_select; | |
799 | struct mlx5_cq_context ctx; | |
800 | u8 rsvd[192]; | |
801 | __be64 pas[0]; | |
802 | }; | |
803 | ||
804 | struct mlx5_modify_cq_mbox_out { | |
805 | struct mlx5_outbox_hdr hdr; | |
bde51583 | 806 | u8 rsvd[8]; |
3bdb31f6 EC |
807 | }; |
808 | ||
cd23b14b EC |
809 | struct mlx5_enable_hca_mbox_in { |
810 | struct mlx5_inbox_hdr hdr; | |
811 | u8 rsvd[8]; | |
812 | }; | |
813 | ||
814 | struct mlx5_enable_hca_mbox_out { | |
815 | struct mlx5_outbox_hdr hdr; | |
816 | u8 rsvd[8]; | |
817 | }; | |
818 | ||
819 | struct mlx5_disable_hca_mbox_in { | |
820 | struct mlx5_inbox_hdr hdr; | |
821 | u8 rsvd[8]; | |
822 | }; | |
823 | ||
824 | struct mlx5_disable_hca_mbox_out { | |
825 | struct mlx5_outbox_hdr hdr; | |
826 | u8 rsvd[8]; | |
827 | }; | |
828 | ||
e126ba97 EC |
829 | struct mlx5_eq_context { |
830 | u8 status; | |
831 | u8 ec_oi; | |
832 | u8 st; | |
833 | u8 rsvd2[7]; | |
834 | __be16 page_pffset; | |
835 | __be32 log_sz_usr_page; | |
836 | u8 rsvd3[7]; | |
837 | u8 intr; | |
838 | u8 log_page_size; | |
839 | u8 rsvd4[15]; | |
840 | __be32 consumer_counter; | |
841 | __be32 produser_counter; | |
842 | u8 rsvd5[16]; | |
843 | }; | |
844 | ||
845 | struct mlx5_create_eq_mbox_in { | |
846 | struct mlx5_inbox_hdr hdr; | |
847 | u8 rsvd0[3]; | |
848 | u8 input_eqn; | |
849 | u8 rsvd1[4]; | |
850 | struct mlx5_eq_context ctx; | |
851 | u8 rsvd2[8]; | |
852 | __be64 events_mask; | |
853 | u8 rsvd3[176]; | |
854 | __be64 pas[0]; | |
855 | }; | |
856 | ||
857 | struct mlx5_create_eq_mbox_out { | |
858 | struct mlx5_outbox_hdr hdr; | |
859 | u8 rsvd0[3]; | |
860 | u8 eq_number; | |
861 | u8 rsvd1[4]; | |
862 | }; | |
863 | ||
864 | struct mlx5_destroy_eq_mbox_in { | |
865 | struct mlx5_inbox_hdr hdr; | |
866 | u8 rsvd0[3]; | |
867 | u8 eqn; | |
868 | u8 rsvd1[4]; | |
869 | }; | |
870 | ||
871 | struct mlx5_destroy_eq_mbox_out { | |
872 | struct mlx5_outbox_hdr hdr; | |
873 | u8 rsvd[8]; | |
874 | }; | |
875 | ||
876 | struct mlx5_map_eq_mbox_in { | |
877 | struct mlx5_inbox_hdr hdr; | |
878 | __be64 mask; | |
879 | u8 mu; | |
880 | u8 rsvd0[2]; | |
881 | u8 eqn; | |
882 | u8 rsvd1[24]; | |
883 | }; | |
884 | ||
885 | struct mlx5_map_eq_mbox_out { | |
886 | struct mlx5_outbox_hdr hdr; | |
887 | u8 rsvd[8]; | |
888 | }; | |
889 | ||
890 | struct mlx5_query_eq_mbox_in { | |
891 | struct mlx5_inbox_hdr hdr; | |
892 | u8 rsvd0[3]; | |
893 | u8 eqn; | |
894 | u8 rsvd1[4]; | |
895 | }; | |
896 | ||
897 | struct mlx5_query_eq_mbox_out { | |
898 | struct mlx5_outbox_hdr hdr; | |
899 | u8 rsvd[8]; | |
900 | struct mlx5_eq_context ctx; | |
901 | }; | |
902 | ||
968e78dd HE |
903 | enum { |
904 | MLX5_MKEY_STATUS_FREE = 1 << 6, | |
905 | }; | |
906 | ||
e126ba97 EC |
907 | struct mlx5_mkey_seg { |
908 | /* This is a two bit field occupying bits 31-30. | |
909 | * bit 31 is always 0, | |
910 | * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation | |
911 | */ | |
912 | u8 status; | |
913 | u8 pcie_control; | |
914 | u8 flags; | |
915 | u8 version; | |
916 | __be32 qpn_mkey7_0; | |
917 | u8 rsvd1[4]; | |
918 | __be32 flags_pd; | |
919 | __be64 start_addr; | |
920 | __be64 len; | |
921 | __be32 bsfs_octo_size; | |
922 | u8 rsvd2[16]; | |
923 | __be32 xlt_oct_size; | |
924 | u8 rsvd3[3]; | |
925 | u8 log2_page_size; | |
926 | u8 rsvd4[4]; | |
927 | }; | |
928 | ||
929 | struct mlx5_query_special_ctxs_mbox_in { | |
930 | struct mlx5_inbox_hdr hdr; | |
931 | u8 rsvd[8]; | |
932 | }; | |
933 | ||
934 | struct mlx5_query_special_ctxs_mbox_out { | |
935 | struct mlx5_outbox_hdr hdr; | |
936 | __be32 dump_fill_mkey; | |
937 | __be32 reserved_lkey; | |
938 | }; | |
939 | ||
940 | struct mlx5_create_mkey_mbox_in { | |
941 | struct mlx5_inbox_hdr hdr; | |
942 | __be32 input_mkey_index; | |
e420f0c0 | 943 | __be32 flags; |
e126ba97 EC |
944 | struct mlx5_mkey_seg seg; |
945 | u8 rsvd1[16]; | |
946 | __be32 xlat_oct_act_size; | |
8c8a4914 EC |
947 | __be32 rsvd2; |
948 | u8 rsvd3[168]; | |
e126ba97 EC |
949 | __be64 pas[0]; |
950 | }; | |
951 | ||
952 | struct mlx5_create_mkey_mbox_out { | |
953 | struct mlx5_outbox_hdr hdr; | |
954 | __be32 mkey; | |
955 | u8 rsvd[4]; | |
956 | }; | |
957 | ||
958 | struct mlx5_destroy_mkey_mbox_in { | |
959 | struct mlx5_inbox_hdr hdr; | |
960 | __be32 mkey; | |
961 | u8 rsvd[4]; | |
962 | }; | |
963 | ||
964 | struct mlx5_destroy_mkey_mbox_out { | |
965 | struct mlx5_outbox_hdr hdr; | |
966 | u8 rsvd[8]; | |
967 | }; | |
968 | ||
969 | struct mlx5_query_mkey_mbox_in { | |
970 | struct mlx5_inbox_hdr hdr; | |
971 | __be32 mkey; | |
972 | }; | |
973 | ||
974 | struct mlx5_query_mkey_mbox_out { | |
975 | struct mlx5_outbox_hdr hdr; | |
976 | __be64 pas[0]; | |
977 | }; | |
978 | ||
979 | struct mlx5_modify_mkey_mbox_in { | |
980 | struct mlx5_inbox_hdr hdr; | |
981 | __be32 mkey; | |
982 | __be64 pas[0]; | |
983 | }; | |
984 | ||
985 | struct mlx5_modify_mkey_mbox_out { | |
986 | struct mlx5_outbox_hdr hdr; | |
3bdb31f6 | 987 | u8 rsvd[8]; |
e126ba97 EC |
988 | }; |
989 | ||
990 | struct mlx5_dump_mkey_mbox_in { | |
991 | struct mlx5_inbox_hdr hdr; | |
992 | }; | |
993 | ||
994 | struct mlx5_dump_mkey_mbox_out { | |
995 | struct mlx5_outbox_hdr hdr; | |
996 | __be32 mkey; | |
997 | }; | |
998 | ||
999 | struct mlx5_mad_ifc_mbox_in { | |
1000 | struct mlx5_inbox_hdr hdr; | |
1001 | __be16 remote_lid; | |
1002 | u8 rsvd0; | |
1003 | u8 port; | |
1004 | u8 rsvd1[4]; | |
1005 | u8 data[256]; | |
1006 | }; | |
1007 | ||
1008 | struct mlx5_mad_ifc_mbox_out { | |
1009 | struct mlx5_outbox_hdr hdr; | |
1010 | u8 rsvd[8]; | |
1011 | u8 data[256]; | |
1012 | }; | |
1013 | ||
1014 | struct mlx5_access_reg_mbox_in { | |
1015 | struct mlx5_inbox_hdr hdr; | |
1016 | u8 rsvd0[2]; | |
1017 | __be16 register_id; | |
1018 | __be32 arg; | |
1019 | __be32 data[0]; | |
1020 | }; | |
1021 | ||
1022 | struct mlx5_access_reg_mbox_out { | |
1023 | struct mlx5_outbox_hdr hdr; | |
1024 | u8 rsvd[8]; | |
1025 | __be32 data[0]; | |
1026 | }; | |
1027 | ||
1028 | #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) | |
1029 | ||
1030 | enum { | |
1031 | MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 | |
1032 | }; | |
1033 | ||
3121e3c4 SG |
1034 | struct mlx5_allocate_psv_in { |
1035 | struct mlx5_inbox_hdr hdr; | |
1036 | __be32 npsv_pd; | |
1037 | __be32 rsvd_psv0; | |
1038 | }; | |
1039 | ||
1040 | struct mlx5_allocate_psv_out { | |
1041 | struct mlx5_outbox_hdr hdr; | |
1042 | u8 rsvd[8]; | |
1043 | __be32 psv_idx[4]; | |
1044 | }; | |
1045 | ||
1046 | struct mlx5_destroy_psv_in { | |
1047 | struct mlx5_inbox_hdr hdr; | |
1048 | __be32 psv_number; | |
1049 | u8 rsvd[4]; | |
1050 | }; | |
1051 | ||
1052 | struct mlx5_destroy_psv_out { | |
1053 | struct mlx5_outbox_hdr hdr; | |
1054 | u8 rsvd[8]; | |
1055 | }; | |
1056 | ||
e281682b SM |
1057 | #define MLX5_CMD_OP_MAX 0x920 |
1058 | ||
1059 | enum { | |
1060 | VPORT_STATE_DOWN = 0x0, | |
1061 | VPORT_STATE_UP = 0x1, | |
1062 | }; | |
1063 | ||
1064 | enum { | |
1065 | MLX5_L3_PROT_TYPE_IPV4 = 0, | |
1066 | MLX5_L3_PROT_TYPE_IPV6 = 1, | |
1067 | }; | |
1068 | ||
1069 | enum { | |
1070 | MLX5_L4_PROT_TYPE_TCP = 0, | |
1071 | MLX5_L4_PROT_TYPE_UDP = 1, | |
1072 | }; | |
1073 | ||
1074 | enum { | |
1075 | MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, | |
1076 | MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, | |
1077 | MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, | |
1078 | MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, | |
1079 | MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, | |
1080 | }; | |
1081 | ||
1082 | enum { | |
1083 | MLX5_MATCH_OUTER_HEADERS = 1 << 0, | |
1084 | MLX5_MATCH_MISC_PARAMETERS = 1 << 1, | |
1085 | MLX5_MATCH_INNER_HEADERS = 1 << 2, | |
1086 | ||
1087 | }; | |
1088 | ||
1089 | enum { | |
1090 | MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, | |
1091 | MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, | |
1092 | }; | |
1093 | ||
1094 | enum { | |
1095 | MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0, | |
1096 | MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1, | |
1097 | MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2, | |
1098 | }; | |
1099 | ||
1100 | enum { | |
1101 | MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, | |
1102 | MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1, | |
1103 | }; | |
1104 | ||
938fe83c SM |
1105 | /* MLX5 DEV CAPs */ |
1106 | ||
1107 | /* TODO: EAT.ME */ | |
1108 | enum mlx5_cap_mode { | |
1109 | HCA_CAP_OPMOD_GET_MAX = 0, | |
1110 | HCA_CAP_OPMOD_GET_CUR = 1, | |
1111 | }; | |
1112 | ||
1113 | enum mlx5_cap_type { | |
1114 | MLX5_CAP_GENERAL = 0, | |
1115 | MLX5_CAP_ETHERNET_OFFLOADS, | |
1116 | MLX5_CAP_ODP, | |
1117 | MLX5_CAP_ATOMIC, | |
1118 | MLX5_CAP_ROCE, | |
1119 | MLX5_CAP_IPOIB_OFFLOADS, | |
1120 | MLX5_CAP_EOIB_OFFLOADS, | |
1121 | MLX5_CAP_FLOW_TABLE, | |
1122 | /* NUM OF CAP Types */ | |
1123 | MLX5_CAP_NUM | |
1124 | }; | |
1125 | ||
1126 | /* GET Dev Caps macros */ | |
1127 | #define MLX5_CAP_GEN(mdev, cap) \ | |
1128 | MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap) | |
1129 | ||
1130 | #define MLX5_CAP_GEN_MAX(mdev, cap) \ | |
1131 | MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap) | |
1132 | ||
1133 | #define MLX5_CAP_ETH(mdev, cap) \ | |
1134 | MLX5_GET(per_protocol_networking_offload_caps,\ | |
1135 | mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap) | |
1136 | ||
1137 | #define MLX5_CAP_ETH_MAX(mdev, cap) \ | |
1138 | MLX5_GET(per_protocol_networking_offload_caps,\ | |
1139 | mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap) | |
1140 | ||
1141 | #define MLX5_CAP_ROCE(mdev, cap) \ | |
1142 | MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap) | |
1143 | ||
1144 | #define MLX5_CAP_ROCE_MAX(mdev, cap) \ | |
1145 | MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap) | |
1146 | ||
1147 | #define MLX5_CAP_ATOMIC(mdev, cap) \ | |
1148 | MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap) | |
1149 | ||
1150 | #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ | |
1151 | MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap) | |
1152 | ||
1153 | #define MLX5_CAP_FLOWTABLE(mdev, cap) \ | |
1154 | MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap) | |
1155 | ||
1156 | #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ | |
1157 | MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap) | |
1158 | ||
1159 | #define MLX5_CAP_ODP(mdev, cap)\ | |
1160 | MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap) | |
1161 | ||
f62b8bb8 AV |
1162 | enum { |
1163 | MLX5_CMD_STAT_OK = 0x0, | |
1164 | MLX5_CMD_STAT_INT_ERR = 0x1, | |
1165 | MLX5_CMD_STAT_BAD_OP_ERR = 0x2, | |
1166 | MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, | |
1167 | MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, | |
1168 | MLX5_CMD_STAT_BAD_RES_ERR = 0x5, | |
1169 | MLX5_CMD_STAT_RES_BUSY = 0x6, | |
1170 | MLX5_CMD_STAT_LIM_ERR = 0x8, | |
1171 | MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, | |
1172 | MLX5_CMD_STAT_IX_ERR = 0xa, | |
1173 | MLX5_CMD_STAT_NO_RES_ERR = 0xf, | |
1174 | MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, | |
1175 | MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, | |
1176 | MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, | |
1177 | MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, | |
1178 | MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, | |
1179 | }; | |
1180 | ||
707c4602 MD |
1181 | static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) |
1182 | { | |
1183 | if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) | |
1184 | return 0; | |
1185 | return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; | |
1186 | } | |
1187 | ||
e126ba97 | 1188 | #endif /* MLX5_DEVICE_H */ |