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IB/mlx5: Support IB_WR_REG_SIG_MR
[linux-2.6-block.git] / include / linux / mlx5 / device.h
CommitLineData
e126ba97
EC		 1/*
2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
38
39#if defined(__LITTLE_ENDIAN)
40#define MLX5_SET_HOST_ENDIANNESS 0
41#elif defined(__BIG_ENDIAN)
42#define MLX5_SET_HOST_ENDIANNESS 0x80
43#else
44#error Host endianness not defined
45#endif
46
47enum {
48 MLX5_MAX_COMMANDS = 32,
49 MLX5_CMD_DATA_BLOCK_SIZE = 512,
50 MLX5_PCI_CMD_XPORT = 7,
3121e3c4
SG		 51 MLX5_MKEY_BSF_OCTO_SIZE = 4,
52 MLX5_MAX_PSVS = 4,
e126ba97
EC		 53};
54
55enum {
56 MLX5_EXTENDED_UD_AV = 0x80000000,
57};
58
59enum {
60 MLX5_CQ_STATE_ARMED = 9,
61 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
62 MLX5_CQ_STATE_FIRED = 0xa,
63};
64
65enum {
66 MLX5_STAT_RATE_OFFSET = 5,
67};
68
69enum {
70 MLX5_INLINE_SEG = 0x80000000,
71};
72
73enum {
74 MLX5_PERM_LOCAL_READ = 1 << 2,
75 MLX5_PERM_LOCAL_WRITE = 1 << 3,
76 MLX5_PERM_REMOTE_READ = 1 << 4,
77 MLX5_PERM_REMOTE_WRITE = 1 << 5,
78 MLX5_PERM_ATOMIC = 1 << 6,
79 MLX5_PERM_UMR_EN = 1 << 7,
80};
81
82enum {
83 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
84 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
85 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
86 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
87 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
88};
89
90enum {
91 MLX5_ACCESS_MODE_PA = 0,
92 MLX5_ACCESS_MODE_MTT = 1,
93 MLX5_ACCESS_MODE_KLM = 2
94};
95
96enum {
97 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
98 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
99 MLX5_MKEY_BSF_EN = 1 << 30,
100 MLX5_MKEY_LEN64 = 1 << 31,
101};
102
103enum {
104 MLX5_EN_RD = (u64)1,
105 MLX5_EN_WR = (u64)2
106};
107
108enum {
c1be5232
EC		 109 MLX5_BF_REGS_PER_PAGE = 4,
110 MLX5_MAX_UAR_PAGES = 1 << 8,
111 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
112 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
e126ba97
EC		 113};
114
115enum {
116 MLX5_MKEY_MASK_LEN = 1ull << 0,
117 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
118 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
119 MLX5_MKEY_MASK_PD = 1ull << 7,
120 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
121 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
122 MLX5_MKEY_MASK_KEY = 1ull << 13,
123 MLX5_MKEY_MASK_QPN = 1ull << 14,
124 MLX5_MKEY_MASK_LR = 1ull << 17,
125 MLX5_MKEY_MASK_LW = 1ull << 18,
126 MLX5_MKEY_MASK_RR = 1ull << 19,
127 MLX5_MKEY_MASK_RW = 1ull << 20,
128 MLX5_MKEY_MASK_A = 1ull << 21,
129 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
130 MLX5_MKEY_MASK_FREE = 1ull << 29,
131};
132
133enum mlx5_event {
134 MLX5_EVENT_TYPE_COMP = 0x0,
135
136 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
137 MLX5_EVENT_TYPE_COMM_EST = 0x02,
138 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
139 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
140 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
141
142 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
143 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
144 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
145 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
146 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
147 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
148
149 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
150 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
151 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
152 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
153
154 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
155 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
156
157 MLX5_EVENT_TYPE_CMD = 0x0a,
158 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
159};
160
161enum {
162 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
163 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
164 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
165 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
166 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
167 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
168 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
169};
170
171enum {
172 MLX5_DEV_CAP_FLAG_RC = 1LL << 0,
173 MLX5_DEV_CAP_FLAG_UC = 1LL << 1,
174 MLX5_DEV_CAP_FLAG_UD = 1LL << 2,
175 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
176 MLX5_DEV_CAP_FLAG_SRQ = 1LL << 6,
177 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
178 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
179 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
180 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
181 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
3bdb31f6 182 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
bde51583 183 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
e126ba97
EC		 184 MLX5_DEV_CAP_FLAG_RESIZE_SRQ = 1LL << 32,
185 MLX5_DEV_CAP_FLAG_REMOTE_FENCE = 1LL << 38,
186 MLX5_DEV_CAP_FLAG_TLP_HINTS = 1LL << 39,
187 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
188 MLX5_DEV_CAP_FLAG_DCT = 1LL << 41,
c1868b82 189 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
e126ba97
EC		 190};
191
192enum {
193 MLX5_OPCODE_NOP = 0x00,
194 MLX5_OPCODE_SEND_INVAL = 0x01,
195 MLX5_OPCODE_RDMA_WRITE = 0x08,
196 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
197 MLX5_OPCODE_SEND = 0x0a,
198 MLX5_OPCODE_SEND_IMM = 0x0b,
199 MLX5_OPCODE_RDMA_READ = 0x10,
200 MLX5_OPCODE_ATOMIC_CS = 0x11,
201 MLX5_OPCODE_ATOMIC_FA = 0x12,
202 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
203 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
204 MLX5_OPCODE_BIND_MW = 0x18,
205 MLX5_OPCODE_CONFIG_CMD = 0x1f,
206
207 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
208 MLX5_RECV_OPCODE_SEND = 0x01,
209 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
210 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
211
212 MLX5_CQE_OPCODE_ERROR = 0x1e,
213 MLX5_CQE_OPCODE_RESIZE = 0x16,
214
215 MLX5_OPCODE_SET_PSV = 0x20,
216 MLX5_OPCODE_GET_PSV = 0x21,
217 MLX5_OPCODE_CHECK_PSV = 0x22,
218 MLX5_OPCODE_RGET_PSV = 0x26,
219 MLX5_OPCODE_RCHECK_PSV = 0x27,
220
221 MLX5_OPCODE_UMR = 0x25,
222
223};
224
225enum {
226 MLX5_SET_PORT_RESET_QKEY = 0,
227 MLX5_SET_PORT_GUID0 = 16,
228 MLX5_SET_PORT_NODE_GUID = 17,
229 MLX5_SET_PORT_SYS_GUID = 18,
230 MLX5_SET_PORT_GID_TABLE = 19,
231 MLX5_SET_PORT_PKEY_TABLE = 20,
232};
233
234enum {
235 MLX5_MAX_PAGE_SHIFT = 31
236};
237
1b77d2bd 238enum {
05bdb2ab
EC		 239 MLX5_ADAPTER_PAGE_SHIFT = 12,
240 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
1b77d2bd
EC		 241};
242
87b8de49
EC		 243enum {
244 MLX5_CAP_OFF_DCT = 41,
245 MLX5_CAP_OFF_CMDIF_CSUM = 46,
246};
247
e126ba97
EC		 248struct mlx5_inbox_hdr {
249 __be16 opcode;
250 u8 rsvd[4];
251 __be16 opmod;
252};
253
254struct mlx5_outbox_hdr {
255 u8 status;
256 u8 rsvd[3];
257 __be32 syndrome;
258};
259
260struct mlx5_cmd_query_adapter_mbox_in {
261 struct mlx5_inbox_hdr hdr;
262 u8 rsvd[8];
263};
264
265struct mlx5_cmd_query_adapter_mbox_out {
266 struct mlx5_outbox_hdr hdr;
267 u8 rsvd0[24];
268 u8 intapin;
269 u8 rsvd1[13];
270 __be16 vsd_vendor_id;
271 u8 vsd[208];
272 u8 vsd_psid[16];
273};
274
275struct mlx5_hca_cap {
276 u8 rsvd1[16];
277 u8 log_max_srq_sz;
278 u8 log_max_qp_sz;
279 u8 rsvd2;
280 u8 log_max_qp;
281 u8 log_max_strq_sz;
282 u8 log_max_srqs;
283 u8 rsvd4[2];
284 u8 rsvd5;
285 u8 log_max_cq_sz;
286 u8 rsvd6;
287 u8 log_max_cq;
288 u8 log_max_eq_sz;
289 u8 log_max_mkey;
290 u8 rsvd7;
291 u8 log_max_eq;
292 u8 max_indirection;
293 u8 log_max_mrw_sz;
294 u8 log_max_bsf_list_sz;
295 u8 log_max_klm_list_sz;
296 u8 rsvd_8_0;
297 u8 log_max_ra_req_dc;
298 u8 rsvd_8_1;
299 u8 log_max_ra_res_dc;
300 u8 rsvd9;
301 u8 log_max_ra_req_qp;
302 u8 rsvd10;
303 u8 log_max_ra_res_qp;
304 u8 rsvd11[4];
305 __be16 max_qp_count;
306 __be16 rsvd12;
307 u8 rsvd13;
308 u8 local_ca_ack_delay;
309 u8 rsvd14;
310 u8 num_ports;
311 u8 log_max_msg;
312 u8 rsvd15[3];
313 __be16 stat_rate_support;
314 u8 rsvd16[2];
315 __be64 flags;
316 u8 rsvd17;
317 u8 uar_sz;
318 u8 rsvd18;
319 u8 log_pg_sz;
320 __be16 bf_log_bf_reg_size;
321 u8 rsvd19[4];
322 __be16 max_desc_sz_sq;
323 u8 rsvd20[2];
324 __be16 max_desc_sz_rq;
325 u8 rsvd21[2];
326 __be16 max_desc_sz_sq_dc;
0a324f31
ML		 327 __be32 max_qp_mcg;
328 u8 rsvd22[3];
e126ba97 329 u8 log_max_mcg;
0a324f31 330 u8 rsvd23;
e126ba97 331 u8 log_max_pd;
0a324f31 332 u8 rsvd24;
e126ba97 333 u8 log_max_xrcd;
0a324f31 334 u8 rsvd25[42];
288dde9f 335 __be16 log_uar_page_sz;
0a324f31 336 u8 rsvd26[28];
87b8de49 337 u8 log_max_atomic_size_qp;
0a324f31 338 u8 rsvd27[2];
87b8de49 339 u8 log_max_atomic_size_dc;
0a324f31 340 u8 rsvd28[76];
e126ba97
EC		 341};
342
343
344struct mlx5_cmd_query_hca_cap_mbox_in {
345 struct mlx5_inbox_hdr hdr;
346 u8 rsvd[8];
347};
348
349
350struct mlx5_cmd_query_hca_cap_mbox_out {
351 struct mlx5_outbox_hdr hdr;
352 u8 rsvd0[8];
353 struct mlx5_hca_cap hca_cap;
354};
355
356
357struct mlx5_cmd_set_hca_cap_mbox_in {
358 struct mlx5_inbox_hdr hdr;
359 u8 rsvd[8];
360 struct mlx5_hca_cap hca_cap;
361};
362
363
364struct mlx5_cmd_set_hca_cap_mbox_out {
365 struct mlx5_outbox_hdr hdr;
366 u8 rsvd0[8];
367};
368
369
370struct mlx5_cmd_init_hca_mbox_in {
371 struct mlx5_inbox_hdr hdr;
372 u8 rsvd0[2];
373 __be16 profile;
374 u8 rsvd1[4];
375};
376
377struct mlx5_cmd_init_hca_mbox_out {
378 struct mlx5_outbox_hdr hdr;
379 u8 rsvd[8];
380};
381
382struct mlx5_cmd_teardown_hca_mbox_in {
383 struct mlx5_inbox_hdr hdr;
384 u8 rsvd0[2];
385 __be16 profile;
386 u8 rsvd1[4];
387};
388
389struct mlx5_cmd_teardown_hca_mbox_out {
390 struct mlx5_outbox_hdr hdr;
391 u8 rsvd[8];
392};
393
394struct mlx5_cmd_layout {
395 u8 type;
396 u8 rsvd0[3];
397 __be32 inlen;
398 __be64 in_ptr;
399 __be32 in[4];
400 __be32 out[4];
401 __be64 out_ptr;
402 __be32 outlen;
403 u8 token;
404 u8 sig;
405 u8 rsvd1;
406 u8 status_own;
407};
408
409
410struct health_buffer {
411 __be32 assert_var[5];
412 __be32 rsvd0[3];
413 __be32 assert_exit_ptr;
414 __be32 assert_callra;
415 __be32 rsvd1[2];
416 __be32 fw_ver;
417 __be32 hw_id;
418 __be32 rsvd2;
419 u8 irisc_index;
420 u8 synd;
421 __be16 ext_sync;
422};
423
424struct mlx5_init_seg {
425 __be32 fw_rev;
426 __be32 cmdif_rev_fw_sub;
427 __be32 rsvd0[2];
428 __be32 cmdq_addr_h;
429 __be32 cmdq_addr_l_sz;
430 __be32 cmd_dbell;
431 __be32 rsvd1[121];
432 struct health_buffer health;
433 __be32 rsvd2[884];
434 __be32 health_counter;
2f6daec1 435 __be32 rsvd3[1019];
e126ba97
EC		 436 __be64 ieee1588_clk;
437 __be32 ieee1588_clk_type;
438 __be32 clr_intx;
439};
440
441struct mlx5_eqe_comp {
442 __be32 reserved[6];
443 __be32 cqn;
444};
445
446struct mlx5_eqe_qp_srq {
447 __be32 reserved[6];
448 __be32 qp_srq_n;
449};
450
451struct mlx5_eqe_cq_err {
452 __be32 cqn;
453 u8 reserved1[7];
454 u8 syndrome;
455};
456
457struct mlx5_eqe_dropped_packet {
458};
459
460struct mlx5_eqe_port_state {
461 u8 reserved0[8];
462 u8 port;
463};
464
465struct mlx5_eqe_gpio {
466 __be32 reserved0[2];
467 __be64 gpio_event;
468};
469
470struct mlx5_eqe_congestion {
471 u8 type;
472 u8 rsvd0;
473 u8 congestion_level;
474};
475
476struct mlx5_eqe_stall_vl {
477 u8 rsvd0[3];
478 u8 port_vl;
479};
480
481struct mlx5_eqe_cmd {
482 __be32 vector;
483 __be32 rsvd[6];
484};
485
486struct mlx5_eqe_page_req {
487 u8 rsvd0[2];
488 __be16 func_id;
0a324f31
ML		 489 __be32 num_pages;
490 __be32 rsvd1[5];
e126ba97
EC		 491};
492
493union ev_data {
494 __be32 raw[7];
495 struct mlx5_eqe_cmd cmd;
496 struct mlx5_eqe_comp comp;
497 struct mlx5_eqe_qp_srq qp_srq;
498 struct mlx5_eqe_cq_err cq_err;
499 struct mlx5_eqe_dropped_packet dp;
500 struct mlx5_eqe_port_state port;
501 struct mlx5_eqe_gpio gpio;
502 struct mlx5_eqe_congestion cong;
503 struct mlx5_eqe_stall_vl stall_vl;
504 struct mlx5_eqe_page_req req_pages;
505} __packed;
506
507struct mlx5_eqe {
508 u8 rsvd0;
509 u8 type;
510 u8 rsvd1;
511 u8 sub_type;
512 __be32 rsvd2[7];
513 union ev_data data;
514 __be16 rsvd3;
515 u8 signature;
516 u8 owner;
517} __packed;
518
519struct mlx5_cmd_prot_block {
520 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
521 u8 rsvd0[48];
522 __be64 next;
523 __be32 block_num;
524 u8 rsvd1;
525 u8 token;
526 u8 ctrl_sig;
527 u8 sig;
528};
529
530struct mlx5_err_cqe {
531 u8 rsvd0[32];
532 __be32 srqn;
533 u8 rsvd1[18];
534 u8 vendor_err_synd;
535 u8 syndrome;
536 __be32 s_wqe_opcode_qpn;
537 __be16 wqe_counter;
538 u8 signature;
539 u8 op_own;
540};
541
542struct mlx5_cqe64 {
543 u8 rsvd0[17];
544 u8 ml_path;
545 u8 rsvd20[4];
546 __be16 slid;
547 __be32 flags_rqpn;
548 u8 rsvd28[4];
549 __be32 srqn;
550 __be32 imm_inval_pkey;
551 u8 rsvd40[4];
552 __be32 byte_cnt;
553 __be64 timestamp;
554 __be32 sop_drop_qpn;
555 __be16 wqe_counter;
556 u8 signature;
557 u8 op_own;
558};
559
560struct mlx5_wqe_srq_next_seg {
561 u8 rsvd0[2];
562 __be16 next_wqe_index;
563 u8 signature;
564 u8 rsvd1[11];
565};
566
567union mlx5_ext_cqe {
568 struct ib_grh grh;
569 u8 inl[64];
570};
571
572struct mlx5_cqe128 {
573 union mlx5_ext_cqe inl_grh;
574 struct mlx5_cqe64 cqe64;
575};
576
577struct mlx5_srq_ctx {
578 u8 state_log_sz;
579 u8 rsvd0[3];
580 __be32 flags_xrcd;
581 __be32 pgoff_cqn;
582 u8 rsvd1[4];
583 u8 log_pg_sz;
584 u8 rsvd2[7];
585 __be32 pd;
586 __be16 lwm;
587 __be16 wqe_cnt;
588 u8 rsvd3[8];
589 __be64 db_record;
590};
591
592struct mlx5_create_srq_mbox_in {
593 struct mlx5_inbox_hdr hdr;
594 __be32 input_srqn;
595 u8 rsvd0[4];
596 struct mlx5_srq_ctx ctx;
597 u8 rsvd1[208];
598 __be64 pas[0];
599};
600
601struct mlx5_create_srq_mbox_out {
602 struct mlx5_outbox_hdr hdr;
603 __be32 srqn;
604 u8 rsvd[4];
605};
606
607struct mlx5_destroy_srq_mbox_in {
608 struct mlx5_inbox_hdr hdr;
609 __be32 srqn;
610 u8 rsvd[4];
611};
612
613struct mlx5_destroy_srq_mbox_out {
614 struct mlx5_outbox_hdr hdr;
615 u8 rsvd[8];
616};
617
618struct mlx5_query_srq_mbox_in {
619 struct mlx5_inbox_hdr hdr;
620 __be32 srqn;
621 u8 rsvd0[4];
622};
623
624struct mlx5_query_srq_mbox_out {
625 struct mlx5_outbox_hdr hdr;
626 u8 rsvd0[8];
627 struct mlx5_srq_ctx ctx;
628 u8 rsvd1[32];
629 __be64 pas[0];
630};
631
632struct mlx5_arm_srq_mbox_in {
633 struct mlx5_inbox_hdr hdr;
634 __be32 srqn;
635 __be16 rsvd;
636 __be16 lwm;
637};
638
639struct mlx5_arm_srq_mbox_out {
640 struct mlx5_outbox_hdr hdr;
641 u8 rsvd[8];
642};
643
644struct mlx5_cq_context {
645 u8 status;
646 u8 cqe_sz_flags;
647 u8 st;
648 u8 rsvd3;
649 u8 rsvd4[6];
650 __be16 page_offset;
651 __be32 log_sz_usr_page;
652 __be16 cq_period;
653 __be16 cq_max_count;
654 __be16 rsvd20;
655 __be16 c_eqn;
656 u8 log_pg_sz;
657 u8 rsvd25[7];
658 __be32 last_notified_index;
659 __be32 solicit_producer_index;
660 __be32 consumer_counter;
661 __be32 producer_counter;
662 u8 rsvd48[8];
663 __be64 db_record_addr;
664};
665
666struct mlx5_create_cq_mbox_in {
667 struct mlx5_inbox_hdr hdr;
668 __be32 input_cqn;
669 u8 rsvdx[4];
670 struct mlx5_cq_context ctx;
671 u8 rsvd6[192];
672 __be64 pas[0];
673};
674
675struct mlx5_create_cq_mbox_out {
676 struct mlx5_outbox_hdr hdr;
677 __be32 cqn;
678 u8 rsvd0[4];
679};
680
681struct mlx5_destroy_cq_mbox_in {
682 struct mlx5_inbox_hdr hdr;
683 __be32 cqn;
684 u8 rsvd0[4];
685};
686
687struct mlx5_destroy_cq_mbox_out {
688 struct mlx5_outbox_hdr hdr;
689 u8 rsvd0[8];
690};
691
692struct mlx5_query_cq_mbox_in {
693 struct mlx5_inbox_hdr hdr;
694 __be32 cqn;
695 u8 rsvd0[4];
696};
697
698struct mlx5_query_cq_mbox_out {
699 struct mlx5_outbox_hdr hdr;
700 u8 rsvd0[8];
701 struct mlx5_cq_context ctx;
702 u8 rsvd6[16];
703 __be64 pas[0];
704};
705
3bdb31f6
EC		 706struct mlx5_modify_cq_mbox_in {
707 struct mlx5_inbox_hdr hdr;
708 __be32 cqn;
709 __be32 field_select;
710 struct mlx5_cq_context ctx;
711 u8 rsvd[192];
712 __be64 pas[0];
713};
714
715struct mlx5_modify_cq_mbox_out {
716 struct mlx5_outbox_hdr hdr;
bde51583 717 u8 rsvd[8];
3bdb31f6
EC		 718};
719
cd23b14b
EC		 720struct mlx5_enable_hca_mbox_in {
721 struct mlx5_inbox_hdr hdr;
722 u8 rsvd[8];
723};
724
725struct mlx5_enable_hca_mbox_out {
726 struct mlx5_outbox_hdr hdr;
727 u8 rsvd[8];
728};
729
730struct mlx5_disable_hca_mbox_in {
731 struct mlx5_inbox_hdr hdr;
732 u8 rsvd[8];
733};
734
735struct mlx5_disable_hca_mbox_out {
736 struct mlx5_outbox_hdr hdr;
737 u8 rsvd[8];
738};
739
e126ba97
EC		 740struct mlx5_eq_context {
741 u8 status;
742 u8 ec_oi;
743 u8 st;
744 u8 rsvd2[7];
745 __be16 page_pffset;
746 __be32 log_sz_usr_page;
747 u8 rsvd3[7];
748 u8 intr;
749 u8 log_page_size;
750 u8 rsvd4[15];
751 __be32 consumer_counter;
752 __be32 produser_counter;
753 u8 rsvd5[16];
754};
755
756struct mlx5_create_eq_mbox_in {
757 struct mlx5_inbox_hdr hdr;
758 u8 rsvd0[3];
759 u8 input_eqn;
760 u8 rsvd1[4];
761 struct mlx5_eq_context ctx;
762 u8 rsvd2[8];
763 __be64 events_mask;
764 u8 rsvd3[176];
765 __be64 pas[0];
766};
767
768struct mlx5_create_eq_mbox_out {
769 struct mlx5_outbox_hdr hdr;
770 u8 rsvd0[3];
771 u8 eq_number;
772 u8 rsvd1[4];
773};
774
775struct mlx5_destroy_eq_mbox_in {
776 struct mlx5_inbox_hdr hdr;
777 u8 rsvd0[3];
778 u8 eqn;
779 u8 rsvd1[4];
780};
781
782struct mlx5_destroy_eq_mbox_out {
783 struct mlx5_outbox_hdr hdr;
784 u8 rsvd[8];
785};
786
787struct mlx5_map_eq_mbox_in {
788 struct mlx5_inbox_hdr hdr;
789 __be64 mask;
790 u8 mu;
791 u8 rsvd0[2];
792 u8 eqn;
793 u8 rsvd1[24];
794};
795
796struct mlx5_map_eq_mbox_out {
797 struct mlx5_outbox_hdr hdr;
798 u8 rsvd[8];
799};
800
801struct mlx5_query_eq_mbox_in {
802 struct mlx5_inbox_hdr hdr;
803 u8 rsvd0[3];
804 u8 eqn;
805 u8 rsvd1[4];
806};
807
808struct mlx5_query_eq_mbox_out {
809 struct mlx5_outbox_hdr hdr;
810 u8 rsvd[8];
811 struct mlx5_eq_context ctx;
812};
813
814struct mlx5_mkey_seg {
815 /* This is a two bit field occupying bits 31-30.
816 * bit 31 is always 0,
817 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
818 */
819 u8 status;
820 u8 pcie_control;
821 u8 flags;
822 u8 version;
823 __be32 qpn_mkey7_0;
824 u8 rsvd1[4];
825 __be32 flags_pd;
826 __be64 start_addr;
827 __be64 len;
828 __be32 bsfs_octo_size;
829 u8 rsvd2[16];
830 __be32 xlt_oct_size;
831 u8 rsvd3[3];
832 u8 log2_page_size;
833 u8 rsvd4[4];
834};
835
836struct mlx5_query_special_ctxs_mbox_in {
837 struct mlx5_inbox_hdr hdr;
838 u8 rsvd[8];
839};
840
841struct mlx5_query_special_ctxs_mbox_out {
842 struct mlx5_outbox_hdr hdr;
843 __be32 dump_fill_mkey;
844 __be32 reserved_lkey;
845};
846
847struct mlx5_create_mkey_mbox_in {
848 struct mlx5_inbox_hdr hdr;
849 __be32 input_mkey_index;
850 u8 rsvd0[4];
851 struct mlx5_mkey_seg seg;
852 u8 rsvd1[16];
853 __be32 xlat_oct_act_size;
8c8a4914
EC		 854 __be32 rsvd2;
855 u8 rsvd3[168];
e126ba97
EC		 856 __be64 pas[0];
857};
858
859struct mlx5_create_mkey_mbox_out {
860 struct mlx5_outbox_hdr hdr;
861 __be32 mkey;
862 u8 rsvd[4];
863};
864
865struct mlx5_destroy_mkey_mbox_in {
866 struct mlx5_inbox_hdr hdr;
867 __be32 mkey;
868 u8 rsvd[4];
869};
870
871struct mlx5_destroy_mkey_mbox_out {
872 struct mlx5_outbox_hdr hdr;
873 u8 rsvd[8];
874};
875
876struct mlx5_query_mkey_mbox_in {
877 struct mlx5_inbox_hdr hdr;
878 __be32 mkey;
879};
880
881struct mlx5_query_mkey_mbox_out {
882 struct mlx5_outbox_hdr hdr;
883 __be64 pas[0];
884};
885
886struct mlx5_modify_mkey_mbox_in {
887 struct mlx5_inbox_hdr hdr;
888 __be32 mkey;
889 __be64 pas[0];
890};
891
892struct mlx5_modify_mkey_mbox_out {
893 struct mlx5_outbox_hdr hdr;
3bdb31f6 894 u8 rsvd[8];
e126ba97
EC		 895};
896
897struct mlx5_dump_mkey_mbox_in {
898 struct mlx5_inbox_hdr hdr;
899};
900
901struct mlx5_dump_mkey_mbox_out {
902 struct mlx5_outbox_hdr hdr;
903 __be32 mkey;
904};
905
906struct mlx5_mad_ifc_mbox_in {
907 struct mlx5_inbox_hdr hdr;
908 __be16 remote_lid;
909 u8 rsvd0;
910 u8 port;
911 u8 rsvd1[4];
912 u8 data[256];
913};
914
915struct mlx5_mad_ifc_mbox_out {
916 struct mlx5_outbox_hdr hdr;
917 u8 rsvd[8];
918 u8 data[256];
919};
920
921struct mlx5_access_reg_mbox_in {
922 struct mlx5_inbox_hdr hdr;
923 u8 rsvd0[2];
924 __be16 register_id;
925 __be32 arg;
926 __be32 data[0];
927};
928
929struct mlx5_access_reg_mbox_out {
930 struct mlx5_outbox_hdr hdr;
931 u8 rsvd[8];
932 __be32 data[0];
933};
934
935#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
936
937enum {
938 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
939};
940
3121e3c4
SG		 941struct mlx5_allocate_psv_in {
942 struct mlx5_inbox_hdr hdr;
943 __be32 npsv_pd;
944 __be32 rsvd_psv0;
945};
946
947struct mlx5_allocate_psv_out {
948 struct mlx5_outbox_hdr hdr;
949 u8 rsvd[8];
950 __be32 psv_idx[4];
951};
952
953struct mlx5_destroy_psv_in {
954 struct mlx5_inbox_hdr hdr;
955 __be32 psv_number;
956 u8 rsvd[4];
957};
958
959struct mlx5_destroy_psv_out {
960 struct mlx5_outbox_hdr hdr;
961 u8 rsvd[8];
962};
963
e126ba97 964#endif /* MLX5_DEVICE_H */
Linux 6.x block layer and io_uring tree(s)