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net/mlx5_core: HW data structs/types definitions cleanup
[linux-2.6-block.git] / include / linux / mlx5 / device.h
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e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
e281682b 38#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 39
40#if defined(__LITTLE_ENDIAN)
41#define MLX5_SET_HOST_ENDIANNESS 0
42#elif defined(__BIG_ENDIAN)
43#define MLX5_SET_HOST_ENDIANNESS 0x80
44#else
45#error Host endianness not defined
46#endif
47
d29b796a
EC		 48/* helper macros */
49#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51#define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
52#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
53#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
54#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
58
59#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
60#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
61#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
62#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
63#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
64
65/* insert a value to a struct */
66#define MLX5_SET(typ, p, fld, v) do { \
67 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
68 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
69 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
70 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
71 << __mlx5_dw_bit_off(typ, fld))); \
72} while (0)
73
e281682b
SM		 74#define MLX5_SET_TO_ONES(typ, p, fld) do { \
75 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
76 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
77 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
78 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
79 << __mlx5_dw_bit_off(typ, fld))); \
80} while (0)
81
d29b796a
EC		 82#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
83__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
84__mlx5_mask(typ, fld))
85
86#define MLX5_GET_PR(typ, p, fld) ({ \
87 u32 ___t = MLX5_GET(typ, p, fld); \
88 pr_debug(#fld " = 0x%x\n", ___t); \
89 ___t; \
90})
91
92#define MLX5_SET64(typ, p, fld, v) do { \
93 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
94 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
95 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
96} while (0)
97
98#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
99
e126ba97
EC		 100enum {
101 MLX5_MAX_COMMANDS = 32,
102 MLX5_CMD_DATA_BLOCK_SIZE = 512,
103 MLX5_PCI_CMD_XPORT = 7,
3121e3c4
SG		 104 MLX5_MKEY_BSF_OCTO_SIZE = 4,
105 MLX5_MAX_PSVS = 4,
e126ba97
EC		 106};
107
108enum {
109 MLX5_EXTENDED_UD_AV = 0x80000000,
110};
111
112enum {
113 MLX5_CQ_STATE_ARMED = 9,
114 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
115 MLX5_CQ_STATE_FIRED = 0xa,
116};
117
118enum {
119 MLX5_STAT_RATE_OFFSET = 5,
120};
121
122enum {
123 MLX5_INLINE_SEG = 0x80000000,
124};
125
c7a08ac7
EC		 126enum {
127 MLX5_MIN_PKEY_TABLE_SIZE = 128,
128 MLX5_MAX_LOG_PKEY_TABLE = 5,
129};
130
e420f0c0
HE		 131enum {
132 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
133};
134
135enum {
136 MLX5_PFAULT_SUBTYPE_WQE = 0,
137 MLX5_PFAULT_SUBTYPE_RDMA = 1,
138};
139
e126ba97
EC		 140enum {
141 MLX5_PERM_LOCAL_READ = 1 << 2,
142 MLX5_PERM_LOCAL_WRITE = 1 << 3,
143 MLX5_PERM_REMOTE_READ = 1 << 4,
144 MLX5_PERM_REMOTE_WRITE = 1 << 5,
145 MLX5_PERM_ATOMIC = 1 << 6,
146 MLX5_PERM_UMR_EN = 1 << 7,
147};
148
149enum {
150 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
151 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
152 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
153 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
154 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
155};
156
157enum {
158 MLX5_ACCESS_MODE_PA = 0,
159 MLX5_ACCESS_MODE_MTT = 1,
160 MLX5_ACCESS_MODE_KLM = 2
161};
162
163enum {
164 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
165 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
166 MLX5_MKEY_BSF_EN = 1 << 30,
167 MLX5_MKEY_LEN64 = 1 << 31,
168};
169
170enum {
171 MLX5_EN_RD = (u64)1,
172 MLX5_EN_WR = (u64)2
173};
174
175enum {
c1be5232
EC		 176 MLX5_BF_REGS_PER_PAGE = 4,
177 MLX5_MAX_UAR_PAGES = 1 << 8,
178 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
179 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
e126ba97
EC		 180};
181
182enum {
183 MLX5_MKEY_MASK_LEN = 1ull << 0,
184 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
185 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
186 MLX5_MKEY_MASK_PD = 1ull << 7,
187 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
d5436ba0 188 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
e126ba97
EC		 189 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
190 MLX5_MKEY_MASK_KEY = 1ull << 13,
191 MLX5_MKEY_MASK_QPN = 1ull << 14,
192 MLX5_MKEY_MASK_LR = 1ull << 17,
193 MLX5_MKEY_MASK_LW = 1ull << 18,
194 MLX5_MKEY_MASK_RR = 1ull << 19,
195 MLX5_MKEY_MASK_RW = 1ull << 20,
196 MLX5_MKEY_MASK_A = 1ull << 21,
197 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
198 MLX5_MKEY_MASK_FREE = 1ull << 29,
199};
200
968e78dd
HE		 201enum {
202 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
203
204 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
205 MLX5_UMR_CHECK_FREE = (2 << 5),
206
207 MLX5_UMR_INLINE = (1 << 7),
208};
209
cc149f75
HE		 210#define MLX5_UMR_MTT_ALIGNMENT 0x40
211#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
832a6b06 212#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
cc149f75 213
e126ba97
EC		 214enum mlx5_event {
215 MLX5_EVENT_TYPE_COMP = 0x0,
216
217 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
218 MLX5_EVENT_TYPE_COMM_EST = 0x02,
219 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
220 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
221 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
222
223 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
224 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
225 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
226 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
227 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
228 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
229
230 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
231 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
232 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
233 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
234
235 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
236 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
237
238 MLX5_EVENT_TYPE_CMD = 0x0a,
239 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
e420f0c0
HE		 240
241 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
e126ba97
EC		 242};
243
244enum {
245 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
246 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
247 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
248 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
249 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
250 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
251 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
252};
253
254enum {
e126ba97 255 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
e126ba97
EC		 256 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
257 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
258 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
259 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
f360d88a 260 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
6cb7ff3d 261 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
3bdb31f6 262 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
bde51583 263 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
c7a08ac7 264 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
e126ba97 265 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
c1868b82 266 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
e126ba97
EC		 267};
268
269enum {
270 MLX5_OPCODE_NOP = 0x00,
271 MLX5_OPCODE_SEND_INVAL = 0x01,
272 MLX5_OPCODE_RDMA_WRITE = 0x08,
273 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
274 MLX5_OPCODE_SEND = 0x0a,
275 MLX5_OPCODE_SEND_IMM = 0x0b,
e281682b 276 MLX5_OPCODE_LSO = 0x0e,
e126ba97
EC		 277 MLX5_OPCODE_RDMA_READ = 0x10,
278 MLX5_OPCODE_ATOMIC_CS = 0x11,
279 MLX5_OPCODE_ATOMIC_FA = 0x12,
280 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
281 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
282 MLX5_OPCODE_BIND_MW = 0x18,
283 MLX5_OPCODE_CONFIG_CMD = 0x1f,
284
285 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
286 MLX5_RECV_OPCODE_SEND = 0x01,
287 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
288 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
289
290 MLX5_CQE_OPCODE_ERROR = 0x1e,
291 MLX5_CQE_OPCODE_RESIZE = 0x16,
292
293 MLX5_OPCODE_SET_PSV = 0x20,
294 MLX5_OPCODE_GET_PSV = 0x21,
295 MLX5_OPCODE_CHECK_PSV = 0x22,
296 MLX5_OPCODE_RGET_PSV = 0x26,
297 MLX5_OPCODE_RCHECK_PSV = 0x27,
298
299 MLX5_OPCODE_UMR = 0x25,
300
301};
302
303enum {
304 MLX5_SET_PORT_RESET_QKEY = 0,
305 MLX5_SET_PORT_GUID0 = 16,
306 MLX5_SET_PORT_NODE_GUID = 17,
307 MLX5_SET_PORT_SYS_GUID = 18,
308 MLX5_SET_PORT_GID_TABLE = 19,
309 MLX5_SET_PORT_PKEY_TABLE = 20,
310};
311
312enum {
313 MLX5_MAX_PAGE_SHIFT = 31
314};
315
1b77d2bd 316enum {
05bdb2ab
EC		 317 MLX5_ADAPTER_PAGE_SHIFT = 12,
318 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
1b77d2bd
EC		 319};
320
87b8de49 321enum {
87b8de49
EC		 322 MLX5_CAP_OFF_CMDIF_CSUM = 46,
323};
324
c7a08ac7
EC		 325enum {
326 HCA_CAP_OPMOD_GET_MAX = 0,
327 HCA_CAP_OPMOD_GET_CUR = 1,
e420f0c0
HE		 328 HCA_CAP_OPMOD_GET_ODP_MAX = 4,
329 HCA_CAP_OPMOD_GET_ODP_CUR = 5
c7a08ac7
EC		 330};
331
e126ba97
EC		 332struct mlx5_inbox_hdr {
333 __be16 opcode;
334 u8 rsvd[4];
335 __be16 opmod;
336};
337
338struct mlx5_outbox_hdr {
339 u8 status;
340 u8 rsvd[3];
341 __be32 syndrome;
342};
343
344struct mlx5_cmd_query_adapter_mbox_in {
345 struct mlx5_inbox_hdr hdr;
346 u8 rsvd[8];
347};
348
349struct mlx5_cmd_query_adapter_mbox_out {
350 struct mlx5_outbox_hdr hdr;
351 u8 rsvd0[24];
352 u8 intapin;
353 u8 rsvd1[13];
354 __be16 vsd_vendor_id;
355 u8 vsd[208];
356 u8 vsd_psid[16];
357};
358
e420f0c0
HE		 359enum mlx5_odp_transport_cap_bits {
360 MLX5_ODP_SUPPORT_SEND = 1 << 31,
361 MLX5_ODP_SUPPORT_RECV = 1 << 30,
362 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
363 MLX5_ODP_SUPPORT_READ = 1 << 28,
364};
365
366struct mlx5_odp_caps {
367 char reserved[0x10];
368 struct {
369 __be32 rc_odp_caps;
370 __be32 uc_odp_caps;
371 __be32 ud_odp_caps;
372 } per_transport_caps;
373 char reserved2[0xe4];
374};
375
e126ba97
EC		 376struct mlx5_cmd_init_hca_mbox_in {
377 struct mlx5_inbox_hdr hdr;
378 u8 rsvd0[2];
379 __be16 profile;
380 u8 rsvd1[4];
381};
382
383struct mlx5_cmd_init_hca_mbox_out {
384 struct mlx5_outbox_hdr hdr;
385 u8 rsvd[8];
386};
387
388struct mlx5_cmd_teardown_hca_mbox_in {
389 struct mlx5_inbox_hdr hdr;
390 u8 rsvd0[2];
391 __be16 profile;
392 u8 rsvd1[4];
393};
394
395struct mlx5_cmd_teardown_hca_mbox_out {
396 struct mlx5_outbox_hdr hdr;
397 u8 rsvd[8];
398};
399
400struct mlx5_cmd_layout {
401 u8 type;
402 u8 rsvd0[3];
403 __be32 inlen;
404 __be64 in_ptr;
405 __be32 in[4];
406 __be32 out[4];
407 __be64 out_ptr;
408 __be32 outlen;
409 u8 token;
410 u8 sig;
411 u8 rsvd1;
412 u8 status_own;
413};
414
415
416struct health_buffer {
417 __be32 assert_var[5];
418 __be32 rsvd0[3];
419 __be32 assert_exit_ptr;
420 __be32 assert_callra;
421 __be32 rsvd1[2];
422 __be32 fw_ver;
423 __be32 hw_id;
424 __be32 rsvd2;
425 u8 irisc_index;
426 u8 synd;
427 __be16 ext_sync;
428};
429
430struct mlx5_init_seg {
431 __be32 fw_rev;
432 __be32 cmdif_rev_fw_sub;
433 __be32 rsvd0[2];
434 __be32 cmdq_addr_h;
435 __be32 cmdq_addr_l_sz;
436 __be32 cmd_dbell;
437 __be32 rsvd1[121];
438 struct health_buffer health;
439 __be32 rsvd2[884];
440 __be32 health_counter;
2f6daec1 441 __be32 rsvd3[1019];
e126ba97
EC		 442 __be64 ieee1588_clk;
443 __be32 ieee1588_clk_type;
444 __be32 clr_intx;
445};
446
447struct mlx5_eqe_comp {
448 __be32 reserved[6];
449 __be32 cqn;
450};
451
452struct mlx5_eqe_qp_srq {
453 __be32 reserved[6];
454 __be32 qp_srq_n;
455};
456
457struct mlx5_eqe_cq_err {
458 __be32 cqn;
459 u8 reserved1[7];
460 u8 syndrome;
461};
462
e126ba97
EC		 463struct mlx5_eqe_port_state {
464 u8 reserved0[8];
465 u8 port;
466};
467
468struct mlx5_eqe_gpio {
469 __be32 reserved0[2];
470 __be64 gpio_event;
471};
472
473struct mlx5_eqe_congestion {
474 u8 type;
475 u8 rsvd0;
476 u8 congestion_level;
477};
478
479struct mlx5_eqe_stall_vl {
480 u8 rsvd0[3];
481 u8 port_vl;
482};
483
484struct mlx5_eqe_cmd {
485 __be32 vector;
486 __be32 rsvd[6];
487};
488
489struct mlx5_eqe_page_req {
490 u8 rsvd0[2];
491 __be16 func_id;
0a324f31
ML		 492 __be32 num_pages;
493 __be32 rsvd1[5];
e126ba97
EC		 494};
495
e420f0c0
HE		 496struct mlx5_eqe_page_fault {
497 __be32 bytes_committed;
498 union {
499 struct {
500 u16 reserved1;
501 __be16 wqe_index;
502 u16 reserved2;
503 __be16 packet_length;
504 u8 reserved3[12];
505 } __packed wqe;
506 struct {
507 __be32 r_key;
508 u16 reserved1;
509 __be16 packet_length;
510 __be32 rdma_op_len;
511 __be64 rdma_va;
512 } __packed rdma;
513 } __packed;
514 __be32 flags_qpn;
515} __packed;
516
e126ba97
EC		 517union ev_data {
518 __be32 raw[7];
519 struct mlx5_eqe_cmd cmd;
520 struct mlx5_eqe_comp comp;
521 struct mlx5_eqe_qp_srq qp_srq;
522 struct mlx5_eqe_cq_err cq_err;
e126ba97
EC		 523 struct mlx5_eqe_port_state port;
524 struct mlx5_eqe_gpio gpio;
525 struct mlx5_eqe_congestion cong;
526 struct mlx5_eqe_stall_vl stall_vl;
527 struct mlx5_eqe_page_req req_pages;
e420f0c0 528 struct mlx5_eqe_page_fault page_fault;
e126ba97
EC		 529} __packed;
530
531struct mlx5_eqe {
532 u8 rsvd0;
533 u8 type;
534 u8 rsvd1;
535 u8 sub_type;
536 __be32 rsvd2[7];
537 union ev_data data;
538 __be16 rsvd3;
539 u8 signature;
540 u8 owner;
541} __packed;
542
543struct mlx5_cmd_prot_block {
544 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
545 u8 rsvd0[48];
546 __be64 next;
547 __be32 block_num;
548 u8 rsvd1;
549 u8 token;
550 u8 ctrl_sig;
551 u8 sig;
552};
553
e281682b
SM		 554enum {
555 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
556};
557
e126ba97
EC		 558struct mlx5_err_cqe {
559 u8 rsvd0[32];
560 __be32 srqn;
561 u8 rsvd1[18];
562 u8 vendor_err_synd;
563 u8 syndrome;
564 __be32 s_wqe_opcode_qpn;
565 __be16 wqe_counter;
566 u8 signature;
567 u8 op_own;
568};
569
570struct mlx5_cqe64 {
e281682b
SM		 571 u8 rsvd0[4];
572 u8 lro_tcppsh_abort_dupack;
573 u8 lro_min_ttl;
574 __be16 lro_tcp_win;
575 __be32 lro_ack_seq_num;
576 __be32 rss_hash_result;
577 u8 rss_hash_type;
e126ba97 578 u8 ml_path;
e281682b
SM		 579 u8 rsvd20[2];
580 __be16 check_sum;
e126ba97
EC		 581 __be16 slid;
582 __be32 flags_rqpn;
e281682b
SM		 583 u8 hds_ip_ext;
584 u8 l4_hdr_type_etc;
585 __be16 vlan_info;
586 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
e126ba97
EC		 587 __be32 imm_inval_pkey;
588 u8 rsvd40[4];
589 __be32 byte_cnt;
590 __be64 timestamp;
591 __be32 sop_drop_qpn;
592 __be16 wqe_counter;
593 u8 signature;
594 u8 op_own;
595};
596
e281682b
SM		 597static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
598{
599 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
600}
601
602static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
603{
604 return (cqe->l4_hdr_type_etc >> 4) & 0x7;
605}
606
607static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
608{
609 return !!(cqe->l4_hdr_type_etc & 0x1);
610}
611
612enum {
613 CQE_L4_HDR_TYPE_NONE = 0x0,
614 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
615 CQE_L4_HDR_TYPE_UDP = 0x2,
616 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
617 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
618};
619
620enum {
621 CQE_RSS_HTYPE_IP = 0x3 << 6,
622 CQE_RSS_HTYPE_L4 = 0x3 << 2,
623};
624
625enum {
626 CQE_L2_OK = 1 << 0,
627 CQE_L3_OK = 1 << 1,
628 CQE_L4_OK = 1 << 2,
629};
630
d5436ba0
SG		 631struct mlx5_sig_err_cqe {
632 u8 rsvd0[16];
633 __be32 expected_trans_sig;
634 __be32 actual_trans_sig;
635 __be32 expected_reftag;
636 __be32 actual_reftag;
637 __be16 syndrome;
638 u8 rsvd22[2];
639 __be32 mkey;
640 __be64 err_offset;
641 u8 rsvd30[8];
642 __be32 qpn;
643 u8 rsvd38[2];
644 u8 signature;
645 u8 op_own;
646};
647
e126ba97
EC		 648struct mlx5_wqe_srq_next_seg {
649 u8 rsvd0[2];
650 __be16 next_wqe_index;
651 u8 signature;
652 u8 rsvd1[11];
653};
654
655union mlx5_ext_cqe {
656 struct ib_grh grh;
657 u8 inl[64];
658};
659
660struct mlx5_cqe128 {
661 union mlx5_ext_cqe inl_grh;
662 struct mlx5_cqe64 cqe64;
663};
664
665struct mlx5_srq_ctx {
666 u8 state_log_sz;
667 u8 rsvd0[3];
668 __be32 flags_xrcd;
669 __be32 pgoff_cqn;
670 u8 rsvd1[4];
671 u8 log_pg_sz;
672 u8 rsvd2[7];
673 __be32 pd;
674 __be16 lwm;
675 __be16 wqe_cnt;
676 u8 rsvd3[8];
677 __be64 db_record;
678};
679
680struct mlx5_create_srq_mbox_in {
681 struct mlx5_inbox_hdr hdr;
682 __be32 input_srqn;
683 u8 rsvd0[4];
684 struct mlx5_srq_ctx ctx;
685 u8 rsvd1[208];
686 __be64 pas[0];
687};
688
689struct mlx5_create_srq_mbox_out {
690 struct mlx5_outbox_hdr hdr;
691 __be32 srqn;
692 u8 rsvd[4];
693};
694
695struct mlx5_destroy_srq_mbox_in {
696 struct mlx5_inbox_hdr hdr;
697 __be32 srqn;
698 u8 rsvd[4];
699};
700
701struct mlx5_destroy_srq_mbox_out {
702 struct mlx5_outbox_hdr hdr;
703 u8 rsvd[8];
704};
705
706struct mlx5_query_srq_mbox_in {
707 struct mlx5_inbox_hdr hdr;
708 __be32 srqn;
709 u8 rsvd0[4];
710};
711
712struct mlx5_query_srq_mbox_out {
713 struct mlx5_outbox_hdr hdr;
714 u8 rsvd0[8];
715 struct mlx5_srq_ctx ctx;
716 u8 rsvd1[32];
717 __be64 pas[0];
718};
719
720struct mlx5_arm_srq_mbox_in {
721 struct mlx5_inbox_hdr hdr;
722 __be32 srqn;
723 __be16 rsvd;
724 __be16 lwm;
725};
726
727struct mlx5_arm_srq_mbox_out {
728 struct mlx5_outbox_hdr hdr;
729 u8 rsvd[8];
730};
731
732struct mlx5_cq_context {
733 u8 status;
734 u8 cqe_sz_flags;
735 u8 st;
736 u8 rsvd3;
737 u8 rsvd4[6];
738 __be16 page_offset;
739 __be32 log_sz_usr_page;
740 __be16 cq_period;
741 __be16 cq_max_count;
742 __be16 rsvd20;
743 __be16 c_eqn;
744 u8 log_pg_sz;
745 u8 rsvd25[7];
746 __be32 last_notified_index;
747 __be32 solicit_producer_index;
748 __be32 consumer_counter;
749 __be32 producer_counter;
750 u8 rsvd48[8];
751 __be64 db_record_addr;
752};
753
754struct mlx5_create_cq_mbox_in {
755 struct mlx5_inbox_hdr hdr;
756 __be32 input_cqn;
757 u8 rsvdx[4];
758 struct mlx5_cq_context ctx;
759 u8 rsvd6[192];
760 __be64 pas[0];
761};
762
763struct mlx5_create_cq_mbox_out {
764 struct mlx5_outbox_hdr hdr;
765 __be32 cqn;
766 u8 rsvd0[4];
767};
768
769struct mlx5_destroy_cq_mbox_in {
770 struct mlx5_inbox_hdr hdr;
771 __be32 cqn;
772 u8 rsvd0[4];
773};
774
775struct mlx5_destroy_cq_mbox_out {
776 struct mlx5_outbox_hdr hdr;
777 u8 rsvd0[8];
778};
779
780struct mlx5_query_cq_mbox_in {
781 struct mlx5_inbox_hdr hdr;
782 __be32 cqn;
783 u8 rsvd0[4];
784};
785
786struct mlx5_query_cq_mbox_out {
787 struct mlx5_outbox_hdr hdr;
788 u8 rsvd0[8];
789 struct mlx5_cq_context ctx;
790 u8 rsvd6[16];
791 __be64 pas[0];
792};
793
3bdb31f6
EC		 794struct mlx5_modify_cq_mbox_in {
795 struct mlx5_inbox_hdr hdr;
796 __be32 cqn;
797 __be32 field_select;
798 struct mlx5_cq_context ctx;
799 u8 rsvd[192];
800 __be64 pas[0];
801};
802
803struct mlx5_modify_cq_mbox_out {
804 struct mlx5_outbox_hdr hdr;
bde51583 805 u8 rsvd[8];
3bdb31f6
EC		 806};
807
cd23b14b
EC		 808struct mlx5_enable_hca_mbox_in {
809 struct mlx5_inbox_hdr hdr;
810 u8 rsvd[8];
811};
812
813struct mlx5_enable_hca_mbox_out {
814 struct mlx5_outbox_hdr hdr;
815 u8 rsvd[8];
816};
817
818struct mlx5_disable_hca_mbox_in {
819 struct mlx5_inbox_hdr hdr;
820 u8 rsvd[8];
821};
822
823struct mlx5_disable_hca_mbox_out {
824 struct mlx5_outbox_hdr hdr;
825 u8 rsvd[8];
826};
827
e126ba97
EC		 828struct mlx5_eq_context {
829 u8 status;
830 u8 ec_oi;
831 u8 st;
832 u8 rsvd2[7];
833 __be16 page_pffset;
834 __be32 log_sz_usr_page;
835 u8 rsvd3[7];
836 u8 intr;
837 u8 log_page_size;
838 u8 rsvd4[15];
839 __be32 consumer_counter;
840 __be32 produser_counter;
841 u8 rsvd5[16];
842};
843
844struct mlx5_create_eq_mbox_in {
845 struct mlx5_inbox_hdr hdr;
846 u8 rsvd0[3];
847 u8 input_eqn;
848 u8 rsvd1[4];
849 struct mlx5_eq_context ctx;
850 u8 rsvd2[8];
851 __be64 events_mask;
852 u8 rsvd3[176];
853 __be64 pas[0];
854};
855
856struct mlx5_create_eq_mbox_out {
857 struct mlx5_outbox_hdr hdr;
858 u8 rsvd0[3];
859 u8 eq_number;
860 u8 rsvd1[4];
861};
862
863struct mlx5_destroy_eq_mbox_in {
864 struct mlx5_inbox_hdr hdr;
865 u8 rsvd0[3];
866 u8 eqn;
867 u8 rsvd1[4];
868};
869
870struct mlx5_destroy_eq_mbox_out {
871 struct mlx5_outbox_hdr hdr;
872 u8 rsvd[8];
873};
874
875struct mlx5_map_eq_mbox_in {
876 struct mlx5_inbox_hdr hdr;
877 __be64 mask;
878 u8 mu;
879 u8 rsvd0[2];
880 u8 eqn;
881 u8 rsvd1[24];
882};
883
884struct mlx5_map_eq_mbox_out {
885 struct mlx5_outbox_hdr hdr;
886 u8 rsvd[8];
887};
888
889struct mlx5_query_eq_mbox_in {
890 struct mlx5_inbox_hdr hdr;
891 u8 rsvd0[3];
892 u8 eqn;
893 u8 rsvd1[4];
894};
895
896struct mlx5_query_eq_mbox_out {
897 struct mlx5_outbox_hdr hdr;
898 u8 rsvd[8];
899 struct mlx5_eq_context ctx;
900};
901
968e78dd
HE		 902enum {
903 MLX5_MKEY_STATUS_FREE = 1 << 6,
904};
905
e126ba97
EC		 906struct mlx5_mkey_seg {
907 /* This is a two bit field occupying bits 31-30.
908 * bit 31 is always 0,
909 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
910 */
911 u8 status;
912 u8 pcie_control;
913 u8 flags;
914 u8 version;
915 __be32 qpn_mkey7_0;
916 u8 rsvd1[4];
917 __be32 flags_pd;
918 __be64 start_addr;
919 __be64 len;
920 __be32 bsfs_octo_size;
921 u8 rsvd2[16];
922 __be32 xlt_oct_size;
923 u8 rsvd3[3];
924 u8 log2_page_size;
925 u8 rsvd4[4];
926};
927
928struct mlx5_query_special_ctxs_mbox_in {
929 struct mlx5_inbox_hdr hdr;
930 u8 rsvd[8];
931};
932
933struct mlx5_query_special_ctxs_mbox_out {
934 struct mlx5_outbox_hdr hdr;
935 __be32 dump_fill_mkey;
936 __be32 reserved_lkey;
937};
938
939struct mlx5_create_mkey_mbox_in {
940 struct mlx5_inbox_hdr hdr;
941 __be32 input_mkey_index;
e420f0c0 942 __be32 flags;
e126ba97
EC		 943 struct mlx5_mkey_seg seg;
944 u8 rsvd1[16];
945 __be32 xlat_oct_act_size;
8c8a4914
EC		 946 __be32 rsvd2;
947 u8 rsvd3[168];
e126ba97
EC		 948 __be64 pas[0];
949};
950
951struct mlx5_create_mkey_mbox_out {
952 struct mlx5_outbox_hdr hdr;
953 __be32 mkey;
954 u8 rsvd[4];
955};
956
957struct mlx5_destroy_mkey_mbox_in {
958 struct mlx5_inbox_hdr hdr;
959 __be32 mkey;
960 u8 rsvd[4];
961};
962
963struct mlx5_destroy_mkey_mbox_out {
964 struct mlx5_outbox_hdr hdr;
965 u8 rsvd[8];
966};
967
968struct mlx5_query_mkey_mbox_in {
969 struct mlx5_inbox_hdr hdr;
970 __be32 mkey;
971};
972
973struct mlx5_query_mkey_mbox_out {
974 struct mlx5_outbox_hdr hdr;
975 __be64 pas[0];
976};
977
978struct mlx5_modify_mkey_mbox_in {
979 struct mlx5_inbox_hdr hdr;
980 __be32 mkey;
981 __be64 pas[0];
982};
983
984struct mlx5_modify_mkey_mbox_out {
985 struct mlx5_outbox_hdr hdr;
3bdb31f6 986 u8 rsvd[8];
e126ba97
EC		 987};
988
989struct mlx5_dump_mkey_mbox_in {
990 struct mlx5_inbox_hdr hdr;
991};
992
993struct mlx5_dump_mkey_mbox_out {
994 struct mlx5_outbox_hdr hdr;
995 __be32 mkey;
996};
997
998struct mlx5_mad_ifc_mbox_in {
999 struct mlx5_inbox_hdr hdr;
1000 __be16 remote_lid;
1001 u8 rsvd0;
1002 u8 port;
1003 u8 rsvd1[4];
1004 u8 data[256];
1005};
1006
1007struct mlx5_mad_ifc_mbox_out {
1008 struct mlx5_outbox_hdr hdr;
1009 u8 rsvd[8];
1010 u8 data[256];
1011};
1012
1013struct mlx5_access_reg_mbox_in {
1014 struct mlx5_inbox_hdr hdr;
1015 u8 rsvd0[2];
1016 __be16 register_id;
1017 __be32 arg;
1018 __be32 data[0];
1019};
1020
1021struct mlx5_access_reg_mbox_out {
1022 struct mlx5_outbox_hdr hdr;
1023 u8 rsvd[8];
1024 __be32 data[0];
1025};
1026
1027#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
1028
1029enum {
1030 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
1031};
1032
3121e3c4
SG		 1033struct mlx5_allocate_psv_in {
1034 struct mlx5_inbox_hdr hdr;
1035 __be32 npsv_pd;
1036 __be32 rsvd_psv0;
1037};
1038
1039struct mlx5_allocate_psv_out {
1040 struct mlx5_outbox_hdr hdr;
1041 u8 rsvd[8];
1042 __be32 psv_idx[4];
1043};
1044
1045struct mlx5_destroy_psv_in {
1046 struct mlx5_inbox_hdr hdr;
1047 __be32 psv_number;
1048 u8 rsvd[4];
1049};
1050
1051struct mlx5_destroy_psv_out {
1052 struct mlx5_outbox_hdr hdr;
1053 u8 rsvd[8];
1054};
1055
e281682b
SM		 1056#define MLX5_CMD_OP_MAX 0x920
1057
1058enum {
1059 VPORT_STATE_DOWN = 0x0,
1060 VPORT_STATE_UP = 0x1,
1061};
1062
1063enum {
1064 MLX5_L3_PROT_TYPE_IPV4 = 0,
1065 MLX5_L3_PROT_TYPE_IPV6 = 1,
1066};
1067
1068enum {
1069 MLX5_L4_PROT_TYPE_TCP = 0,
1070 MLX5_L4_PROT_TYPE_UDP = 1,
1071};
1072
1073enum {
1074 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
1075 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
1076 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
1077 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
1078 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
1079};
1080
1081enum {
1082 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
1083 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
1084 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1085
1086};
1087
1088enum {
1089 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
1090 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
1091};
1092
1093enum {
1094 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
1095 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
1096 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
1097};
1098
1099enum {
1100 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1101 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
1102};
1103
e126ba97 1104#endif /* MLX5_DEVICE_H */
Linux 6.x block layer and io_uring tree(s)