projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net/mlx5_core: New init and exit flow for mlx5_core
[linux-2.6-block.git] / include / linux / mlx5 / device.h
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
e281682b 38#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 39
40#if defined(__LITTLE_ENDIAN)
41#define MLX5_SET_HOST_ENDIANNESS 0
42#elif defined(__BIG_ENDIAN)
43#define MLX5_SET_HOST_ENDIANNESS 0x80
44#else
45#error Host endianness not defined
46#endif
47
d29b796a
EC		 48/* helper macros */
49#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51#define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
52#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
53#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
54#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
58
59#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
60#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
61#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
938fe83c
SM		 62#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
63#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
d29b796a
EC		 64#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
65#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
66
67/* insert a value to a struct */
68#define MLX5_SET(typ, p, fld, v) do { \
69 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
70 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
71 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
72 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
73 << __mlx5_dw_bit_off(typ, fld))); \
74} while (0)
75
e281682b
SM		 76#define MLX5_SET_TO_ONES(typ, p, fld) do { \
77 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
78 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
79 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
80 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
81 << __mlx5_dw_bit_off(typ, fld))); \
82} while (0)
83
d29b796a
EC		 84#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
85__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
86__mlx5_mask(typ, fld))
87
88#define MLX5_GET_PR(typ, p, fld) ({ \
89 u32 ___t = MLX5_GET(typ, p, fld); \
90 pr_debug(#fld " = 0x%x\n", ___t); \
91 ___t; \
92})
93
94#define MLX5_SET64(typ, p, fld, v) do { \
95 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
96 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
97 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
98} while (0)
99
100#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
101
707c4602
MD		 102#define MLX5_GET64_PR(typ, p, fld) ({ \
103 u64 ___t = MLX5_GET64(typ, p, fld); \
104 pr_debug(#fld " = 0x%llx\n", ___t); \
105 ___t; \
106})
107
e126ba97
EC		 108enum {
109 MLX5_MAX_COMMANDS = 32,
110 MLX5_CMD_DATA_BLOCK_SIZE = 512,
111 MLX5_PCI_CMD_XPORT = 7,
3121e3c4
SG		 112 MLX5_MKEY_BSF_OCTO_SIZE = 4,
113 MLX5_MAX_PSVS = 4,
e126ba97
EC		 114};
115
116enum {
117 MLX5_EXTENDED_UD_AV = 0x80000000,
118};
119
120enum {
121 MLX5_CQ_STATE_ARMED = 9,
122 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
123 MLX5_CQ_STATE_FIRED = 0xa,
124};
125
126enum {
127 MLX5_STAT_RATE_OFFSET = 5,
128};
129
130enum {
131 MLX5_INLINE_SEG = 0x80000000,
132};
133
fc11fbf9
SM		 134enum {
135 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
136};
137
c7a08ac7
EC		 138enum {
139 MLX5_MIN_PKEY_TABLE_SIZE = 128,
140 MLX5_MAX_LOG_PKEY_TABLE = 5,
141};
142
e420f0c0
HE		 143enum {
144 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
145};
146
147enum {
148 MLX5_PFAULT_SUBTYPE_WQE = 0,
149 MLX5_PFAULT_SUBTYPE_RDMA = 1,
150};
151
e126ba97
EC		 152enum {
153 MLX5_PERM_LOCAL_READ = 1 << 2,
154 MLX5_PERM_LOCAL_WRITE = 1 << 3,
155 MLX5_PERM_REMOTE_READ = 1 << 4,
156 MLX5_PERM_REMOTE_WRITE = 1 << 5,
157 MLX5_PERM_ATOMIC = 1 << 6,
158 MLX5_PERM_UMR_EN = 1 << 7,
159};
160
161enum {
162 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
163 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
164 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
165 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
166 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
167};
168
169enum {
170 MLX5_ACCESS_MODE_PA = 0,
171 MLX5_ACCESS_MODE_MTT = 1,
172 MLX5_ACCESS_MODE_KLM = 2
173};
174
175enum {
176 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
177 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
178 MLX5_MKEY_BSF_EN = 1 << 30,
179 MLX5_MKEY_LEN64 = 1 << 31,
180};
181
182enum {
183 MLX5_EN_RD = (u64)1,
184 MLX5_EN_WR = (u64)2
185};
186
187enum {
c1be5232
EC		 188 MLX5_BF_REGS_PER_PAGE = 4,
189 MLX5_MAX_UAR_PAGES = 1 << 8,
190 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
191 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
e126ba97
EC		 192};
193
194enum {
195 MLX5_MKEY_MASK_LEN = 1ull << 0,
196 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
197 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
198 MLX5_MKEY_MASK_PD = 1ull << 7,
199 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
d5436ba0 200 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
e126ba97
EC		 201 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
202 MLX5_MKEY_MASK_KEY = 1ull << 13,
203 MLX5_MKEY_MASK_QPN = 1ull << 14,
204 MLX5_MKEY_MASK_LR = 1ull << 17,
205 MLX5_MKEY_MASK_LW = 1ull << 18,
206 MLX5_MKEY_MASK_RR = 1ull << 19,
207 MLX5_MKEY_MASK_RW = 1ull << 20,
208 MLX5_MKEY_MASK_A = 1ull << 21,
209 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
210 MLX5_MKEY_MASK_FREE = 1ull << 29,
211};
212
968e78dd
HE		 213enum {
214 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
215
216 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
217 MLX5_UMR_CHECK_FREE = (2 << 5),
218
219 MLX5_UMR_INLINE = (1 << 7),
220};
221
cc149f75
HE		 222#define MLX5_UMR_MTT_ALIGNMENT 0x40
223#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
832a6b06 224#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
cc149f75 225
e126ba97
EC		 226enum mlx5_event {
227 MLX5_EVENT_TYPE_COMP = 0x0,
228
229 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
230 MLX5_EVENT_TYPE_COMM_EST = 0x02,
231 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
232 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
233 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
234
235 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
236 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
237 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
238 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
239 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
240 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
241
242 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
243 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
244 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
245 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
246
247 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
248 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
249
250 MLX5_EVENT_TYPE_CMD = 0x0a,
251 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
e420f0c0
HE		 252
253 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
e126ba97
EC		 254};
255
256enum {
257 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
258 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
259 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
260 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
261 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
262 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
263 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
264};
265
266enum {
e126ba97 267 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
e126ba97
EC		 268 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
269 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
270 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
271 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
f360d88a 272 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
6cb7ff3d 273 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
3bdb31f6 274 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
bde51583 275 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
c7a08ac7 276 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
e126ba97 277 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
c1868b82 278 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
e126ba97
EC		 279};
280
281enum {
282 MLX5_OPCODE_NOP = 0x00,
283 MLX5_OPCODE_SEND_INVAL = 0x01,
284 MLX5_OPCODE_RDMA_WRITE = 0x08,
285 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
286 MLX5_OPCODE_SEND = 0x0a,
287 MLX5_OPCODE_SEND_IMM = 0x0b,
e281682b 288 MLX5_OPCODE_LSO = 0x0e,
e126ba97
EC		 289 MLX5_OPCODE_RDMA_READ = 0x10,
290 MLX5_OPCODE_ATOMIC_CS = 0x11,
291 MLX5_OPCODE_ATOMIC_FA = 0x12,
292 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
293 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
294 MLX5_OPCODE_BIND_MW = 0x18,
295 MLX5_OPCODE_CONFIG_CMD = 0x1f,
296
297 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
298 MLX5_RECV_OPCODE_SEND = 0x01,
299 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
300 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
301
302 MLX5_CQE_OPCODE_ERROR = 0x1e,
303 MLX5_CQE_OPCODE_RESIZE = 0x16,
304
305 MLX5_OPCODE_SET_PSV = 0x20,
306 MLX5_OPCODE_GET_PSV = 0x21,
307 MLX5_OPCODE_CHECK_PSV = 0x22,
308 MLX5_OPCODE_RGET_PSV = 0x26,
309 MLX5_OPCODE_RCHECK_PSV = 0x27,
310
311 MLX5_OPCODE_UMR = 0x25,
312
313};
314
315enum {
316 MLX5_SET_PORT_RESET_QKEY = 0,
317 MLX5_SET_PORT_GUID0 = 16,
318 MLX5_SET_PORT_NODE_GUID = 17,
319 MLX5_SET_PORT_SYS_GUID = 18,
320 MLX5_SET_PORT_GID_TABLE = 19,
321 MLX5_SET_PORT_PKEY_TABLE = 20,
322};
323
324enum {
325 MLX5_MAX_PAGE_SHIFT = 31
326};
327
1b77d2bd 328enum {
05bdb2ab
EC		 329 MLX5_ADAPTER_PAGE_SHIFT = 12,
330 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
1b77d2bd
EC		 331};
332
87b8de49 333enum {
87b8de49
EC		 334 MLX5_CAP_OFF_CMDIF_CSUM = 46,
335};
336
e126ba97
EC		 337struct mlx5_inbox_hdr {
338 __be16 opcode;
339 u8 rsvd[4];
340 __be16 opmod;
341};
342
343struct mlx5_outbox_hdr {
344 u8 status;
345 u8 rsvd[3];
346 __be32 syndrome;
347};
348
349struct mlx5_cmd_query_adapter_mbox_in {
350 struct mlx5_inbox_hdr hdr;
351 u8 rsvd[8];
352};
353
354struct mlx5_cmd_query_adapter_mbox_out {
355 struct mlx5_outbox_hdr hdr;
356 u8 rsvd0[24];
357 u8 intapin;
358 u8 rsvd1[13];
359 __be16 vsd_vendor_id;
360 u8 vsd[208];
361 u8 vsd_psid[16];
362};
363
e420f0c0
HE		 364enum mlx5_odp_transport_cap_bits {
365 MLX5_ODP_SUPPORT_SEND = 1 << 31,
366 MLX5_ODP_SUPPORT_RECV = 1 << 30,
367 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
368 MLX5_ODP_SUPPORT_READ = 1 << 28,
369};
370
371struct mlx5_odp_caps {
372 char reserved[0x10];
373 struct {
374 __be32 rc_odp_caps;
375 __be32 uc_odp_caps;
376 __be32 ud_odp_caps;
377 } per_transport_caps;
378 char reserved2[0xe4];
379};
380
e126ba97
EC		 381struct mlx5_cmd_init_hca_mbox_in {
382 struct mlx5_inbox_hdr hdr;
383 u8 rsvd0[2];
384 __be16 profile;
385 u8 rsvd1[4];
386};
387
388struct mlx5_cmd_init_hca_mbox_out {
389 struct mlx5_outbox_hdr hdr;
390 u8 rsvd[8];
391};
392
393struct mlx5_cmd_teardown_hca_mbox_in {
394 struct mlx5_inbox_hdr hdr;
395 u8 rsvd0[2];
396 __be16 profile;
397 u8 rsvd1[4];
398};
399
400struct mlx5_cmd_teardown_hca_mbox_out {
401 struct mlx5_outbox_hdr hdr;
402 u8 rsvd[8];
403};
404
a3c87420
SG		 405struct mlx5_cmd_query_special_contexts_mbox_in {
406 struct mlx5_inbox_hdr hdr;
407 u8 rsvd[8];
408};
409
410struct mlx5_cmd_query_special_contexts_mbox_out {
411 struct mlx5_outbox_hdr hdr;
412 __be32 dump_fill_mkey;
413 __be32 resd_lkey;
414};
415
e126ba97
EC		 416struct mlx5_cmd_layout {
417 u8 type;
418 u8 rsvd0[3];
419 __be32 inlen;
420 __be64 in_ptr;
421 __be32 in[4];
422 __be32 out[4];
423 __be64 out_ptr;
424 __be32 outlen;
425 u8 token;
426 u8 sig;
427 u8 rsvd1;
428 u8 status_own;
429};
430
431
432struct health_buffer {
433 __be32 assert_var[5];
434 __be32 rsvd0[3];
435 __be32 assert_exit_ptr;
436 __be32 assert_callra;
437 __be32 rsvd1[2];
438 __be32 fw_ver;
439 __be32 hw_id;
440 __be32 rsvd2;
441 u8 irisc_index;
442 u8 synd;
443 __be16 ext_sync;
444};
445
446struct mlx5_init_seg {
447 __be32 fw_rev;
448 __be32 cmdif_rev_fw_sub;
449 __be32 rsvd0[2];
450 __be32 cmdq_addr_h;
451 __be32 cmdq_addr_l_sz;
452 __be32 cmd_dbell;
453 __be32 rsvd1[121];
454 struct health_buffer health;
455 __be32 rsvd2[884];
456 __be32 health_counter;
2f6daec1 457 __be32 rsvd3[1019];
e126ba97
EC		 458 __be64 ieee1588_clk;
459 __be32 ieee1588_clk_type;
460 __be32 clr_intx;
461};
462
463struct mlx5_eqe_comp {
464 __be32 reserved[6];
465 __be32 cqn;
466};
467
468struct mlx5_eqe_qp_srq {
469 __be32 reserved[6];
470 __be32 qp_srq_n;
471};
472
473struct mlx5_eqe_cq_err {
474 __be32 cqn;
475 u8 reserved1[7];
476 u8 syndrome;
477};
478
e126ba97
EC		 479struct mlx5_eqe_port_state {
480 u8 reserved0[8];
481 u8 port;
482};
483
484struct mlx5_eqe_gpio {
485 __be32 reserved0[2];
486 __be64 gpio_event;
487};
488
489struct mlx5_eqe_congestion {
490 u8 type;
491 u8 rsvd0;
492 u8 congestion_level;
493};
494
495struct mlx5_eqe_stall_vl {
496 u8 rsvd0[3];
497 u8 port_vl;
498};
499
500struct mlx5_eqe_cmd {
501 __be32 vector;
502 __be32 rsvd[6];
503};
504
505struct mlx5_eqe_page_req {
506 u8 rsvd0[2];
507 __be16 func_id;
0a324f31
ML		 508 __be32 num_pages;
509 __be32 rsvd1[5];
e126ba97
EC		 510};
511
e420f0c0
HE		 512struct mlx5_eqe_page_fault {
513 __be32 bytes_committed;
514 union {
515 struct {
516 u16 reserved1;
517 __be16 wqe_index;
518 u16 reserved2;
519 __be16 packet_length;
520 u8 reserved3[12];
521 } __packed wqe;
522 struct {
523 __be32 r_key;
524 u16 reserved1;
525 __be16 packet_length;
526 __be32 rdma_op_len;
527 __be64 rdma_va;
528 } __packed rdma;
529 } __packed;
530 __be32 flags_qpn;
531} __packed;
532
e126ba97
EC		 533union ev_data {
534 __be32 raw[7];
535 struct mlx5_eqe_cmd cmd;
536 struct mlx5_eqe_comp comp;
537 struct mlx5_eqe_qp_srq qp_srq;
538 struct mlx5_eqe_cq_err cq_err;
e126ba97
EC		 539 struct mlx5_eqe_port_state port;
540 struct mlx5_eqe_gpio gpio;
541 struct mlx5_eqe_congestion cong;
542 struct mlx5_eqe_stall_vl stall_vl;
543 struct mlx5_eqe_page_req req_pages;
e420f0c0 544 struct mlx5_eqe_page_fault page_fault;
e126ba97
EC		 545} __packed;
546
547struct mlx5_eqe {
548 u8 rsvd0;
549 u8 type;
550 u8 rsvd1;
551 u8 sub_type;
552 __be32 rsvd2[7];
553 union ev_data data;
554 __be16 rsvd3;
555 u8 signature;
556 u8 owner;
557} __packed;
558
559struct mlx5_cmd_prot_block {
560 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
561 u8 rsvd0[48];
562 __be64 next;
563 __be32 block_num;
564 u8 rsvd1;
565 u8 token;
566 u8 ctrl_sig;
567 u8 sig;
568};
569
e281682b
SM		 570enum {
571 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
572};
573
e126ba97
EC		 574struct mlx5_err_cqe {
575 u8 rsvd0[32];
576 __be32 srqn;
577 u8 rsvd1[18];
578 u8 vendor_err_synd;
579 u8 syndrome;
580 __be32 s_wqe_opcode_qpn;
581 __be16 wqe_counter;
582 u8 signature;
583 u8 op_own;
584};
585
586struct mlx5_cqe64 {
e281682b
SM		 587 u8 rsvd0[4];
588 u8 lro_tcppsh_abort_dupack;
589 u8 lro_min_ttl;
590 __be16 lro_tcp_win;
591 __be32 lro_ack_seq_num;
592 __be32 rss_hash_result;
593 u8 rss_hash_type;
e126ba97 594 u8 ml_path;
e281682b
SM		 595 u8 rsvd20[2];
596 __be16 check_sum;
e126ba97
EC		 597 __be16 slid;
598 __be32 flags_rqpn;
e281682b
SM		 599 u8 hds_ip_ext;
600 u8 l4_hdr_type_etc;
601 __be16 vlan_info;
602 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
e126ba97
EC		 603 __be32 imm_inval_pkey;
604 u8 rsvd40[4];
605 __be32 byte_cnt;
606 __be64 timestamp;
607 __be32 sop_drop_qpn;
608 __be16 wqe_counter;
609 u8 signature;
610 u8 op_own;
611};
612
e281682b
SM		 613static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
614{
615 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
616}
617
618static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
619{
620 return (cqe->l4_hdr_type_etc >> 4) & 0x7;
621}
622
623static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
624{
625 return !!(cqe->l4_hdr_type_etc & 0x1);
626}
627
628enum {
629 CQE_L4_HDR_TYPE_NONE = 0x0,
630 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
631 CQE_L4_HDR_TYPE_UDP = 0x2,
632 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
633 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
634};
635
636enum {
637 CQE_RSS_HTYPE_IP = 0x3 << 6,
638 CQE_RSS_HTYPE_L4 = 0x3 << 2,
639};
640
641enum {
642 CQE_L2_OK = 1 << 0,
643 CQE_L3_OK = 1 << 1,
644 CQE_L4_OK = 1 << 2,
645};
646
d5436ba0
SG		 647struct mlx5_sig_err_cqe {
648 u8 rsvd0[16];
649 __be32 expected_trans_sig;
650 __be32 actual_trans_sig;
651 __be32 expected_reftag;
652 __be32 actual_reftag;
653 __be16 syndrome;
654 u8 rsvd22[2];
655 __be32 mkey;
656 __be64 err_offset;
657 u8 rsvd30[8];
658 __be32 qpn;
659 u8 rsvd38[2];
660 u8 signature;
661 u8 op_own;
662};
663
e126ba97
EC		 664struct mlx5_wqe_srq_next_seg {
665 u8 rsvd0[2];
666 __be16 next_wqe_index;
667 u8 signature;
668 u8 rsvd1[11];
669};
670
671union mlx5_ext_cqe {
672 struct ib_grh grh;
673 u8 inl[64];
674};
675
676struct mlx5_cqe128 {
677 union mlx5_ext_cqe inl_grh;
678 struct mlx5_cqe64 cqe64;
679};
680
681struct mlx5_srq_ctx {
682 u8 state_log_sz;
683 u8 rsvd0[3];
684 __be32 flags_xrcd;
685 __be32 pgoff_cqn;
686 u8 rsvd1[4];
687 u8 log_pg_sz;
688 u8 rsvd2[7];
689 __be32 pd;
690 __be16 lwm;
691 __be16 wqe_cnt;
692 u8 rsvd3[8];
693 __be64 db_record;
694};
695
696struct mlx5_create_srq_mbox_in {
697 struct mlx5_inbox_hdr hdr;
698 __be32 input_srqn;
699 u8 rsvd0[4];
700 struct mlx5_srq_ctx ctx;
701 u8 rsvd1[208];
702 __be64 pas[0];
703};
704
705struct mlx5_create_srq_mbox_out {
706 struct mlx5_outbox_hdr hdr;
707 __be32 srqn;
708 u8 rsvd[4];
709};
710
711struct mlx5_destroy_srq_mbox_in {
712 struct mlx5_inbox_hdr hdr;
713 __be32 srqn;
714 u8 rsvd[4];
715};
716
717struct mlx5_destroy_srq_mbox_out {
718 struct mlx5_outbox_hdr hdr;
719 u8 rsvd[8];
720};
721
722struct mlx5_query_srq_mbox_in {
723 struct mlx5_inbox_hdr hdr;
724 __be32 srqn;
725 u8 rsvd0[4];
726};
727
728struct mlx5_query_srq_mbox_out {
729 struct mlx5_outbox_hdr hdr;
730 u8 rsvd0[8];
731 struct mlx5_srq_ctx ctx;
732 u8 rsvd1[32];
733 __be64 pas[0];
734};
735
736struct mlx5_arm_srq_mbox_in {
737 struct mlx5_inbox_hdr hdr;
738 __be32 srqn;
739 __be16 rsvd;
740 __be16 lwm;
741};
742
743struct mlx5_arm_srq_mbox_out {
744 struct mlx5_outbox_hdr hdr;
745 u8 rsvd[8];
746};
747
748struct mlx5_cq_context {
749 u8 status;
750 u8 cqe_sz_flags;
751 u8 st;
752 u8 rsvd3;
753 u8 rsvd4[6];
754 __be16 page_offset;
755 __be32 log_sz_usr_page;
756 __be16 cq_period;
757 __be16 cq_max_count;
758 __be16 rsvd20;
759 __be16 c_eqn;
760 u8 log_pg_sz;
761 u8 rsvd25[7];
762 __be32 last_notified_index;
763 __be32 solicit_producer_index;
764 __be32 consumer_counter;
765 __be32 producer_counter;
766 u8 rsvd48[8];
767 __be64 db_record_addr;
768};
769
770struct mlx5_create_cq_mbox_in {
771 struct mlx5_inbox_hdr hdr;
772 __be32 input_cqn;
773 u8 rsvdx[4];
774 struct mlx5_cq_context ctx;
775 u8 rsvd6[192];
776 __be64 pas[0];
777};
778
779struct mlx5_create_cq_mbox_out {
780 struct mlx5_outbox_hdr hdr;
781 __be32 cqn;
782 u8 rsvd0[4];
783};
784
785struct mlx5_destroy_cq_mbox_in {
786 struct mlx5_inbox_hdr hdr;
787 __be32 cqn;
788 u8 rsvd0[4];
789};
790
791struct mlx5_destroy_cq_mbox_out {
792 struct mlx5_outbox_hdr hdr;
793 u8 rsvd0[8];
794};
795
796struct mlx5_query_cq_mbox_in {
797 struct mlx5_inbox_hdr hdr;
798 __be32 cqn;
799 u8 rsvd0[4];
800};
801
802struct mlx5_query_cq_mbox_out {
803 struct mlx5_outbox_hdr hdr;
804 u8 rsvd0[8];
805 struct mlx5_cq_context ctx;
806 u8 rsvd6[16];
807 __be64 pas[0];
808};
809
3bdb31f6
EC		 810struct mlx5_modify_cq_mbox_in {
811 struct mlx5_inbox_hdr hdr;
812 __be32 cqn;
813 __be32 field_select;
814 struct mlx5_cq_context ctx;
815 u8 rsvd[192];
816 __be64 pas[0];
817};
818
819struct mlx5_modify_cq_mbox_out {
820 struct mlx5_outbox_hdr hdr;
bde51583 821 u8 rsvd[8];
3bdb31f6
EC		 822};
823
cd23b14b
EC		 824struct mlx5_enable_hca_mbox_in {
825 struct mlx5_inbox_hdr hdr;
826 u8 rsvd[8];
827};
828
829struct mlx5_enable_hca_mbox_out {
830 struct mlx5_outbox_hdr hdr;
831 u8 rsvd[8];
832};
833
834struct mlx5_disable_hca_mbox_in {
835 struct mlx5_inbox_hdr hdr;
836 u8 rsvd[8];
837};
838
839struct mlx5_disable_hca_mbox_out {
840 struct mlx5_outbox_hdr hdr;
841 u8 rsvd[8];
842};
843
e126ba97
EC		 844struct mlx5_eq_context {
845 u8 status;
846 u8 ec_oi;
847 u8 st;
848 u8 rsvd2[7];
849 __be16 page_pffset;
850 __be32 log_sz_usr_page;
851 u8 rsvd3[7];
852 u8 intr;
853 u8 log_page_size;
854 u8 rsvd4[15];
855 __be32 consumer_counter;
856 __be32 produser_counter;
857 u8 rsvd5[16];
858};
859
860struct mlx5_create_eq_mbox_in {
861 struct mlx5_inbox_hdr hdr;
862 u8 rsvd0[3];
863 u8 input_eqn;
864 u8 rsvd1[4];
865 struct mlx5_eq_context ctx;
866 u8 rsvd2[8];
867 __be64 events_mask;
868 u8 rsvd3[176];
869 __be64 pas[0];
870};
871
872struct mlx5_create_eq_mbox_out {
873 struct mlx5_outbox_hdr hdr;
874 u8 rsvd0[3];
875 u8 eq_number;
876 u8 rsvd1[4];
877};
878
879struct mlx5_destroy_eq_mbox_in {
880 struct mlx5_inbox_hdr hdr;
881 u8 rsvd0[3];
882 u8 eqn;
883 u8 rsvd1[4];
884};
885
886struct mlx5_destroy_eq_mbox_out {
887 struct mlx5_outbox_hdr hdr;
888 u8 rsvd[8];
889};
890
891struct mlx5_map_eq_mbox_in {
892 struct mlx5_inbox_hdr hdr;
893 __be64 mask;
894 u8 mu;
895 u8 rsvd0[2];
896 u8 eqn;
897 u8 rsvd1[24];
898};
899
900struct mlx5_map_eq_mbox_out {
901 struct mlx5_outbox_hdr hdr;
902 u8 rsvd[8];
903};
904
905struct mlx5_query_eq_mbox_in {
906 struct mlx5_inbox_hdr hdr;
907 u8 rsvd0[3];
908 u8 eqn;
909 u8 rsvd1[4];
910};
911
912struct mlx5_query_eq_mbox_out {
913 struct mlx5_outbox_hdr hdr;
914 u8 rsvd[8];
915 struct mlx5_eq_context ctx;
916};
917
968e78dd
HE		 918enum {
919 MLX5_MKEY_STATUS_FREE = 1 << 6,
920};
921
e126ba97
EC		 922struct mlx5_mkey_seg {
923 /* This is a two bit field occupying bits 31-30.
924 * bit 31 is always 0,
925 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
926 */
927 u8 status;
928 u8 pcie_control;
929 u8 flags;
930 u8 version;
931 __be32 qpn_mkey7_0;
932 u8 rsvd1[4];
933 __be32 flags_pd;
934 __be64 start_addr;
935 __be64 len;
936 __be32 bsfs_octo_size;
937 u8 rsvd2[16];
938 __be32 xlt_oct_size;
939 u8 rsvd3[3];
940 u8 log2_page_size;
941 u8 rsvd4[4];
942};
943
944struct mlx5_query_special_ctxs_mbox_in {
945 struct mlx5_inbox_hdr hdr;
946 u8 rsvd[8];
947};
948
949struct mlx5_query_special_ctxs_mbox_out {
950 struct mlx5_outbox_hdr hdr;
951 __be32 dump_fill_mkey;
952 __be32 reserved_lkey;
953};
954
955struct mlx5_create_mkey_mbox_in {
956 struct mlx5_inbox_hdr hdr;
957 __be32 input_mkey_index;
e420f0c0 958 __be32 flags;
e126ba97
EC		 959 struct mlx5_mkey_seg seg;
960 u8 rsvd1[16];
961 __be32 xlat_oct_act_size;
8c8a4914
EC		 962 __be32 rsvd2;
963 u8 rsvd3[168];
e126ba97
EC		 964 __be64 pas[0];
965};
966
967struct mlx5_create_mkey_mbox_out {
968 struct mlx5_outbox_hdr hdr;
969 __be32 mkey;
970 u8 rsvd[4];
971};
972
973struct mlx5_destroy_mkey_mbox_in {
974 struct mlx5_inbox_hdr hdr;
975 __be32 mkey;
976 u8 rsvd[4];
977};
978
979struct mlx5_destroy_mkey_mbox_out {
980 struct mlx5_outbox_hdr hdr;
981 u8 rsvd[8];
982};
983
984struct mlx5_query_mkey_mbox_in {
985 struct mlx5_inbox_hdr hdr;
986 __be32 mkey;
987};
988
989struct mlx5_query_mkey_mbox_out {
990 struct mlx5_outbox_hdr hdr;
991 __be64 pas[0];
992};
993
994struct mlx5_modify_mkey_mbox_in {
995 struct mlx5_inbox_hdr hdr;
996 __be32 mkey;
997 __be64 pas[0];
998};
999
1000struct mlx5_modify_mkey_mbox_out {
1001 struct mlx5_outbox_hdr hdr;
3bdb31f6 1002 u8 rsvd[8];
e126ba97
EC		 1003};
1004
1005struct mlx5_dump_mkey_mbox_in {
1006 struct mlx5_inbox_hdr hdr;
1007};
1008
1009struct mlx5_dump_mkey_mbox_out {
1010 struct mlx5_outbox_hdr hdr;
1011 __be32 mkey;
1012};
1013
1014struct mlx5_mad_ifc_mbox_in {
1015 struct mlx5_inbox_hdr hdr;
1016 __be16 remote_lid;
1017 u8 rsvd0;
1018 u8 port;
1019 u8 rsvd1[4];
1020 u8 data[256];
1021};
1022
1023struct mlx5_mad_ifc_mbox_out {
1024 struct mlx5_outbox_hdr hdr;
1025 u8 rsvd[8];
1026 u8 data[256];
1027};
1028
1029struct mlx5_access_reg_mbox_in {
1030 struct mlx5_inbox_hdr hdr;
1031 u8 rsvd0[2];
1032 __be16 register_id;
1033 __be32 arg;
1034 __be32 data[0];
1035};
1036
1037struct mlx5_access_reg_mbox_out {
1038 struct mlx5_outbox_hdr hdr;
1039 u8 rsvd[8];
1040 __be32 data[0];
1041};
1042
1043#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
1044
1045enum {
1046 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
1047};
1048
3121e3c4
SG		 1049struct mlx5_allocate_psv_in {
1050 struct mlx5_inbox_hdr hdr;
1051 __be32 npsv_pd;
1052 __be32 rsvd_psv0;
1053};
1054
1055struct mlx5_allocate_psv_out {
1056 struct mlx5_outbox_hdr hdr;
1057 u8 rsvd[8];
1058 __be32 psv_idx[4];
1059};
1060
1061struct mlx5_destroy_psv_in {
1062 struct mlx5_inbox_hdr hdr;
1063 __be32 psv_number;
1064 u8 rsvd[4];
1065};
1066
1067struct mlx5_destroy_psv_out {
1068 struct mlx5_outbox_hdr hdr;
1069 u8 rsvd[8];
1070};
1071
e281682b
SM		 1072#define MLX5_CMD_OP_MAX 0x920
1073
1074enum {
1075 VPORT_STATE_DOWN = 0x0,
1076 VPORT_STATE_UP = 0x1,
1077};
1078
1079enum {
1080 MLX5_L3_PROT_TYPE_IPV4 = 0,
1081 MLX5_L3_PROT_TYPE_IPV6 = 1,
1082};
1083
1084enum {
1085 MLX5_L4_PROT_TYPE_TCP = 0,
1086 MLX5_L4_PROT_TYPE_UDP = 1,
1087};
1088
1089enum {
1090 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
1091 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
1092 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
1093 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
1094 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
1095};
1096
1097enum {
1098 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
1099 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
1100 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1101
1102};
1103
1104enum {
1105 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
1106 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
1107};
1108
1109enum {
1110 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
1111 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
1112 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
1113};
1114
1115enum {
1116 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1117 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
1118};
1119
938fe83c
SM		 1120/* MLX5 DEV CAPs */
1121
1122/* TODO: EAT.ME */
1123enum mlx5_cap_mode {
1124 HCA_CAP_OPMOD_GET_MAX = 0,
1125 HCA_CAP_OPMOD_GET_CUR = 1,
1126};
1127
1128enum mlx5_cap_type {
1129 MLX5_CAP_GENERAL = 0,
1130 MLX5_CAP_ETHERNET_OFFLOADS,
1131 MLX5_CAP_ODP,
1132 MLX5_CAP_ATOMIC,
1133 MLX5_CAP_ROCE,
1134 MLX5_CAP_IPOIB_OFFLOADS,
1135 MLX5_CAP_EOIB_OFFLOADS,
1136 MLX5_CAP_FLOW_TABLE,
1137 /* NUM OF CAP Types */
1138 MLX5_CAP_NUM
1139};
1140
1141/* GET Dev Caps macros */
1142#define MLX5_CAP_GEN(mdev, cap) \
1143 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1144
1145#define MLX5_CAP_GEN_MAX(mdev, cap) \
1146 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
1147
1148#define MLX5_CAP_ETH(mdev, cap) \
1149 MLX5_GET(per_protocol_networking_offload_caps,\
1150 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1151
1152#define MLX5_CAP_ETH_MAX(mdev, cap) \
1153 MLX5_GET(per_protocol_networking_offload_caps,\
1154 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1155
1156#define MLX5_CAP_ROCE(mdev, cap) \
1157 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1158
1159#define MLX5_CAP_ROCE_MAX(mdev, cap) \
1160 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1161
1162#define MLX5_CAP_ATOMIC(mdev, cap) \
1163 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1164
1165#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1166 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1167
1168#define MLX5_CAP_FLOWTABLE(mdev, cap) \
1169 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1170
1171#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1172 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1173
1174#define MLX5_CAP_ODP(mdev, cap)\
1175 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1176
f62b8bb8
AV		 1177enum {
1178 MLX5_CMD_STAT_OK = 0x0,
1179 MLX5_CMD_STAT_INT_ERR = 0x1,
1180 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1181 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1182 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1183 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1184 MLX5_CMD_STAT_RES_BUSY = 0x6,
1185 MLX5_CMD_STAT_LIM_ERR = 0x8,
1186 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1187 MLX5_CMD_STAT_IX_ERR = 0xa,
1188 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1189 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1190 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1191 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1192 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1193 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1194};
1195
efea389d
GP		 1196enum {
1197 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1198 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1199 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1200 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1201 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1202 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1203 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11
1204};
1205
707c4602
MD		 1206static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1207{
1208 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1209 return 0;
1210 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1211}
1212
e126ba97 1213#endif /* MLX5_DEVICE_H */
Linux 6.x block layer and io_uring tree(s)