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net/mlx5_core: Export transport objects
[linux-2.6-block.git] / include / linux / mlx5 / device.h
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e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
e281682b 38#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 39
40#if defined(__LITTLE_ENDIAN)
41#define MLX5_SET_HOST_ENDIANNESS 0
42#elif defined(__BIG_ENDIAN)
43#define MLX5_SET_HOST_ENDIANNESS 0x80
44#else
45#error Host endianness not defined
46#endif
47
d29b796a
EC		 48/* helper macros */
49#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51#define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
52#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
53#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
54#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
58
59#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
60#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
61#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
938fe83c
SM		 62#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
63#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
d29b796a
EC		 64#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
65#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
66
67/* insert a value to a struct */
68#define MLX5_SET(typ, p, fld, v) do { \
69 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
70 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
71 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
72 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
73 << __mlx5_dw_bit_off(typ, fld))); \
74} while (0)
75
e281682b
SM		 76#define MLX5_SET_TO_ONES(typ, p, fld) do { \
77 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
78 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
79 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
80 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
81 << __mlx5_dw_bit_off(typ, fld))); \
82} while (0)
83
d29b796a
EC		 84#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
85__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
86__mlx5_mask(typ, fld))
87
88#define MLX5_GET_PR(typ, p, fld) ({ \
89 u32 ___t = MLX5_GET(typ, p, fld); \
90 pr_debug(#fld " = 0x%x\n", ___t); \
91 ___t; \
92})
93
94#define MLX5_SET64(typ, p, fld, v) do { \
95 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
96 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
97 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
98} while (0)
99
100#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
101
707c4602
MD		 102#define MLX5_GET64_PR(typ, p, fld) ({ \
103 u64 ___t = MLX5_GET64(typ, p, fld); \
104 pr_debug(#fld " = 0x%llx\n", ___t); \
105 ___t; \
106})
107
e126ba97
EC		 108enum {
109 MLX5_MAX_COMMANDS = 32,
110 MLX5_CMD_DATA_BLOCK_SIZE = 512,
111 MLX5_PCI_CMD_XPORT = 7,
3121e3c4
SG		 112 MLX5_MKEY_BSF_OCTO_SIZE = 4,
113 MLX5_MAX_PSVS = 4,
e126ba97
EC		 114};
115
116enum {
117 MLX5_EXTENDED_UD_AV = 0x80000000,
118};
119
120enum {
121 MLX5_CQ_STATE_ARMED = 9,
122 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
123 MLX5_CQ_STATE_FIRED = 0xa,
124};
125
126enum {
127 MLX5_STAT_RATE_OFFSET = 5,
128};
129
130enum {
131 MLX5_INLINE_SEG = 0x80000000,
132};
133
fc11fbf9
SM		 134enum {
135 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
136};
137
c7a08ac7
EC		 138enum {
139 MLX5_MIN_PKEY_TABLE_SIZE = 128,
140 MLX5_MAX_LOG_PKEY_TABLE = 5,
141};
142
e420f0c0
HE		 143enum {
144 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
145};
146
147enum {
148 MLX5_PFAULT_SUBTYPE_WQE = 0,
149 MLX5_PFAULT_SUBTYPE_RDMA = 1,
150};
151
e126ba97
EC		 152enum {
153 MLX5_PERM_LOCAL_READ = 1 << 2,
154 MLX5_PERM_LOCAL_WRITE = 1 << 3,
155 MLX5_PERM_REMOTE_READ = 1 << 4,
156 MLX5_PERM_REMOTE_WRITE = 1 << 5,
157 MLX5_PERM_ATOMIC = 1 << 6,
158 MLX5_PERM_UMR_EN = 1 << 7,
159};
160
161enum {
162 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
163 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
164 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
165 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
166 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
167};
168
169enum {
170 MLX5_ACCESS_MODE_PA = 0,
171 MLX5_ACCESS_MODE_MTT = 1,
172 MLX5_ACCESS_MODE_KLM = 2
173};
174
175enum {
176 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
177 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
178 MLX5_MKEY_BSF_EN = 1 << 30,
179 MLX5_MKEY_LEN64 = 1 << 31,
180};
181
182enum {
183 MLX5_EN_RD = (u64)1,
184 MLX5_EN_WR = (u64)2
185};
186
187enum {
c1be5232
EC		 188 MLX5_BF_REGS_PER_PAGE = 4,
189 MLX5_MAX_UAR_PAGES = 1 << 8,
190 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
191 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
e126ba97
EC		 192};
193
194enum {
195 MLX5_MKEY_MASK_LEN = 1ull << 0,
196 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
197 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
198 MLX5_MKEY_MASK_PD = 1ull << 7,
199 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
d5436ba0 200 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
e126ba97
EC		 201 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
202 MLX5_MKEY_MASK_KEY = 1ull << 13,
203 MLX5_MKEY_MASK_QPN = 1ull << 14,
204 MLX5_MKEY_MASK_LR = 1ull << 17,
205 MLX5_MKEY_MASK_LW = 1ull << 18,
206 MLX5_MKEY_MASK_RR = 1ull << 19,
207 MLX5_MKEY_MASK_RW = 1ull << 20,
208 MLX5_MKEY_MASK_A = 1ull << 21,
209 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
210 MLX5_MKEY_MASK_FREE = 1ull << 29,
211};
212
968e78dd
HE		 213enum {
214 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
215
216 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
217 MLX5_UMR_CHECK_FREE = (2 << 5),
218
219 MLX5_UMR_INLINE = (1 << 7),
220};
221
cc149f75
HE		 222#define MLX5_UMR_MTT_ALIGNMENT 0x40
223#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
832a6b06 224#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
cc149f75 225
e126ba97
EC		 226enum mlx5_event {
227 MLX5_EVENT_TYPE_COMP = 0x0,
228
229 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
230 MLX5_EVENT_TYPE_COMM_EST = 0x02,
231 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
232 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
233 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
234
235 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
236 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
237 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
238 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
239 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
240 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
241
242 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
243 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
244 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
245 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
246
247 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
248 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
249
250 MLX5_EVENT_TYPE_CMD = 0x0a,
251 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
e420f0c0
HE		 252
253 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
e126ba97
EC		 254};
255
256enum {
257 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
258 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
259 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
260 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
261 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
262 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
263 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
264};
265
266enum {
e126ba97 267 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
e126ba97
EC		 268 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
269 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
270 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
271 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
f360d88a 272 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
6cb7ff3d 273 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
3bdb31f6 274 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
bde51583 275 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
c7a08ac7 276 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
e126ba97 277 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
c1868b82 278 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
e126ba97
EC		 279};
280
3cca2606
AS		 281enum {
282 MLX5_ROCE_VERSION_1 = 0,
283 MLX5_ROCE_VERSION_2 = 2,
284};
285
286enum {
287 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
288 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
289};
290
291enum {
292 MLX5_ROCE_L3_TYPE_IPV4 = 0,
293 MLX5_ROCE_L3_TYPE_IPV6 = 1,
294};
295
296enum {
297 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
298 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
299};
300
e126ba97
EC		 301enum {
302 MLX5_OPCODE_NOP = 0x00,
303 MLX5_OPCODE_SEND_INVAL = 0x01,
304 MLX5_OPCODE_RDMA_WRITE = 0x08,
305 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
306 MLX5_OPCODE_SEND = 0x0a,
307 MLX5_OPCODE_SEND_IMM = 0x0b,
e281682b 308 MLX5_OPCODE_LSO = 0x0e,
e126ba97
EC		 309 MLX5_OPCODE_RDMA_READ = 0x10,
310 MLX5_OPCODE_ATOMIC_CS = 0x11,
311 MLX5_OPCODE_ATOMIC_FA = 0x12,
312 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
313 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
314 MLX5_OPCODE_BIND_MW = 0x18,
315 MLX5_OPCODE_CONFIG_CMD = 0x1f,
316
317 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
318 MLX5_RECV_OPCODE_SEND = 0x01,
319 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
320 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
321
322 MLX5_CQE_OPCODE_ERROR = 0x1e,
323 MLX5_CQE_OPCODE_RESIZE = 0x16,
324
325 MLX5_OPCODE_SET_PSV = 0x20,
326 MLX5_OPCODE_GET_PSV = 0x21,
327 MLX5_OPCODE_CHECK_PSV = 0x22,
328 MLX5_OPCODE_RGET_PSV = 0x26,
329 MLX5_OPCODE_RCHECK_PSV = 0x27,
330
331 MLX5_OPCODE_UMR = 0x25,
332
333};
334
335enum {
336 MLX5_SET_PORT_RESET_QKEY = 0,
337 MLX5_SET_PORT_GUID0 = 16,
338 MLX5_SET_PORT_NODE_GUID = 17,
339 MLX5_SET_PORT_SYS_GUID = 18,
340 MLX5_SET_PORT_GID_TABLE = 19,
341 MLX5_SET_PORT_PKEY_TABLE = 20,
342};
343
344enum {
345 MLX5_MAX_PAGE_SHIFT = 31
346};
347
1b77d2bd 348enum {
05bdb2ab
EC		 349 MLX5_ADAPTER_PAGE_SHIFT = 12,
350 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
1b77d2bd
EC		 351};
352
87b8de49 353enum {
87b8de49
EC		 354 MLX5_CAP_OFF_CMDIF_CSUM = 46,
355};
356
e126ba97
EC		 357struct mlx5_inbox_hdr {
358 __be16 opcode;
359 u8 rsvd[4];
360 __be16 opmod;
361};
362
363struct mlx5_outbox_hdr {
364 u8 status;
365 u8 rsvd[3];
366 __be32 syndrome;
367};
368
369struct mlx5_cmd_query_adapter_mbox_in {
370 struct mlx5_inbox_hdr hdr;
371 u8 rsvd[8];
372};
373
374struct mlx5_cmd_query_adapter_mbox_out {
375 struct mlx5_outbox_hdr hdr;
376 u8 rsvd0[24];
377 u8 intapin;
378 u8 rsvd1[13];
379 __be16 vsd_vendor_id;
380 u8 vsd[208];
381 u8 vsd_psid[16];
382};
383
e420f0c0
HE		 384enum mlx5_odp_transport_cap_bits {
385 MLX5_ODP_SUPPORT_SEND = 1 << 31,
386 MLX5_ODP_SUPPORT_RECV = 1 << 30,
387 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
388 MLX5_ODP_SUPPORT_READ = 1 << 28,
389};
390
391struct mlx5_odp_caps {
392 char reserved[0x10];
393 struct {
394 __be32 rc_odp_caps;
395 __be32 uc_odp_caps;
396 __be32 ud_odp_caps;
397 } per_transport_caps;
398 char reserved2[0xe4];
399};
400
e126ba97
EC		 401struct mlx5_cmd_init_hca_mbox_in {
402 struct mlx5_inbox_hdr hdr;
403 u8 rsvd0[2];
404 __be16 profile;
405 u8 rsvd1[4];
406};
407
408struct mlx5_cmd_init_hca_mbox_out {
409 struct mlx5_outbox_hdr hdr;
410 u8 rsvd[8];
411};
412
413struct mlx5_cmd_teardown_hca_mbox_in {
414 struct mlx5_inbox_hdr hdr;
415 u8 rsvd0[2];
416 __be16 profile;
417 u8 rsvd1[4];
418};
419
420struct mlx5_cmd_teardown_hca_mbox_out {
421 struct mlx5_outbox_hdr hdr;
422 u8 rsvd[8];
423};
424
425struct mlx5_cmd_layout {
426 u8 type;
427 u8 rsvd0[3];
428 __be32 inlen;
429 __be64 in_ptr;
430 __be32 in[4];
431 __be32 out[4];
432 __be64 out_ptr;
433 __be32 outlen;
434 u8 token;
435 u8 sig;
436 u8 rsvd1;
437 u8 status_own;
438};
439
440
441struct health_buffer {
442 __be32 assert_var[5];
443 __be32 rsvd0[3];
444 __be32 assert_exit_ptr;
445 __be32 assert_callra;
446 __be32 rsvd1[2];
447 __be32 fw_ver;
448 __be32 hw_id;
449 __be32 rsvd2;
450 u8 irisc_index;
451 u8 synd;
78ccb258 452 __be16 ext_synd;
e126ba97
EC		 453};
454
455struct mlx5_init_seg {
456 __be32 fw_rev;
457 __be32 cmdif_rev_fw_sub;
458 __be32 rsvd0[2];
459 __be32 cmdq_addr_h;
460 __be32 cmdq_addr_l_sz;
461 __be32 cmd_dbell;
e3297246
EC		 462 __be32 rsvd1[120];
463 __be32 initializing;
e126ba97 464 struct health_buffer health;
b368d7cb
MB		 465 __be32 rsvd2[880];
466 __be32 internal_timer_h;
467 __be32 internal_timer_l;
468 __be32 rsvd3[2];
e126ba97 469 __be32 health_counter;
b368d7cb 470 __be32 rsvd4[1019];
e126ba97
EC		 471 __be64 ieee1588_clk;
472 __be32 ieee1588_clk_type;
473 __be32 clr_intx;
474};
475
476struct mlx5_eqe_comp {
477 __be32 reserved[6];
478 __be32 cqn;
479};
480
481struct mlx5_eqe_qp_srq {
482 __be32 reserved[6];
483 __be32 qp_srq_n;
484};
485
486struct mlx5_eqe_cq_err {
487 __be32 cqn;
488 u8 reserved1[7];
489 u8 syndrome;
490};
491
e126ba97
EC		 492struct mlx5_eqe_port_state {
493 u8 reserved0[8];
494 u8 port;
495};
496
497struct mlx5_eqe_gpio {
498 __be32 reserved0[2];
499 __be64 gpio_event;
500};
501
502struct mlx5_eqe_congestion {
503 u8 type;
504 u8 rsvd0;
505 u8 congestion_level;
506};
507
508struct mlx5_eqe_stall_vl {
509 u8 rsvd0[3];
510 u8 port_vl;
511};
512
513struct mlx5_eqe_cmd {
514 __be32 vector;
515 __be32 rsvd[6];
516};
517
518struct mlx5_eqe_page_req {
519 u8 rsvd0[2];
520 __be16 func_id;
0a324f31
ML		 521 __be32 num_pages;
522 __be32 rsvd1[5];
e126ba97
EC		 523};
524
e420f0c0
HE		 525struct mlx5_eqe_page_fault {
526 __be32 bytes_committed;
527 union {
528 struct {
529 u16 reserved1;
530 __be16 wqe_index;
531 u16 reserved2;
532 __be16 packet_length;
533 u8 reserved3[12];
534 } __packed wqe;
535 struct {
536 __be32 r_key;
537 u16 reserved1;
538 __be16 packet_length;
539 __be32 rdma_op_len;
540 __be64 rdma_va;
541 } __packed rdma;
542 } __packed;
543 __be32 flags_qpn;
544} __packed;
545
e126ba97
EC		 546union ev_data {
547 __be32 raw[7];
548 struct mlx5_eqe_cmd cmd;
549 struct mlx5_eqe_comp comp;
550 struct mlx5_eqe_qp_srq qp_srq;
551 struct mlx5_eqe_cq_err cq_err;
e126ba97
EC		 552 struct mlx5_eqe_port_state port;
553 struct mlx5_eqe_gpio gpio;
554 struct mlx5_eqe_congestion cong;
555 struct mlx5_eqe_stall_vl stall_vl;
556 struct mlx5_eqe_page_req req_pages;
e420f0c0 557 struct mlx5_eqe_page_fault page_fault;
e126ba97
EC		 558} __packed;
559
560struct mlx5_eqe {
561 u8 rsvd0;
562 u8 type;
563 u8 rsvd1;
564 u8 sub_type;
565 __be32 rsvd2[7];
566 union ev_data data;
567 __be16 rsvd3;
568 u8 signature;
569 u8 owner;
570} __packed;
571
572struct mlx5_cmd_prot_block {
573 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
574 u8 rsvd0[48];
575 __be64 next;
576 __be32 block_num;
577 u8 rsvd1;
578 u8 token;
579 u8 ctrl_sig;
580 u8 sig;
581};
582
e281682b
SM		 583enum {
584 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
585};
586
e126ba97
EC		 587struct mlx5_err_cqe {
588 u8 rsvd0[32];
589 __be32 srqn;
590 u8 rsvd1[18];
591 u8 vendor_err_synd;
592 u8 syndrome;
593 __be32 s_wqe_opcode_qpn;
594 __be16 wqe_counter;
595 u8 signature;
596 u8 op_own;
597};
598
599struct mlx5_cqe64 {
e281682b
SM		 600 u8 rsvd0[4];
601 u8 lro_tcppsh_abort_dupack;
602 u8 lro_min_ttl;
603 __be16 lro_tcp_win;
604 __be32 lro_ack_seq_num;
605 __be32 rss_hash_result;
606 u8 rss_hash_type;
e126ba97 607 u8 ml_path;
e281682b
SM		 608 u8 rsvd20[2];
609 __be16 check_sum;
e126ba97
EC		 610 __be16 slid;
611 __be32 flags_rqpn;
e281682b
SM		 612 u8 hds_ip_ext;
613 u8 l4_hdr_type_etc;
614 __be16 vlan_info;
615 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
e126ba97
EC		 616 __be32 imm_inval_pkey;
617 u8 rsvd40[4];
618 __be32 byte_cnt;
619 __be64 timestamp;
620 __be32 sop_drop_qpn;
621 __be16 wqe_counter;
622 u8 signature;
623 u8 op_own;
624};
625
e281682b
SM		 626static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
627{
628 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
629}
630
631static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
632{
633 return (cqe->l4_hdr_type_etc >> 4) & 0x7;
634}
635
636static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
637{
638 return !!(cqe->l4_hdr_type_etc & 0x1);
639}
640
641enum {
642 CQE_L4_HDR_TYPE_NONE = 0x0,
643 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
644 CQE_L4_HDR_TYPE_UDP = 0x2,
645 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
646 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
647};
648
649enum {
650 CQE_RSS_HTYPE_IP = 0x3 << 6,
651 CQE_RSS_HTYPE_L4 = 0x3 << 2,
652};
653
cb34be6d
AS		 654enum {
655 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
656 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
657 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
658};
659
e281682b
SM		 660enum {
661 CQE_L2_OK = 1 << 0,
662 CQE_L3_OK = 1 << 1,
663 CQE_L4_OK = 1 << 2,
664};
665
d5436ba0
SG		 666struct mlx5_sig_err_cqe {
667 u8 rsvd0[16];
668 __be32 expected_trans_sig;
669 __be32 actual_trans_sig;
670 __be32 expected_reftag;
671 __be32 actual_reftag;
672 __be16 syndrome;
673 u8 rsvd22[2];
674 __be32 mkey;
675 __be64 err_offset;
676 u8 rsvd30[8];
677 __be32 qpn;
678 u8 rsvd38[2];
679 u8 signature;
680 u8 op_own;
681};
682
e126ba97
EC		 683struct mlx5_wqe_srq_next_seg {
684 u8 rsvd0[2];
685 __be16 next_wqe_index;
686 u8 signature;
687 u8 rsvd1[11];
688};
689
690union mlx5_ext_cqe {
691 struct ib_grh grh;
692 u8 inl[64];
693};
694
695struct mlx5_cqe128 {
696 union mlx5_ext_cqe inl_grh;
697 struct mlx5_cqe64 cqe64;
698};
699
700struct mlx5_srq_ctx {
701 u8 state_log_sz;
702 u8 rsvd0[3];
703 __be32 flags_xrcd;
704 __be32 pgoff_cqn;
705 u8 rsvd1[4];
706 u8 log_pg_sz;
707 u8 rsvd2[7];
708 __be32 pd;
709 __be16 lwm;
710 __be16 wqe_cnt;
711 u8 rsvd3[8];
712 __be64 db_record;
713};
714
715struct mlx5_create_srq_mbox_in {
716 struct mlx5_inbox_hdr hdr;
717 __be32 input_srqn;
718 u8 rsvd0[4];
719 struct mlx5_srq_ctx ctx;
720 u8 rsvd1[208];
721 __be64 pas[0];
722};
723
724struct mlx5_create_srq_mbox_out {
725 struct mlx5_outbox_hdr hdr;
726 __be32 srqn;
727 u8 rsvd[4];
728};
729
730struct mlx5_destroy_srq_mbox_in {
731 struct mlx5_inbox_hdr hdr;
732 __be32 srqn;
733 u8 rsvd[4];
734};
735
736struct mlx5_destroy_srq_mbox_out {
737 struct mlx5_outbox_hdr hdr;
738 u8 rsvd[8];
739};
740
741struct mlx5_query_srq_mbox_in {
742 struct mlx5_inbox_hdr hdr;
743 __be32 srqn;
744 u8 rsvd0[4];
745};
746
747struct mlx5_query_srq_mbox_out {
748 struct mlx5_outbox_hdr hdr;
749 u8 rsvd0[8];
750 struct mlx5_srq_ctx ctx;
751 u8 rsvd1[32];
752 __be64 pas[0];
753};
754
755struct mlx5_arm_srq_mbox_in {
756 struct mlx5_inbox_hdr hdr;
757 __be32 srqn;
758 __be16 rsvd;
759 __be16 lwm;
760};
761
762struct mlx5_arm_srq_mbox_out {
763 struct mlx5_outbox_hdr hdr;
764 u8 rsvd[8];
765};
766
767struct mlx5_cq_context {
768 u8 status;
769 u8 cqe_sz_flags;
770 u8 st;
771 u8 rsvd3;
772 u8 rsvd4[6];
773 __be16 page_offset;
774 __be32 log_sz_usr_page;
775 __be16 cq_period;
776 __be16 cq_max_count;
777 __be16 rsvd20;
778 __be16 c_eqn;
779 u8 log_pg_sz;
780 u8 rsvd25[7];
781 __be32 last_notified_index;
782 __be32 solicit_producer_index;
783 __be32 consumer_counter;
784 __be32 producer_counter;
785 u8 rsvd48[8];
786 __be64 db_record_addr;
787};
788
789struct mlx5_create_cq_mbox_in {
790 struct mlx5_inbox_hdr hdr;
791 __be32 input_cqn;
792 u8 rsvdx[4];
793 struct mlx5_cq_context ctx;
794 u8 rsvd6[192];
795 __be64 pas[0];
796};
797
798struct mlx5_create_cq_mbox_out {
799 struct mlx5_outbox_hdr hdr;
800 __be32 cqn;
801 u8 rsvd0[4];
802};
803
804struct mlx5_destroy_cq_mbox_in {
805 struct mlx5_inbox_hdr hdr;
806 __be32 cqn;
807 u8 rsvd0[4];
808};
809
810struct mlx5_destroy_cq_mbox_out {
811 struct mlx5_outbox_hdr hdr;
812 u8 rsvd0[8];
813};
814
815struct mlx5_query_cq_mbox_in {
816 struct mlx5_inbox_hdr hdr;
817 __be32 cqn;
818 u8 rsvd0[4];
819};
820
821struct mlx5_query_cq_mbox_out {
822 struct mlx5_outbox_hdr hdr;
823 u8 rsvd0[8];
824 struct mlx5_cq_context ctx;
825 u8 rsvd6[16];
826 __be64 pas[0];
827};
828
3bdb31f6
EC		 829struct mlx5_modify_cq_mbox_in {
830 struct mlx5_inbox_hdr hdr;
831 __be32 cqn;
832 __be32 field_select;
833 struct mlx5_cq_context ctx;
834 u8 rsvd[192];
835 __be64 pas[0];
836};
837
838struct mlx5_modify_cq_mbox_out {
839 struct mlx5_outbox_hdr hdr;
bde51583 840 u8 rsvd[8];
3bdb31f6
EC		 841};
842
cd23b14b
EC		 843struct mlx5_enable_hca_mbox_in {
844 struct mlx5_inbox_hdr hdr;
845 u8 rsvd[8];
846};
847
848struct mlx5_enable_hca_mbox_out {
849 struct mlx5_outbox_hdr hdr;
850 u8 rsvd[8];
851};
852
853struct mlx5_disable_hca_mbox_in {
854 struct mlx5_inbox_hdr hdr;
855 u8 rsvd[8];
856};
857
858struct mlx5_disable_hca_mbox_out {
859 struct mlx5_outbox_hdr hdr;
860 u8 rsvd[8];
861};
862
e126ba97
EC		 863struct mlx5_eq_context {
864 u8 status;
865 u8 ec_oi;
866 u8 st;
867 u8 rsvd2[7];
868 __be16 page_pffset;
869 __be32 log_sz_usr_page;
870 u8 rsvd3[7];
871 u8 intr;
872 u8 log_page_size;
873 u8 rsvd4[15];
874 __be32 consumer_counter;
875 __be32 produser_counter;
876 u8 rsvd5[16];
877};
878
879struct mlx5_create_eq_mbox_in {
880 struct mlx5_inbox_hdr hdr;
881 u8 rsvd0[3];
882 u8 input_eqn;
883 u8 rsvd1[4];
884 struct mlx5_eq_context ctx;
885 u8 rsvd2[8];
886 __be64 events_mask;
887 u8 rsvd3[176];
888 __be64 pas[0];
889};
890
891struct mlx5_create_eq_mbox_out {
892 struct mlx5_outbox_hdr hdr;
893 u8 rsvd0[3];
894 u8 eq_number;
895 u8 rsvd1[4];
896};
897
898struct mlx5_destroy_eq_mbox_in {
899 struct mlx5_inbox_hdr hdr;
900 u8 rsvd0[3];
901 u8 eqn;
902 u8 rsvd1[4];
903};
904
905struct mlx5_destroy_eq_mbox_out {
906 struct mlx5_outbox_hdr hdr;
907 u8 rsvd[8];
908};
909
910struct mlx5_map_eq_mbox_in {
911 struct mlx5_inbox_hdr hdr;
912 __be64 mask;
913 u8 mu;
914 u8 rsvd0[2];
915 u8 eqn;
916 u8 rsvd1[24];
917};
918
919struct mlx5_map_eq_mbox_out {
920 struct mlx5_outbox_hdr hdr;
921 u8 rsvd[8];
922};
923
924struct mlx5_query_eq_mbox_in {
925 struct mlx5_inbox_hdr hdr;
926 u8 rsvd0[3];
927 u8 eqn;
928 u8 rsvd1[4];
929};
930
931struct mlx5_query_eq_mbox_out {
932 struct mlx5_outbox_hdr hdr;
933 u8 rsvd[8];
934 struct mlx5_eq_context ctx;
935};
936
968e78dd
HE		 937enum {
938 MLX5_MKEY_STATUS_FREE = 1 << 6,
939};
940
e126ba97
EC		 941struct mlx5_mkey_seg {
942 /* This is a two bit field occupying bits 31-30.
943 * bit 31 is always 0,
944 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
945 */
946 u8 status;
947 u8 pcie_control;
948 u8 flags;
949 u8 version;
950 __be32 qpn_mkey7_0;
951 u8 rsvd1[4];
952 __be32 flags_pd;
953 __be64 start_addr;
954 __be64 len;
955 __be32 bsfs_octo_size;
956 u8 rsvd2[16];
957 __be32 xlt_oct_size;
958 u8 rsvd3[3];
959 u8 log2_page_size;
960 u8 rsvd4[4];
961};
962
963struct mlx5_query_special_ctxs_mbox_in {
964 struct mlx5_inbox_hdr hdr;
965 u8 rsvd[8];
966};
967
968struct mlx5_query_special_ctxs_mbox_out {
969 struct mlx5_outbox_hdr hdr;
970 __be32 dump_fill_mkey;
971 __be32 reserved_lkey;
972};
973
974struct mlx5_create_mkey_mbox_in {
975 struct mlx5_inbox_hdr hdr;
976 __be32 input_mkey_index;
e420f0c0 977 __be32 flags;
e126ba97
EC		 978 struct mlx5_mkey_seg seg;
979 u8 rsvd1[16];
980 __be32 xlat_oct_act_size;
8c8a4914
EC		 981 __be32 rsvd2;
982 u8 rsvd3[168];
e126ba97
EC		 983 __be64 pas[0];
984};
985
986struct mlx5_create_mkey_mbox_out {
987 struct mlx5_outbox_hdr hdr;
988 __be32 mkey;
989 u8 rsvd[4];
990};
991
992struct mlx5_destroy_mkey_mbox_in {
993 struct mlx5_inbox_hdr hdr;
994 __be32 mkey;
995 u8 rsvd[4];
996};
997
998struct mlx5_destroy_mkey_mbox_out {
999 struct mlx5_outbox_hdr hdr;
1000 u8 rsvd[8];
1001};
1002
1003struct mlx5_query_mkey_mbox_in {
1004 struct mlx5_inbox_hdr hdr;
1005 __be32 mkey;
1006};
1007
1008struct mlx5_query_mkey_mbox_out {
1009 struct mlx5_outbox_hdr hdr;
1010 __be64 pas[0];
1011};
1012
1013struct mlx5_modify_mkey_mbox_in {
1014 struct mlx5_inbox_hdr hdr;
1015 __be32 mkey;
1016 __be64 pas[0];
1017};
1018
1019struct mlx5_modify_mkey_mbox_out {
1020 struct mlx5_outbox_hdr hdr;
3bdb31f6 1021 u8 rsvd[8];
e126ba97
EC		 1022};
1023
1024struct mlx5_dump_mkey_mbox_in {
1025 struct mlx5_inbox_hdr hdr;
1026};
1027
1028struct mlx5_dump_mkey_mbox_out {
1029 struct mlx5_outbox_hdr hdr;
1030 __be32 mkey;
1031};
1032
1033struct mlx5_mad_ifc_mbox_in {
1034 struct mlx5_inbox_hdr hdr;
1035 __be16 remote_lid;
1036 u8 rsvd0;
1037 u8 port;
1038 u8 rsvd1[4];
1039 u8 data[256];
1040};
1041
1042struct mlx5_mad_ifc_mbox_out {
1043 struct mlx5_outbox_hdr hdr;
1044 u8 rsvd[8];
1045 u8 data[256];
1046};
1047
1048struct mlx5_access_reg_mbox_in {
1049 struct mlx5_inbox_hdr hdr;
1050 u8 rsvd0[2];
1051 __be16 register_id;
1052 __be32 arg;
1053 __be32 data[0];
1054};
1055
1056struct mlx5_access_reg_mbox_out {
1057 struct mlx5_outbox_hdr hdr;
1058 u8 rsvd[8];
1059 __be32 data[0];
1060};
1061
1062#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
1063
1064enum {
1065 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
1066};
1067
3121e3c4
SG		 1068struct mlx5_allocate_psv_in {
1069 struct mlx5_inbox_hdr hdr;
1070 __be32 npsv_pd;
1071 __be32 rsvd_psv0;
1072};
1073
1074struct mlx5_allocate_psv_out {
1075 struct mlx5_outbox_hdr hdr;
1076 u8 rsvd[8];
1077 __be32 psv_idx[4];
1078};
1079
1080struct mlx5_destroy_psv_in {
1081 struct mlx5_inbox_hdr hdr;
1082 __be32 psv_number;
1083 u8 rsvd[4];
1084};
1085
1086struct mlx5_destroy_psv_out {
1087 struct mlx5_outbox_hdr hdr;
1088 u8 rsvd[8];
1089};
1090
e281682b
SM		 1091#define MLX5_CMD_OP_MAX 0x920
1092
1093enum {
1094 VPORT_STATE_DOWN = 0x0,
1095 VPORT_STATE_UP = 0x1,
1096};
1097
1098enum {
1099 MLX5_L3_PROT_TYPE_IPV4 = 0,
1100 MLX5_L3_PROT_TYPE_IPV6 = 1,
1101};
1102
1103enum {
1104 MLX5_L4_PROT_TYPE_TCP = 0,
1105 MLX5_L4_PROT_TYPE_UDP = 1,
1106};
1107
1108enum {
1109 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
1110 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
1111 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
1112 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
1113 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
1114};
1115
1116enum {
1117 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
1118 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
1119 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1120
1121};
1122
1123enum {
1124 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
1125 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
1126};
1127
1128enum {
1129 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
1130 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
1131 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
1132};
1133
1134enum {
1135 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1136 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
1137};
1138
938fe83c
SM		 1139/* MLX5 DEV CAPs */
1140
1141/* TODO: EAT.ME */
1142enum mlx5_cap_mode {
1143 HCA_CAP_OPMOD_GET_MAX = 0,
1144 HCA_CAP_OPMOD_GET_CUR = 1,
1145};
1146
1147enum mlx5_cap_type {
1148 MLX5_CAP_GENERAL = 0,
1149 MLX5_CAP_ETHERNET_OFFLOADS,
1150 MLX5_CAP_ODP,
1151 MLX5_CAP_ATOMIC,
1152 MLX5_CAP_ROCE,
1153 MLX5_CAP_IPOIB_OFFLOADS,
1154 MLX5_CAP_EOIB_OFFLOADS,
1155 MLX5_CAP_FLOW_TABLE,
1156 /* NUM OF CAP Types */
1157 MLX5_CAP_NUM
1158};
1159
1160/* GET Dev Caps macros */
1161#define MLX5_CAP_GEN(mdev, cap) \
1162 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1163
1164#define MLX5_CAP_GEN_MAX(mdev, cap) \
1165 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
1166
1167#define MLX5_CAP_ETH(mdev, cap) \
1168 MLX5_GET(per_protocol_networking_offload_caps,\
1169 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1170
1171#define MLX5_CAP_ETH_MAX(mdev, cap) \
1172 MLX5_GET(per_protocol_networking_offload_caps,\
1173 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1174
1175#define MLX5_CAP_ROCE(mdev, cap) \
1176 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1177
1178#define MLX5_CAP_ROCE_MAX(mdev, cap) \
1179 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1180
1181#define MLX5_CAP_ATOMIC(mdev, cap) \
1182 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1183
1184#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1185 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1186
1187#define MLX5_CAP_FLOWTABLE(mdev, cap) \
1188 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1189
1190#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1191 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1192
1193#define MLX5_CAP_ODP(mdev, cap)\
1194 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1195
f62b8bb8
AV		 1196enum {
1197 MLX5_CMD_STAT_OK = 0x0,
1198 MLX5_CMD_STAT_INT_ERR = 0x1,
1199 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1200 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1201 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1202 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1203 MLX5_CMD_STAT_RES_BUSY = 0x6,
1204 MLX5_CMD_STAT_LIM_ERR = 0x8,
1205 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1206 MLX5_CMD_STAT_IX_ERR = 0xa,
1207 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1208 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1209 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1210 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1211 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1212 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1213};
1214
efea389d
GP		 1215enum {
1216 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1217 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1218 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1219 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1220 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1221 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1222 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11
1223};
1224
707c4602
MD		 1225static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1226{
1227 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1228 return 0;
1229 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1230}
1231
e126ba97 1232#endif /* MLX5_DEVICE_H */
Linux 6.x block layer and io_uring tree(s)