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IB/mlx5: Add support for hca_core_clock and timestamp_mask
[linux-2.6-block.git] / include / linux / mlx5 / device.h
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
e281682b 38#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 39
40#if defined(__LITTLE_ENDIAN)
41#define MLX5_SET_HOST_ENDIANNESS 0
42#elif defined(__BIG_ENDIAN)
43#define MLX5_SET_HOST_ENDIANNESS 0x80
44#else
45#error Host endianness not defined
46#endif
47
d29b796a
EC		 48/* helper macros */
49#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51#define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
52#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
53#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
54#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
58
59#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
60#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
61#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
938fe83c
SM		 62#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
63#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
d29b796a
EC		 64#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
65#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
66
67/* insert a value to a struct */
68#define MLX5_SET(typ, p, fld, v) do { \
69 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
70 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
71 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
72 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
73 << __mlx5_dw_bit_off(typ, fld))); \
74} while (0)
75
e281682b
SM		 76#define MLX5_SET_TO_ONES(typ, p, fld) do { \
77 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
78 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
79 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
80 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
81 << __mlx5_dw_bit_off(typ, fld))); \
82} while (0)
83
d29b796a
EC		 84#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
85__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
86__mlx5_mask(typ, fld))
87
88#define MLX5_GET_PR(typ, p, fld) ({ \
89 u32 ___t = MLX5_GET(typ, p, fld); \
90 pr_debug(#fld " = 0x%x\n", ___t); \
91 ___t; \
92})
93
94#define MLX5_SET64(typ, p, fld, v) do { \
95 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
96 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
97 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
98} while (0)
99
100#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
101
707c4602
MD		 102#define MLX5_GET64_PR(typ, p, fld) ({ \
103 u64 ___t = MLX5_GET64(typ, p, fld); \
104 pr_debug(#fld " = 0x%llx\n", ___t); \
105 ___t; \
106})
107
e126ba97
EC		 108enum {
109 MLX5_MAX_COMMANDS = 32,
110 MLX5_CMD_DATA_BLOCK_SIZE = 512,
111 MLX5_PCI_CMD_XPORT = 7,
3121e3c4
SG		 112 MLX5_MKEY_BSF_OCTO_SIZE = 4,
113 MLX5_MAX_PSVS = 4,
e126ba97
EC		 114};
115
116enum {
117 MLX5_EXTENDED_UD_AV = 0x80000000,
118};
119
120enum {
121 MLX5_CQ_STATE_ARMED = 9,
122 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
123 MLX5_CQ_STATE_FIRED = 0xa,
124};
125
126enum {
127 MLX5_STAT_RATE_OFFSET = 5,
128};
129
130enum {
131 MLX5_INLINE_SEG = 0x80000000,
132};
133
fc11fbf9
SM		 134enum {
135 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
136};
137
c7a08ac7
EC		 138enum {
139 MLX5_MIN_PKEY_TABLE_SIZE = 128,
140 MLX5_MAX_LOG_PKEY_TABLE = 5,
141};
142
e420f0c0
HE		 143enum {
144 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
145};
146
147enum {
148 MLX5_PFAULT_SUBTYPE_WQE = 0,
149 MLX5_PFAULT_SUBTYPE_RDMA = 1,
150};
151
e126ba97
EC		 152enum {
153 MLX5_PERM_LOCAL_READ = 1 << 2,
154 MLX5_PERM_LOCAL_WRITE = 1 << 3,
155 MLX5_PERM_REMOTE_READ = 1 << 4,
156 MLX5_PERM_REMOTE_WRITE = 1 << 5,
157 MLX5_PERM_ATOMIC = 1 << 6,
158 MLX5_PERM_UMR_EN = 1 << 7,
159};
160
161enum {
162 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
163 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
164 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
165 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
166 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
167};
168
169enum {
170 MLX5_ACCESS_MODE_PA = 0,
171 MLX5_ACCESS_MODE_MTT = 1,
172 MLX5_ACCESS_MODE_KLM = 2
173};
174
175enum {
176 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
177 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
178 MLX5_MKEY_BSF_EN = 1 << 30,
179 MLX5_MKEY_LEN64 = 1 << 31,
180};
181
182enum {
183 MLX5_EN_RD = (u64)1,
184 MLX5_EN_WR = (u64)2
185};
186
187enum {
c1be5232
EC		 188 MLX5_BF_REGS_PER_PAGE = 4,
189 MLX5_MAX_UAR_PAGES = 1 << 8,
190 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
191 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
e126ba97
EC		 192};
193
194enum {
195 MLX5_MKEY_MASK_LEN = 1ull << 0,
196 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
197 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
198 MLX5_MKEY_MASK_PD = 1ull << 7,
199 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
d5436ba0 200 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
e126ba97
EC		 201 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
202 MLX5_MKEY_MASK_KEY = 1ull << 13,
203 MLX5_MKEY_MASK_QPN = 1ull << 14,
204 MLX5_MKEY_MASK_LR = 1ull << 17,
205 MLX5_MKEY_MASK_LW = 1ull << 18,
206 MLX5_MKEY_MASK_RR = 1ull << 19,
207 MLX5_MKEY_MASK_RW = 1ull << 20,
208 MLX5_MKEY_MASK_A = 1ull << 21,
209 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
210 MLX5_MKEY_MASK_FREE = 1ull << 29,
211};
212
968e78dd
HE		 213enum {
214 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
215
216 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
217 MLX5_UMR_CHECK_FREE = (2 << 5),
218
219 MLX5_UMR_INLINE = (1 << 7),
220};
221
cc149f75
HE		 222#define MLX5_UMR_MTT_ALIGNMENT 0x40
223#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
832a6b06 224#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
cc149f75 225
e126ba97
EC		 226enum mlx5_event {
227 MLX5_EVENT_TYPE_COMP = 0x0,
228
229 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
230 MLX5_EVENT_TYPE_COMM_EST = 0x02,
231 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
232 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
233 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
234
235 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
236 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
237 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
238 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
239 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
240 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
241
242 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
243 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
244 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
245 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
246
247 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
248 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
249
250 MLX5_EVENT_TYPE_CMD = 0x0a,
251 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
e420f0c0
HE		 252
253 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
e126ba97
EC		 254};
255
256enum {
257 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
258 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
259 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
260 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
261 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
262 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
263 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
264};
265
266enum {
e126ba97 267 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
e126ba97
EC		 268 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
269 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
270 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
271 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
f360d88a 272 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
6cb7ff3d 273 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
3bdb31f6 274 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
bde51583 275 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
c7a08ac7 276 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
e126ba97 277 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
c1868b82 278 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
e126ba97
EC		 279};
280
3cca2606
AS		 281enum {
282 MLX5_ROCE_VERSION_1 = 0,
283 MLX5_ROCE_VERSION_2 = 2,
284};
285
286enum {
287 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
288 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
289};
290
291enum {
292 MLX5_ROCE_L3_TYPE_IPV4 = 0,
293 MLX5_ROCE_L3_TYPE_IPV6 = 1,
294};
295
296enum {
297 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
298 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
299};
300
e126ba97
EC		 301enum {
302 MLX5_OPCODE_NOP = 0x00,
303 MLX5_OPCODE_SEND_INVAL = 0x01,
304 MLX5_OPCODE_RDMA_WRITE = 0x08,
305 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
306 MLX5_OPCODE_SEND = 0x0a,
307 MLX5_OPCODE_SEND_IMM = 0x0b,
e281682b 308 MLX5_OPCODE_LSO = 0x0e,
e126ba97
EC		 309 MLX5_OPCODE_RDMA_READ = 0x10,
310 MLX5_OPCODE_ATOMIC_CS = 0x11,
311 MLX5_OPCODE_ATOMIC_FA = 0x12,
312 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
313 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
314 MLX5_OPCODE_BIND_MW = 0x18,
315 MLX5_OPCODE_CONFIG_CMD = 0x1f,
316
317 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
318 MLX5_RECV_OPCODE_SEND = 0x01,
319 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
320 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
321
322 MLX5_CQE_OPCODE_ERROR = 0x1e,
323 MLX5_CQE_OPCODE_RESIZE = 0x16,
324
325 MLX5_OPCODE_SET_PSV = 0x20,
326 MLX5_OPCODE_GET_PSV = 0x21,
327 MLX5_OPCODE_CHECK_PSV = 0x22,
328 MLX5_OPCODE_RGET_PSV = 0x26,
329 MLX5_OPCODE_RCHECK_PSV = 0x27,
330
331 MLX5_OPCODE_UMR = 0x25,
332
333};
334
335enum {
336 MLX5_SET_PORT_RESET_QKEY = 0,
337 MLX5_SET_PORT_GUID0 = 16,
338 MLX5_SET_PORT_NODE_GUID = 17,
339 MLX5_SET_PORT_SYS_GUID = 18,
340 MLX5_SET_PORT_GID_TABLE = 19,
341 MLX5_SET_PORT_PKEY_TABLE = 20,
342};
343
344enum {
345 MLX5_MAX_PAGE_SHIFT = 31
346};
347
1b77d2bd 348enum {
05bdb2ab
EC		 349 MLX5_ADAPTER_PAGE_SHIFT = 12,
350 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
1b77d2bd
EC		 351};
352
87b8de49 353enum {
87b8de49
EC		 354 MLX5_CAP_OFF_CMDIF_CSUM = 46,
355};
356
e126ba97
EC		 357struct mlx5_inbox_hdr {
358 __be16 opcode;
359 u8 rsvd[4];
360 __be16 opmod;
361};
362
363struct mlx5_outbox_hdr {
364 u8 status;
365 u8 rsvd[3];
366 __be32 syndrome;
367};
368
369struct mlx5_cmd_query_adapter_mbox_in {
370 struct mlx5_inbox_hdr hdr;
371 u8 rsvd[8];
372};
373
374struct mlx5_cmd_query_adapter_mbox_out {
375 struct mlx5_outbox_hdr hdr;
376 u8 rsvd0[24];
377 u8 intapin;
378 u8 rsvd1[13];
379 __be16 vsd_vendor_id;
380 u8 vsd[208];
381 u8 vsd_psid[16];
382};
383
e420f0c0
HE		 384enum mlx5_odp_transport_cap_bits {
385 MLX5_ODP_SUPPORT_SEND = 1 << 31,
386 MLX5_ODP_SUPPORT_RECV = 1 << 30,
387 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
388 MLX5_ODP_SUPPORT_READ = 1 << 28,
389};
390
391struct mlx5_odp_caps {
392 char reserved[0x10];
393 struct {
394 __be32 rc_odp_caps;
395 __be32 uc_odp_caps;
396 __be32 ud_odp_caps;
397 } per_transport_caps;
398 char reserved2[0xe4];
399};
400
e126ba97
EC		 401struct mlx5_cmd_init_hca_mbox_in {
402 struct mlx5_inbox_hdr hdr;
403 u8 rsvd0[2];
404 __be16 profile;
405 u8 rsvd1[4];
406};
407
408struct mlx5_cmd_init_hca_mbox_out {
409 struct mlx5_outbox_hdr hdr;
410 u8 rsvd[8];
411};
412
413struct mlx5_cmd_teardown_hca_mbox_in {
414 struct mlx5_inbox_hdr hdr;
415 u8 rsvd0[2];
416 __be16 profile;
417 u8 rsvd1[4];
418};
419
420struct mlx5_cmd_teardown_hca_mbox_out {
421 struct mlx5_outbox_hdr hdr;
422 u8 rsvd[8];
423};
424
425struct mlx5_cmd_layout {
426 u8 type;
427 u8 rsvd0[3];
428 __be32 inlen;
429 __be64 in_ptr;
430 __be32 in[4];
431 __be32 out[4];
432 __be64 out_ptr;
433 __be32 outlen;
434 u8 token;
435 u8 sig;
436 u8 rsvd1;
437 u8 status_own;
438};
439
440
441struct health_buffer {
442 __be32 assert_var[5];
443 __be32 rsvd0[3];
444 __be32 assert_exit_ptr;
445 __be32 assert_callra;
446 __be32 rsvd1[2];
447 __be32 fw_ver;
448 __be32 hw_id;
449 __be32 rsvd2;
450 u8 irisc_index;
451 u8 synd;
78ccb258 452 __be16 ext_synd;
e126ba97
EC		 453};
454
455struct mlx5_init_seg {
456 __be32 fw_rev;
457 __be32 cmdif_rev_fw_sub;
458 __be32 rsvd0[2];
459 __be32 cmdq_addr_h;
460 __be32 cmdq_addr_l_sz;
461 __be32 cmd_dbell;
e3297246
EC		 462 __be32 rsvd1[120];
463 __be32 initializing;
e126ba97
EC		 464 struct health_buffer health;
465 __be32 rsvd2[884];
466 __be32 health_counter;
2f6daec1 467 __be32 rsvd3[1019];
e126ba97
EC		 468 __be64 ieee1588_clk;
469 __be32 ieee1588_clk_type;
470 __be32 clr_intx;
471};
472
473struct mlx5_eqe_comp {
474 __be32 reserved[6];
475 __be32 cqn;
476};
477
478struct mlx5_eqe_qp_srq {
479 __be32 reserved[6];
480 __be32 qp_srq_n;
481};
482
483struct mlx5_eqe_cq_err {
484 __be32 cqn;
485 u8 reserved1[7];
486 u8 syndrome;
487};
488
e126ba97
EC		 489struct mlx5_eqe_port_state {
490 u8 reserved0[8];
491 u8 port;
492};
493
494struct mlx5_eqe_gpio {
495 __be32 reserved0[2];
496 __be64 gpio_event;
497};
498
499struct mlx5_eqe_congestion {
500 u8 type;
501 u8 rsvd0;
502 u8 congestion_level;
503};
504
505struct mlx5_eqe_stall_vl {
506 u8 rsvd0[3];
507 u8 port_vl;
508};
509
510struct mlx5_eqe_cmd {
511 __be32 vector;
512 __be32 rsvd[6];
513};
514
515struct mlx5_eqe_page_req {
516 u8 rsvd0[2];
517 __be16 func_id;
0a324f31
ML		 518 __be32 num_pages;
519 __be32 rsvd1[5];
e126ba97
EC		 520};
521
e420f0c0
HE		 522struct mlx5_eqe_page_fault {
523 __be32 bytes_committed;
524 union {
525 struct {
526 u16 reserved1;
527 __be16 wqe_index;
528 u16 reserved2;
529 __be16 packet_length;
530 u8 reserved3[12];
531 } __packed wqe;
532 struct {
533 __be32 r_key;
534 u16 reserved1;
535 __be16 packet_length;
536 __be32 rdma_op_len;
537 __be64 rdma_va;
538 } __packed rdma;
539 } __packed;
540 __be32 flags_qpn;
541} __packed;
542
e126ba97
EC		 543union ev_data {
544 __be32 raw[7];
545 struct mlx5_eqe_cmd cmd;
546 struct mlx5_eqe_comp comp;
547 struct mlx5_eqe_qp_srq qp_srq;
548 struct mlx5_eqe_cq_err cq_err;
e126ba97
EC		 549 struct mlx5_eqe_port_state port;
550 struct mlx5_eqe_gpio gpio;
551 struct mlx5_eqe_congestion cong;
552 struct mlx5_eqe_stall_vl stall_vl;
553 struct mlx5_eqe_page_req req_pages;
e420f0c0 554 struct mlx5_eqe_page_fault page_fault;
e126ba97
EC		 555} __packed;
556
557struct mlx5_eqe {
558 u8 rsvd0;
559 u8 type;
560 u8 rsvd1;
561 u8 sub_type;
562 __be32 rsvd2[7];
563 union ev_data data;
564 __be16 rsvd3;
565 u8 signature;
566 u8 owner;
567} __packed;
568
569struct mlx5_cmd_prot_block {
570 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
571 u8 rsvd0[48];
572 __be64 next;
573 __be32 block_num;
574 u8 rsvd1;
575 u8 token;
576 u8 ctrl_sig;
577 u8 sig;
578};
579
e281682b
SM		 580enum {
581 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
582};
583
e126ba97
EC		 584struct mlx5_err_cqe {
585 u8 rsvd0[32];
586 __be32 srqn;
587 u8 rsvd1[18];
588 u8 vendor_err_synd;
589 u8 syndrome;
590 __be32 s_wqe_opcode_qpn;
591 __be16 wqe_counter;
592 u8 signature;
593 u8 op_own;
594};
595
596struct mlx5_cqe64 {
e281682b
SM		 597 u8 rsvd0[4];
598 u8 lro_tcppsh_abort_dupack;
599 u8 lro_min_ttl;
600 __be16 lro_tcp_win;
601 __be32 lro_ack_seq_num;
602 __be32 rss_hash_result;
603 u8 rss_hash_type;
e126ba97 604 u8 ml_path;
e281682b
SM		 605 u8 rsvd20[2];
606 __be16 check_sum;
e126ba97
EC		 607 __be16 slid;
608 __be32 flags_rqpn;
e281682b
SM		 609 u8 hds_ip_ext;
610 u8 l4_hdr_type_etc;
611 __be16 vlan_info;
612 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
e126ba97
EC		 613 __be32 imm_inval_pkey;
614 u8 rsvd40[4];
615 __be32 byte_cnt;
616 __be64 timestamp;
617 __be32 sop_drop_qpn;
618 __be16 wqe_counter;
619 u8 signature;
620 u8 op_own;
621};
622
e281682b
SM		 623static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
624{
625 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
626}
627
628static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
629{
630 return (cqe->l4_hdr_type_etc >> 4) & 0x7;
631}
632
633static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
634{
635 return !!(cqe->l4_hdr_type_etc & 0x1);
636}
637
638enum {
639 CQE_L4_HDR_TYPE_NONE = 0x0,
640 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
641 CQE_L4_HDR_TYPE_UDP = 0x2,
642 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
643 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
644};
645
646enum {
647 CQE_RSS_HTYPE_IP = 0x3 << 6,
648 CQE_RSS_HTYPE_L4 = 0x3 << 2,
649};
650
cb34be6d
AS		 651enum {
652 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
653 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
654 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
655};
656
e281682b
SM		 657enum {
658 CQE_L2_OK = 1 << 0,
659 CQE_L3_OK = 1 << 1,
660 CQE_L4_OK = 1 << 2,
661};
662
d5436ba0
SG		 663struct mlx5_sig_err_cqe {
664 u8 rsvd0[16];
665 __be32 expected_trans_sig;
666 __be32 actual_trans_sig;
667 __be32 expected_reftag;
668 __be32 actual_reftag;
669 __be16 syndrome;
670 u8 rsvd22[2];
671 __be32 mkey;
672 __be64 err_offset;
673 u8 rsvd30[8];
674 __be32 qpn;
675 u8 rsvd38[2];
676 u8 signature;
677 u8 op_own;
678};
679
e126ba97
EC		 680struct mlx5_wqe_srq_next_seg {
681 u8 rsvd0[2];
682 __be16 next_wqe_index;
683 u8 signature;
684 u8 rsvd1[11];
685};
686
687union mlx5_ext_cqe {
688 struct ib_grh grh;
689 u8 inl[64];
690};
691
692struct mlx5_cqe128 {
693 union mlx5_ext_cqe inl_grh;
694 struct mlx5_cqe64 cqe64;
695};
696
697struct mlx5_srq_ctx {
698 u8 state_log_sz;
699 u8 rsvd0[3];
700 __be32 flags_xrcd;
701 __be32 pgoff_cqn;
702 u8 rsvd1[4];
703 u8 log_pg_sz;
704 u8 rsvd2[7];
705 __be32 pd;
706 __be16 lwm;
707 __be16 wqe_cnt;
708 u8 rsvd3[8];
709 __be64 db_record;
710};
711
712struct mlx5_create_srq_mbox_in {
713 struct mlx5_inbox_hdr hdr;
714 __be32 input_srqn;
715 u8 rsvd0[4];
716 struct mlx5_srq_ctx ctx;
717 u8 rsvd1[208];
718 __be64 pas[0];
719};
720
721struct mlx5_create_srq_mbox_out {
722 struct mlx5_outbox_hdr hdr;
723 __be32 srqn;
724 u8 rsvd[4];
725};
726
727struct mlx5_destroy_srq_mbox_in {
728 struct mlx5_inbox_hdr hdr;
729 __be32 srqn;
730 u8 rsvd[4];
731};
732
733struct mlx5_destroy_srq_mbox_out {
734 struct mlx5_outbox_hdr hdr;
735 u8 rsvd[8];
736};
737
738struct mlx5_query_srq_mbox_in {
739 struct mlx5_inbox_hdr hdr;
740 __be32 srqn;
741 u8 rsvd0[4];
742};
743
744struct mlx5_query_srq_mbox_out {
745 struct mlx5_outbox_hdr hdr;
746 u8 rsvd0[8];
747 struct mlx5_srq_ctx ctx;
748 u8 rsvd1[32];
749 __be64 pas[0];
750};
751
752struct mlx5_arm_srq_mbox_in {
753 struct mlx5_inbox_hdr hdr;
754 __be32 srqn;
755 __be16 rsvd;
756 __be16 lwm;
757};
758
759struct mlx5_arm_srq_mbox_out {
760 struct mlx5_outbox_hdr hdr;
761 u8 rsvd[8];
762};
763
764struct mlx5_cq_context {
765 u8 status;
766 u8 cqe_sz_flags;
767 u8 st;
768 u8 rsvd3;
769 u8 rsvd4[6];
770 __be16 page_offset;
771 __be32 log_sz_usr_page;
772 __be16 cq_period;
773 __be16 cq_max_count;
774 __be16 rsvd20;
775 __be16 c_eqn;
776 u8 log_pg_sz;
777 u8 rsvd25[7];
778 __be32 last_notified_index;
779 __be32 solicit_producer_index;
780 __be32 consumer_counter;
781 __be32 producer_counter;
782 u8 rsvd48[8];
783 __be64 db_record_addr;
784};
785
786struct mlx5_create_cq_mbox_in {
787 struct mlx5_inbox_hdr hdr;
788 __be32 input_cqn;
789 u8 rsvdx[4];
790 struct mlx5_cq_context ctx;
791 u8 rsvd6[192];
792 __be64 pas[0];
793};
794
795struct mlx5_create_cq_mbox_out {
796 struct mlx5_outbox_hdr hdr;
797 __be32 cqn;
798 u8 rsvd0[4];
799};
800
801struct mlx5_destroy_cq_mbox_in {
802 struct mlx5_inbox_hdr hdr;
803 __be32 cqn;
804 u8 rsvd0[4];
805};
806
807struct mlx5_destroy_cq_mbox_out {
808 struct mlx5_outbox_hdr hdr;
809 u8 rsvd0[8];
810};
811
812struct mlx5_query_cq_mbox_in {
813 struct mlx5_inbox_hdr hdr;
814 __be32 cqn;
815 u8 rsvd0[4];
816};
817
818struct mlx5_query_cq_mbox_out {
819 struct mlx5_outbox_hdr hdr;
820 u8 rsvd0[8];
821 struct mlx5_cq_context ctx;
822 u8 rsvd6[16];
823 __be64 pas[0];
824};
825
3bdb31f6
EC		 826struct mlx5_modify_cq_mbox_in {
827 struct mlx5_inbox_hdr hdr;
828 __be32 cqn;
829 __be32 field_select;
830 struct mlx5_cq_context ctx;
831 u8 rsvd[192];
832 __be64 pas[0];
833};
834
835struct mlx5_modify_cq_mbox_out {
836 struct mlx5_outbox_hdr hdr;
bde51583 837 u8 rsvd[8];
3bdb31f6
EC		 838};
839
cd23b14b
EC		 840struct mlx5_enable_hca_mbox_in {
841 struct mlx5_inbox_hdr hdr;
842 u8 rsvd[8];
843};
844
845struct mlx5_enable_hca_mbox_out {
846 struct mlx5_outbox_hdr hdr;
847 u8 rsvd[8];
848};
849
850struct mlx5_disable_hca_mbox_in {
851 struct mlx5_inbox_hdr hdr;
852 u8 rsvd[8];
853};
854
855struct mlx5_disable_hca_mbox_out {
856 struct mlx5_outbox_hdr hdr;
857 u8 rsvd[8];
858};
859
e126ba97
EC		 860struct mlx5_eq_context {
861 u8 status;
862 u8 ec_oi;
863 u8 st;
864 u8 rsvd2[7];
865 __be16 page_pffset;
866 __be32 log_sz_usr_page;
867 u8 rsvd3[7];
868 u8 intr;
869 u8 log_page_size;
870 u8 rsvd4[15];
871 __be32 consumer_counter;
872 __be32 produser_counter;
873 u8 rsvd5[16];
874};
875
876struct mlx5_create_eq_mbox_in {
877 struct mlx5_inbox_hdr hdr;
878 u8 rsvd0[3];
879 u8 input_eqn;
880 u8 rsvd1[4];
881 struct mlx5_eq_context ctx;
882 u8 rsvd2[8];
883 __be64 events_mask;
884 u8 rsvd3[176];
885 __be64 pas[0];
886};
887
888struct mlx5_create_eq_mbox_out {
889 struct mlx5_outbox_hdr hdr;
890 u8 rsvd0[3];
891 u8 eq_number;
892 u8 rsvd1[4];
893};
894
895struct mlx5_destroy_eq_mbox_in {
896 struct mlx5_inbox_hdr hdr;
897 u8 rsvd0[3];
898 u8 eqn;
899 u8 rsvd1[4];
900};
901
902struct mlx5_destroy_eq_mbox_out {
903 struct mlx5_outbox_hdr hdr;
904 u8 rsvd[8];
905};
906
907struct mlx5_map_eq_mbox_in {
908 struct mlx5_inbox_hdr hdr;
909 __be64 mask;
910 u8 mu;
911 u8 rsvd0[2];
912 u8 eqn;
913 u8 rsvd1[24];
914};
915
916struct mlx5_map_eq_mbox_out {
917 struct mlx5_outbox_hdr hdr;
918 u8 rsvd[8];
919};
920
921struct mlx5_query_eq_mbox_in {
922 struct mlx5_inbox_hdr hdr;
923 u8 rsvd0[3];
924 u8 eqn;
925 u8 rsvd1[4];
926};
927
928struct mlx5_query_eq_mbox_out {
929 struct mlx5_outbox_hdr hdr;
930 u8 rsvd[8];
931 struct mlx5_eq_context ctx;
932};
933
968e78dd
HE		 934enum {
935 MLX5_MKEY_STATUS_FREE = 1 << 6,
936};
937
e126ba97
EC		 938struct mlx5_mkey_seg {
939 /* This is a two bit field occupying bits 31-30.
940 * bit 31 is always 0,
941 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
942 */
943 u8 status;
944 u8 pcie_control;
945 u8 flags;
946 u8 version;
947 __be32 qpn_mkey7_0;
948 u8 rsvd1[4];
949 __be32 flags_pd;
950 __be64 start_addr;
951 __be64 len;
952 __be32 bsfs_octo_size;
953 u8 rsvd2[16];
954 __be32 xlt_oct_size;
955 u8 rsvd3[3];
956 u8 log2_page_size;
957 u8 rsvd4[4];
958};
959
960struct mlx5_query_special_ctxs_mbox_in {
961 struct mlx5_inbox_hdr hdr;
962 u8 rsvd[8];
963};
964
965struct mlx5_query_special_ctxs_mbox_out {
966 struct mlx5_outbox_hdr hdr;
967 __be32 dump_fill_mkey;
968 __be32 reserved_lkey;
969};
970
971struct mlx5_create_mkey_mbox_in {
972 struct mlx5_inbox_hdr hdr;
973 __be32 input_mkey_index;
e420f0c0 974 __be32 flags;
e126ba97
EC		 975 struct mlx5_mkey_seg seg;
976 u8 rsvd1[16];
977 __be32 xlat_oct_act_size;
8c8a4914
EC		 978 __be32 rsvd2;
979 u8 rsvd3[168];
e126ba97
EC		 980 __be64 pas[0];
981};
982
983struct mlx5_create_mkey_mbox_out {
984 struct mlx5_outbox_hdr hdr;
985 __be32 mkey;
986 u8 rsvd[4];
987};
988
989struct mlx5_destroy_mkey_mbox_in {
990 struct mlx5_inbox_hdr hdr;
991 __be32 mkey;
992 u8 rsvd[4];
993};
994
995struct mlx5_destroy_mkey_mbox_out {
996 struct mlx5_outbox_hdr hdr;
997 u8 rsvd[8];
998};
999
1000struct mlx5_query_mkey_mbox_in {
1001 struct mlx5_inbox_hdr hdr;
1002 __be32 mkey;
1003};
1004
1005struct mlx5_query_mkey_mbox_out {
1006 struct mlx5_outbox_hdr hdr;
1007 __be64 pas[0];
1008};
1009
1010struct mlx5_modify_mkey_mbox_in {
1011 struct mlx5_inbox_hdr hdr;
1012 __be32 mkey;
1013 __be64 pas[0];
1014};
1015
1016struct mlx5_modify_mkey_mbox_out {
1017 struct mlx5_outbox_hdr hdr;
3bdb31f6 1018 u8 rsvd[8];
e126ba97
EC		 1019};
1020
1021struct mlx5_dump_mkey_mbox_in {
1022 struct mlx5_inbox_hdr hdr;
1023};
1024
1025struct mlx5_dump_mkey_mbox_out {
1026 struct mlx5_outbox_hdr hdr;
1027 __be32 mkey;
1028};
1029
1030struct mlx5_mad_ifc_mbox_in {
1031 struct mlx5_inbox_hdr hdr;
1032 __be16 remote_lid;
1033 u8 rsvd0;
1034 u8 port;
1035 u8 rsvd1[4];
1036 u8 data[256];
1037};
1038
1039struct mlx5_mad_ifc_mbox_out {
1040 struct mlx5_outbox_hdr hdr;
1041 u8 rsvd[8];
1042 u8 data[256];
1043};
1044
1045struct mlx5_access_reg_mbox_in {
1046 struct mlx5_inbox_hdr hdr;
1047 u8 rsvd0[2];
1048 __be16 register_id;
1049 __be32 arg;
1050 __be32 data[0];
1051};
1052
1053struct mlx5_access_reg_mbox_out {
1054 struct mlx5_outbox_hdr hdr;
1055 u8 rsvd[8];
1056 __be32 data[0];
1057};
1058
1059#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
1060
1061enum {
1062 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
1063};
1064
3121e3c4
SG		 1065struct mlx5_allocate_psv_in {
1066 struct mlx5_inbox_hdr hdr;
1067 __be32 npsv_pd;
1068 __be32 rsvd_psv0;
1069};
1070
1071struct mlx5_allocate_psv_out {
1072 struct mlx5_outbox_hdr hdr;
1073 u8 rsvd[8];
1074 __be32 psv_idx[4];
1075};
1076
1077struct mlx5_destroy_psv_in {
1078 struct mlx5_inbox_hdr hdr;
1079 __be32 psv_number;
1080 u8 rsvd[4];
1081};
1082
1083struct mlx5_destroy_psv_out {
1084 struct mlx5_outbox_hdr hdr;
1085 u8 rsvd[8];
1086};
1087
e281682b
SM		 1088#define MLX5_CMD_OP_MAX 0x920
1089
1090enum {
1091 VPORT_STATE_DOWN = 0x0,
1092 VPORT_STATE_UP = 0x1,
1093};
1094
1095enum {
1096 MLX5_L3_PROT_TYPE_IPV4 = 0,
1097 MLX5_L3_PROT_TYPE_IPV6 = 1,
1098};
1099
1100enum {
1101 MLX5_L4_PROT_TYPE_TCP = 0,
1102 MLX5_L4_PROT_TYPE_UDP = 1,
1103};
1104
1105enum {
1106 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
1107 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
1108 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
1109 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
1110 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
1111};
1112
1113enum {
1114 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
1115 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
1116 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1117
1118};
1119
1120enum {
1121 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
1122 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
1123};
1124
1125enum {
1126 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
1127 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
1128 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
1129};
1130
1131enum {
1132 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1133 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
1134};
1135
938fe83c
SM		 1136/* MLX5 DEV CAPs */
1137
1138/* TODO: EAT.ME */
1139enum mlx5_cap_mode {
1140 HCA_CAP_OPMOD_GET_MAX = 0,
1141 HCA_CAP_OPMOD_GET_CUR = 1,
1142};
1143
1144enum mlx5_cap_type {
1145 MLX5_CAP_GENERAL = 0,
1146 MLX5_CAP_ETHERNET_OFFLOADS,
1147 MLX5_CAP_ODP,
1148 MLX5_CAP_ATOMIC,
1149 MLX5_CAP_ROCE,
1150 MLX5_CAP_IPOIB_OFFLOADS,
1151 MLX5_CAP_EOIB_OFFLOADS,
1152 MLX5_CAP_FLOW_TABLE,
1153 /* NUM OF CAP Types */
1154 MLX5_CAP_NUM
1155};
1156
1157/* GET Dev Caps macros */
1158#define MLX5_CAP_GEN(mdev, cap) \
1159 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1160
1161#define MLX5_CAP_GEN_MAX(mdev, cap) \
1162 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
1163
1164#define MLX5_CAP_ETH(mdev, cap) \
1165 MLX5_GET(per_protocol_networking_offload_caps,\
1166 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1167
1168#define MLX5_CAP_ETH_MAX(mdev, cap) \
1169 MLX5_GET(per_protocol_networking_offload_caps,\
1170 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1171
1172#define MLX5_CAP_ROCE(mdev, cap) \
1173 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1174
1175#define MLX5_CAP_ROCE_MAX(mdev, cap) \
1176 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1177
1178#define MLX5_CAP_ATOMIC(mdev, cap) \
1179 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1180
1181#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1182 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1183
1184#define MLX5_CAP_FLOWTABLE(mdev, cap) \
1185 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1186
1187#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1188 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1189
1190#define MLX5_CAP_ODP(mdev, cap)\
1191 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1192
f62b8bb8
AV		 1193enum {
1194 MLX5_CMD_STAT_OK = 0x0,
1195 MLX5_CMD_STAT_INT_ERR = 0x1,
1196 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1197 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1198 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1199 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1200 MLX5_CMD_STAT_RES_BUSY = 0x6,
1201 MLX5_CMD_STAT_LIM_ERR = 0x8,
1202 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1203 MLX5_CMD_STAT_IX_ERR = 0xa,
1204 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1205 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1206 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1207 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1208 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1209 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1210};
1211
efea389d
GP		 1212enum {
1213 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1214 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1215 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1216 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1217 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1218 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1219 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11
1220};
1221
707c4602
MD		 1222static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1223{
1224 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1225 return 0;
1226 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1227}
1228
e126ba97 1229#endif /* MLX5_DEVICE_H */
Linux 6.x block layer and io_uring tree(s)