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net/mlx5: E-Switch, Introduce Vport administration functions
[linux-2.6-block.git] / include / linux / mlx5 / device.h
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
e281682b 38#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 39
40#if defined(__LITTLE_ENDIAN)
41#define MLX5_SET_HOST_ENDIANNESS 0
42#elif defined(__BIG_ENDIAN)
43#define MLX5_SET_HOST_ENDIANNESS 0x80
44#else
45#error Host endianness not defined
46#endif
47
d29b796a
EC		 48/* helper macros */
49#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51#define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
52#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
53#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
54#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
58
59#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
60#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
61#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
938fe83c
SM		 62#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
63#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
d29b796a
EC		 64#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
65#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
66
67/* insert a value to a struct */
68#define MLX5_SET(typ, p, fld, v) do { \
69 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
70 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
71 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
72 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
73 << __mlx5_dw_bit_off(typ, fld))); \
74} while (0)
75
e281682b
SM		 76#define MLX5_SET_TO_ONES(typ, p, fld) do { \
77 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
78 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
79 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
80 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
81 << __mlx5_dw_bit_off(typ, fld))); \
82} while (0)
83
d29b796a
EC		 84#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
85__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
86__mlx5_mask(typ, fld))
87
88#define MLX5_GET_PR(typ, p, fld) ({ \
89 u32 ___t = MLX5_GET(typ, p, fld); \
90 pr_debug(#fld " = 0x%x\n", ___t); \
91 ___t; \
92})
93
94#define MLX5_SET64(typ, p, fld, v) do { \
95 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
96 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
97 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
98} while (0)
99
100#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
101
707c4602
MD		 102#define MLX5_GET64_PR(typ, p, fld) ({ \
103 u64 ___t = MLX5_GET64(typ, p, fld); \
104 pr_debug(#fld " = 0x%llx\n", ___t); \
105 ___t; \
106})
107
e126ba97
EC		 108enum {
109 MLX5_MAX_COMMANDS = 32,
110 MLX5_CMD_DATA_BLOCK_SIZE = 512,
111 MLX5_PCI_CMD_XPORT = 7,
3121e3c4
SG		 112 MLX5_MKEY_BSF_OCTO_SIZE = 4,
113 MLX5_MAX_PSVS = 4,
e126ba97
EC		 114};
115
116enum {
117 MLX5_EXTENDED_UD_AV = 0x80000000,
118};
119
120enum {
121 MLX5_CQ_STATE_ARMED = 9,
122 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
123 MLX5_CQ_STATE_FIRED = 0xa,
124};
125
126enum {
127 MLX5_STAT_RATE_OFFSET = 5,
128};
129
130enum {
131 MLX5_INLINE_SEG = 0x80000000,
132};
133
fc11fbf9
SM		 134enum {
135 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
136};
137
c7a08ac7
EC		 138enum {
139 MLX5_MIN_PKEY_TABLE_SIZE = 128,
140 MLX5_MAX_LOG_PKEY_TABLE = 5,
141};
142
e420f0c0
HE		 143enum {
144 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
145};
146
147enum {
148 MLX5_PFAULT_SUBTYPE_WQE = 0,
149 MLX5_PFAULT_SUBTYPE_RDMA = 1,
150};
151
e126ba97
EC		 152enum {
153 MLX5_PERM_LOCAL_READ = 1 << 2,
154 MLX5_PERM_LOCAL_WRITE = 1 << 3,
155 MLX5_PERM_REMOTE_READ = 1 << 4,
156 MLX5_PERM_REMOTE_WRITE = 1 << 5,
157 MLX5_PERM_ATOMIC = 1 << 6,
158 MLX5_PERM_UMR_EN = 1 << 7,
159};
160
161enum {
162 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
163 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
164 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
165 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
166 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
167};
168
169enum {
170 MLX5_ACCESS_MODE_PA = 0,
171 MLX5_ACCESS_MODE_MTT = 1,
172 MLX5_ACCESS_MODE_KLM = 2
173};
174
175enum {
176 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
177 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
178 MLX5_MKEY_BSF_EN = 1 << 30,
179 MLX5_MKEY_LEN64 = 1 << 31,
180};
181
182enum {
183 MLX5_EN_RD = (u64)1,
184 MLX5_EN_WR = (u64)2
185};
186
187enum {
c1be5232
EC		 188 MLX5_BF_REGS_PER_PAGE = 4,
189 MLX5_MAX_UAR_PAGES = 1 << 8,
190 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
191 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
e126ba97
EC		 192};
193
194enum {
195 MLX5_MKEY_MASK_LEN = 1ull << 0,
196 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
197 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
198 MLX5_MKEY_MASK_PD = 1ull << 7,
199 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
d5436ba0 200 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
e126ba97
EC		 201 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
202 MLX5_MKEY_MASK_KEY = 1ull << 13,
203 MLX5_MKEY_MASK_QPN = 1ull << 14,
204 MLX5_MKEY_MASK_LR = 1ull << 17,
205 MLX5_MKEY_MASK_LW = 1ull << 18,
206 MLX5_MKEY_MASK_RR = 1ull << 19,
207 MLX5_MKEY_MASK_RW = 1ull << 20,
208 MLX5_MKEY_MASK_A = 1ull << 21,
209 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
210 MLX5_MKEY_MASK_FREE = 1ull << 29,
211};
212
968e78dd
HE		 213enum {
214 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
215
216 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
217 MLX5_UMR_CHECK_FREE = (2 << 5),
218
219 MLX5_UMR_INLINE = (1 << 7),
220};
221
cc149f75
HE		 222#define MLX5_UMR_MTT_ALIGNMENT 0x40
223#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
832a6b06 224#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
cc149f75 225
e126ba97
EC		 226enum mlx5_event {
227 MLX5_EVENT_TYPE_COMP = 0x0,
228
229 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
230 MLX5_EVENT_TYPE_COMM_EST = 0x02,
231 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
232 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
233 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
234
235 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
236 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
237 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
238 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
239 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
240 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
241
242 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
243 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
244 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
245 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
246
247 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
248 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
249
250 MLX5_EVENT_TYPE_CMD = 0x0a,
251 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
e420f0c0
HE		 252
253 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
073bb189 254 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
e126ba97
EC		 255};
256
257enum {
258 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
259 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
260 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
261 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
262 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
263 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
264 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
265};
266
267enum {
e126ba97 268 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
e126ba97
EC		 269 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
270 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
271 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
272 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
f360d88a 273 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
6cb7ff3d 274 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
3bdb31f6 275 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
bde51583 276 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
c7a08ac7 277 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
e126ba97 278 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
c1868b82 279 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
e126ba97
EC		 280};
281
282enum {
283 MLX5_OPCODE_NOP = 0x00,
284 MLX5_OPCODE_SEND_INVAL = 0x01,
285 MLX5_OPCODE_RDMA_WRITE = 0x08,
286 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
287 MLX5_OPCODE_SEND = 0x0a,
288 MLX5_OPCODE_SEND_IMM = 0x0b,
e281682b 289 MLX5_OPCODE_LSO = 0x0e,
e126ba97
EC		 290 MLX5_OPCODE_RDMA_READ = 0x10,
291 MLX5_OPCODE_ATOMIC_CS = 0x11,
292 MLX5_OPCODE_ATOMIC_FA = 0x12,
293 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
294 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
295 MLX5_OPCODE_BIND_MW = 0x18,
296 MLX5_OPCODE_CONFIG_CMD = 0x1f,
297
298 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
299 MLX5_RECV_OPCODE_SEND = 0x01,
300 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
301 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
302
303 MLX5_CQE_OPCODE_ERROR = 0x1e,
304 MLX5_CQE_OPCODE_RESIZE = 0x16,
305
306 MLX5_OPCODE_SET_PSV = 0x20,
307 MLX5_OPCODE_GET_PSV = 0x21,
308 MLX5_OPCODE_CHECK_PSV = 0x22,
309 MLX5_OPCODE_RGET_PSV = 0x26,
310 MLX5_OPCODE_RCHECK_PSV = 0x27,
311
312 MLX5_OPCODE_UMR = 0x25,
313
314};
315
316enum {
317 MLX5_SET_PORT_RESET_QKEY = 0,
318 MLX5_SET_PORT_GUID0 = 16,
319 MLX5_SET_PORT_NODE_GUID = 17,
320 MLX5_SET_PORT_SYS_GUID = 18,
321 MLX5_SET_PORT_GID_TABLE = 19,
322 MLX5_SET_PORT_PKEY_TABLE = 20,
323};
324
325enum {
326 MLX5_MAX_PAGE_SHIFT = 31
327};
328
1b77d2bd 329enum {
05bdb2ab
EC		 330 MLX5_ADAPTER_PAGE_SHIFT = 12,
331 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
1b77d2bd
EC		 332};
333
87b8de49 334enum {
87b8de49
EC		 335 MLX5_CAP_OFF_CMDIF_CSUM = 46,
336};
337
e126ba97
EC		 338struct mlx5_inbox_hdr {
339 __be16 opcode;
340 u8 rsvd[4];
341 __be16 opmod;
342};
343
344struct mlx5_outbox_hdr {
345 u8 status;
346 u8 rsvd[3];
347 __be32 syndrome;
348};
349
350struct mlx5_cmd_query_adapter_mbox_in {
351 struct mlx5_inbox_hdr hdr;
352 u8 rsvd[8];
353};
354
355struct mlx5_cmd_query_adapter_mbox_out {
356 struct mlx5_outbox_hdr hdr;
357 u8 rsvd0[24];
358 u8 intapin;
359 u8 rsvd1[13];
360 __be16 vsd_vendor_id;
361 u8 vsd[208];
362 u8 vsd_psid[16];
363};
364
e420f0c0
HE		 365enum mlx5_odp_transport_cap_bits {
366 MLX5_ODP_SUPPORT_SEND = 1 << 31,
367 MLX5_ODP_SUPPORT_RECV = 1 << 30,
368 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
369 MLX5_ODP_SUPPORT_READ = 1 << 28,
370};
371
372struct mlx5_odp_caps {
373 char reserved[0x10];
374 struct {
375 __be32 rc_odp_caps;
376 __be32 uc_odp_caps;
377 __be32 ud_odp_caps;
378 } per_transport_caps;
379 char reserved2[0xe4];
380};
381
e126ba97
EC		 382struct mlx5_cmd_init_hca_mbox_in {
383 struct mlx5_inbox_hdr hdr;
384 u8 rsvd0[2];
385 __be16 profile;
386 u8 rsvd1[4];
387};
388
389struct mlx5_cmd_init_hca_mbox_out {
390 struct mlx5_outbox_hdr hdr;
391 u8 rsvd[8];
392};
393
394struct mlx5_cmd_teardown_hca_mbox_in {
395 struct mlx5_inbox_hdr hdr;
396 u8 rsvd0[2];
397 __be16 profile;
398 u8 rsvd1[4];
399};
400
401struct mlx5_cmd_teardown_hca_mbox_out {
402 struct mlx5_outbox_hdr hdr;
403 u8 rsvd[8];
404};
405
406struct mlx5_cmd_layout {
407 u8 type;
408 u8 rsvd0[3];
409 __be32 inlen;
410 __be64 in_ptr;
411 __be32 in[4];
412 __be32 out[4];
413 __be64 out_ptr;
414 __be32 outlen;
415 u8 token;
416 u8 sig;
417 u8 rsvd1;
418 u8 status_own;
419};
420
421
422struct health_buffer {
423 __be32 assert_var[5];
424 __be32 rsvd0[3];
425 __be32 assert_exit_ptr;
426 __be32 assert_callra;
427 __be32 rsvd1[2];
428 __be32 fw_ver;
429 __be32 hw_id;
430 __be32 rsvd2;
431 u8 irisc_index;
432 u8 synd;
78ccb258 433 __be16 ext_synd;
e126ba97
EC		 434};
435
436struct mlx5_init_seg {
437 __be32 fw_rev;
438 __be32 cmdif_rev_fw_sub;
439 __be32 rsvd0[2];
440 __be32 cmdq_addr_h;
441 __be32 cmdq_addr_l_sz;
442 __be32 cmd_dbell;
e3297246
EC		 443 __be32 rsvd1[120];
444 __be32 initializing;
e126ba97
EC		 445 struct health_buffer health;
446 __be32 rsvd2[884];
447 __be32 health_counter;
2f6daec1 448 __be32 rsvd3[1019];
e126ba97
EC		 449 __be64 ieee1588_clk;
450 __be32 ieee1588_clk_type;
451 __be32 clr_intx;
452};
453
454struct mlx5_eqe_comp {
455 __be32 reserved[6];
456 __be32 cqn;
457};
458
459struct mlx5_eqe_qp_srq {
460 __be32 reserved[6];
461 __be32 qp_srq_n;
462};
463
464struct mlx5_eqe_cq_err {
465 __be32 cqn;
466 u8 reserved1[7];
467 u8 syndrome;
468};
469
e126ba97
EC		 470struct mlx5_eqe_port_state {
471 u8 reserved0[8];
472 u8 port;
473};
474
475struct mlx5_eqe_gpio {
476 __be32 reserved0[2];
477 __be64 gpio_event;
478};
479
480struct mlx5_eqe_congestion {
481 u8 type;
482 u8 rsvd0;
483 u8 congestion_level;
484};
485
486struct mlx5_eqe_stall_vl {
487 u8 rsvd0[3];
488 u8 port_vl;
489};
490
491struct mlx5_eqe_cmd {
492 __be32 vector;
493 __be32 rsvd[6];
494};
495
496struct mlx5_eqe_page_req {
497 u8 rsvd0[2];
498 __be16 func_id;
0a324f31
ML		 499 __be32 num_pages;
500 __be32 rsvd1[5];
e126ba97
EC		 501};
502
e420f0c0
HE		 503struct mlx5_eqe_page_fault {
504 __be32 bytes_committed;
505 union {
506 struct {
507 u16 reserved1;
508 __be16 wqe_index;
509 u16 reserved2;
510 __be16 packet_length;
511 u8 reserved3[12];
512 } __packed wqe;
513 struct {
514 __be32 r_key;
515 u16 reserved1;
516 __be16 packet_length;
517 __be32 rdma_op_len;
518 __be64 rdma_va;
519 } __packed rdma;
520 } __packed;
521 __be32 flags_qpn;
522} __packed;
523
073bb189
SM		 524struct mlx5_eqe_vport_change {
525 u8 rsvd0[2];
526 __be16 vport_num;
527 __be32 rsvd1[6];
528} __packed;
529
e126ba97
EC		 530union ev_data {
531 __be32 raw[7];
532 struct mlx5_eqe_cmd cmd;
533 struct mlx5_eqe_comp comp;
534 struct mlx5_eqe_qp_srq qp_srq;
535 struct mlx5_eqe_cq_err cq_err;
e126ba97
EC		 536 struct mlx5_eqe_port_state port;
537 struct mlx5_eqe_gpio gpio;
538 struct mlx5_eqe_congestion cong;
539 struct mlx5_eqe_stall_vl stall_vl;
540 struct mlx5_eqe_page_req req_pages;
e420f0c0 541 struct mlx5_eqe_page_fault page_fault;
073bb189 542 struct mlx5_eqe_vport_change vport_change;
e126ba97
EC		 543} __packed;
544
545struct mlx5_eqe {
546 u8 rsvd0;
547 u8 type;
548 u8 rsvd1;
549 u8 sub_type;
550 __be32 rsvd2[7];
551 union ev_data data;
552 __be16 rsvd3;
553 u8 signature;
554 u8 owner;
555} __packed;
556
557struct mlx5_cmd_prot_block {
558 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
559 u8 rsvd0[48];
560 __be64 next;
561 __be32 block_num;
562 u8 rsvd1;
563 u8 token;
564 u8 ctrl_sig;
565 u8 sig;
566};
567
e281682b
SM		 568enum {
569 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
570};
571
e126ba97
EC		 572struct mlx5_err_cqe {
573 u8 rsvd0[32];
574 __be32 srqn;
575 u8 rsvd1[18];
576 u8 vendor_err_synd;
577 u8 syndrome;
578 __be32 s_wqe_opcode_qpn;
579 __be16 wqe_counter;
580 u8 signature;
581 u8 op_own;
582};
583
584struct mlx5_cqe64 {
e281682b
SM		 585 u8 rsvd0[4];
586 u8 lro_tcppsh_abort_dupack;
587 u8 lro_min_ttl;
588 __be16 lro_tcp_win;
589 __be32 lro_ack_seq_num;
590 __be32 rss_hash_result;
591 u8 rss_hash_type;
e126ba97 592 u8 ml_path;
e281682b
SM		 593 u8 rsvd20[2];
594 __be16 check_sum;
e126ba97
EC		 595 __be16 slid;
596 __be32 flags_rqpn;
e281682b
SM		 597 u8 hds_ip_ext;
598 u8 l4_hdr_type_etc;
599 __be16 vlan_info;
600 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
e126ba97
EC		 601 __be32 imm_inval_pkey;
602 u8 rsvd40[4];
603 __be32 byte_cnt;
604 __be64 timestamp;
605 __be32 sop_drop_qpn;
606 __be16 wqe_counter;
607 u8 signature;
608 u8 op_own;
609};
610
e281682b
SM		 611static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
612{
613 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
614}
615
616static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
617{
618 return (cqe->l4_hdr_type_etc >> 4) & 0x7;
619}
620
621static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
622{
623 return !!(cqe->l4_hdr_type_etc & 0x1);
624}
625
626enum {
627 CQE_L4_HDR_TYPE_NONE = 0x0,
628 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
629 CQE_L4_HDR_TYPE_UDP = 0x2,
630 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
631 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
632};
633
634enum {
635 CQE_RSS_HTYPE_IP = 0x3 << 6,
636 CQE_RSS_HTYPE_L4 = 0x3 << 2,
637};
638
639enum {
640 CQE_L2_OK = 1 << 0,
641 CQE_L3_OK = 1 << 1,
642 CQE_L4_OK = 1 << 2,
643};
644
d5436ba0
SG		 645struct mlx5_sig_err_cqe {
646 u8 rsvd0[16];
647 __be32 expected_trans_sig;
648 __be32 actual_trans_sig;
649 __be32 expected_reftag;
650 __be32 actual_reftag;
651 __be16 syndrome;
652 u8 rsvd22[2];
653 __be32 mkey;
654 __be64 err_offset;
655 u8 rsvd30[8];
656 __be32 qpn;
657 u8 rsvd38[2];
658 u8 signature;
659 u8 op_own;
660};
661
e126ba97
EC		 662struct mlx5_wqe_srq_next_seg {
663 u8 rsvd0[2];
664 __be16 next_wqe_index;
665 u8 signature;
666 u8 rsvd1[11];
667};
668
669union mlx5_ext_cqe {
670 struct ib_grh grh;
671 u8 inl[64];
672};
673
674struct mlx5_cqe128 {
675 union mlx5_ext_cqe inl_grh;
676 struct mlx5_cqe64 cqe64;
677};
678
679struct mlx5_srq_ctx {
680 u8 state_log_sz;
681 u8 rsvd0[3];
682 __be32 flags_xrcd;
683 __be32 pgoff_cqn;
684 u8 rsvd1[4];
685 u8 log_pg_sz;
686 u8 rsvd2[7];
687 __be32 pd;
688 __be16 lwm;
689 __be16 wqe_cnt;
690 u8 rsvd3[8];
691 __be64 db_record;
692};
693
694struct mlx5_create_srq_mbox_in {
695 struct mlx5_inbox_hdr hdr;
696 __be32 input_srqn;
697 u8 rsvd0[4];
698 struct mlx5_srq_ctx ctx;
699 u8 rsvd1[208];
700 __be64 pas[0];
701};
702
703struct mlx5_create_srq_mbox_out {
704 struct mlx5_outbox_hdr hdr;
705 __be32 srqn;
706 u8 rsvd[4];
707};
708
709struct mlx5_destroy_srq_mbox_in {
710 struct mlx5_inbox_hdr hdr;
711 __be32 srqn;
712 u8 rsvd[4];
713};
714
715struct mlx5_destroy_srq_mbox_out {
716 struct mlx5_outbox_hdr hdr;
717 u8 rsvd[8];
718};
719
720struct mlx5_query_srq_mbox_in {
721 struct mlx5_inbox_hdr hdr;
722 __be32 srqn;
723 u8 rsvd0[4];
724};
725
726struct mlx5_query_srq_mbox_out {
727 struct mlx5_outbox_hdr hdr;
728 u8 rsvd0[8];
729 struct mlx5_srq_ctx ctx;
730 u8 rsvd1[32];
731 __be64 pas[0];
732};
733
734struct mlx5_arm_srq_mbox_in {
735 struct mlx5_inbox_hdr hdr;
736 __be32 srqn;
737 __be16 rsvd;
738 __be16 lwm;
739};
740
741struct mlx5_arm_srq_mbox_out {
742 struct mlx5_outbox_hdr hdr;
743 u8 rsvd[8];
744};
745
746struct mlx5_cq_context {
747 u8 status;
748 u8 cqe_sz_flags;
749 u8 st;
750 u8 rsvd3;
751 u8 rsvd4[6];
752 __be16 page_offset;
753 __be32 log_sz_usr_page;
754 __be16 cq_period;
755 __be16 cq_max_count;
756 __be16 rsvd20;
757 __be16 c_eqn;
758 u8 log_pg_sz;
759 u8 rsvd25[7];
760 __be32 last_notified_index;
761 __be32 solicit_producer_index;
762 __be32 consumer_counter;
763 __be32 producer_counter;
764 u8 rsvd48[8];
765 __be64 db_record_addr;
766};
767
768struct mlx5_create_cq_mbox_in {
769 struct mlx5_inbox_hdr hdr;
770 __be32 input_cqn;
771 u8 rsvdx[4];
772 struct mlx5_cq_context ctx;
773 u8 rsvd6[192];
774 __be64 pas[0];
775};
776
777struct mlx5_create_cq_mbox_out {
778 struct mlx5_outbox_hdr hdr;
779 __be32 cqn;
780 u8 rsvd0[4];
781};
782
783struct mlx5_destroy_cq_mbox_in {
784 struct mlx5_inbox_hdr hdr;
785 __be32 cqn;
786 u8 rsvd0[4];
787};
788
789struct mlx5_destroy_cq_mbox_out {
790 struct mlx5_outbox_hdr hdr;
791 u8 rsvd0[8];
792};
793
794struct mlx5_query_cq_mbox_in {
795 struct mlx5_inbox_hdr hdr;
796 __be32 cqn;
797 u8 rsvd0[4];
798};
799
800struct mlx5_query_cq_mbox_out {
801 struct mlx5_outbox_hdr hdr;
802 u8 rsvd0[8];
803 struct mlx5_cq_context ctx;
804 u8 rsvd6[16];
805 __be64 pas[0];
806};
807
3bdb31f6
EC		 808struct mlx5_modify_cq_mbox_in {
809 struct mlx5_inbox_hdr hdr;
810 __be32 cqn;
811 __be32 field_select;
812 struct mlx5_cq_context ctx;
813 u8 rsvd[192];
814 __be64 pas[0];
815};
816
817struct mlx5_modify_cq_mbox_out {
818 struct mlx5_outbox_hdr hdr;
bde51583 819 u8 rsvd[8];
3bdb31f6
EC		 820};
821
cd23b14b
EC		 822struct mlx5_enable_hca_mbox_in {
823 struct mlx5_inbox_hdr hdr;
824 u8 rsvd[8];
825};
826
827struct mlx5_enable_hca_mbox_out {
828 struct mlx5_outbox_hdr hdr;
829 u8 rsvd[8];
830};
831
832struct mlx5_disable_hca_mbox_in {
833 struct mlx5_inbox_hdr hdr;
834 u8 rsvd[8];
835};
836
837struct mlx5_disable_hca_mbox_out {
838 struct mlx5_outbox_hdr hdr;
839 u8 rsvd[8];
840};
841
e126ba97
EC		 842struct mlx5_eq_context {
843 u8 status;
844 u8 ec_oi;
845 u8 st;
846 u8 rsvd2[7];
847 __be16 page_pffset;
848 __be32 log_sz_usr_page;
849 u8 rsvd3[7];
850 u8 intr;
851 u8 log_page_size;
852 u8 rsvd4[15];
853 __be32 consumer_counter;
854 __be32 produser_counter;
855 u8 rsvd5[16];
856};
857
858struct mlx5_create_eq_mbox_in {
859 struct mlx5_inbox_hdr hdr;
860 u8 rsvd0[3];
861 u8 input_eqn;
862 u8 rsvd1[4];
863 struct mlx5_eq_context ctx;
864 u8 rsvd2[8];
865 __be64 events_mask;
866 u8 rsvd3[176];
867 __be64 pas[0];
868};
869
870struct mlx5_create_eq_mbox_out {
871 struct mlx5_outbox_hdr hdr;
872 u8 rsvd0[3];
873 u8 eq_number;
874 u8 rsvd1[4];
875};
876
877struct mlx5_destroy_eq_mbox_in {
878 struct mlx5_inbox_hdr hdr;
879 u8 rsvd0[3];
880 u8 eqn;
881 u8 rsvd1[4];
882};
883
884struct mlx5_destroy_eq_mbox_out {
885 struct mlx5_outbox_hdr hdr;
886 u8 rsvd[8];
887};
888
889struct mlx5_map_eq_mbox_in {
890 struct mlx5_inbox_hdr hdr;
891 __be64 mask;
892 u8 mu;
893 u8 rsvd0[2];
894 u8 eqn;
895 u8 rsvd1[24];
896};
897
898struct mlx5_map_eq_mbox_out {
899 struct mlx5_outbox_hdr hdr;
900 u8 rsvd[8];
901};
902
903struct mlx5_query_eq_mbox_in {
904 struct mlx5_inbox_hdr hdr;
905 u8 rsvd0[3];
906 u8 eqn;
907 u8 rsvd1[4];
908};
909
910struct mlx5_query_eq_mbox_out {
911 struct mlx5_outbox_hdr hdr;
912 u8 rsvd[8];
913 struct mlx5_eq_context ctx;
914};
915
968e78dd
HE		 916enum {
917 MLX5_MKEY_STATUS_FREE = 1 << 6,
918};
919
e126ba97
EC		 920struct mlx5_mkey_seg {
921 /* This is a two bit field occupying bits 31-30.
922 * bit 31 is always 0,
923 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
924 */
925 u8 status;
926 u8 pcie_control;
927 u8 flags;
928 u8 version;
929 __be32 qpn_mkey7_0;
930 u8 rsvd1[4];
931 __be32 flags_pd;
932 __be64 start_addr;
933 __be64 len;
934 __be32 bsfs_octo_size;
935 u8 rsvd2[16];
936 __be32 xlt_oct_size;
937 u8 rsvd3[3];
938 u8 log2_page_size;
939 u8 rsvd4[4];
940};
941
942struct mlx5_query_special_ctxs_mbox_in {
943 struct mlx5_inbox_hdr hdr;
944 u8 rsvd[8];
945};
946
947struct mlx5_query_special_ctxs_mbox_out {
948 struct mlx5_outbox_hdr hdr;
949 __be32 dump_fill_mkey;
950 __be32 reserved_lkey;
951};
952
953struct mlx5_create_mkey_mbox_in {
954 struct mlx5_inbox_hdr hdr;
955 __be32 input_mkey_index;
e420f0c0 956 __be32 flags;
e126ba97
EC		 957 struct mlx5_mkey_seg seg;
958 u8 rsvd1[16];
959 __be32 xlat_oct_act_size;
8c8a4914
EC		 960 __be32 rsvd2;
961 u8 rsvd3[168];
e126ba97
EC		 962 __be64 pas[0];
963};
964
965struct mlx5_create_mkey_mbox_out {
966 struct mlx5_outbox_hdr hdr;
967 __be32 mkey;
968 u8 rsvd[4];
969};
970
971struct mlx5_destroy_mkey_mbox_in {
972 struct mlx5_inbox_hdr hdr;
973 __be32 mkey;
974 u8 rsvd[4];
975};
976
977struct mlx5_destroy_mkey_mbox_out {
978 struct mlx5_outbox_hdr hdr;
979 u8 rsvd[8];
980};
981
982struct mlx5_query_mkey_mbox_in {
983 struct mlx5_inbox_hdr hdr;
984 __be32 mkey;
985};
986
987struct mlx5_query_mkey_mbox_out {
988 struct mlx5_outbox_hdr hdr;
989 __be64 pas[0];
990};
991
992struct mlx5_modify_mkey_mbox_in {
993 struct mlx5_inbox_hdr hdr;
994 __be32 mkey;
995 __be64 pas[0];
996};
997
998struct mlx5_modify_mkey_mbox_out {
999 struct mlx5_outbox_hdr hdr;
3bdb31f6 1000 u8 rsvd[8];
e126ba97
EC		 1001};
1002
1003struct mlx5_dump_mkey_mbox_in {
1004 struct mlx5_inbox_hdr hdr;
1005};
1006
1007struct mlx5_dump_mkey_mbox_out {
1008 struct mlx5_outbox_hdr hdr;
1009 __be32 mkey;
1010};
1011
1012struct mlx5_mad_ifc_mbox_in {
1013 struct mlx5_inbox_hdr hdr;
1014 __be16 remote_lid;
1015 u8 rsvd0;
1016 u8 port;
1017 u8 rsvd1[4];
1018 u8 data[256];
1019};
1020
1021struct mlx5_mad_ifc_mbox_out {
1022 struct mlx5_outbox_hdr hdr;
1023 u8 rsvd[8];
1024 u8 data[256];
1025};
1026
1027struct mlx5_access_reg_mbox_in {
1028 struct mlx5_inbox_hdr hdr;
1029 u8 rsvd0[2];
1030 __be16 register_id;
1031 __be32 arg;
1032 __be32 data[0];
1033};
1034
1035struct mlx5_access_reg_mbox_out {
1036 struct mlx5_outbox_hdr hdr;
1037 u8 rsvd[8];
1038 __be32 data[0];
1039};
1040
1041#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
1042
1043enum {
1044 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
1045};
1046
3121e3c4
SG		 1047struct mlx5_allocate_psv_in {
1048 struct mlx5_inbox_hdr hdr;
1049 __be32 npsv_pd;
1050 __be32 rsvd_psv0;
1051};
1052
1053struct mlx5_allocate_psv_out {
1054 struct mlx5_outbox_hdr hdr;
1055 u8 rsvd[8];
1056 __be32 psv_idx[4];
1057};
1058
1059struct mlx5_destroy_psv_in {
1060 struct mlx5_inbox_hdr hdr;
1061 __be32 psv_number;
1062 u8 rsvd[4];
1063};
1064
1065struct mlx5_destroy_psv_out {
1066 struct mlx5_outbox_hdr hdr;
1067 u8 rsvd[8];
1068};
1069
e281682b
SM		 1070#define MLX5_CMD_OP_MAX 0x920
1071
1072enum {
1073 VPORT_STATE_DOWN = 0x0,
1074 VPORT_STATE_UP = 0x1,
1075};
1076
81848731
SM		 1077enum {
1078 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
1079 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
1080 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
1081};
1082
e281682b
SM		 1083enum {
1084 MLX5_L3_PROT_TYPE_IPV4 = 0,
1085 MLX5_L3_PROT_TYPE_IPV6 = 1,
1086};
1087
1088enum {
1089 MLX5_L4_PROT_TYPE_TCP = 0,
1090 MLX5_L4_PROT_TYPE_UDP = 1,
1091};
1092
1093enum {
1094 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
1095 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
1096 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
1097 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
1098 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
1099};
1100
1101enum {
1102 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
1103 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
1104 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1105
1106};
1107
1108enum {
1109 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
1110 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
1111};
1112
1113enum {
1114 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
1115 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
1116 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
1117};
1118
e16aea27
SM		 1119enum mlx5_list_type {
1120 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
1121 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
1122 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
1123};
1124
e281682b
SM		 1125enum {
1126 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1127 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
1128};
1129
938fe83c
SM		 1130/* MLX5 DEV CAPs */
1131
1132/* TODO: EAT.ME */
1133enum mlx5_cap_mode {
1134 HCA_CAP_OPMOD_GET_MAX = 0,
1135 HCA_CAP_OPMOD_GET_CUR = 1,
1136};
1137
1138enum mlx5_cap_type {
1139 MLX5_CAP_GENERAL = 0,
1140 MLX5_CAP_ETHERNET_OFFLOADS,
1141 MLX5_CAP_ODP,
1142 MLX5_CAP_ATOMIC,
1143 MLX5_CAP_ROCE,
1144 MLX5_CAP_IPOIB_OFFLOADS,
1145 MLX5_CAP_EOIB_OFFLOADS,
1146 MLX5_CAP_FLOW_TABLE,
495716b1 1147 MLX5_CAP_ESWITCH_FLOW_TABLE,
938fe83c
SM		 1148 /* NUM OF CAP Types */
1149 MLX5_CAP_NUM
1150};
1151
1152/* GET Dev Caps macros */
1153#define MLX5_CAP_GEN(mdev, cap) \
1154 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1155
1156#define MLX5_CAP_GEN_MAX(mdev, cap) \
1157 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
1158
1159#define MLX5_CAP_ETH(mdev, cap) \
1160 MLX5_GET(per_protocol_networking_offload_caps,\
1161 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1162
1163#define MLX5_CAP_ETH_MAX(mdev, cap) \
1164 MLX5_GET(per_protocol_networking_offload_caps,\
1165 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1166
1167#define MLX5_CAP_ROCE(mdev, cap) \
1168 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1169
1170#define MLX5_CAP_ROCE_MAX(mdev, cap) \
1171 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1172
1173#define MLX5_CAP_ATOMIC(mdev, cap) \
1174 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1175
1176#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1177 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1178
1179#define MLX5_CAP_FLOWTABLE(mdev, cap) \
1180 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1181
1182#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1183 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1184
495716b1
SM		 1185#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1186 MLX5_GET(flow_table_eswitch_cap, \
1187 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1188
1189#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1190 MLX5_GET(flow_table_eswitch_cap, \
1191 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1192
1193#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1194 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1195
1196#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1197 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1198
938fe83c
SM		 1199#define MLX5_CAP_ODP(mdev, cap)\
1200 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1201
f62b8bb8
AV		 1202enum {
1203 MLX5_CMD_STAT_OK = 0x0,
1204 MLX5_CMD_STAT_INT_ERR = 0x1,
1205 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1206 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1207 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1208 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1209 MLX5_CMD_STAT_RES_BUSY = 0x6,
1210 MLX5_CMD_STAT_LIM_ERR = 0x8,
1211 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1212 MLX5_CMD_STAT_IX_ERR = 0xa,
1213 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1214 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1215 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1216 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1217 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1218 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1219};
1220
efea389d
GP		 1221enum {
1222 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1223 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1224 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1225 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1226 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1227 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1228 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11
1229};
1230
707c4602
MD		 1231static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1232{
1233 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1234 return 0;
1235 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1236}
1237
e126ba97 1238#endif /* MLX5_DEVICE_H */
Linux 6.x block layer and io_uring tree(s)