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IB/mlx5: Remove per-MR pas and dma pointers
[linux-2.6-block.git] / include / linux / mlx5 / device.h
CommitLineData
e126ba97
EC		 1/*
2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
38
39#if defined(__LITTLE_ENDIAN)
40#define MLX5_SET_HOST_ENDIANNESS 0
41#elif defined(__BIG_ENDIAN)
42#define MLX5_SET_HOST_ENDIANNESS 0x80
43#else
44#error Host endianness not defined
45#endif
46
d29b796a
EC		 47/* helper macros */
48#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
49#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
50#define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
51#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
52#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
53#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
54#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
55#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
56#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
57
58#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
59#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
60#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
61#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
62#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
63
64/* insert a value to a struct */
65#define MLX5_SET(typ, p, fld, v) do { \
66 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
67 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
68 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
69 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
70 << __mlx5_dw_bit_off(typ, fld))); \
71} while (0)
72
73#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
74__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
75__mlx5_mask(typ, fld))
76
77#define MLX5_GET_PR(typ, p, fld) ({ \
78 u32 ___t = MLX5_GET(typ, p, fld); \
79 pr_debug(#fld " = 0x%x\n", ___t); \
80 ___t; \
81})
82
83#define MLX5_SET64(typ, p, fld, v) do { \
84 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
85 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
86 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
87} while (0)
88
89#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
90
e126ba97
EC		 91enum {
92 MLX5_MAX_COMMANDS = 32,
93 MLX5_CMD_DATA_BLOCK_SIZE = 512,
94 MLX5_PCI_CMD_XPORT = 7,
3121e3c4
SG		 95 MLX5_MKEY_BSF_OCTO_SIZE = 4,
96 MLX5_MAX_PSVS = 4,
e126ba97
EC		 97};
98
99enum {
100 MLX5_EXTENDED_UD_AV = 0x80000000,
101};
102
103enum {
104 MLX5_CQ_STATE_ARMED = 9,
105 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
106 MLX5_CQ_STATE_FIRED = 0xa,
107};
108
109enum {
110 MLX5_STAT_RATE_OFFSET = 5,
111};
112
113enum {
114 MLX5_INLINE_SEG = 0x80000000,
115};
116
c7a08ac7
EC		 117enum {
118 MLX5_MIN_PKEY_TABLE_SIZE = 128,
119 MLX5_MAX_LOG_PKEY_TABLE = 5,
120};
121
e126ba97
EC		 122enum {
123 MLX5_PERM_LOCAL_READ = 1 << 2,
124 MLX5_PERM_LOCAL_WRITE = 1 << 3,
125 MLX5_PERM_REMOTE_READ = 1 << 4,
126 MLX5_PERM_REMOTE_WRITE = 1 << 5,
127 MLX5_PERM_ATOMIC = 1 << 6,
128 MLX5_PERM_UMR_EN = 1 << 7,
129};
130
131enum {
132 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
133 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
134 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
135 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
136 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
137};
138
139enum {
140 MLX5_ACCESS_MODE_PA = 0,
141 MLX5_ACCESS_MODE_MTT = 1,
142 MLX5_ACCESS_MODE_KLM = 2
143};
144
145enum {
146 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
147 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
148 MLX5_MKEY_BSF_EN = 1 << 30,
149 MLX5_MKEY_LEN64 = 1 << 31,
150};
151
152enum {
153 MLX5_EN_RD = (u64)1,
154 MLX5_EN_WR = (u64)2
155};
156
157enum {
c1be5232
EC		 158 MLX5_BF_REGS_PER_PAGE = 4,
159 MLX5_MAX_UAR_PAGES = 1 << 8,
160 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
161 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
e126ba97
EC		 162};
163
164enum {
165 MLX5_MKEY_MASK_LEN = 1ull << 0,
166 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
167 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
168 MLX5_MKEY_MASK_PD = 1ull << 7,
169 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
d5436ba0 170 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
e126ba97
EC		 171 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
172 MLX5_MKEY_MASK_KEY = 1ull << 13,
173 MLX5_MKEY_MASK_QPN = 1ull << 14,
174 MLX5_MKEY_MASK_LR = 1ull << 17,
175 MLX5_MKEY_MASK_LW = 1ull << 18,
176 MLX5_MKEY_MASK_RR = 1ull << 19,
177 MLX5_MKEY_MASK_RW = 1ull << 20,
178 MLX5_MKEY_MASK_A = 1ull << 21,
179 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
180 MLX5_MKEY_MASK_FREE = 1ull << 29,
181};
182
183enum mlx5_event {
184 MLX5_EVENT_TYPE_COMP = 0x0,
185
186 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
187 MLX5_EVENT_TYPE_COMM_EST = 0x02,
188 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
189 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
190 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
191
192 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
193 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
194 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
195 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
196 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
197 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
198
199 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
200 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
201 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
202 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
203
204 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
205 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
206
207 MLX5_EVENT_TYPE_CMD = 0x0a,
208 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
209};
210
211enum {
212 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
213 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
214 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
215 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
216 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
217 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
218 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
219};
220
221enum {
e126ba97 222 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
e126ba97
EC		 223 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
224 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
225 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
226 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
f360d88a 227 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
3bdb31f6 228 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
bde51583 229 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
c7a08ac7 230 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
e126ba97 231 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
c1868b82 232 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
e126ba97
EC		 233};
234
235enum {
236 MLX5_OPCODE_NOP = 0x00,
237 MLX5_OPCODE_SEND_INVAL = 0x01,
238 MLX5_OPCODE_RDMA_WRITE = 0x08,
239 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
240 MLX5_OPCODE_SEND = 0x0a,
241 MLX5_OPCODE_SEND_IMM = 0x0b,
242 MLX5_OPCODE_RDMA_READ = 0x10,
243 MLX5_OPCODE_ATOMIC_CS = 0x11,
244 MLX5_OPCODE_ATOMIC_FA = 0x12,
245 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
246 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
247 MLX5_OPCODE_BIND_MW = 0x18,
248 MLX5_OPCODE_CONFIG_CMD = 0x1f,
249
250 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
251 MLX5_RECV_OPCODE_SEND = 0x01,
252 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
253 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
254
255 MLX5_CQE_OPCODE_ERROR = 0x1e,
256 MLX5_CQE_OPCODE_RESIZE = 0x16,
257
258 MLX5_OPCODE_SET_PSV = 0x20,
259 MLX5_OPCODE_GET_PSV = 0x21,
260 MLX5_OPCODE_CHECK_PSV = 0x22,
261 MLX5_OPCODE_RGET_PSV = 0x26,
262 MLX5_OPCODE_RCHECK_PSV = 0x27,
263
264 MLX5_OPCODE_UMR = 0x25,
265
266};
267
268enum {
269 MLX5_SET_PORT_RESET_QKEY = 0,
270 MLX5_SET_PORT_GUID0 = 16,
271 MLX5_SET_PORT_NODE_GUID = 17,
272 MLX5_SET_PORT_SYS_GUID = 18,
273 MLX5_SET_PORT_GID_TABLE = 19,
274 MLX5_SET_PORT_PKEY_TABLE = 20,
275};
276
277enum {
278 MLX5_MAX_PAGE_SHIFT = 31
279};
280
1b77d2bd 281enum {
05bdb2ab
EC		 282 MLX5_ADAPTER_PAGE_SHIFT = 12,
283 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
1b77d2bd
EC		 284};
285
87b8de49 286enum {
87b8de49
EC		 287 MLX5_CAP_OFF_CMDIF_CSUM = 46,
288};
289
c7a08ac7
EC		 290enum {
291 HCA_CAP_OPMOD_GET_MAX = 0,
292 HCA_CAP_OPMOD_GET_CUR = 1,
293};
294
e126ba97
EC		 295struct mlx5_inbox_hdr {
296 __be16 opcode;
297 u8 rsvd[4];
298 __be16 opmod;
299};
300
301struct mlx5_outbox_hdr {
302 u8 status;
303 u8 rsvd[3];
304 __be32 syndrome;
305};
306
307struct mlx5_cmd_query_adapter_mbox_in {
308 struct mlx5_inbox_hdr hdr;
309 u8 rsvd[8];
310};
311
312struct mlx5_cmd_query_adapter_mbox_out {
313 struct mlx5_outbox_hdr hdr;
314 u8 rsvd0[24];
315 u8 intapin;
316 u8 rsvd1[13];
317 __be16 vsd_vendor_id;
318 u8 vsd[208];
319 u8 vsd_psid[16];
320};
321
e126ba97
EC		 322struct mlx5_cmd_init_hca_mbox_in {
323 struct mlx5_inbox_hdr hdr;
324 u8 rsvd0[2];
325 __be16 profile;
326 u8 rsvd1[4];
327};
328
329struct mlx5_cmd_init_hca_mbox_out {
330 struct mlx5_outbox_hdr hdr;
331 u8 rsvd[8];
332};
333
334struct mlx5_cmd_teardown_hca_mbox_in {
335 struct mlx5_inbox_hdr hdr;
336 u8 rsvd0[2];
337 __be16 profile;
338 u8 rsvd1[4];
339};
340
341struct mlx5_cmd_teardown_hca_mbox_out {
342 struct mlx5_outbox_hdr hdr;
343 u8 rsvd[8];
344};
345
346struct mlx5_cmd_layout {
347 u8 type;
348 u8 rsvd0[3];
349 __be32 inlen;
350 __be64 in_ptr;
351 __be32 in[4];
352 __be32 out[4];
353 __be64 out_ptr;
354 __be32 outlen;
355 u8 token;
356 u8 sig;
357 u8 rsvd1;
358 u8 status_own;
359};
360
361
362struct health_buffer {
363 __be32 assert_var[5];
364 __be32 rsvd0[3];
365 __be32 assert_exit_ptr;
366 __be32 assert_callra;
367 __be32 rsvd1[2];
368 __be32 fw_ver;
369 __be32 hw_id;
370 __be32 rsvd2;
371 u8 irisc_index;
372 u8 synd;
373 __be16 ext_sync;
374};
375
376struct mlx5_init_seg {
377 __be32 fw_rev;
378 __be32 cmdif_rev_fw_sub;
379 __be32 rsvd0[2];
380 __be32 cmdq_addr_h;
381 __be32 cmdq_addr_l_sz;
382 __be32 cmd_dbell;
383 __be32 rsvd1[121];
384 struct health_buffer health;
385 __be32 rsvd2[884];
386 __be32 health_counter;
2f6daec1 387 __be32 rsvd3[1019];
e126ba97
EC		 388 __be64 ieee1588_clk;
389 __be32 ieee1588_clk_type;
390 __be32 clr_intx;
391};
392
393struct mlx5_eqe_comp {
394 __be32 reserved[6];
395 __be32 cqn;
396};
397
398struct mlx5_eqe_qp_srq {
399 __be32 reserved[6];
400 __be32 qp_srq_n;
401};
402
403struct mlx5_eqe_cq_err {
404 __be32 cqn;
405 u8 reserved1[7];
406 u8 syndrome;
407};
408
e126ba97
EC		 409struct mlx5_eqe_port_state {
410 u8 reserved0[8];
411 u8 port;
412};
413
414struct mlx5_eqe_gpio {
415 __be32 reserved0[2];
416 __be64 gpio_event;
417};
418
419struct mlx5_eqe_congestion {
420 u8 type;
421 u8 rsvd0;
422 u8 congestion_level;
423};
424
425struct mlx5_eqe_stall_vl {
426 u8 rsvd0[3];
427 u8 port_vl;
428};
429
430struct mlx5_eqe_cmd {
431 __be32 vector;
432 __be32 rsvd[6];
433};
434
435struct mlx5_eqe_page_req {
436 u8 rsvd0[2];
437 __be16 func_id;
0a324f31
ML		 438 __be32 num_pages;
439 __be32 rsvd1[5];
e126ba97
EC		 440};
441
442union ev_data {
443 __be32 raw[7];
444 struct mlx5_eqe_cmd cmd;
445 struct mlx5_eqe_comp comp;
446 struct mlx5_eqe_qp_srq qp_srq;
447 struct mlx5_eqe_cq_err cq_err;
e126ba97
EC		 448 struct mlx5_eqe_port_state port;
449 struct mlx5_eqe_gpio gpio;
450 struct mlx5_eqe_congestion cong;
451 struct mlx5_eqe_stall_vl stall_vl;
452 struct mlx5_eqe_page_req req_pages;
453} __packed;
454
455struct mlx5_eqe {
456 u8 rsvd0;
457 u8 type;
458 u8 rsvd1;
459 u8 sub_type;
460 __be32 rsvd2[7];
461 union ev_data data;
462 __be16 rsvd3;
463 u8 signature;
464 u8 owner;
465} __packed;
466
467struct mlx5_cmd_prot_block {
468 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
469 u8 rsvd0[48];
470 __be64 next;
471 __be32 block_num;
472 u8 rsvd1;
473 u8 token;
474 u8 ctrl_sig;
475 u8 sig;
476};
477
478struct mlx5_err_cqe {
479 u8 rsvd0[32];
480 __be32 srqn;
481 u8 rsvd1[18];
482 u8 vendor_err_synd;
483 u8 syndrome;
484 __be32 s_wqe_opcode_qpn;
485 __be16 wqe_counter;
486 u8 signature;
487 u8 op_own;
488};
489
490struct mlx5_cqe64 {
491 u8 rsvd0[17];
492 u8 ml_path;
493 u8 rsvd20[4];
494 __be16 slid;
495 __be32 flags_rqpn;
496 u8 rsvd28[4];
497 __be32 srqn;
498 __be32 imm_inval_pkey;
499 u8 rsvd40[4];
500 __be32 byte_cnt;
501 __be64 timestamp;
502 __be32 sop_drop_qpn;
503 __be16 wqe_counter;
504 u8 signature;
505 u8 op_own;
506};
507
d5436ba0
SG		 508struct mlx5_sig_err_cqe {
509 u8 rsvd0[16];
510 __be32 expected_trans_sig;
511 __be32 actual_trans_sig;
512 __be32 expected_reftag;
513 __be32 actual_reftag;
514 __be16 syndrome;
515 u8 rsvd22[2];
516 __be32 mkey;
517 __be64 err_offset;
518 u8 rsvd30[8];
519 __be32 qpn;
520 u8 rsvd38[2];
521 u8 signature;
522 u8 op_own;
523};
524
e126ba97
EC		 525struct mlx5_wqe_srq_next_seg {
526 u8 rsvd0[2];
527 __be16 next_wqe_index;
528 u8 signature;
529 u8 rsvd1[11];
530};
531
532union mlx5_ext_cqe {
533 struct ib_grh grh;
534 u8 inl[64];
535};
536
537struct mlx5_cqe128 {
538 union mlx5_ext_cqe inl_grh;
539 struct mlx5_cqe64 cqe64;
540};
541
542struct mlx5_srq_ctx {
543 u8 state_log_sz;
544 u8 rsvd0[3];
545 __be32 flags_xrcd;
546 __be32 pgoff_cqn;
547 u8 rsvd1[4];
548 u8 log_pg_sz;
549 u8 rsvd2[7];
550 __be32 pd;
551 __be16 lwm;
552 __be16 wqe_cnt;
553 u8 rsvd3[8];
554 __be64 db_record;
555};
556
557struct mlx5_create_srq_mbox_in {
558 struct mlx5_inbox_hdr hdr;
559 __be32 input_srqn;
560 u8 rsvd0[4];
561 struct mlx5_srq_ctx ctx;
562 u8 rsvd1[208];
563 __be64 pas[0];
564};
565
566struct mlx5_create_srq_mbox_out {
567 struct mlx5_outbox_hdr hdr;
568 __be32 srqn;
569 u8 rsvd[4];
570};
571
572struct mlx5_destroy_srq_mbox_in {
573 struct mlx5_inbox_hdr hdr;
574 __be32 srqn;
575 u8 rsvd[4];
576};
577
578struct mlx5_destroy_srq_mbox_out {
579 struct mlx5_outbox_hdr hdr;
580 u8 rsvd[8];
581};
582
583struct mlx5_query_srq_mbox_in {
584 struct mlx5_inbox_hdr hdr;
585 __be32 srqn;
586 u8 rsvd0[4];
587};
588
589struct mlx5_query_srq_mbox_out {
590 struct mlx5_outbox_hdr hdr;
591 u8 rsvd0[8];
592 struct mlx5_srq_ctx ctx;
593 u8 rsvd1[32];
594 __be64 pas[0];
595};
596
597struct mlx5_arm_srq_mbox_in {
598 struct mlx5_inbox_hdr hdr;
599 __be32 srqn;
600 __be16 rsvd;
601 __be16 lwm;
602};
603
604struct mlx5_arm_srq_mbox_out {
605 struct mlx5_outbox_hdr hdr;
606 u8 rsvd[8];
607};
608
609struct mlx5_cq_context {
610 u8 status;
611 u8 cqe_sz_flags;
612 u8 st;
613 u8 rsvd3;
614 u8 rsvd4[6];
615 __be16 page_offset;
616 __be32 log_sz_usr_page;
617 __be16 cq_period;
618 __be16 cq_max_count;
619 __be16 rsvd20;
620 __be16 c_eqn;
621 u8 log_pg_sz;
622 u8 rsvd25[7];
623 __be32 last_notified_index;
624 __be32 solicit_producer_index;
625 __be32 consumer_counter;
626 __be32 producer_counter;
627 u8 rsvd48[8];
628 __be64 db_record_addr;
629};
630
631struct mlx5_create_cq_mbox_in {
632 struct mlx5_inbox_hdr hdr;
633 __be32 input_cqn;
634 u8 rsvdx[4];
635 struct mlx5_cq_context ctx;
636 u8 rsvd6[192];
637 __be64 pas[0];
638};
639
640struct mlx5_create_cq_mbox_out {
641 struct mlx5_outbox_hdr hdr;
642 __be32 cqn;
643 u8 rsvd0[4];
644};
645
646struct mlx5_destroy_cq_mbox_in {
647 struct mlx5_inbox_hdr hdr;
648 __be32 cqn;
649 u8 rsvd0[4];
650};
651
652struct mlx5_destroy_cq_mbox_out {
653 struct mlx5_outbox_hdr hdr;
654 u8 rsvd0[8];
655};
656
657struct mlx5_query_cq_mbox_in {
658 struct mlx5_inbox_hdr hdr;
659 __be32 cqn;
660 u8 rsvd0[4];
661};
662
663struct mlx5_query_cq_mbox_out {
664 struct mlx5_outbox_hdr hdr;
665 u8 rsvd0[8];
666 struct mlx5_cq_context ctx;
667 u8 rsvd6[16];
668 __be64 pas[0];
669};
670
3bdb31f6
EC		 671struct mlx5_modify_cq_mbox_in {
672 struct mlx5_inbox_hdr hdr;
673 __be32 cqn;
674 __be32 field_select;
675 struct mlx5_cq_context ctx;
676 u8 rsvd[192];
677 __be64 pas[0];
678};
679
680struct mlx5_modify_cq_mbox_out {
681 struct mlx5_outbox_hdr hdr;
bde51583 682 u8 rsvd[8];
3bdb31f6
EC		 683};
684
cd23b14b
EC		 685struct mlx5_enable_hca_mbox_in {
686 struct mlx5_inbox_hdr hdr;
687 u8 rsvd[8];
688};
689
690struct mlx5_enable_hca_mbox_out {
691 struct mlx5_outbox_hdr hdr;
692 u8 rsvd[8];
693};
694
695struct mlx5_disable_hca_mbox_in {
696 struct mlx5_inbox_hdr hdr;
697 u8 rsvd[8];
698};
699
700struct mlx5_disable_hca_mbox_out {
701 struct mlx5_outbox_hdr hdr;
702 u8 rsvd[8];
703};
704
e126ba97
EC		 705struct mlx5_eq_context {
706 u8 status;
707 u8 ec_oi;
708 u8 st;
709 u8 rsvd2[7];
710 __be16 page_pffset;
711 __be32 log_sz_usr_page;
712 u8 rsvd3[7];
713 u8 intr;
714 u8 log_page_size;
715 u8 rsvd4[15];
716 __be32 consumer_counter;
717 __be32 produser_counter;
718 u8 rsvd5[16];
719};
720
721struct mlx5_create_eq_mbox_in {
722 struct mlx5_inbox_hdr hdr;
723 u8 rsvd0[3];
724 u8 input_eqn;
725 u8 rsvd1[4];
726 struct mlx5_eq_context ctx;
727 u8 rsvd2[8];
728 __be64 events_mask;
729 u8 rsvd3[176];
730 __be64 pas[0];
731};
732
733struct mlx5_create_eq_mbox_out {
734 struct mlx5_outbox_hdr hdr;
735 u8 rsvd0[3];
736 u8 eq_number;
737 u8 rsvd1[4];
738};
739
740struct mlx5_destroy_eq_mbox_in {
741 struct mlx5_inbox_hdr hdr;
742 u8 rsvd0[3];
743 u8 eqn;
744 u8 rsvd1[4];
745};
746
747struct mlx5_destroy_eq_mbox_out {
748 struct mlx5_outbox_hdr hdr;
749 u8 rsvd[8];
750};
751
752struct mlx5_map_eq_mbox_in {
753 struct mlx5_inbox_hdr hdr;
754 __be64 mask;
755 u8 mu;
756 u8 rsvd0[2];
757 u8 eqn;
758 u8 rsvd1[24];
759};
760
761struct mlx5_map_eq_mbox_out {
762 struct mlx5_outbox_hdr hdr;
763 u8 rsvd[8];
764};
765
766struct mlx5_query_eq_mbox_in {
767 struct mlx5_inbox_hdr hdr;
768 u8 rsvd0[3];
769 u8 eqn;
770 u8 rsvd1[4];
771};
772
773struct mlx5_query_eq_mbox_out {
774 struct mlx5_outbox_hdr hdr;
775 u8 rsvd[8];
776 struct mlx5_eq_context ctx;
777};
778
779struct mlx5_mkey_seg {
780 /* This is a two bit field occupying bits 31-30.
781 * bit 31 is always 0,
782 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
783 */
784 u8 status;
785 u8 pcie_control;
786 u8 flags;
787 u8 version;
788 __be32 qpn_mkey7_0;
789 u8 rsvd1[4];
790 __be32 flags_pd;
791 __be64 start_addr;
792 __be64 len;
793 __be32 bsfs_octo_size;
794 u8 rsvd2[16];
795 __be32 xlt_oct_size;
796 u8 rsvd3[3];
797 u8 log2_page_size;
798 u8 rsvd4[4];
799};
800
801struct mlx5_query_special_ctxs_mbox_in {
802 struct mlx5_inbox_hdr hdr;
803 u8 rsvd[8];
804};
805
806struct mlx5_query_special_ctxs_mbox_out {
807 struct mlx5_outbox_hdr hdr;
808 __be32 dump_fill_mkey;
809 __be32 reserved_lkey;
810};
811
812struct mlx5_create_mkey_mbox_in {
813 struct mlx5_inbox_hdr hdr;
814 __be32 input_mkey_index;
815 u8 rsvd0[4];
816 struct mlx5_mkey_seg seg;
817 u8 rsvd1[16];
818 __be32 xlat_oct_act_size;
8c8a4914
EC		 819 __be32 rsvd2;
820 u8 rsvd3[168];
e126ba97
EC		 821 __be64 pas[0];
822};
823
824struct mlx5_create_mkey_mbox_out {
825 struct mlx5_outbox_hdr hdr;
826 __be32 mkey;
827 u8 rsvd[4];
828};
829
830struct mlx5_destroy_mkey_mbox_in {
831 struct mlx5_inbox_hdr hdr;
832 __be32 mkey;
833 u8 rsvd[4];
834};
835
836struct mlx5_destroy_mkey_mbox_out {
837 struct mlx5_outbox_hdr hdr;
838 u8 rsvd[8];
839};
840
841struct mlx5_query_mkey_mbox_in {
842 struct mlx5_inbox_hdr hdr;
843 __be32 mkey;
844};
845
846struct mlx5_query_mkey_mbox_out {
847 struct mlx5_outbox_hdr hdr;
848 __be64 pas[0];
849};
850
851struct mlx5_modify_mkey_mbox_in {
852 struct mlx5_inbox_hdr hdr;
853 __be32 mkey;
854 __be64 pas[0];
855};
856
857struct mlx5_modify_mkey_mbox_out {
858 struct mlx5_outbox_hdr hdr;
3bdb31f6 859 u8 rsvd[8];
e126ba97
EC		 860};
861
862struct mlx5_dump_mkey_mbox_in {
863 struct mlx5_inbox_hdr hdr;
864};
865
866struct mlx5_dump_mkey_mbox_out {
867 struct mlx5_outbox_hdr hdr;
868 __be32 mkey;
869};
870
871struct mlx5_mad_ifc_mbox_in {
872 struct mlx5_inbox_hdr hdr;
873 __be16 remote_lid;
874 u8 rsvd0;
875 u8 port;
876 u8 rsvd1[4];
877 u8 data[256];
878};
879
880struct mlx5_mad_ifc_mbox_out {
881 struct mlx5_outbox_hdr hdr;
882 u8 rsvd[8];
883 u8 data[256];
884};
885
886struct mlx5_access_reg_mbox_in {
887 struct mlx5_inbox_hdr hdr;
888 u8 rsvd0[2];
889 __be16 register_id;
890 __be32 arg;
891 __be32 data[0];
892};
893
894struct mlx5_access_reg_mbox_out {
895 struct mlx5_outbox_hdr hdr;
896 u8 rsvd[8];
897 __be32 data[0];
898};
899
900#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
901
902enum {
903 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
904};
905
3121e3c4
SG		 906struct mlx5_allocate_psv_in {
907 struct mlx5_inbox_hdr hdr;
908 __be32 npsv_pd;
909 __be32 rsvd_psv0;
910};
911
912struct mlx5_allocate_psv_out {
913 struct mlx5_outbox_hdr hdr;
914 u8 rsvd[8];
915 __be32 psv_idx[4];
916};
917
918struct mlx5_destroy_psv_in {
919 struct mlx5_inbox_hdr hdr;
920 __be32 psv_number;
921 u8 rsvd[4];
922};
923
924struct mlx5_destroy_psv_out {
925 struct mlx5_outbox_hdr hdr;
926 u8 rsvd[8];
927};
928
e126ba97 929#endif /* MLX5_DEVICE_H */
Linux 6.x block layer and io_uring tree(s)