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IB/mlx4: SR-IOV IB context objects and proxy/tunnel SQP support
[linux-2.6-block.git] / include / linux / mlx4 / device.h
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX4_DEVICE_H
34#define MLX4_DEVICE_H
35
36#include <linux/pci.h>
37#include <linux/completion.h>
38#include <linux/radix-tree.h>
d9236c3f 39#include <linux/cpu_rmap.h>
225c7b1f 40
60063497 41#include <linux/atomic.h>
225c7b1f 42
0b7ca5a9
YP		 43#define MAX_MSIX_P_PORT 17
44#define MAX_MSIX 64
45#define MSIX_LEGACY_SZ 4
46#define MIN_MSIX_P_PORT 5
47
225c7b1f
RD		 48enum {
49 MLX4_FLAG_MSI_X = 1 << 0,
5ae2a7a8 50 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
623ed84b
JM		 51 MLX4_FLAG_MASTER = 1 << 2,
52 MLX4_FLAG_SLAVE = 1 << 3,
53 MLX4_FLAG_SRIOV = 1 << 4,
225c7b1f
RD		 54};
55
56enum {
57 MLX4_MAX_PORTS = 2
58};
59
396f2feb
JM		 60/* base qkey for use in sriov tunnel-qp/proxy-qp communication.
61 * These qkeys must not be allowed for general use. This is a 64k range,
62 * and to test for violation, we use the mask (protect against future chg).
63 */
64#define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
65#define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
66
cd9281d8
JM		 67enum {
68 MLX4_BOARD_ID_LEN = 64
69};
70
623ed84b
JM		 71enum {
72 MLX4_MAX_NUM_PF = 16,
73 MLX4_MAX_NUM_VF = 64,
74 MLX4_MFUNC_MAX = 80,
3fc929e2 75 MLX4_MAX_EQ_NUM = 1024,
623ed84b
JM		 76 MLX4_MFUNC_EQ_NUM = 4,
77 MLX4_MFUNC_MAX_EQES = 8,
78 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
79};
80
0ff1fb65
HHZ		 81/* Driver supports 3 diffrent device methods to manage traffic steering:
82 * -device managed - High level API for ib and eth flow steering. FW is
83 * managing flow steering tables.
c96d97f4
HHZ		 84 * - B0 steering mode - Common low level API for ib and (if supported) eth.
85 * - A0 steering mode - Limited low level API for eth. In case of IB,
86 * B0 mode is in use.
87 */
88enum {
89 MLX4_STEERING_MODE_A0,
0ff1fb65
HHZ		 90 MLX4_STEERING_MODE_B0,
91 MLX4_STEERING_MODE_DEVICE_MANAGED
c96d97f4
HHZ		 92};
93
94static inline const char *mlx4_steering_mode_str(int steering_mode)
95{
96 switch (steering_mode) {
97 case MLX4_STEERING_MODE_A0:
98 return "A0 steering";
99
100 case MLX4_STEERING_MODE_B0:
101 return "B0 steering";
0ff1fb65
HHZ		 102
103 case MLX4_STEERING_MODE_DEVICE_MANAGED:
104 return "Device managed flow steering";
105
c96d97f4
HHZ		 106 default:
107 return "Unrecognize steering mode";
108 }
109}
110
225c7b1f 111enum {
52eafc68
OG		 112 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
113 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
114 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
012a8ff5 115 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
52eafc68
OG		 116 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
117 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
118 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
119 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
120 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
121 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
122 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
123 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
124 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
125 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
126 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
127 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
ccf86321
OG		 128 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
129 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
f3a9d1f2 130 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
559a9f1d
OD		 131 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
132 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
ccf86321
OG		 133 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
134 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
f2a3f6a3 135 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
58a60168 136 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
00f5ce99
JM		 137 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
138 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
225c7b1f
RD		 139};
140
b3416f44
SP		 141enum {
142 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
143 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
0ff1fb65
HHZ		 144 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
145 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3
b3416f44
SP		 146};
147
97285b78
MA		 148#define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
149
95d04f07
RD		 150enum {
151 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
152 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
153 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
154 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
155 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
156};
157
225c7b1f
RD		 158enum mlx4_event {
159 MLX4_EVENT_TYPE_COMP = 0x00,
160 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
161 MLX4_EVENT_TYPE_COMM_EST = 0x02,
162 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
163 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
164 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
165 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
166 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
167 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
168 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
169 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
170 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
171 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
172 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
173 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
174 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
175 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
623ed84b
JM		 176 MLX4_EVENT_TYPE_CMD = 0x0a,
177 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
178 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
5984be90 179 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
623ed84b 180 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
00f5ce99 181 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
623ed84b 182 MLX4_EVENT_TYPE_NONE = 0xff,
225c7b1f
RD		 183};
184
185enum {
186 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
187 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
188};
189
5984be90
JM		 190enum {
191 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
192};
193
225c7b1f
RD		 194enum {
195 MLX4_PERM_LOCAL_READ = 1 << 10,
196 MLX4_PERM_LOCAL_WRITE = 1 << 11,
197 MLX4_PERM_REMOTE_READ = 1 << 12,
198 MLX4_PERM_REMOTE_WRITE = 1 << 13,
199 MLX4_PERM_ATOMIC = 1 << 14
200};
201
202enum {
203 MLX4_OPCODE_NOP = 0x00,
204 MLX4_OPCODE_SEND_INVAL = 0x01,
205 MLX4_OPCODE_RDMA_WRITE = 0x08,
206 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
207 MLX4_OPCODE_SEND = 0x0a,
208 MLX4_OPCODE_SEND_IMM = 0x0b,
209 MLX4_OPCODE_LSO = 0x0e,
210 MLX4_OPCODE_RDMA_READ = 0x10,
211 MLX4_OPCODE_ATOMIC_CS = 0x11,
212 MLX4_OPCODE_ATOMIC_FA = 0x12,
6fa8f719
VS		 213 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
214 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
225c7b1f
RD		 215 MLX4_OPCODE_BIND_MW = 0x18,
216 MLX4_OPCODE_FMR = 0x19,
217 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
218 MLX4_OPCODE_CONFIG_CMD = 0x1f,
219
220 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
221 MLX4_RECV_OPCODE_SEND = 0x01,
222 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
223 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
224
225 MLX4_CQE_OPCODE_ERROR = 0x1e,
226 MLX4_CQE_OPCODE_RESIZE = 0x16,
227};
228
229enum {
230 MLX4_STAT_RATE_OFFSET = 5
231};
232
da995a8a 233enum mlx4_protocol {
0345584e
YP		 234 MLX4_PROT_IB_IPV6 = 0,
235 MLX4_PROT_ETH,
236 MLX4_PROT_IB_IPV4,
237 MLX4_PROT_FCOE
da995a8a
AS		 238};
239
29bdc883
VS		 240enum {
241 MLX4_MTT_FLAG_PRESENT = 1
242};
243
93fc9e1b
YP		 244enum mlx4_qp_region {
245 MLX4_QP_REGION_FW = 0,
246 MLX4_QP_REGION_ETH_ADDR,
247 MLX4_QP_REGION_FC_ADDR,
248 MLX4_QP_REGION_FC_EXCH,
249 MLX4_NUM_QP_REGION
250};
251
7ff93f8b 252enum mlx4_port_type {
623ed84b 253 MLX4_PORT_TYPE_NONE = 0,
27bf91d6
YP		 254 MLX4_PORT_TYPE_IB = 1,
255 MLX4_PORT_TYPE_ETH = 2,
256 MLX4_PORT_TYPE_AUTO = 3
7ff93f8b
YP		 257};
258
2a2336f8
YP		 259enum mlx4_special_vlan_idx {
260 MLX4_NO_VLAN_IDX = 0,
261 MLX4_VLAN_MISS_IDX,
262 MLX4_VLAN_REGULAR
263};
264
0345584e
YP		 265enum mlx4_steer_type {
266 MLX4_MC_STEER = 0,
267 MLX4_UC_STEER,
268 MLX4_NUM_STEERS
269};
270
93fc9e1b
YP		 271enum {
272 MLX4_NUM_FEXCH = 64 * 1024,
273};
274
5a0fd094
EC		 275enum {
276 MLX4_MAX_FAST_REG_PAGES = 511,
277};
278
00f5ce99
JM		 279enum {
280 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
281 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
282 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
283};
284
285/* Port mgmt change event handling */
286enum {
287 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
288 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
289 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
290 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
291 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
292};
293
294#define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
295 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
296
ea54b10c
JM		 297static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
298{
299 return (major << 32) | (minor << 16) | subminor;
300}
301
3fc929e2 302struct mlx4_phys_caps {
6634961c
JM		 303 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
304 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
3fc929e2
MA		 305 u32 num_phys_eqs;
306};
307
225c7b1f
RD		 308struct mlx4_caps {
309 u64 fw_ver;
623ed84b 310 u32 function;
225c7b1f 311 int num_ports;
5ae2a7a8 312 int vl_cap[MLX4_MAX_PORTS + 1];
b79acb49 313 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
9a5aa622 314 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
b79acb49
YP		 315 u64 def_mac[MLX4_MAX_PORTS + 1];
316 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
5ae2a7a8
RD		 317 int gid_table_len[MLX4_MAX_PORTS + 1];
318 int pkey_table_len[MLX4_MAX_PORTS + 1];
7699517d
YP		 319 int trans_type[MLX4_MAX_PORTS + 1];
320 int vendor_oui[MLX4_MAX_PORTS + 1];
321 int wavelength[MLX4_MAX_PORTS + 1];
322 u64 trans_code[MLX4_MAX_PORTS + 1];
225c7b1f
RD		 323 int local_ca_ack_delay;
324 int num_uars;
f5311ac1 325 u32 uar_page_size;
225c7b1f
RD		 326 int bf_reg_size;
327 int bf_regs_per_page;
328 int max_sq_sg;
329 int max_rq_sg;
330 int num_qps;
331 int max_wqes;
332 int max_sq_desc_sz;
333 int max_rq_desc_sz;
334 int max_qp_init_rdma;
335 int max_qp_dest_rdma;
225c7b1f 336 int sqp_start;
396f2feb
JM		 337 u32 base_sqpn;
338 u32 base_tunnel_sqpn;
225c7b1f
RD		 339 int num_srqs;
340 int max_srq_wqes;
341 int max_srq_sge;
342 int reserved_srqs;
343 int num_cqs;
344 int max_cqes;
345 int reserved_cqs;
346 int num_eqs;
347 int reserved_eqs;
b8dd786f 348 int num_comp_vectors;
0b7ca5a9 349 int comp_pool;
225c7b1f 350 int num_mpts;
a5bbe892 351 int max_fmr_maps;
2b8fb286 352 int num_mtts;
225c7b1f
RD		 353 int fmr_reserved_mtts;
354 int reserved_mtts;
355 int reserved_mrws;
356 int reserved_uars;
357 int num_mgms;
358 int num_amgms;
359 int reserved_mcgs;
360 int num_qp_per_mgm;
c96d97f4 361 int steering_mode;
0ff1fb65 362 int fs_log_max_ucast_qp_range_size;
225c7b1f
RD		 363 int num_pds;
364 int reserved_pds;
012a8ff5
SH		 365 int max_xrcds;
366 int reserved_xrcds;
225c7b1f 367 int mtt_entry_sz;
149983af 368 u32 max_msg_sz;
225c7b1f 369 u32 page_size_cap;
52eafc68 370 u64 flags;
b3416f44 371 u64 flags2;
95d04f07
RD		 372 u32 bmme_flags;
373 u32 reserved_lkey;
225c7b1f 374 u16 stat_rate_support;
5ae2a7a8 375 u8 port_width_cap[MLX4_MAX_PORTS + 1];
b832be1e 376 int max_gso_sz;
b3416f44 377 int max_rss_tbl_sz;
93fc9e1b
YP		 378 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
379 int reserved_qps;
380 int reserved_qps_base[MLX4_NUM_QP_REGION];
381 int log_num_macs;
382 int log_num_vlans;
383 int log_num_prios;
7ff93f8b
YP		 384 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
385 u8 supported_type[MLX4_MAX_PORTS + 1];
8d0fc7b6
YP		 386 u8 suggested_type[MLX4_MAX_PORTS + 1];
387 u8 default_sense[MLX4_MAX_PORTS + 1];
65dab25d 388 u32 port_mask[MLX4_MAX_PORTS + 1];
27bf91d6 389 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
f2a3f6a3 390 u32 max_counters;
096335b3 391 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
1ffeb2eb 392 u16 sqp_demux;
225c7b1f
RD		 393};
394
395struct mlx4_buf_list {
396 void *buf;
397 dma_addr_t map;
398};
399
400struct mlx4_buf {
b57aacfa
RD		 401 struct mlx4_buf_list direct;
402 struct mlx4_buf_list *page_list;
225c7b1f
RD		 403 int nbufs;
404 int npages;
405 int page_shift;
406};
407
408struct mlx4_mtt {
2b8fb286 409 u32 offset;
225c7b1f
RD		 410 int order;
411 int page_shift;
412};
413
6296883c
YP		 414enum {
415 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
416};
417
418struct mlx4_db_pgdir {
419 struct list_head list;
420 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
421 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
422 unsigned long *bits[2];
423 __be32 *db_page;
424 dma_addr_t db_dma;
425};
426
427struct mlx4_ib_user_db_page;
428
429struct mlx4_db {
430 __be32 *db;
431 union {
432 struct mlx4_db_pgdir *pgdir;
433 struct mlx4_ib_user_db_page *user_page;
434 } u;
435 dma_addr_t dma;
436 int index;
437 int order;
438};
439
38ae6a53
YP		 440struct mlx4_hwq_resources {
441 struct mlx4_db db;
442 struct mlx4_mtt mtt;
443 struct mlx4_buf buf;
444};
445
225c7b1f
RD		 446struct mlx4_mr {
447 struct mlx4_mtt mtt;
448 u64 iova;
449 u64 size;
450 u32 key;
451 u32 pd;
452 u32 access;
453 int enabled;
454};
455
8ad11fb6
JM		 456struct mlx4_fmr {
457 struct mlx4_mr mr;
458 struct mlx4_mpt_entry *mpt;
459 __be64 *mtts;
460 dma_addr_t dma_handle;
461 int max_pages;
462 int max_maps;
463 int maps;
464 u8 page_shift;
465};
466
225c7b1f
RD		 467struct mlx4_uar {
468 unsigned long pfn;
469 int index;
c1b43dca
EC		 470 struct list_head bf_list;
471 unsigned free_bf_bmap;
472 void __iomem *map;
473 void __iomem *bf_map;
474};
475
476struct mlx4_bf {
477 unsigned long offset;
478 int buf_size;
479 struct mlx4_uar *uar;
480 void __iomem *reg;
225c7b1f
RD		 481};
482
483struct mlx4_cq {
484 void (*comp) (struct mlx4_cq *);
485 void (*event) (struct mlx4_cq *, enum mlx4_event);
486
487 struct mlx4_uar *uar;
488
489 u32 cons_index;
490
491 __be32 *set_ci_db;
492 __be32 *arm_db;
493 int arm_sn;
494
495 int cqn;
b8dd786f 496 unsigned vector;
225c7b1f
RD		 497
498 atomic_t refcount;
499 struct completion free;
500};
501
502struct mlx4_qp {
503 void (*event) (struct mlx4_qp *, enum mlx4_event);
504
505 int qpn;
506
507 atomic_t refcount;
508 struct completion free;
509};
510
511struct mlx4_srq {
512 void (*event) (struct mlx4_srq *, enum mlx4_event);
513
514 int srqn;
515 int max;
516 int max_gs;
517 int wqe_shift;
518
519 atomic_t refcount;
520 struct completion free;
521};
522
523struct mlx4_av {
524 __be32 port_pd;
525 u8 reserved1;
526 u8 g_slid;
527 __be16 dlid;
528 u8 reserved2;
529 u8 gid_index;
530 u8 stat_rate;
531 u8 hop_limit;
532 __be32 sl_tclass_flowlabel;
533 u8 dgid[16];
534};
535
fa417f7b
EC		 536struct mlx4_eth_av {
537 __be32 port_pd;
538 u8 reserved1;
539 u8 smac_idx;
540 u16 reserved2;
541 u8 reserved3;
542 u8 gid_index;
543 u8 stat_rate;
544 u8 hop_limit;
545 __be32 sl_tclass_flowlabel;
546 u8 dgid[16];
547 u32 reserved4[2];
548 __be16 vlan;
549 u8 mac[6];
550};
551
552union mlx4_ext_av {
553 struct mlx4_av ib;
554 struct mlx4_eth_av eth;
555};
556
f2a3f6a3
OG		 557struct mlx4_counter {
558 u8 reserved1[3];
559 u8 counter_mode;
560 __be32 num_ifc;
561 u32 reserved2[2];
562 __be64 rx_frames;
563 __be64 rx_bytes;
564 __be64 tx_frames;
565 __be64 tx_bytes;
566};
567
225c7b1f
RD		 568struct mlx4_dev {
569 struct pci_dev *pdev;
570 unsigned long flags;
623ed84b 571 unsigned long num_slaves;
225c7b1f 572 struct mlx4_caps caps;
3fc929e2 573 struct mlx4_phys_caps phys_caps;
225c7b1f 574 struct radix_tree_root qp_table_tree;
725c8999 575 u8 rev_id;
cd9281d8 576 char board_id[MLX4_BOARD_ID_LEN];
ab9c17a0 577 int num_vfs;
592e49dd
HHZ		 578 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
579 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
225c7b1f
RD		 580};
581
00f5ce99
JM		 582struct mlx4_eqe {
583 u8 reserved1;
584 u8 type;
585 u8 reserved2;
586 u8 subtype;
587 union {
588 u32 raw[6];
589 struct {
590 __be32 cqn;
591 } __packed comp;
592 struct {
593 u16 reserved1;
594 __be16 token;
595 u32 reserved2;
596 u8 reserved3[3];
597 u8 status;
598 __be64 out_param;
599 } __packed cmd;
600 struct {
601 __be32 qpn;
602 } __packed qp;
603 struct {
604 __be32 srqn;
605 } __packed srq;
606 struct {
607 __be32 cqn;
608 u32 reserved1;
609 u8 reserved2[3];
610 u8 syndrome;
611 } __packed cq_err;
612 struct {
613 u32 reserved1[2];
614 __be32 port;
615 } __packed port_change;
616 struct {
617 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
618 u32 reserved;
619 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
620 } __packed comm_channel_arm;
621 struct {
622 u8 port;
623 u8 reserved[3];
624 __be64 mac;
625 } __packed mac_update;
626 struct {
627 __be32 slave_id;
628 } __packed flr_event;
629 struct {
630 __be16 current_temperature;
631 __be16 warning_threshold;
632 } __packed warming;
633 struct {
634 u8 reserved[3];
635 u8 port;
636 union {
637 struct {
638 __be16 mstr_sm_lid;
639 __be16 port_lid;
640 __be32 changed_attr;
641 u8 reserved[3];
642 u8 mstr_sm_sl;
643 __be64 gid_prefix;
644 } __packed port_info;
645 struct {
646 __be32 block_ptr;
647 __be32 tbl_entries_mask;
648 } __packed tbl_change_info;
649 } params;
650 } __packed port_mgmt_change;
651 } event;
652 u8 slave_id;
653 u8 reserved3[2];
654 u8 owner;
655} __packed;
656
225c7b1f
RD		 657struct mlx4_init_port_param {
658 int set_guid0;
659 int set_node_guid;
660 int set_si_guid;
661 u16 mtu;
662 int port_width_cap;
663 u16 vl_cap;
664 u16 max_gid;
665 u16 max_pkey;
666 u64 guid0;
667 u64 node_guid;
668 u64 si_guid;
669};
670
7ff93f8b
YP		 671#define mlx4_foreach_port(port, dev, type) \
672 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
65dab25d 673 if ((type) == (dev)->caps.port_mask[(port)])
7ff93f8b 674
65dab25d
JM		 675#define mlx4_foreach_ib_transport_port(port, dev) \
676 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
677 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
678 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
623ed84b 679
752a50ca
JM		 680#define MLX4_INVALID_SLAVE_ID 0xFF
681
00f5ce99
JM		 682void handle_port_mgmt_change_event(struct work_struct *work);
683
2aca1172
JM		 684static inline int mlx4_master_func_num(struct mlx4_dev *dev)
685{
686 return dev->caps.function;
687}
688
623ed84b
JM		 689static inline int mlx4_is_master(struct mlx4_dev *dev)
690{
691 return dev->flags & MLX4_FLAG_MASTER;
692}
693
694static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
695{
696 return (qpn < dev->caps.sqp_start + 8);
697}
fa417f7b 698
623ed84b
JM		 699static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
700{
701 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
702}
703
704static inline int mlx4_is_slave(struct mlx4_dev *dev)
705{
706 return dev->flags & MLX4_FLAG_SLAVE;
707}
fa417f7b 708
225c7b1f
RD		 709int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
710 struct mlx4_buf *buf);
711void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
1c69fc2a
RD		 712static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
713{
313abe55 714 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
b57aacfa 715 return buf->direct.buf + offset;
1c69fc2a 716 else
b57aacfa 717 return buf->page_list[offset >> PAGE_SHIFT].buf +
1c69fc2a
RD		 718 (offset & (PAGE_SIZE - 1));
719}
225c7b1f
RD		 720
721int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
722void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
012a8ff5
SH		 723int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
724void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
225c7b1f
RD		 725
726int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
727void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
c1b43dca
EC		 728int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf);
729void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
225c7b1f
RD		 730
731int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
732 struct mlx4_mtt *mtt);
733void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
734u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
735
736int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
737 int npages, int page_shift, struct mlx4_mr *mr);
738void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
739int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
740int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
741 int start_index, int npages, u64 *page_list);
742int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
743 struct mlx4_buf *buf);
744
6296883c
YP		 745int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
746void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
747
38ae6a53
YP		 748int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
749 int size, int max_direct);
750void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
751 int size);
752
225c7b1f 753int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
e463c7b1 754 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
b8dd786f 755 unsigned vector, int collapsed);
225c7b1f
RD		 756void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
757
a3cdcbfa
YP		 758int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
759void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
760
761int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
225c7b1f
RD		 762void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
763
18abd5ea
SH		 764int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
765 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
225c7b1f
RD		 766void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
767int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
65541cb7 768int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
225c7b1f 769
5ae2a7a8 770int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
225c7b1f
RD		 771int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
772
ffe455ad
EE		 773int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
774 int block_mcast_loopback, enum mlx4_protocol prot);
775int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
776 enum mlx4_protocol prot);
521e575b 777int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
0ff1fb65
HHZ		 778 u8 port, int block_mcast_loopback,
779 enum mlx4_protocol protocol, u64 *reg_id);
da995a8a 780int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
0ff1fb65
HHZ		 781 enum mlx4_protocol protocol, u64 reg_id);
782
783enum {
784 MLX4_DOMAIN_UVERBS = 0x1000,
785 MLX4_DOMAIN_ETHTOOL = 0x2000,
786 MLX4_DOMAIN_RFS = 0x3000,
787 MLX4_DOMAIN_NIC = 0x5000,
788};
789
790enum mlx4_net_trans_rule_id {
791 MLX4_NET_TRANS_RULE_ID_ETH = 0,
792 MLX4_NET_TRANS_RULE_ID_IB,
793 MLX4_NET_TRANS_RULE_ID_IPV6,
794 MLX4_NET_TRANS_RULE_ID_IPV4,
795 MLX4_NET_TRANS_RULE_ID_TCP,
796 MLX4_NET_TRANS_RULE_ID_UDP,
797 MLX4_NET_TRANS_RULE_NUM, /* should be last */
798};
799
a8edc3bf
HHZ		 800extern const u16 __sw_id_hw[];
801
7fb40f87
HHZ		 802static inline int map_hw_to_sw_id(u16 header_id)
803{
804
805 int i;
806 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
807 if (header_id == __sw_id_hw[i])
808 return i;
809 }
810 return -EINVAL;
811}
812
0ff1fb65
HHZ		 813enum mlx4_net_trans_promisc_mode {
814 MLX4_FS_PROMISC_NONE = 0,
815 MLX4_FS_PROMISC_UPLINK,
592e49dd 816 /* For future use. Not implemented yet */
0ff1fb65
HHZ		 817 MLX4_FS_PROMISC_FUNCTION_PORT,
818 MLX4_FS_PROMISC_ALL_MULTI,
819};
820
821struct mlx4_spec_eth {
822 u8 dst_mac[6];
823 u8 dst_mac_msk[6];
824 u8 src_mac[6];
825 u8 src_mac_msk[6];
826 u8 ether_type_enable;
827 __be16 ether_type;
828 __be16 vlan_id_msk;
829 __be16 vlan_id;
830};
831
832struct mlx4_spec_tcp_udp {
833 __be16 dst_port;
834 __be16 dst_port_msk;
835 __be16 src_port;
836 __be16 src_port_msk;
837};
838
839struct mlx4_spec_ipv4 {
840 __be32 dst_ip;
841 __be32 dst_ip_msk;
842 __be32 src_ip;
843 __be32 src_ip_msk;
844};
845
846struct mlx4_spec_ib {
847 __be32 r_qpn;
848 __be32 qpn_msk;
849 u8 dst_gid[16];
850 u8 dst_gid_msk[16];
851};
852
853struct mlx4_spec_list {
854 struct list_head list;
855 enum mlx4_net_trans_rule_id id;
856 union {
857 struct mlx4_spec_eth eth;
858 struct mlx4_spec_ib ib;
859 struct mlx4_spec_ipv4 ipv4;
860 struct mlx4_spec_tcp_udp tcp_udp;
861 };
862};
863
864enum mlx4_net_trans_hw_rule_queue {
865 MLX4_NET_TRANS_Q_FIFO,
866 MLX4_NET_TRANS_Q_LIFO,
867};
868
869struct mlx4_net_trans_rule {
870 struct list_head list;
871 enum mlx4_net_trans_hw_rule_queue queue_mode;
872 bool exclusive;
873 bool allow_loopback;
874 enum mlx4_net_trans_promisc_mode promisc_mode;
875 u8 port;
876 u16 priority;
877 u32 qpn;
878};
879
592e49dd
HHZ		 880int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
881 enum mlx4_net_trans_promisc_mode mode);
882int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
883 enum mlx4_net_trans_promisc_mode mode);
1679200f
YP		 884int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
885int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
886int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
887int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
888int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
889
ffe455ad
EE		 890int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
891void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
892int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
893int mlx4_get_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn);
894void mlx4_put_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int qpn);
93ece0c1 895void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
9a9a232a
YP		 896int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
897 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
898int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
899 u8 promisc);
e5395e92
AV		 900int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
901int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
902 u8 *pg, u16 *ratelimit);
4c3eb3ca 903int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
2a2336f8
YP		 904int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
905void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
906
8ad11fb6
JM		 907int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
908 int npages, u64 iova, u32 *lkey, u32 *rkey);
909int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
910 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
911int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
912void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
913 u32 *lkey, u32 *rkey);
914int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
915int mlx4_SYNC_TPT(struct mlx4_dev *dev);
e7c1c2c4 916int mlx4_test_interrupts(struct mlx4_dev *dev);
d9236c3f
AV		 917int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
918 int *vector);
0b7ca5a9 919void mlx4_release_eq(struct mlx4_dev *dev, int vec);
8ad11fb6 920
14c07b13
YP		 921int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
922int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
923
f2a3f6a3
OG		 924int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
925void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
926
0ff1fb65
HHZ		 927int mlx4_flow_attach(struct mlx4_dev *dev,
928 struct mlx4_net_trans_rule *rule, u64 *reg_id);
929int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
930
396f2feb
JM		 931int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
932
225c7b1f 933#endif /* MLX4_DEVICE_H */
Linux 6.x block layer and io_uring tree(s)