[linux-block.git] / include / linux / dmaengine.h

/*
 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59
 * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 *
 * The full GNU General Public License is included in this distribution in the
 * file called COPYING.
 */
#ifndef DMAENGINE_H
#define DMAENGINE_H

#include <linux/device.h>
#include <linux/uio.h>
#include <linux/kref.h>
#include <linux/completion.h>
#include <linux/rcupdate.h>
#include <linux/dma-mapping.h>

/**
 * typedef dma_cookie_t - an opaque DMA cookie
 *
 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
 */
typedef s32 dma_cookie_t;

#define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)

/**
 * enum dma_status - DMA transaction status
 * @DMA_SUCCESS: transaction completed successfully
 * @DMA_IN_PROGRESS: transaction not yet processed
 * @DMA_ERROR: transaction failed
 */
enum dma_status {
	DMA_SUCCESS,
	DMA_IN_PROGRESS,
	DMA_ERROR,
};

/**
 * enum dma_transaction_type - DMA transaction types/indexes
 */
enum dma_transaction_type {
	DMA_MEMCPY,
	DMA_XOR,
	DMA_PQ_XOR,
	DMA_DUAL_XOR,
	DMA_PQ_UPDATE,
	DMA_ZERO_SUM,
	DMA_PQ_ZERO_SUM,
	DMA_MEMSET,
	DMA_MEMCPY_CRC32C,
	DMA_INTERRUPT,
	DMA_PRIVATE,
	DMA_SLAVE,
};

/* last transaction type for creation of the capabilities mask */
#define DMA_TX_TYPE_END (DMA_SLAVE + 1)


/**
 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
 * 	control completion, and communicate status.
 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
 * 	this transaction
 * @DMA_CTRL_ACK - the descriptor cannot be reused until the client
 * 	acknowledges receipt, i.e. has has a chance to establish any
 * 	dependency chains
 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
 */
enum dma_ctrl_flags {
	DMA_PREP_INTERRUPT = (1 << 0),
	DMA_CTRL_ACK = (1 << 1),
	DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
	DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
};

/**
 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
 * See linux/cpumask.h
 */
typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;

/**
 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
 * @refcount: local_t used for open-coded "bigref" counting
 * @memcpy_count: transaction counter
 * @bytes_transferred: byte counter
 */

struct dma_chan_percpu {
	/* stats */
	unsigned long memcpy_count;
	unsigned long bytes_transferred;
};

/**
 * struct dma_chan - devices supply DMA channels, clients use them
 * @device: ptr to the dma device who supplies this channel, always !%NULL
 * @cookie: last cookie value returned to client
 * @chan_id: channel ID for sysfs
 * @class_dev: class device for sysfs
 * @refcount: kref, used in "bigref" slow-mode
 * @slow_ref: indicates that the DMA channel is free
 * @rcu: the DMA channel's RCU head
 * @device_node: used to add this to the device chan list
 * @local: per-cpu pointer to a struct dma_chan_percpu
 * @client-count: how many clients are using this channel
 * @table_count: number of appearances in the mem-to-mem allocation table
 */
struct dma_chan {
	struct dma_device *device;
	dma_cookie_t cookie;

	/* sysfs */
	int chan_id;
	struct device dev;

	struct list_head device_node;
	struct dma_chan_percpu *local;
	int client_count;
	int table_count;
};

#define to_dma_chan(p) container_of(p, struct dma_chan, dev)

void dma_chan_cleanup(struct kref *kref);

/**
 * typedef dma_filter_fn - callback filter for dma_request_channel
 * @chan: channel to be reviewed
 * @filter_param: opaque parameter passed through dma_request_channel
 *
 * When this optional parameter is specified in a call to dma_request_channel a
 * suitable channel is passed to this routine for further dispositioning before
 * being returned.  Where 'suitable' indicates a non-busy channel that
 * satisfies the given capability mask.  It returns 'true' to indicate that the
 * channel is suitable.
 */
typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);

typedef void (*dma_async_tx_callback)(void *dma_async_param);
/**
 * struct dma_async_tx_descriptor - async transaction descriptor
 * ---dma generic offload fields---
 * @cookie: tracking cookie for this transaction, set to -EBUSY if
 *	this tx is sitting on a dependency list
 * @flags: flags to augment operation preparation, control completion, and
 * 	communicate status
 * @phys: physical address of the descriptor
 * @tx_list: driver common field for operations that require multiple
 *	descriptors
 * @chan: target channel for this operation
 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
 * @callback: routine to call after this operation is complete
 * @callback_param: general parameter to pass to the callback routine
 * ---async_tx api specific fields---
 * @next: at completion submit this descriptor
 * @parent: pointer to the next level up in the dependency chain
 * @lock: protect the parent and next pointers
 */
struct dma_async_tx_descriptor {
	dma_cookie_t cookie;
	enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
	dma_addr_t phys;
	struct list_head tx_list;
	struct dma_chan *chan;
	dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
	dma_async_tx_callback callback;
	void *callback_param;
	struct dma_async_tx_descriptor *next;
	struct dma_async_tx_descriptor *parent;
	spinlock_t lock;
};

/**
 * struct dma_device - info on the entity supplying DMA services
 * @chancnt: how many DMA channels are supported
 * @channels: the list of struct dma_chan
 * @global_node: list_head for global dma_device_list
 * @cap_mask: one or more dma_capability flags
 * @max_xor: maximum number of xor sources, 0 if no capability
 * @refcount: reference count
 * @done: IO completion struct
 * @dev_id: unique device ID
 * @dev: struct device reference for dma mapping api
 * @device_alloc_chan_resources: allocate resources and return the
 *	number of allocated descriptors
 * @device_free_chan_resources: release DMA channel's resources
 * @device_prep_dma_memcpy: prepares a memcpy operation
 * @device_prep_dma_xor: prepares a xor operation
 * @device_prep_dma_zero_sum: prepares a zero_sum operation
 * @device_prep_dma_memset: prepares a memset operation
 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
 * @device_prep_slave_sg: prepares a slave dma operation
 * @device_terminate_all: terminate all pending operations
 * @device_issue_pending: push pending transactions to hardware
 */
struct dma_device {

	unsigned int chancnt;
	struct list_head channels;
	struct list_head global_node;
	dma_cap_mask_t  cap_mask;
	int max_xor;

	int dev_id;
	struct device *dev;

	int (*device_alloc_chan_resources)(struct dma_chan *chan);
	void (*device_free_chan_resources)(struct dma_chan *chan);

	struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
		struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
		size_t len, unsigned long flags);
	struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
		struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
		unsigned int src_cnt, size_t len, unsigned long flags);
	struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)(
		struct dma_chan *chan, dma_addr_t *src,	unsigned int src_cnt,
		size_t len, u32 *result, unsigned long flags);
	struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
		struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
		unsigned long flags);
	struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
		struct dma_chan *chan, unsigned long flags);

	struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
		struct dma_chan *chan, struct scatterlist *sgl,
		unsigned int sg_len, enum dma_data_direction direction,
		unsigned long flags);
	void (*device_terminate_all)(struct dma_chan *chan);

	enum dma_status (*device_is_tx_complete)(struct dma_chan *chan,
			dma_cookie_t cookie, dma_cookie_t *last,
			dma_cookie_t *used);
	void (*device_issue_pending)(struct dma_chan *chan);
};

/* --- public DMA engine API --- */

void dmaengine_get(void);
void dmaengine_put(void);
dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
	void *dest, void *src, size_t len);
dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
	struct page *page, unsigned int offset, void *kdata, size_t len);
dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
	struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
	unsigned int src_off, size_t len);
void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
	struct dma_chan *chan);

static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
{
	tx->flags |= DMA_CTRL_ACK;
}

static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
{
	return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
}

#define first_dma_cap(mask) __first_dma_cap(&(mask))
static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
{
	return min_t(int, DMA_TX_TYPE_END,
		find_first_bit(srcp->bits, DMA_TX_TYPE_END));
}

#define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
{
	return min_t(int, DMA_TX_TYPE_END,
		find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
}

#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
static inline void
__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
{
	set_bit(tx_type, dstp->bits);
}

#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
{
	bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
}

#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
static inline int
__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
{
	return test_bit(tx_type, srcp->bits);
}

#define for_each_dma_cap_mask(cap, mask) \
	for ((cap) = first_dma_cap(mask);	\
		(cap) < DMA_TX_TYPE_END;	\
		(cap) = next_dma_cap((cap), (mask)))

/**
 * dma_async_issue_pending - flush pending transactions to HW
 * @chan: target DMA channel
 *
 * This allows drivers to push copies to HW in batches,
 * reducing MMIO writes where possible.
 */
static inline void dma_async_issue_pending(struct dma_chan *chan)
{
	chan->device->device_issue_pending(chan);
}

#define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)

/**
 * dma_async_is_tx_complete - poll for transaction completion
 * @chan: DMA channel
 * @cookie: transaction identifier to check status of
 * @last: returns last completed cookie, can be NULL
 * @used: returns last issued cookie, can be NULL
 *
 * If @last and @used are passed in, upon return they reflect the driver
 * internal state and can be used with dma_async_is_complete() to check
 * the status of multiple cookies without re-checking hardware state.
 */
static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
	dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
{
	return chan->device->device_is_tx_complete(chan, cookie, last, used);
}

#define dma_async_memcpy_complete(chan, cookie, last, used)\
	dma_async_is_tx_complete(chan, cookie, last, used)

/**
 * dma_async_is_complete - test a cookie against chan state
 * @cookie: transaction identifier to test status of
 * @last_complete: last know completed transaction
 * @last_used: last cookie value handed out
 *
 * dma_async_is_complete() is used in dma_async_memcpy_complete()
 * the test logic is separated for lightweight testing of multiple cookies
 */
static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
			dma_cookie_t last_complete, dma_cookie_t last_used)
{
	if (last_complete <= last_used) {
		if ((cookie <= last_complete) || (cookie > last_used))
			return DMA_SUCCESS;
	} else {
		if ((cookie <= last_complete) && (cookie > last_used))
			return DMA_SUCCESS;
	}
	return DMA_IN_PROGRESS;
}

enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
#ifdef CONFIG_DMA_ENGINE
enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
#else
static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
{
	return DMA_SUCCESS;
}
#endif

/* --- DMA device --- */

int dma_async_device_register(struct dma_device *device);
void dma_async_device_unregister(struct dma_device *device);
void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
void dma_issue_pending_all(void);
#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param);
void dma_release_channel(struct dma_chan *chan);

/* --- Helper iov-locking functions --- */

struct dma_page_list {
	char __user *base_address;
	int nr_pages;
	struct page **pages;
};

struct dma_pinned_list {
	int nr_iovecs;
	struct dma_page_list page_list[0];
};

struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);

dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
	struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
	struct dma_pinned_list *pinned_list, struct page *page,
	unsigned int offset, size_t len);

#endif /* DMAENGINE_H */
Commit	Line	Data
c13c8260 CL	1	/*
	2	* Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License as published by the Free
	6	* Software Foundation; either version 2 of the License, or (at your option)
	7	* any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc., 59
	16	* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	17	*
	18	* The full GNU General Public License is included in this distribution in the
	19	* file called COPYING.
	20	*/
	21	#ifndef DMAENGINE_H
	22	#define DMAENGINE_H
1c0f16e5	23
c13c8260 CL	24	#include <linux/device.h>
	25	#include <linux/uio.h>
	26	#include <linux/kref.h>
	27	#include <linux/completion.h>
	28	#include <linux/rcupdate.h>
7405f74b	29	#include <linux/dma-mapping.h>
c13c8260	30
c13c8260	31	/**
fe4ada2d	32	* typedef dma_cookie_t - an opaque DMA cookie
c13c8260 CL	33	*
	34	* if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
	35	*/
	36	typedef s32 dma_cookie_t;
	37
	38	#define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
	39
	40	/**
	41	* enum dma_status - DMA transaction status
	42	* @DMA_SUCCESS: transaction completed successfully
	43	* @DMA_IN_PROGRESS: transaction not yet processed
	44	* @DMA_ERROR: transaction failed
	45	*/
	46	enum dma_status {
	47	DMA_SUCCESS,
	48	DMA_IN_PROGRESS,
	49	DMA_ERROR,
	50	};
	51
7405f74b DW	52	/**
	53	* enum dma_transaction_type - DMA transaction types/indexes
	54	*/
	55	enum dma_transaction_type {
	56	DMA_MEMCPY,
	57	DMA_XOR,
	58	DMA_PQ_XOR,
	59	DMA_DUAL_XOR,
	60	DMA_PQ_UPDATE,
	61	DMA_ZERO_SUM,
	62	DMA_PQ_ZERO_SUM,
	63	DMA_MEMSET,
	64	DMA_MEMCPY_CRC32C,
	65	DMA_INTERRUPT,
59b5ec21	66	DMA_PRIVATE,
dc0ee643	67	DMA_SLAVE,
7405f74b DW	68	};
	69
	70	/* last transaction type for creation of the capabilities mask */
dc0ee643 HS	71	#define DMA_TX_TYPE_END (DMA_SLAVE + 1)
dc0ee643 HS	72
7405f74b	73
d4c56f97	74	/**
636bdeaa DW	75	* enum dma_ctrl_flags - DMA flags to augment operation preparation,
636bdeaa DW	76	* control completion, and communicate status.
d4c56f97 DW	77	* @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
d4c56f97 DW	78	* this transaction
636bdeaa DW	79	* @DMA_CTRL_ACK - the descriptor cannot be reused until the client
	80	* acknowledges receipt, i.e. has has a chance to establish any
	81	* dependency chains
e1d181ef DW	82	* @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
e1d181ef DW	83	* @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
d4c56f97	84	*/
636bdeaa	85	enum dma_ctrl_flags {
d4c56f97	86	DMA_PREP_INTERRUPT = (1 << 0),
636bdeaa	87	DMA_CTRL_ACK = (1 << 1),
e1d181ef DW	88	DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
e1d181ef DW	89	DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
d4c56f97 DW	90	};
d4c56f97 DW	91
7405f74b DW	92	/**
	93	* dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
	94	* See linux/cpumask.h
	95	*/
	96	typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
	97
c13c8260 CL	98	/**
	99	* struct dma_chan_percpu - the per-CPU part of struct dma_chan
	100	* @refcount: local_t used for open-coded "bigref" counting
	101	* @memcpy_count: transaction counter
	102	* @bytes_transferred: byte counter
	103	*/
	104
	105	struct dma_chan_percpu {
c13c8260 CL	106	/* stats */
	107	unsigned long memcpy_count;
	108	unsigned long bytes_transferred;
	109	};
	110
	111	/**
	112	* struct dma_chan - devices supply DMA channels, clients use them
fe4ada2d	113	* @device: ptr to the dma device who supplies this channel, always !%NULL
c13c8260	114	* @cookie: last cookie value returned to client
fe4ada2d RD	115	* @chan_id: channel ID for sysfs
fe4ada2d RD	116	* @class_dev: class device for sysfs
c13c8260	117	* @refcount: kref, used in "bigref" slow-mode
fe4ada2d RD	118	* @slow_ref: indicates that the DMA channel is free
fe4ada2d RD	119	* @rcu: the DMA channel's RCU head
c13c8260 CL	120	* @device_node: used to add this to the device chan list
c13c8260 CL	121	* @local: per-cpu pointer to a struct dma_chan_percpu
7cc5bf9a	122	* @client-count: how many clients are using this channel
bec08513	123	* @table_count: number of appearances in the mem-to-mem allocation table
c13c8260 CL	124	*/
c13c8260 CL	125	struct dma_chan {
c13c8260 CL	126	struct dma_device *device;
	127	dma_cookie_t cookie;
	128
	129	/* sysfs */
	130	int chan_id;
891f78ea	131	struct device dev;
c13c8260	132
c13c8260 CL	133	struct list_head device_node;
c13c8260 CL	134	struct dma_chan_percpu *local;
7cc5bf9a	135	int client_count;
bec08513	136	int table_count;
c13c8260 CL	137	};
c13c8260 CL	138
891f78ea	139	#define to_dma_chan(p) container_of(p, struct dma_chan, dev)
d379b01e	140
c13c8260 CL	141	void dma_chan_cleanup(struct kref *kref);
c13c8260 CL	142
59b5ec21 DW	143	/**
	144	* typedef dma_filter_fn - callback filter for dma_request_channel
	145	* @chan: channel to be reviewed
	146	* @filter_param: opaque parameter passed through dma_request_channel
	147	*
	148	* When this optional parameter is specified in a call to dma_request_channel a
	149	* suitable channel is passed to this routine for further dispositioning before
	150	* being returned. Where 'suitable' indicates a non-busy channel that
7dd60251 DW	151	* satisfies the given capability mask. It returns 'true' to indicate that the
7dd60251 DW	152	* channel is suitable.
59b5ec21	153	*/
7dd60251	154	typedef bool (dma_filter_fn)(struct dma_chan chan, void *filter_param);
59b5ec21	155
7405f74b DW	156	typedef void (dma_async_tx_callback)(void dma_async_param);
	157	/**
	158	* struct dma_async_tx_descriptor - async transaction descriptor
	159	* ---dma generic offload fields---
	160	* @cookie: tracking cookie for this transaction, set to -EBUSY if
	161	* this tx is sitting on a dependency list
636bdeaa DW	162	* @flags: flags to augment operation preparation, control completion, and
636bdeaa DW	163	* communicate status
7405f74b DW	164	* @phys: physical address of the descriptor
	165	* @tx_list: driver common field for operations that require multiple
	166	* descriptors
	167	* @chan: target channel for this operation
	168	* @tx_submit: set the prepared descriptor(s) to be executed by the engine
7405f74b DW	169	* @callback: routine to call after this operation is complete
	170	* @callback_param: general parameter to pass to the callback routine
	171	* ---async_tx api specific fields---
19242d72	172	* @next: at completion submit this descriptor
7405f74b	173	* @parent: pointer to the next level up in the dependency chain
19242d72	174	* @lock: protect the parent and next pointers
7405f74b DW	175	*/
	176	struct dma_async_tx_descriptor {
	177	dma_cookie_t cookie;
636bdeaa	178	enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
7405f74b DW	179	dma_addr_t phys;
	180	struct list_head tx_list;
	181	struct dma_chan *chan;
	182	dma_cookie_t (tx_submit)(struct dma_async_tx_descriptor tx);
7405f74b DW	183	dma_async_tx_callback callback;
7405f74b DW	184	void *callback_param;
19242d72	185	struct dma_async_tx_descriptor *next;
7405f74b DW	186	struct dma_async_tx_descriptor *parent;
	187	spinlock_t lock;
	188	};
	189
c13c8260 CL	190	/**
	191	* struct dma_device - info on the entity supplying DMA services
	192	* @chancnt: how many DMA channels are supported
	193	* @channels: the list of struct dma_chan
	194	* @global_node: list_head for global dma_device_list
7405f74b DW	195	* @cap_mask: one or more dma_capability flags
7405f74b DW	196	* @max_xor: maximum number of xor sources, 0 if no capability
fe4ada2d RD	197	* @refcount: reference count
	198	* @done: IO completion struct
	199	* @dev_id: unique device ID
7405f74b	200	* @dev: struct device reference for dma mapping api
fe4ada2d RD	201	* @device_alloc_chan_resources: allocate resources and return the
	202	* number of allocated descriptors
	203	* @device_free_chan_resources: release DMA channel's resources
7405f74b DW	204	* @device_prep_dma_memcpy: prepares a memcpy operation
	205	* @device_prep_dma_xor: prepares a xor operation
	206	* @device_prep_dma_zero_sum: prepares a zero_sum operation
	207	* @device_prep_dma_memset: prepares a memset operation
	208	* @device_prep_dma_interrupt: prepares an end of chain interrupt operation
dc0ee643 HS	209	* @device_prep_slave_sg: prepares a slave dma operation
dc0ee643 HS	210	* @device_terminate_all: terminate all pending operations
7405f74b	211	* @device_issue_pending: push pending transactions to hardware
c13c8260 CL	212	*/
	213	struct dma_device {
	214
	215	unsigned int chancnt;
	216	struct list_head channels;
	217	struct list_head global_node;
7405f74b DW	218	dma_cap_mask_t cap_mask;
7405f74b DW	219	int max_xor;
c13c8260	220
c13c8260	221	int dev_id;
7405f74b	222	struct device *dev;
c13c8260	223
aa1e6f1a	224	int (device_alloc_chan_resources)(struct dma_chan chan);
c13c8260	225	void (device_free_chan_resources)(struct dma_chan chan);
7405f74b DW	226
7405f74b DW	227	struct dma_async_tx_descriptor (device_prep_dma_memcpy)(
0036731c	228	struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
d4c56f97	229	size_t len, unsigned long flags);
7405f74b	230	struct dma_async_tx_descriptor (device_prep_dma_xor)(
0036731c	231	struct dma_chan chan, dma_addr_t dest, dma_addr_t src,
d4c56f97	232	unsigned int src_cnt, size_t len, unsigned long flags);
7405f74b	233	struct dma_async_tx_descriptor (device_prep_dma_zero_sum)(
0036731c	234	struct dma_chan chan, dma_addr_t src, unsigned int src_cnt,
d4c56f97	235	size_t len, u32 *result, unsigned long flags);
7405f74b	236	struct dma_async_tx_descriptor (device_prep_dma_memset)(
0036731c	237	struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
d4c56f97	238	unsigned long flags);
7405f74b	239	struct dma_async_tx_descriptor (device_prep_dma_interrupt)(
636bdeaa	240	struct dma_chan *chan, unsigned long flags);
7405f74b	241
dc0ee643 HS	242	struct dma_async_tx_descriptor (device_prep_slave_sg)(
	243	struct dma_chan chan, struct scatterlist sgl,
	244	unsigned int sg_len, enum dma_data_direction direction,
	245	unsigned long flags);
	246	void (device_terminate_all)(struct dma_chan chan);
	247
7405f74b	248	enum dma_status (device_is_tx_complete)(struct dma_chan chan,
c13c8260 CL	249	dma_cookie_t cookie, dma_cookie_t *last,
c13c8260 CL	250	dma_cookie_t *used);
7405f74b	251	void (device_issue_pending)(struct dma_chan chan);
c13c8260 CL	252	};
	253
	254	/* --- public DMA engine API --- */
	255
209b84a8 DW	256	void dmaengine_get(void);
209b84a8 DW	257	void dmaengine_put(void);
7405f74b DW	258	dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
	259	void dest, void src, size_t len);
	260	dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
	261	struct page page, unsigned int offset, void kdata, size_t len);
	262	dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
	263	struct page dest_pg, unsigned int dest_off, struct page src_pg,
	264	unsigned int src_off, size_t len);
	265	void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
	266	struct dma_chan *chan);
c13c8260	267
0839875e	268	static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
7405f74b	269	{
636bdeaa DW	270	tx->flags \|= DMA_CTRL_ACK;
	271	}
	272
0839875e	273	static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
636bdeaa	274	{
0839875e	275	return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
c13c8260 CL	276	}
c13c8260 CL	277
7405f74b DW	278	#define first_dma_cap(mask) __first_dma_cap(&(mask))
7405f74b DW	279	static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
c13c8260	280	{
7405f74b DW	281	return min_t(int, DMA_TX_TYPE_END,
	282	find_first_bit(srcp->bits, DMA_TX_TYPE_END));
	283	}
c13c8260	284
7405f74b DW	285	#define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
	286	static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
	287	{
	288	return min_t(int, DMA_TX_TYPE_END,
	289	find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
c13c8260 CL	290	}
c13c8260 CL	291
7405f74b DW	292	#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
	293	static inline void
	294	__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
c13c8260	295	{
7405f74b DW	296	set_bit(tx_type, dstp->bits);
7405f74b DW	297	}
c13c8260	298
33df8ca0 DW	299	#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
	300	static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
	301	{
	302	bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
	303	}
	304
7405f74b DW	305	#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
	306	static inline int
	307	__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
	308	{
	309	return test_bit(tx_type, srcp->bits);
c13c8260 CL	310	}
c13c8260 CL	311
7405f74b DW	312	#define for_each_dma_cap_mask(cap, mask) \
	313	for ((cap) = first_dma_cap(mask); \
	314	(cap) < DMA_TX_TYPE_END; \
	315	(cap) = next_dma_cap((cap), (mask)))
	316
c13c8260	317	/**
7405f74b	318	* dma_async_issue_pending - flush pending transactions to HW
fe4ada2d	319	* @chan: target DMA channel
c13c8260 CL	320	*
	321	* This allows drivers to push copies to HW in batches,
	322	* reducing MMIO writes where possible.
	323	*/
7405f74b	324	static inline void dma_async_issue_pending(struct dma_chan *chan)
c13c8260	325	{
ec8670f1	326	chan->device->device_issue_pending(chan);
c13c8260 CL	327	}
c13c8260 CL	328
7405f74b DW	329	#define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
7405f74b DW	330
c13c8260	331	/**
7405f74b	332	* dma_async_is_tx_complete - poll for transaction completion
c13c8260 CL	333	* @chan: DMA channel
	334	* @cookie: transaction identifier to check status of
	335	* @last: returns last completed cookie, can be NULL
	336	* @used: returns last issued cookie, can be NULL
	337	*
	338	* If @last and @used are passed in, upon return they reflect the driver
	339	* internal state and can be used with dma_async_is_complete() to check
	340	* the status of multiple cookies without re-checking hardware state.
	341	*/
7405f74b	342	static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
c13c8260 CL	343	dma_cookie_t cookie, dma_cookie_t last, dma_cookie_t used)
c13c8260 CL	344	{
7405f74b	345	return chan->device->device_is_tx_complete(chan, cookie, last, used);
c13c8260 CL	346	}
c13c8260 CL	347
7405f74b DW	348	#define dma_async_memcpy_complete(chan, cookie, last, used)\
	349	dma_async_is_tx_complete(chan, cookie, last, used)
	350
c13c8260 CL	351	/**
	352	* dma_async_is_complete - test a cookie against chan state
	353	* @cookie: transaction identifier to test status of
	354	* @last_complete: last know completed transaction
	355	* @last_used: last cookie value handed out
	356	*
	357	* dma_async_is_complete() is used in dma_async_memcpy_complete()
8a5703f8	358	* the test logic is separated for lightweight testing of multiple cookies
c13c8260 CL	359	*/
	360	static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
	361	dma_cookie_t last_complete, dma_cookie_t last_used)
	362	{
	363	if (last_complete <= last_used) {
	364	if ((cookie <= last_complete) \|\| (cookie > last_used))
	365	return DMA_SUCCESS;
	366	} else {
	367	if ((cookie <= last_complete) && (cookie > last_used))
	368	return DMA_SUCCESS;
	369	}
	370	return DMA_IN_PROGRESS;
	371	}
	372
7405f74b	373	enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
07f2211e DW	374	#ifdef CONFIG_DMA_ENGINE
	375	enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
	376	#else
	377	static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
	378	{
	379	return DMA_SUCCESS;
	380	}
	381	#endif
c13c8260 CL	382
	383	/* --- DMA device --- */
	384
	385	int dma_async_device_register(struct dma_device *device);
	386	void dma_async_device_unregister(struct dma_device *device);
07f2211e	387	void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
bec08513	388	struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
2ba05622	389	void dma_issue_pending_all(void);
59b5ec21 DW	390	#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
	391	struct dma_chan __dma_request_channel(dma_cap_mask_t mask, dma_filter_fn fn, void *fn_param);
	392	void dma_release_channel(struct dma_chan *chan);
c13c8260	393
de5506e1 CL	394	/* --- Helper iov-locking functions --- */
	395
	396	struct dma_page_list {
b2ddb901	397	char __user *base_address;
de5506e1 CL	398	int nr_pages;
	399	struct page **pages;
	400	};
	401
	402	struct dma_pinned_list {
	403	int nr_iovecs;
	404	struct dma_page_list page_list[0];
	405	};
	406
	407	struct dma_pinned_list dma_pin_iovec_pages(struct iovec iov, size_t len);
	408	void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
	409
	410	dma_cookie_t dma_memcpy_to_iovec(struct dma_chan chan, struct iovec iov,
	411	struct dma_pinned_list pinned_list, unsigned char kdata, size_t len);
	412	dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan chan, struct iovec iov,
	413	struct dma_pinned_list pinned_list, struct page page,
	414	unsigned int offset, size_t len);
	415
c13c8260	416	#endif /* DMAENGINE_H */