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c13c8260 CL |
1 | /* |
2 | * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the Free | |
6 | * Software Foundation; either version 2 of the License, or (at your option) | |
7 | * any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
16 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called COPYING. | |
20 | */ | |
21 | #ifndef DMAENGINE_H | |
22 | #define DMAENGINE_H | |
1c0f16e5 | 23 | |
c13c8260 CL |
24 | #include <linux/device.h> |
25 | #include <linux/uio.h> | |
26 | #include <linux/kref.h> | |
27 | #include <linux/completion.h> | |
28 | #include <linux/rcupdate.h> | |
7405f74b | 29 | #include <linux/dma-mapping.h> |
c13c8260 CL |
30 | |
31 | /** | |
fd3f8984 | 32 | * enum dma_state - resource PNP/power management state |
c13c8260 CL |
33 | * @DMA_RESOURCE_SUSPEND: DMA device going into low power state |
34 | * @DMA_RESOURCE_RESUME: DMA device returning to full power | |
d379b01e | 35 | * @DMA_RESOURCE_AVAILABLE: DMA device available to the system |
c13c8260 CL |
36 | * @DMA_RESOURCE_REMOVED: DMA device removed from the system |
37 | */ | |
d379b01e | 38 | enum dma_state { |
c13c8260 CL |
39 | DMA_RESOURCE_SUSPEND, |
40 | DMA_RESOURCE_RESUME, | |
d379b01e | 41 | DMA_RESOURCE_AVAILABLE, |
c13c8260 CL |
42 | DMA_RESOURCE_REMOVED, |
43 | }; | |
44 | ||
d379b01e DW |
45 | /** |
46 | * enum dma_state_client - state of the channel in the client | |
47 | * @DMA_ACK: client would like to use, or was using this channel | |
48 | * @DMA_DUP: client has already seen this channel, or is not using this channel | |
49 | * @DMA_NAK: client does not want to see any more channels | |
50 | */ | |
51 | enum dma_state_client { | |
52 | DMA_ACK, | |
53 | DMA_DUP, | |
54 | DMA_NAK, | |
55 | }; | |
56 | ||
c13c8260 | 57 | /** |
fe4ada2d | 58 | * typedef dma_cookie_t - an opaque DMA cookie |
c13c8260 CL |
59 | * |
60 | * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code | |
61 | */ | |
62 | typedef s32 dma_cookie_t; | |
63 | ||
64 | #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0) | |
65 | ||
66 | /** | |
67 | * enum dma_status - DMA transaction status | |
68 | * @DMA_SUCCESS: transaction completed successfully | |
69 | * @DMA_IN_PROGRESS: transaction not yet processed | |
70 | * @DMA_ERROR: transaction failed | |
71 | */ | |
72 | enum dma_status { | |
73 | DMA_SUCCESS, | |
74 | DMA_IN_PROGRESS, | |
75 | DMA_ERROR, | |
76 | }; | |
77 | ||
7405f74b DW |
78 | /** |
79 | * enum dma_transaction_type - DMA transaction types/indexes | |
80 | */ | |
81 | enum dma_transaction_type { | |
82 | DMA_MEMCPY, | |
83 | DMA_XOR, | |
84 | DMA_PQ_XOR, | |
85 | DMA_DUAL_XOR, | |
86 | DMA_PQ_UPDATE, | |
87 | DMA_ZERO_SUM, | |
88 | DMA_PQ_ZERO_SUM, | |
89 | DMA_MEMSET, | |
90 | DMA_MEMCPY_CRC32C, | |
91 | DMA_INTERRUPT, | |
59b5ec21 | 92 | DMA_PRIVATE, |
dc0ee643 | 93 | DMA_SLAVE, |
7405f74b DW |
94 | }; |
95 | ||
96 | /* last transaction type for creation of the capabilities mask */ | |
dc0ee643 HS |
97 | #define DMA_TX_TYPE_END (DMA_SLAVE + 1) |
98 | ||
7405f74b | 99 | |
d4c56f97 | 100 | /** |
636bdeaa DW |
101 | * enum dma_ctrl_flags - DMA flags to augment operation preparation, |
102 | * control completion, and communicate status. | |
d4c56f97 DW |
103 | * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of |
104 | * this transaction | |
636bdeaa DW |
105 | * @DMA_CTRL_ACK - the descriptor cannot be reused until the client |
106 | * acknowledges receipt, i.e. has has a chance to establish any | |
107 | * dependency chains | |
e1d181ef DW |
108 | * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s) |
109 | * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s) | |
d4c56f97 | 110 | */ |
636bdeaa | 111 | enum dma_ctrl_flags { |
d4c56f97 | 112 | DMA_PREP_INTERRUPT = (1 << 0), |
636bdeaa | 113 | DMA_CTRL_ACK = (1 << 1), |
e1d181ef DW |
114 | DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2), |
115 | DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3), | |
d4c56f97 DW |
116 | }; |
117 | ||
7405f74b DW |
118 | /** |
119 | * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. | |
120 | * See linux/cpumask.h | |
121 | */ | |
122 | typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; | |
123 | ||
c13c8260 CL |
124 | /** |
125 | * struct dma_chan_percpu - the per-CPU part of struct dma_chan | |
126 | * @refcount: local_t used for open-coded "bigref" counting | |
127 | * @memcpy_count: transaction counter | |
128 | * @bytes_transferred: byte counter | |
129 | */ | |
130 | ||
131 | struct dma_chan_percpu { | |
c13c8260 CL |
132 | /* stats */ |
133 | unsigned long memcpy_count; | |
134 | unsigned long bytes_transferred; | |
135 | }; | |
136 | ||
137 | /** | |
138 | * struct dma_chan - devices supply DMA channels, clients use them | |
fe4ada2d | 139 | * @device: ptr to the dma device who supplies this channel, always !%NULL |
c13c8260 | 140 | * @cookie: last cookie value returned to client |
fe4ada2d RD |
141 | * @chan_id: channel ID for sysfs |
142 | * @class_dev: class device for sysfs | |
c13c8260 | 143 | * @refcount: kref, used in "bigref" slow-mode |
fe4ada2d RD |
144 | * @slow_ref: indicates that the DMA channel is free |
145 | * @rcu: the DMA channel's RCU head | |
c13c8260 CL |
146 | * @device_node: used to add this to the device chan list |
147 | * @local: per-cpu pointer to a struct dma_chan_percpu | |
7cc5bf9a | 148 | * @client-count: how many clients are using this channel |
bec08513 | 149 | * @table_count: number of appearances in the mem-to-mem allocation table |
c13c8260 CL |
150 | */ |
151 | struct dma_chan { | |
c13c8260 CL |
152 | struct dma_device *device; |
153 | dma_cookie_t cookie; | |
154 | ||
155 | /* sysfs */ | |
156 | int chan_id; | |
891f78ea | 157 | struct device dev; |
c13c8260 CL |
158 | |
159 | struct kref refcount; | |
160 | int slow_ref; | |
161 | struct rcu_head rcu; | |
162 | ||
c13c8260 CL |
163 | struct list_head device_node; |
164 | struct dma_chan_percpu *local; | |
7cc5bf9a | 165 | int client_count; |
bec08513 | 166 | int table_count; |
c13c8260 CL |
167 | }; |
168 | ||
891f78ea | 169 | #define to_dma_chan(p) container_of(p, struct dma_chan, dev) |
d379b01e | 170 | |
c13c8260 CL |
171 | void dma_chan_cleanup(struct kref *kref); |
172 | ||
c13c8260 CL |
173 | /* |
174 | * typedef dma_event_callback - function pointer to a DMA event callback | |
d379b01e DW |
175 | * For each channel added to the system this routine is called for each client. |
176 | * If the client would like to use the channel it returns '1' to signal (ack) | |
177 | * the dmaengine core to take out a reference on the channel and its | |
178 | * corresponding device. A client must not 'ack' an available channel more | |
179 | * than once. When a channel is removed all clients are notified. If a client | |
180 | * is using the channel it must 'ack' the removal. A client must not 'ack' a | |
181 | * removed channel more than once. | |
182 | * @client - 'this' pointer for the client context | |
183 | * @chan - channel to be acted upon | |
184 | * @state - available or removed | |
c13c8260 | 185 | */ |
d379b01e DW |
186 | struct dma_client; |
187 | typedef enum dma_state_client (*dma_event_callback) (struct dma_client *client, | |
188 | struct dma_chan *chan, enum dma_state state); | |
c13c8260 | 189 | |
59b5ec21 DW |
190 | /** |
191 | * typedef dma_filter_fn - callback filter for dma_request_channel | |
192 | * @chan: channel to be reviewed | |
193 | * @filter_param: opaque parameter passed through dma_request_channel | |
194 | * | |
195 | * When this optional parameter is specified in a call to dma_request_channel a | |
196 | * suitable channel is passed to this routine for further dispositioning before | |
197 | * being returned. Where 'suitable' indicates a non-busy channel that | |
198 | * satisfies the given capability mask. | |
199 | */ | |
200 | typedef enum dma_state_client (*dma_filter_fn)(struct dma_chan *chan, void *filter_param); | |
201 | ||
c13c8260 CL |
202 | /** |
203 | * struct dma_client - info on the entity making use of DMA services | |
204 | * @event_callback: func ptr to call when something happens | |
d379b01e DW |
205 | * @cap_mask: only return channels that satisfy the requested capabilities |
206 | * a value of zero corresponds to any capability | |
dc0ee643 HS |
207 | * @slave: data for preparing slave transfer. Must be non-NULL iff the |
208 | * DMA_SLAVE capability is requested. | |
c13c8260 CL |
209 | * @global_node: list_head for global dma_client_list |
210 | */ | |
211 | struct dma_client { | |
212 | dma_event_callback event_callback; | |
d379b01e | 213 | dma_cap_mask_t cap_mask; |
c13c8260 CL |
214 | struct list_head global_node; |
215 | }; | |
216 | ||
7405f74b DW |
217 | typedef void (*dma_async_tx_callback)(void *dma_async_param); |
218 | /** | |
219 | * struct dma_async_tx_descriptor - async transaction descriptor | |
220 | * ---dma generic offload fields--- | |
221 | * @cookie: tracking cookie for this transaction, set to -EBUSY if | |
222 | * this tx is sitting on a dependency list | |
636bdeaa DW |
223 | * @flags: flags to augment operation preparation, control completion, and |
224 | * communicate status | |
7405f74b DW |
225 | * @phys: physical address of the descriptor |
226 | * @tx_list: driver common field for operations that require multiple | |
227 | * descriptors | |
228 | * @chan: target channel for this operation | |
229 | * @tx_submit: set the prepared descriptor(s) to be executed by the engine | |
7405f74b DW |
230 | * @callback: routine to call after this operation is complete |
231 | * @callback_param: general parameter to pass to the callback routine | |
232 | * ---async_tx api specific fields--- | |
19242d72 | 233 | * @next: at completion submit this descriptor |
7405f74b | 234 | * @parent: pointer to the next level up in the dependency chain |
19242d72 | 235 | * @lock: protect the parent and next pointers |
7405f74b DW |
236 | */ |
237 | struct dma_async_tx_descriptor { | |
238 | dma_cookie_t cookie; | |
636bdeaa | 239 | enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ |
7405f74b DW |
240 | dma_addr_t phys; |
241 | struct list_head tx_list; | |
242 | struct dma_chan *chan; | |
243 | dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); | |
7405f74b DW |
244 | dma_async_tx_callback callback; |
245 | void *callback_param; | |
19242d72 | 246 | struct dma_async_tx_descriptor *next; |
7405f74b DW |
247 | struct dma_async_tx_descriptor *parent; |
248 | spinlock_t lock; | |
249 | }; | |
250 | ||
c13c8260 CL |
251 | /** |
252 | * struct dma_device - info on the entity supplying DMA services | |
253 | * @chancnt: how many DMA channels are supported | |
254 | * @channels: the list of struct dma_chan | |
255 | * @global_node: list_head for global dma_device_list | |
7405f74b DW |
256 | * @cap_mask: one or more dma_capability flags |
257 | * @max_xor: maximum number of xor sources, 0 if no capability | |
fe4ada2d RD |
258 | * @refcount: reference count |
259 | * @done: IO completion struct | |
260 | * @dev_id: unique device ID | |
7405f74b | 261 | * @dev: struct device reference for dma mapping api |
fe4ada2d RD |
262 | * @device_alloc_chan_resources: allocate resources and return the |
263 | * number of allocated descriptors | |
264 | * @device_free_chan_resources: release DMA channel's resources | |
7405f74b DW |
265 | * @device_prep_dma_memcpy: prepares a memcpy operation |
266 | * @device_prep_dma_xor: prepares a xor operation | |
267 | * @device_prep_dma_zero_sum: prepares a zero_sum operation | |
268 | * @device_prep_dma_memset: prepares a memset operation | |
269 | * @device_prep_dma_interrupt: prepares an end of chain interrupt operation | |
dc0ee643 HS |
270 | * @device_prep_slave_sg: prepares a slave dma operation |
271 | * @device_terminate_all: terminate all pending operations | |
7405f74b | 272 | * @device_issue_pending: push pending transactions to hardware |
c13c8260 CL |
273 | */ |
274 | struct dma_device { | |
275 | ||
276 | unsigned int chancnt; | |
277 | struct list_head channels; | |
278 | struct list_head global_node; | |
7405f74b DW |
279 | dma_cap_mask_t cap_mask; |
280 | int max_xor; | |
c13c8260 CL |
281 | |
282 | struct kref refcount; | |
283 | struct completion done; | |
284 | ||
285 | int dev_id; | |
7405f74b | 286 | struct device *dev; |
c13c8260 | 287 | |
848c536a HS |
288 | int (*device_alloc_chan_resources)(struct dma_chan *chan, |
289 | struct dma_client *client); | |
c13c8260 | 290 | void (*device_free_chan_resources)(struct dma_chan *chan); |
7405f74b DW |
291 | |
292 | struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( | |
0036731c | 293 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
d4c56f97 | 294 | size_t len, unsigned long flags); |
7405f74b | 295 | struct dma_async_tx_descriptor *(*device_prep_dma_xor)( |
0036731c | 296 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, |
d4c56f97 | 297 | unsigned int src_cnt, size_t len, unsigned long flags); |
7405f74b | 298 | struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)( |
0036731c | 299 | struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, |
d4c56f97 | 300 | size_t len, u32 *result, unsigned long flags); |
7405f74b | 301 | struct dma_async_tx_descriptor *(*device_prep_dma_memset)( |
0036731c | 302 | struct dma_chan *chan, dma_addr_t dest, int value, size_t len, |
d4c56f97 | 303 | unsigned long flags); |
7405f74b | 304 | struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( |
636bdeaa | 305 | struct dma_chan *chan, unsigned long flags); |
7405f74b | 306 | |
dc0ee643 HS |
307 | struct dma_async_tx_descriptor *(*device_prep_slave_sg)( |
308 | struct dma_chan *chan, struct scatterlist *sgl, | |
309 | unsigned int sg_len, enum dma_data_direction direction, | |
310 | unsigned long flags); | |
311 | void (*device_terminate_all)(struct dma_chan *chan); | |
312 | ||
7405f74b | 313 | enum dma_status (*device_is_tx_complete)(struct dma_chan *chan, |
c13c8260 CL |
314 | dma_cookie_t cookie, dma_cookie_t *last, |
315 | dma_cookie_t *used); | |
7405f74b | 316 | void (*device_issue_pending)(struct dma_chan *chan); |
c13c8260 CL |
317 | }; |
318 | ||
319 | /* --- public DMA engine API --- */ | |
320 | ||
209b84a8 DW |
321 | void dmaengine_get(void); |
322 | void dmaengine_put(void); | |
d379b01e | 323 | void dma_async_client_chan_request(struct dma_client *client); |
7405f74b DW |
324 | dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, |
325 | void *dest, void *src, size_t len); | |
326 | dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan, | |
327 | struct page *page, unsigned int offset, void *kdata, size_t len); | |
328 | dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan, | |
329 | struct page *dest_pg, unsigned int dest_off, struct page *src_pg, | |
330 | unsigned int src_off, size_t len); | |
331 | void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, | |
332 | struct dma_chan *chan); | |
c13c8260 | 333 | |
0839875e | 334 | static inline void async_tx_ack(struct dma_async_tx_descriptor *tx) |
7405f74b | 335 | { |
636bdeaa DW |
336 | tx->flags |= DMA_CTRL_ACK; |
337 | } | |
338 | ||
0839875e | 339 | static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx) |
636bdeaa | 340 | { |
0839875e | 341 | return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; |
c13c8260 CL |
342 | } |
343 | ||
7405f74b DW |
344 | #define first_dma_cap(mask) __first_dma_cap(&(mask)) |
345 | static inline int __first_dma_cap(const dma_cap_mask_t *srcp) | |
c13c8260 | 346 | { |
7405f74b DW |
347 | return min_t(int, DMA_TX_TYPE_END, |
348 | find_first_bit(srcp->bits, DMA_TX_TYPE_END)); | |
349 | } | |
c13c8260 | 350 | |
7405f74b DW |
351 | #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask)) |
352 | static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp) | |
353 | { | |
354 | return min_t(int, DMA_TX_TYPE_END, | |
355 | find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1)); | |
c13c8260 CL |
356 | } |
357 | ||
7405f74b DW |
358 | #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) |
359 | static inline void | |
360 | __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
c13c8260 | 361 | { |
7405f74b DW |
362 | set_bit(tx_type, dstp->bits); |
363 | } | |
c13c8260 | 364 | |
33df8ca0 DW |
365 | #define dma_cap_zero(mask) __dma_cap_zero(&(mask)) |
366 | static inline void __dma_cap_zero(dma_cap_mask_t *dstp) | |
367 | { | |
368 | bitmap_zero(dstp->bits, DMA_TX_TYPE_END); | |
369 | } | |
370 | ||
7405f74b DW |
371 | #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) |
372 | static inline int | |
373 | __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) | |
374 | { | |
375 | return test_bit(tx_type, srcp->bits); | |
c13c8260 CL |
376 | } |
377 | ||
7405f74b DW |
378 | #define for_each_dma_cap_mask(cap, mask) \ |
379 | for ((cap) = first_dma_cap(mask); \ | |
380 | (cap) < DMA_TX_TYPE_END; \ | |
381 | (cap) = next_dma_cap((cap), (mask))) | |
382 | ||
c13c8260 | 383 | /** |
7405f74b | 384 | * dma_async_issue_pending - flush pending transactions to HW |
fe4ada2d | 385 | * @chan: target DMA channel |
c13c8260 CL |
386 | * |
387 | * This allows drivers to push copies to HW in batches, | |
388 | * reducing MMIO writes where possible. | |
389 | */ | |
7405f74b | 390 | static inline void dma_async_issue_pending(struct dma_chan *chan) |
c13c8260 | 391 | { |
ec8670f1 | 392 | chan->device->device_issue_pending(chan); |
c13c8260 CL |
393 | } |
394 | ||
7405f74b DW |
395 | #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan) |
396 | ||
c13c8260 | 397 | /** |
7405f74b | 398 | * dma_async_is_tx_complete - poll for transaction completion |
c13c8260 CL |
399 | * @chan: DMA channel |
400 | * @cookie: transaction identifier to check status of | |
401 | * @last: returns last completed cookie, can be NULL | |
402 | * @used: returns last issued cookie, can be NULL | |
403 | * | |
404 | * If @last and @used are passed in, upon return they reflect the driver | |
405 | * internal state and can be used with dma_async_is_complete() to check | |
406 | * the status of multiple cookies without re-checking hardware state. | |
407 | */ | |
7405f74b | 408 | static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, |
c13c8260 CL |
409 | dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) |
410 | { | |
7405f74b | 411 | return chan->device->device_is_tx_complete(chan, cookie, last, used); |
c13c8260 CL |
412 | } |
413 | ||
7405f74b DW |
414 | #define dma_async_memcpy_complete(chan, cookie, last, used)\ |
415 | dma_async_is_tx_complete(chan, cookie, last, used) | |
416 | ||
c13c8260 CL |
417 | /** |
418 | * dma_async_is_complete - test a cookie against chan state | |
419 | * @cookie: transaction identifier to test status of | |
420 | * @last_complete: last know completed transaction | |
421 | * @last_used: last cookie value handed out | |
422 | * | |
423 | * dma_async_is_complete() is used in dma_async_memcpy_complete() | |
8a5703f8 | 424 | * the test logic is separated for lightweight testing of multiple cookies |
c13c8260 CL |
425 | */ |
426 | static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, | |
427 | dma_cookie_t last_complete, dma_cookie_t last_used) | |
428 | { | |
429 | if (last_complete <= last_used) { | |
430 | if ((cookie <= last_complete) || (cookie > last_used)) | |
431 | return DMA_SUCCESS; | |
432 | } else { | |
433 | if ((cookie <= last_complete) && (cookie > last_used)) | |
434 | return DMA_SUCCESS; | |
435 | } | |
436 | return DMA_IN_PROGRESS; | |
437 | } | |
438 | ||
7405f74b | 439 | enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); |
07f2211e DW |
440 | #ifdef CONFIG_DMA_ENGINE |
441 | enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); | |
442 | #else | |
443 | static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) | |
444 | { | |
445 | return DMA_SUCCESS; | |
446 | } | |
447 | #endif | |
c13c8260 CL |
448 | |
449 | /* --- DMA device --- */ | |
450 | ||
451 | int dma_async_device_register(struct dma_device *device); | |
452 | void dma_async_device_unregister(struct dma_device *device); | |
07f2211e | 453 | void dma_run_dependencies(struct dma_async_tx_descriptor *tx); |
bec08513 | 454 | struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); |
2ba05622 | 455 | void dma_issue_pending_all(void); |
59b5ec21 DW |
456 | #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y) |
457 | struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param); | |
458 | void dma_release_channel(struct dma_chan *chan); | |
c13c8260 | 459 | |
de5506e1 CL |
460 | /* --- Helper iov-locking functions --- */ |
461 | ||
462 | struct dma_page_list { | |
b2ddb901 | 463 | char __user *base_address; |
de5506e1 CL |
464 | int nr_pages; |
465 | struct page **pages; | |
466 | }; | |
467 | ||
468 | struct dma_pinned_list { | |
469 | int nr_iovecs; | |
470 | struct dma_page_list page_list[0]; | |
471 | }; | |
472 | ||
473 | struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len); | |
474 | void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list); | |
475 | ||
476 | dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov, | |
477 | struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len); | |
478 | dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov, | |
479 | struct dma_pinned_list *pinned_list, struct page *page, | |
480 | unsigned int offset, size_t len); | |
481 | ||
c13c8260 | 482 | #endif /* DMAENGINE_H */ |