[linux-2.6-block.git] / include / kvm / arm_vgic.h

/*
 * Copyright (C) 2012 ARM Ltd.
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */

#ifndef __ASM_ARM_KVM_VGIC_H
#define __ASM_ARM_KVM_VGIC_H

#include <linux/kernel.h>
#include <linux/kvm.h>
#include <linux/irqreturn.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <kvm/iodev.h>

#define VGIC_NR_IRQS_LEGACY	256
#define VGIC_NR_SGIS		16
#define VGIC_NR_PPIS		16
#define VGIC_NR_PRIVATE_IRQS	(VGIC_NR_SGIS + VGIC_NR_PPIS)

#define VGIC_V2_MAX_LRS		(1 << 6)
#define VGIC_V3_MAX_LRS		16
#define VGIC_MAX_IRQS		1024
#define VGIC_V2_MAX_CPUS	8
#define VGIC_V3_MAX_CPUS	255

#if (VGIC_NR_IRQS_LEGACY & 31)
#error "VGIC_NR_IRQS must be a multiple of 32"
#endif

#if (VGIC_NR_IRQS_LEGACY > VGIC_MAX_IRQS)
#error "VGIC_NR_IRQS must be <= 1024"
#endif

/*
 * The GIC distributor registers describing interrupts have two parts:
 * - 32 per-CPU interrupts (SGI + PPI)
 * - a bunch of shared interrupts (SPI)
 */
struct vgic_bitmap {
	/*
	 * - One UL per VCPU for private interrupts (assumes UL is at
	 *   least 32 bits)
	 * - As many UL as necessary for shared interrupts.
	 *
	 * The private interrupts are accessed via the "private"
	 * field, one UL per vcpu (the state for vcpu n is in
	 * private[n]). The shared interrupts are accessed via the
	 * "shared" pointer (IRQn state is at bit n-32 in the bitmap).
	 */
	unsigned long *private;
	unsigned long *shared;
};

struct vgic_bytemap {
	/*
	 * - 8 u32 per VCPU for private interrupts
	 * - As many u32 as necessary for shared interrupts.
	 *
	 * The private interrupts are accessed via the "private"
	 * field, (the state for vcpu n is in private[n*8] to
	 * private[n*8 + 7]). The shared interrupts are accessed via
	 * the "shared" pointer (IRQn state is at byte (n-32)%4 of the
	 * shared[(n-32)/4] word).
	 */
	u32 *private;
	u32 *shared;
};

struct kvm_vcpu;

enum vgic_type {
	VGIC_V2,		/* Good ol' GICv2 */
	VGIC_V3,		/* New fancy GICv3 */
};

#define LR_STATE_PENDING	(1 << 0)
#define LR_STATE_ACTIVE		(1 << 1)
#define LR_STATE_MASK		(3 << 0)
#define LR_EOI_INT		(1 << 2)
#define LR_HW			(1 << 3)

struct vgic_lr {
	unsigned irq:10;
	union {
		unsigned hwirq:10;
		unsigned source:3;
	};
	unsigned state:4;
};

struct vgic_vmcr {
	u32	ctlr;
	u32	abpr;
	u32	bpr;
	u32	pmr;
};

struct vgic_ops {
	struct vgic_lr	(*get_lr)(const struct kvm_vcpu *, int);
	void	(*set_lr)(struct kvm_vcpu *, int, struct vgic_lr);
	u64	(*get_elrsr)(const struct kvm_vcpu *vcpu);
	u64	(*get_eisr)(const struct kvm_vcpu *vcpu);
	void	(*clear_eisr)(struct kvm_vcpu *vcpu);
	u32	(*get_interrupt_status)(const struct kvm_vcpu *vcpu);
	void	(*enable_underflow)(struct kvm_vcpu *vcpu);
	void	(*disable_underflow)(struct kvm_vcpu *vcpu);
	void	(*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
	void	(*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
	void	(*enable)(struct kvm_vcpu *vcpu);
};

struct vgic_params {
	/* vgic type */
	enum vgic_type	type;
	/* Physical address of vgic virtual cpu interface */
	phys_addr_t	vcpu_base;
	/* Number of list registers */
	u32		nr_lr;
	/* Interrupt number */
	unsigned int	maint_irq;
	/* Virtual control interface base address */
	void __iomem	*vctrl_base;
	int		max_gic_vcpus;
	/* Only needed for the legacy KVM_CREATE_IRQCHIP */
	bool		can_emulate_gicv2;
};

struct vgic_vm_ops {
	bool	(*queue_sgi)(struct kvm_vcpu *, int irq);
	void	(*add_sgi_source)(struct kvm_vcpu *, int irq, int source);
	int	(*init_model)(struct kvm *);
	int	(*map_resources)(struct kvm *, const struct vgic_params *);
};

struct vgic_io_device {
	gpa_t addr;
	int len;
	const struct vgic_io_range *reg_ranges;
	struct kvm_vcpu *redist_vcpu;
	struct kvm_io_device dev;
};

struct irq_phys_map {
	u32			virt_irq;
	u32			phys_irq;
	u32			irq;
};

struct irq_phys_map_entry {
	struct list_head	entry;
	struct rcu_head		rcu;
	struct irq_phys_map	map;
};

struct vgic_dist {
	spinlock_t		lock;
	bool			in_kernel;
	bool			ready;

	/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
	u32			vgic_model;

	int			nr_cpus;
	int			nr_irqs;

	/* Virtual control interface mapping */
	void __iomem		*vctrl_base;

	/* Distributor and vcpu interface mapping in the guest */
	phys_addr_t		vgic_dist_base;
	/* GICv2 and GICv3 use different mapped register blocks */
	union {
		phys_addr_t		vgic_cpu_base;
		phys_addr_t		vgic_redist_base;
	};

	/* Distributor enabled */
	u32			enabled;

	/* Interrupt enabled (one bit per IRQ) */
	struct vgic_bitmap	irq_enabled;

	/* Level-triggered interrupt external input is asserted */
	struct vgic_bitmap	irq_level;

	/*
	 * Interrupt state is pending on the distributor
	 */
	struct vgic_bitmap	irq_pending;

	/*
	 * Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered
	 * interrupts.  Essentially holds the state of the flip-flop in
	 * Figure 4-10 on page 4-101 in ARM IHI 0048B.b.
	 * Once set, it is only cleared for level-triggered interrupts on
	 * guest ACKs (when we queue it) or writes to GICD_ICPENDRn.
	 */
	struct vgic_bitmap	irq_soft_pend;

	/* Level-triggered interrupt queued on VCPU interface */
	struct vgic_bitmap	irq_queued;

	/* Interrupt was active when unqueue from VCPU interface */
	struct vgic_bitmap	irq_active;

	/* Interrupt priority. Not used yet. */
	struct vgic_bytemap	irq_priority;

	/* Level/edge triggered */
	struct vgic_bitmap	irq_cfg;

	/*
	 * Source CPU per SGI and target CPU:
	 *
	 * Each byte represent a SGI observable on a VCPU, each bit of
	 * this byte indicating if the corresponding VCPU has
	 * generated this interrupt. This is a GICv2 feature only.
	 *
	 * For VCPUn (n < 8), irq_sgi_sources[n*16] to [n*16 + 15] are
	 * the SGIs observable on VCPUn.
	 */
	u8			*irq_sgi_sources;

	/*
	 * Target CPU for each SPI:
	 *
	 * Array of available SPI, each byte indicating the target
	 * VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32].
	 */
	u8			*irq_spi_cpu;

	/*
	 * Reverse lookup of irq_spi_cpu for faster compute pending:
	 *
	 * Array of bitmaps, one per VCPU, describing if IRQn is
	 * routed to a particular VCPU.
	 */
	struct vgic_bitmap	*irq_spi_target;

	/* Target MPIDR for each IRQ (needed for GICv3 IROUTERn) only */
	u32			*irq_spi_mpidr;

	/* Bitmap indicating which CPU has something pending */
	unsigned long		*irq_pending_on_cpu;

	/* Bitmap indicating which CPU has active IRQs */
	unsigned long		*irq_active_on_cpu;

	struct vgic_vm_ops	vm_ops;
	struct vgic_io_device	dist_iodev;
	struct vgic_io_device	*redist_iodevs;

	/* Virtual irq to hwirq mapping */
	spinlock_t		irq_phys_map_lock;
	struct list_head	irq_phys_map_list;
};

struct vgic_v2_cpu_if {
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_misr;	/* Saved only */
	u64		vgic_eisr;	/* Saved only */
	u64		vgic_elrsr;	/* Saved only */
	u32		vgic_apr;
	u32		vgic_lr[VGIC_V2_MAX_LRS];
};

struct vgic_v3_cpu_if {
#ifdef CONFIG_KVM_ARM_VGIC_V3
	u32		vgic_hcr;
	u32		vgic_vmcr;
	u32		vgic_sre;	/* Restored only, change ignored */
	u32		vgic_misr;	/* Saved only */
	u32		vgic_eisr;	/* Saved only */
	u32		vgic_elrsr;	/* Saved only */
	u32		vgic_ap0r[4];
	u32		vgic_ap1r[4];
	u64		vgic_lr[VGIC_V3_MAX_LRS];
#endif
};

struct vgic_cpu {
	/* Pending/active/both interrupts on this VCPU */
	DECLARE_BITMAP(pending_percpu, VGIC_NR_PRIVATE_IRQS);
	DECLARE_BITMAP(active_percpu, VGIC_NR_PRIVATE_IRQS);
	DECLARE_BITMAP(pend_act_percpu, VGIC_NR_PRIVATE_IRQS);

	/* Pending/active/both shared interrupts, dynamically sized */
	unsigned long	*pending_shared;
	unsigned long   *active_shared;
	unsigned long   *pend_act_shared;

	/* Number of list registers on this CPU */
	int		nr_lr;

	/* CPU vif control registers for world switch */
	union {
		struct vgic_v2_cpu_if	vgic_v2;
		struct vgic_v3_cpu_if	vgic_v3;
	};

	/* Protected by the distributor's irq_phys_map_lock */
	struct list_head	irq_phys_map_list;

	u64		live_lrs;
};

#define LR_EMPTY	0xff

#define INT_STATUS_EOI		(1 << 0)
#define INT_STATUS_UNDERFLOW	(1 << 1)

struct kvm;
struct kvm_vcpu;

int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
int kvm_vgic_hyp_init(void);
int kvm_vgic_map_resources(struct kvm *kvm);
int kvm_vgic_get_max_vcpus(void);
void kvm_vgic_early_init(struct kvm *kvm);
int kvm_vgic_create(struct kvm *kvm, u32 type);
void kvm_vgic_destroy(struct kvm *kvm);
void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
			bool level);
int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid,
			       struct irq_phys_map *map, bool level);
void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
struct irq_phys_map *kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu,
					   int virt_irq, int irq);
int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, struct irq_phys_map *map);
bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, struct irq_phys_map *map);

#define irqchip_in_kernel(k)	(!!((k)->arch.vgic.in_kernel))
#define vgic_initialized(k)	(!!((k)->arch.vgic.nr_cpus))
#define vgic_ready(k)		((k)->arch.vgic.ready)

int vgic_v2_probe(struct device_node *vgic_node,
		  const struct vgic_ops **ops,
		  const struct vgic_params **params);
#ifdef CONFIG_KVM_ARM_VGIC_V3
int vgic_v3_probe(struct device_node *vgic_node,
		  const struct vgic_ops **ops,
		  const struct vgic_params **params);
#else
static inline int vgic_v3_probe(struct device_node *vgic_node,
				const struct vgic_ops **ops,
				const struct vgic_params **params)
{
	return -ENODEV;
}
#endif

#endif
Commit	Line	Data
1a89dd91 MZ	1	/*
	2	* Copyright (C) 2012 ARM Ltd.
	3	* Author: Marc Zyngier <marc.zyngier@arm.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*/
	18
	19	#ifndef __ASM_ARM_KVM_VGIC_H
	20	#define __ASM_ARM_KVM_VGIC_H
	21
b47ef92a MZ	22	#include <linux/kernel.h>
b47ef92a MZ	23	#include <linux/kvm.h>
b47ef92a MZ	24	#include <linux/irqreturn.h>
	25	#include <linux/spinlock.h>
	26	#include <linux/types.h>
6777f77f	27	#include <kvm/iodev.h>
1a89dd91	28
5fb66da6	29	#define VGIC_NR_IRQS_LEGACY 256
b47ef92a MZ	30	#define VGIC_NR_SGIS 16
	31	#define VGIC_NR_PPIS 16
	32	#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
8f186d52 MZ	33
8f186d52 MZ	34	#define VGIC_V2_MAX_LRS (1 << 6)
b2fb1c0d	35	#define VGIC_V3_MAX_LRS 16
c3c91836	36	#define VGIC_MAX_IRQS 1024
3caa2d8c	37	#define VGIC_V2_MAX_CPUS 8
ef748917	38	#define VGIC_V3_MAX_CPUS 255
b47ef92a	39
5fb66da6	40	#if (VGIC_NR_IRQS_LEGACY & 31)
b47ef92a MZ	41	#error "VGIC_NR_IRQS must be a multiple of 32"
	42	#endif
	43
5fb66da6	44	#if (VGIC_NR_IRQS_LEGACY > VGIC_MAX_IRQS)
b47ef92a MZ	45	#error "VGIC_NR_IRQS must be <= 1024"
	46	#endif
	47
	48	/*
	49	* The GIC distributor registers describing interrupts have two parts:
	50	* - 32 per-CPU interrupts (SGI + PPI)
	51	* - a bunch of shared interrupts (SPI)
	52	*/
	53	struct vgic_bitmap {
c1bfb577 MZ	54	/*
	55	* - One UL per VCPU for private interrupts (assumes UL is at
	56	* least 32 bits)
	57	* - As many UL as necessary for shared interrupts.
	58	*
	59	* The private interrupts are accessed via the "private"
	60	* field, one UL per vcpu (the state for vcpu n is in
	61	* private[n]). The shared interrupts are accessed via the
	62	* "shared" pointer (IRQn state is at bit n-32 in the bitmap).
	63	*/
	64	unsigned long *private;
	65	unsigned long *shared;
b47ef92a MZ	66	};
	67
	68	struct vgic_bytemap {
c1bfb577 MZ	69	/*
	70	* - 8 u32 per VCPU for private interrupts
	71	* - As many u32 as necessary for shared interrupts.
	72	*
	73	* The private interrupts are accessed via the "private"
	74	* field, (the state for vcpu n is in private[n*8] to
	75	* private[n*8 + 7]). The shared interrupts are accessed via
	76	* the "shared" pointer (IRQn state is at byte (n-32)%4 of the
	77	* shared[(n-32)/4] word).
	78	*/
	79	u32 *private;
	80	u32 *shared;
b47ef92a MZ	81	};
b47ef92a MZ	82
8d5c6b06 MZ	83	struct kvm_vcpu;
8d5c6b06 MZ	84
1a9b1305 MZ	85	enum vgic_type {
1a9b1305 MZ	86	VGIC_V2, /* Good ol' GICv2 */
b2fb1c0d	87	VGIC_V3, /* New fancy GICv3 */
1a9b1305 MZ	88	};
1a9b1305 MZ	89
8d5c6b06 MZ	90	#define LR_STATE_PENDING (1 << 0)
	91	#define LR_STATE_ACTIVE (1 << 1)
	92	#define LR_STATE_MASK (3 << 0)
	93	#define LR_EOI_INT (1 << 2)
32d2d801	94	#define LR_HW (1 << 3)
8d5c6b06 MZ	95
8d5c6b06 MZ	96	struct vgic_lr {
32d2d801 MZ	97	unsigned irq:10;
	98	union {
	99	unsigned hwirq:10;
	100	unsigned source:3;
	101	};
	102	unsigned state:4;
8d5c6b06 MZ	103	};
8d5c6b06 MZ	104
beee38b9 MZ	105	struct vgic_vmcr {
	106	u32 ctlr;
	107	u32 abpr;
	108	u32 bpr;
	109	u32 pmr;
	110	};
	111
8d5c6b06 MZ	112	struct vgic_ops {
	113	struct vgic_lr (get_lr)(const struct kvm_vcpu , int);
	114	void (set_lr)(struct kvm_vcpu , int, struct vgic_lr);
69bb2c9f	115	u64 (get_elrsr)(const struct kvm_vcpu vcpu);
8d6a0313	116	u64 (get_eisr)(const struct kvm_vcpu vcpu);
ae705930	117	void (clear_eisr)(struct kvm_vcpu vcpu);
495dd859	118	u32 (get_interrupt_status)(const struct kvm_vcpu vcpu);
909d9b50 MZ	119	void (enable_underflow)(struct kvm_vcpu vcpu);
909d9b50 MZ	120	void (disable_underflow)(struct kvm_vcpu vcpu);
beee38b9 MZ	121	void (get_vmcr)(struct kvm_vcpu vcpu, struct vgic_vmcr *vmcr);
beee38b9 MZ	122	void (set_vmcr)(struct kvm_vcpu vcpu, struct vgic_vmcr *vmcr);
da8dafd1	123	void (enable)(struct kvm_vcpu vcpu);
8d5c6b06 MZ	124	};
8d5c6b06 MZ	125
ca85f623	126	struct vgic_params {
1a9b1305 MZ	127	/* vgic type */
1a9b1305 MZ	128	enum vgic_type type;
ca85f623 MZ	129	/* Physical address of vgic virtual cpu interface */
	130	phys_addr_t vcpu_base;
	131	/* Number of list registers */
	132	u32 nr_lr;
	133	/* Interrupt number */
	134	unsigned int maint_irq;
	135	/* Virtual control interface base address */
	136	void __iomem *vctrl_base;
3caa2d8c	137	int max_gic_vcpus;
b5d84ff6 AP	138	/* Only needed for the legacy KVM_CREATE_IRQCHIP */
b5d84ff6 AP	139	bool can_emulate_gicv2;
ca85f623 MZ	140	};
ca85f623 MZ	141
b26e5fda	142	struct vgic_vm_ops {
b26e5fda AP	143	bool (queue_sgi)(struct kvm_vcpu , int irq);
	144	void (add_sgi_source)(struct kvm_vcpu , int irq, int source);
	145	int (init_model)(struct kvm );
	146	int (map_resources)(struct kvm , const struct vgic_params *);
	147	};
	148
6777f77f AP	149	struct vgic_io_device {
	150	gpa_t addr;
	151	int len;
	152	const struct vgic_io_range *reg_ranges;
	153	struct kvm_vcpu *redist_vcpu;
	154	struct kvm_io_device dev;
	155	};
	156
6c3d63c9 MZ	157	struct irq_phys_map {
	158	u32 virt_irq;
	159	u32 phys_irq;
	160	u32 irq;
6c3d63c9 MZ	161	};
	162
	163	struct irq_phys_map_entry {
	164	struct list_head entry;
	165	struct rcu_head rcu;
	166	struct irq_phys_map map;
	167	};
	168
1a89dd91	169	struct vgic_dist {
b47ef92a	170	spinlock_t lock;
f982cf4e	171	bool in_kernel;
01ac5e34	172	bool ready;
b47ef92a	173
59892136 AP	174	/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
	175	u32 vgic_model;
	176
c1bfb577 MZ	177	int nr_cpus;
	178	int nr_irqs;
	179
b47ef92a MZ	180	/* Virtual control interface mapping */
	181	void __iomem *vctrl_base;
	182
330690cd CD	183	/* Distributor and vcpu interface mapping in the guest */
330690cd CD	184	phys_addr_t vgic_dist_base;
a0675c25 AP	185	/* GICv2 and GICv3 use different mapped register blocks */
	186	union {
	187	phys_addr_t vgic_cpu_base;
	188	phys_addr_t vgic_redist_base;
	189	};
b47ef92a MZ	190
	191	/* Distributor enabled */
	192	u32 enabled;
	193
	194	/* Interrupt enabled (one bit per IRQ) */
	195	struct vgic_bitmap irq_enabled;
	196
faa1b46c CD	197	/* Level-triggered interrupt external input is asserted */
	198	struct vgic_bitmap irq_level;
	199
	200	/*
	201	* Interrupt state is pending on the distributor
	202	*/
227844f5	203	struct vgic_bitmap irq_pending;
b47ef92a	204
faa1b46c CD	205	/*
	206	* Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered
	207	* interrupts. Essentially holds the state of the flip-flop in
	208	* Figure 4-10 on page 4-101 in ARM IHI 0048B.b.
	209	* Once set, it is only cleared for level-triggered interrupts on
	210	* guest ACKs (when we queue it) or writes to GICD_ICPENDRn.
	211	*/
	212	struct vgic_bitmap irq_soft_pend;
	213
dbf20f9d CD	214	/* Level-triggered interrupt queued on VCPU interface */
dbf20f9d CD	215	struct vgic_bitmap irq_queued;
b47ef92a	216
47a98b15 CD	217	/* Interrupt was active when unqueue from VCPU interface */
	218	struct vgic_bitmap irq_active;
	219
b47ef92a MZ	220	/* Interrupt priority. Not used yet. */
	221	struct vgic_bytemap irq_priority;
	222
	223	/* Level/edge triggered */
	224	struct vgic_bitmap irq_cfg;
	225
c1bfb577 MZ	226	/*
	227	* Source CPU per SGI and target CPU:
	228	*
	229	* Each byte represent a SGI observable on a VCPU, each bit of
	230	* this byte indicating if the corresponding VCPU has
	231	* generated this interrupt. This is a GICv2 feature only.
	232	*
	233	* For VCPUn (n < 8), irq_sgi_sources[n16] to [n16 + 15] are
	234	* the SGIs observable on VCPUn.
	235	*/
	236	u8 *irq_sgi_sources;
b47ef92a	237
c1bfb577 MZ	238	/*
	239	* Target CPU for each SPI:
	240	*
	241	* Array of available SPI, each byte indicating the target
	242	* VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32].
	243	*/
	244	u8 *irq_spi_cpu;
	245
	246	/*
	247	* Reverse lookup of irq_spi_cpu for faster compute pending:
	248	*
	249	* Array of bitmaps, one per VCPU, describing if IRQn is
	250	* routed to a particular VCPU.
	251	*/
	252	struct vgic_bitmap *irq_spi_target;
b47ef92a	253
a0675c25 AP	254	/* Target MPIDR for each IRQ (needed for GICv3 IROUTERn) only */
	255	u32 *irq_spi_mpidr;
	256
b47ef92a	257	/* Bitmap indicating which CPU has something pending */
c1bfb577	258	unsigned long *irq_pending_on_cpu;
b26e5fda	259
47a98b15 CD	260	/* Bitmap indicating which CPU has active IRQs */
	261	unsigned long *irq_active_on_cpu;
	262
b26e5fda	263	struct vgic_vm_ops vm_ops;
a9cf86f6	264	struct vgic_io_device dist_iodev;
fb8f61ab	265	struct vgic_io_device *redist_iodevs;
6c3d63c9 MZ	266
	267	/* Virtual irq to hwirq mapping */
	268	spinlock_t irq_phys_map_lock;
	269	struct list_head irq_phys_map_list;
1a89dd91 MZ	270	};
1a89dd91 MZ	271
eede821d MZ	272	struct vgic_v2_cpu_if {
	273	u32 vgic_hcr;
	274	u32 vgic_vmcr;
	275	u32 vgic_misr; /* Saved only */
2df36a5d CD	276	u64 vgic_eisr; /* Saved only */
2df36a5d CD	277	u64 vgic_elrsr; /* Saved only */
eede821d	278	u32 vgic_apr;
8f186d52	279	u32 vgic_lr[VGIC_V2_MAX_LRS];
eede821d MZ	280	};
eede821d MZ	281
b2fb1c0d	282	struct vgic_v3_cpu_if {
4f64cb65	283	#ifdef CONFIG_KVM_ARM_VGIC_V3
b2fb1c0d MZ	284	u32 vgic_hcr;
b2fb1c0d MZ	285	u32 vgic_vmcr;
2f5fa41a	286	u32 vgic_sre; /* Restored only, change ignored */
b2fb1c0d MZ	287	u32 vgic_misr; /* Saved only */
	288	u32 vgic_eisr; /* Saved only */
	289	u32 vgic_elrsr; /* Saved only */
	290	u32 vgic_ap0r[4];
	291	u32 vgic_ap1r[4];
	292	u64 vgic_lr[VGIC_V3_MAX_LRS];
	293	#endif
	294	};
	295
1a89dd91	296	struct vgic_cpu {
47a98b15	297	/* Pending/active/both interrupts on this VCPU */
5fdf876d MM	298	DECLARE_BITMAP(pending_percpu, VGIC_NR_PRIVATE_IRQS);
	299	DECLARE_BITMAP(active_percpu, VGIC_NR_PRIVATE_IRQS);
	300	DECLARE_BITMAP(pend_act_percpu, VGIC_NR_PRIVATE_IRQS);
47a98b15 CD	301
47a98b15 CD	302	/* Pending/active/both shared interrupts, dynamically sized */
c1bfb577	303	unsigned long *pending_shared;
47a98b15 CD	304	unsigned long *active_shared;
47a98b15 CD	305	unsigned long *pend_act_shared;
9d949dce	306
9d949dce MZ	307	/* Number of list registers on this CPU */
	308	int nr_lr;
	309
	310	/* CPU vif control registers for world switch */
eede821d MZ	311	union {
eede821d MZ	312	struct vgic_v2_cpu_if vgic_v2;
b2fb1c0d	313	struct vgic_v3_cpu_if vgic_v3;
eede821d	314	};
6c3d63c9 MZ	315
	316	/* Protected by the distributor's irq_phys_map_lock */
	317	struct list_head irq_phys_map_list;
59f00ff9 MZ	318
59f00ff9 MZ	319	u64 live_lrs;
1a89dd91 MZ	320	};
1a89dd91 MZ	321
9d949dce MZ	322	#define LR_EMPTY 0xff
9d949dce MZ	323
495dd859 MZ	324	#define INT_STATUS_EOI (1 << 0)
	325	#define INT_STATUS_UNDERFLOW (1 << 1)
	326
1a89dd91 MZ	327	struct kvm;
1a89dd91 MZ	328	struct kvm_vcpu;
1a89dd91	329
ce01e4e8	330	int kvm_vgic_addr(struct kvm kvm, unsigned long type, u64 addr, bool write);
01ac5e34	331	int kvm_vgic_hyp_init(void);
6d3cfbe2	332	int kvm_vgic_map_resources(struct kvm *kvm);
3caa2d8c	333	int kvm_vgic_get_max_vcpus(void);
6c3d63c9	334	void kvm_vgic_early_init(struct kvm *kvm);
59892136	335	int kvm_vgic_create(struct kvm *kvm, u32 type);
c1bfb577	336	void kvm_vgic_destroy(struct kvm *kvm);
6c3d63c9	337	void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
c1bfb577	338	void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
9d949dce MZ	339	void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
9d949dce MZ	340	void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
5863c2ce MZ	341	int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
5863c2ce MZ	342	bool level);
773299a5 MZ	343	int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid,
773299a5 MZ	344	struct irq_phys_map *map, bool level);
6d52f35a	345	void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
9d949dce	346	int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
6c3d63c9 MZ	347	struct irq_phys_map kvm_vgic_map_phys_irq(struct kvm_vcpu vcpu,
	348	int virt_irq, int irq);
	349	int kvm_vgic_unmap_phys_irq(struct kvm_vcpu vcpu, struct irq_phys_map map);
0e3dfda9	350	bool kvm_vgic_map_is_active(struct kvm_vcpu vcpu, struct irq_phys_map map);
1a89dd91	351
f982cf4e	352	#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
1f57be28	353	#define vgic_initialized(k) (!!((k)->arch.vgic.nr_cpus))
c52edf5f	354	#define vgic_ready(k) ((k)->arch.vgic.ready)
9d949dce	355
8f186d52 MZ	356	int vgic_v2_probe(struct device_node *vgic_node,
	357	const struct vgic_ops **ops,
	358	const struct vgic_params **params);
4f64cb65	359	#ifdef CONFIG_KVM_ARM_VGIC_V3
b2fb1c0d MZ	360	int vgic_v3_probe(struct device_node *vgic_node,
	361	const struct vgic_ops **ops,
	362	const struct vgic_params **params);
	363	#else
	364	static inline int vgic_v3_probe(struct device_node *vgic_node,
	365	const struct vgic_ops **ops,
	366	const struct vgic_params **params)
	367	{
	368	return -ENODEV;
	369	}
	370	#endif
8f186d52	371
1a89dd91	372	#endif