[linux-2.6-block.git] / include / drm / drm_edid.h

/*
 * Copyright © 2007-2008 Intel Corporation
 *   Jesse Barnes <jesse.barnes@intel.com>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */
#ifndef __DRM_EDID_H__
#define __DRM_EDID_H__

#include <linux/types.h>

#define EDID_LENGTH 128
#define DDC_ADDR 0x50

#ifdef BIG_ENDIAN
#error "EDID structure is little endian, need big endian versions"
#else

struct est_timings {
	u8 t1;
	u8 t2;
	u8 mfg_rsvd;
} __attribute__((packed));

struct std_timing {
	u8 hsize; /* need to multiply by 8 then add 248 */
	u8 vfreq:6; /* need to add 60 */
	u8 aspect_ratio:2; /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
} __attribute__((packed));

/* If detailed data is pixel timing */
struct detailed_pixel_timing {
	u8 hactive_lo;
	u8 hblank_lo;
	u8 hblank_hi:4;
	u8 hactive_hi:4;
	u8 vactive_lo;
	u8 vblank_lo;
	u8 vblank_hi:4;
	u8 vactive_hi:4;
	u8 hsync_offset_lo;
	u8 hsync_pulse_width_lo;
	u8 vsync_pulse_width_lo:4;
	u8 vsync_offset_lo:4;
	u8 vsync_pulse_width_hi:2;
	u8 vsync_offset_hi:2;
	u8 hsync_pulse_width_hi:2;
	u8 hsync_offset_hi:2;
	u8 width_mm_lo;
	u8 height_mm_lo;
	u8 height_mm_hi:4;
	u8 width_mm_hi:4;
	u8 hborder;
	u8 vborder;
	u8 unknown0:1;
	u8 vsync_positive:1;
	u8 hsync_positive:1;
	u8 separate_sync:2;
	u8 stereo:1;
	u8 unknown6:1;
	u8 interlaced:1;
} __attribute__((packed));

/* If it's not pixel timing, it'll be one of the below */
struct detailed_data_string {
	u8 str[13];
} __attribute__((packed));

struct detailed_data_monitor_range {
	u8 min_vfreq;
	u8 max_vfreq;
	u8 min_hfreq_khz;
	u8 max_hfreq_khz;
	u8 pixel_clock_mhz; /* need to multiply by 10 */
	u16 sec_gtf_toggle; /* A000=use above, 20=use below */ /* FIXME: byte order */
	u8 hfreq_start_khz; /* need to multiply by 2 */
	u8 c; /* need to divide by 2 */
	u16 m; /* FIXME: byte order */
	u8 k;
	u8 j; /* need to divide by 2 */
} __attribute__((packed));

struct detailed_data_wpindex {
	u8 white_y_lo:2;
	u8 white_x_lo:2;
	u8 pad:4;
	u8 white_x_hi;
	u8 white_y_hi;
	u8 gamma; /* need to divide by 100 then add 1 */
} __attribute__((packed));

struct detailed_data_color_point {
	u8 windex1;
	u8 wpindex1[3];
	u8 windex2;
	u8 wpindex2[3];
} __attribute__((packed));

struct detailed_non_pixel {
	u8 pad1;
	u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
		    fb=color point data, fa=standard timing data,
		    f9=undefined, f8=mfg. reserved */
	u8 pad2;
	union {
		struct detailed_data_string str;
		struct detailed_data_monitor_range range;
		struct detailed_data_wpindex color;
		struct std_timing timings[5];
	} data;
} __attribute__((packed));

#define EDID_DETAIL_STD_MODES 0xfa
#define EDID_DETAIL_MONITOR_CPDATA 0xfb
#define EDID_DETAIL_MONITOR_NAME 0xfc
#define EDID_DETAIL_MONITOR_RANGE 0xfd
#define EDID_DETAIL_MONITOR_STRING 0xfe
#define EDID_DETAIL_MONITOR_SERIAL 0xff

struct detailed_timing {
	u16 pixel_clock; /* need to multiply by 10 KHz */ /* FIXME: byte order */
	union {
		struct detailed_pixel_timing pixel_data;
		struct detailed_non_pixel other_data;
	} data;
} __attribute__((packed));

struct edid {
	u8 header[8];
	/* Vendor & product info */
	u8 mfg_id[2];
	u8 prod_code[2];
	u32 serial; /* FIXME: byte order */
	u8 mfg_week;
	u8 mfg_year;
	/* EDID version */
	u8 version;
	u8 revision;
	/* Display info: */
	/*   input definition */
	u8 serration_vsync:1;
	u8 sync_on_green:1;
	u8 composite_sync:1;
	u8 separate_syncs:1;
	u8 blank_to_black:1;
	u8 video_level:2;
	u8 digital:1; /* bits below must be zero if set */
	u8 width_cm;
	u8 height_cm;
	u8 gamma;
	/*   feature support */
	u8 default_gtf:1;
	u8 preferred_timing:1;
	u8 standard_color:1;
	u8 display_type:2; /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
	u8 pm_active_off:1;
	u8 pm_suspend:1;
	u8 pm_standby:1;
	/* Color characteristics */
	u8 red_green_lo;
	u8 black_white_lo;
	u8 red_x;
	u8 red_y;
	u8 green_x;
	u8 green_y;
	u8 blue_x;
	u8 blue_y;
	u8 white_x;
	u8 white_y;
	/* Est. timings and mfg rsvd timings*/
	struct est_timings established_timings;
	/* Standard timings 1-8*/
	struct std_timing standard_timings[8];
	/* Detailing timings 1-4 */
	struct detailed_timing detailed_timings[4];
	/* Number of 128 byte ext. blocks */
	u8 extensions;
	/* Checksum */
	u8 checksum;
} __attribute__((packed));

#endif /* little endian structs */

#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))

#endif /* __DRM_EDID_H__ */
Commit	Line	Data
f453ba04 DA	1	/*
	2	* Copyright © 2007-2008 Intel Corporation
	3	* Jesse Barnes <jesse.barnes@intel.com>
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice shall be included in
	13	* all copies or substantial portions of the Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	21	* OTHER DEALINGS IN THE SOFTWARE.
	22	*/
	23	#ifndef __DRM_EDID_H__
	24	#define __DRM_EDID_H__
	25
	26	#include <linux/types.h>
	27
	28	#define EDID_LENGTH 128
	29	#define DDC_ADDR 0x50
	30
	31	#ifdef BIG_ENDIAN
	32	#error "EDID structure is little endian, need big endian versions"
	33	#else
	34
	35	struct est_timings {
	36	u8 t1;
	37	u8 t2;
	38	u8 mfg_rsvd;
	39	} __attribute__((packed));
	40
	41	struct std_timing {
	42	u8 hsize; /* need to multiply by 8 then add 248 */
	43	u8 vfreq:6; /* need to add 60 */
	44	u8 aspect_ratio:2; /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
	45	} __attribute__((packed));
	46
	47	/* If detailed data is pixel timing */
	48	struct detailed_pixel_timing {
	49	u8 hactive_lo;
	50	u8 hblank_lo;
	51	u8 hblank_hi:4;
	52	u8 hactive_hi:4;
	53	u8 vactive_lo;
	54	u8 vblank_lo;
	55	u8 vblank_hi:4;
	56	u8 vactive_hi:4;
	57	u8 hsync_offset_lo;
	58	u8 hsync_pulse_width_lo;
	59	u8 vsync_pulse_width_lo:4;
	60	u8 vsync_offset_lo:4;
f453ba04 DA	61	u8 vsync_pulse_width_hi:2;
f453ba04 DA	62	u8 vsync_offset_hi:2;
fe56cf45 JB	63	u8 hsync_pulse_width_hi:2;
fe56cf45 JB	64	u8 hsync_offset_hi:2;
f453ba04 DA	65	u8 width_mm_lo;
	66	u8 height_mm_lo;
	67	u8 height_mm_hi:4;
	68	u8 width_mm_hi:4;
	69	u8 hborder;
	70	u8 vborder;
	71	u8 unknown0:1;
	72	u8 vsync_positive:1;
	73	u8 hsync_positive:1;
	74	u8 separate_sync:2;
	75	u8 stereo:1;
	76	u8 unknown6:1;
	77	u8 interlaced:1;
	78	} __attribute__((packed));
	79
	80	/* If it's not pixel timing, it'll be one of the below */
	81	struct detailed_data_string {
	82	u8 str[13];
	83	} __attribute__((packed));
	84
	85	struct detailed_data_monitor_range {
	86	u8 min_vfreq;
	87	u8 max_vfreq;
	88	u8 min_hfreq_khz;
	89	u8 max_hfreq_khz;
	90	u8 pixel_clock_mhz; /* need to multiply by 10 */
	91	u16 sec_gtf_toggle; /* A000=use above, 20=use below / / FIXME: byte order */
	92	u8 hfreq_start_khz; /* need to multiply by 2 */
	93	u8 c; /* need to divide by 2 */
	94	u16 m; /* FIXME: byte order */
	95	u8 k;
	96	u8 j; /* need to divide by 2 */
	97	} __attribute__((packed));
	98
	99	struct detailed_data_wpindex {
	100	u8 white_y_lo:2;
	101	u8 white_x_lo:2;
	102	u8 pad:4;
	103	u8 white_x_hi;
	104	u8 white_y_hi;
	105	u8 gamma; /* need to divide by 100 then add 1 */
	106	} __attribute__((packed));
	107
	108	struct detailed_data_color_point {
	109	u8 windex1;
	110	u8 wpindex1[3];
	111	u8 windex2;
	112	u8 wpindex2[3];
	113	} __attribute__((packed));
	114
	115	struct detailed_non_pixel {
	116	u8 pad1;
	117	u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
	118	fb=color point data, fa=standard timing data,
	119	f9=undefined, f8=mfg. reserved */
	120	u8 pad2;
	121	union {
	122	struct detailed_data_string str;
	123	struct detailed_data_monitor_range range;
	124	struct detailed_data_wpindex color;
	125	struct std_timing timings[5];
	126	} data;
	127	} __attribute__((packed));
	128
129	#define EDID_DETAIL_STD_MODES 0xfa
130	#define EDID_DETAIL_MONITOR_CPDATA 0xfb
131	#define EDID_DETAIL_MONITOR_NAME 0xfc
132	#define EDID_DETAIL_MONITOR_RANGE 0xfd
133	#define EDID_DETAIL_MONITOR_STRING 0xfe
134	#define EDID_DETAIL_MONITOR_SERIAL 0xff
135
136	struct detailed_timing {
137	u16 pixel_clock; /* need to multiply by 10 KHz / / FIXME: byte order */
138	union {
139	struct detailed_pixel_timing pixel_data;
140	struct detailed_non_pixel other_data;
141	} data;
142	} __attribute__((packed));
143
144	struct edid {
145	u8 header[8];
146	/* Vendor & product info */
147	u8 mfg_id[2];
148	u8 prod_code[2];
149	u32 serial; /* FIXME: byte order */
150	u8 mfg_week;
151	u8 mfg_year;
152	/* EDID version */
153	u8 version;
154	u8 revision;
155	/* Display info: */
156	/* input definition */
157	u8 serration_vsync:1;
158	u8 sync_on_green:1;
159	u8 composite_sync:1;
160	u8 separate_syncs:1;
161	u8 blank_to_black:1;
162	u8 video_level:2;
163	u8 digital:1; /* bits below must be zero if set */
164	u8 width_cm;
165	u8 height_cm;
166	u8 gamma;
167	/* feature support */
168	u8 default_gtf:1;
169	u8 preferred_timing:1;
170	u8 standard_color:1;
171	u8 display_type:2; /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
172	u8 pm_active_off:1;
173	u8 pm_suspend:1;
174	u8 pm_standby:1;
175	/* Color characteristics */
176	u8 red_green_lo;
177	u8 black_white_lo;
178	u8 red_x;
179	u8 red_y;
180	u8 green_x;
181	u8 green_y;
182	u8 blue_x;
183	u8 blue_y;
184	u8 white_x;
185	u8 white_y;
186	/* Est. timings and mfg rsvd timings*/
187	struct est_timings established_timings;
188	/* Standard timings 1-8*/
189	struct std_timing standard_timings[8];
190	/* Detailing timings 1-4 */
191	struct detailed_timing detailed_timings[4];
192	/* Number of 128 byte ext. blocks */
193	u8 extensions;
194	/* Checksum */
195	u8 checksum;
196	} __attribute__((packed));
197
198	#endif /* little endian structs */
199
200	#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] \| ((e)->prod_code[1] << 8))
201
202	#endif /* __DRM_EDID_H__ */