[linux-2.6-block.git] / include / drm / drm_edid.h

/*
 * Copyright © 2007-2008 Intel Corporation
 *   Jesse Barnes <jesse.barnes@intel.com>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */
#ifndef __DRM_EDID_H__
#define __DRM_EDID_H__

#include <linux/types.h>

#define EDID_LENGTH 128
#define DDC_ADDR 0x50

struct est_timings {
	u8 t1;
	u8 t2;
	u8 mfg_rsvd;
} __attribute__((packed));

/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
#define EDID_TIMING_ASPECT_SHIFT 6
#define EDID_TIMING_ASPECT_MASK  (0x3 << EDID_TIMING_ASPECT_SHIFT)

/* need to add 60 */
#define EDID_TIMING_VFREQ_SHIFT  0
#define EDID_TIMING_VFREQ_MASK   (0x3f << EDID_TIMING_VFREQ_SHIFT)

struct std_timing {
	u8 hsize; /* need to multiply by 8 then add 248 */
	u8 vfreq_aspect;
} __attribute__((packed));

#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
#define DRM_EDID_PT_SEPARATE_SYNC  (3 << 3)
#define DRM_EDID_PT_STEREO         (1 << 5)
#define DRM_EDID_PT_INTERLACED     (1 << 7)

/* If detailed data is pixel timing */
struct detailed_pixel_timing {
	u8 hactive_lo;
	u8 hblank_lo;
	u8 hactive_hblank_hi;
	u8 vactive_lo;
	u8 vblank_lo;
	u8 vactive_vblank_hi;
	u8 hsync_offset_lo;
	u8 hsync_pulse_width_lo;
	u8 vsync_offset_pulse_width_lo;
	u8 hsync_vsync_offset_pulse_width_hi;
	u8 width_mm_lo;
	u8 height_mm_lo;
	u8 width_height_mm_hi;
	u8 hborder;
	u8 vborder;
	u8 misc;
} __attribute__((packed));

/* If it's not pixel timing, it'll be one of the below */
struct detailed_data_string {
	u8 str[13];
} __attribute__((packed));

struct detailed_data_monitor_range {
	u8 min_vfreq;
	u8 max_vfreq;
	u8 min_hfreq_khz;
	u8 max_hfreq_khz;
	u8 pixel_clock_mhz; /* need to multiply by 10 */
	__le16 sec_gtf_toggle; /* A000=use above, 20=use below */
	u8 hfreq_start_khz; /* need to multiply by 2 */
	u8 c; /* need to divide by 2 */
	__le16 m;
	u8 k;
	u8 j; /* need to divide by 2 */
} __attribute__((packed));

struct detailed_data_wpindex {
	u8 white_yx_lo; /* Lower 2 bits each */
	u8 white_x_hi;
	u8 white_y_hi;
	u8 gamma; /* need to divide by 100 then add 1 */
} __attribute__((packed));

struct detailed_data_color_point {
	u8 windex1;
	u8 wpindex1[3];
	u8 windex2;
	u8 wpindex2[3];
} __attribute__((packed));

struct cvt_timing {
	u8 code[3];
} __attribute__((packed));

struct detailed_non_pixel {
	u8 pad1;
	u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
		    fb=color point data, fa=standard timing data,
		    f9=undefined, f8=mfg. reserved */
	u8 pad2;
	union {
		struct detailed_data_string str;
		struct detailed_data_monitor_range range;
		struct detailed_data_wpindex color;
		struct std_timing timings[5];
		struct cvt_timing cvt[4];
	} data;
} __attribute__((packed));

#define EDID_DETAIL_EST_TIMINGS 0xf7
#define EDID_DETAIL_CVT_3BYTE 0xf8
#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
#define EDID_DETAIL_STD_MODES 0xfa
#define EDID_DETAIL_MONITOR_CPDATA 0xfb
#define EDID_DETAIL_MONITOR_NAME 0xfc
#define EDID_DETAIL_MONITOR_RANGE 0xfd
#define EDID_DETAIL_MONITOR_STRING 0xfe
#define EDID_DETAIL_MONITOR_SERIAL 0xff

struct detailed_timing {
	__le16 pixel_clock; /* need to multiply by 10 KHz */
	union {
		struct detailed_pixel_timing pixel_data;
		struct detailed_non_pixel other_data;
	} data;
} __attribute__((packed));

#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
#define DRM_EDID_INPUT_SYNC_ON_GREEN   (1 << 1)
#define DRM_EDID_INPUT_COMPOSITE_SYNC  (1 << 2)
#define DRM_EDID_INPUT_SEPARATE_SYNCS  (1 << 3)
#define DRM_EDID_INPUT_BLANK_TO_BLACK  (1 << 4)
#define DRM_EDID_INPUT_VIDEO_LEVEL     (3 << 5)
#define DRM_EDID_INPUT_DIGITAL         (1 << 7) /* bits below must be zero if set */

#define DRM_EDID_FEATURE_DEFAULT_GTF      (1 << 0)
#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
#define DRM_EDID_FEATURE_STANDARD_COLOR   (1 << 2)
#define DRM_EDID_FEATURE_DISPLAY_TYPE     (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
#define DRM_EDID_FEATURE_PM_ACTIVE_OFF    (1 << 5)
#define DRM_EDID_FEATURE_PM_SUSPEND       (1 << 6)
#define DRM_EDID_FEATURE_PM_STANDBY       (1 << 7)

struct edid {
	u8 header[8];
	/* Vendor & product info */
	u8 mfg_id[2];
	u8 prod_code[2];
	u32 serial; /* FIXME: byte order */
	u8 mfg_week;
	u8 mfg_year;
	/* EDID version */
	u8 version;
	u8 revision;
	/* Display info: */
	u8 input;
	u8 width_cm;
	u8 height_cm;
	u8 gamma;
	u8 features;
	/* Color characteristics */
	u8 red_green_lo;
	u8 black_white_lo;
	u8 red_x;
	u8 red_y;
	u8 green_x;
	u8 green_y;
	u8 blue_x;
	u8 blue_y;
	u8 white_x;
	u8 white_y;
	/* Est. timings and mfg rsvd timings*/
	struct est_timings established_timings;
	/* Standard timings 1-8*/
	struct std_timing standard_timings[8];
	/* Detailing timings 1-4 */
	struct detailed_timing detailed_timings[4];
	/* Number of 128 byte ext. blocks */
	u8 extensions;
	/* Checksum */
	u8 checksum;
} __attribute__((packed));

#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))

/* define the number of Extension EDID block */
#define DRM_MAX_EDID_EXT_NUM 4

#endif /* __DRM_EDID_H__ */
Commit	Line	Data
f453ba04 DA	1	/*
	2	* Copyright © 2007-2008 Intel Corporation
	3	* Jesse Barnes <jesse.barnes@intel.com>
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice shall be included in
	13	* all copies or substantial portions of the Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	21	* OTHER DEALINGS IN THE SOFTWARE.
	22	*/
	23	#ifndef __DRM_EDID_H__
	24	#define __DRM_EDID_H__
	25
	26	#include <linux/types.h>
	27
	28	#define EDID_LENGTH 128
	29	#define DDC_ADDR 0x50
	30
f453ba04 DA	31	struct est_timings {
	32	u8 t1;
	33	u8 t2;
	34	u8 mfg_rsvd;
	35	} __attribute__((packed));
	36
0454beab	37	/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
e14cbee4	38	#define EDID_TIMING_ASPECT_SHIFT 6
0454beab MD	39	#define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT)
	40
	41	/* need to add 60 */
e14cbee4	42	#define EDID_TIMING_VFREQ_SHIFT 0
0454beab MD	43	#define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT)
0454beab MD	44
f453ba04 DA	45	struct std_timing {
f453ba04 DA	46	u8 hsize; /* need to multiply by 8 then add 248 */
0454beab	47	u8 vfreq_aspect;
f453ba04 DA	48	} __attribute__((packed));
f453ba04 DA	49
e14cbee4 MD	50	#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
e14cbee4 MD	51	#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
0454beab	52	#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
e14cbee4 MD	53	#define DRM_EDID_PT_STEREO (1 << 5)
e14cbee4 MD	54	#define DRM_EDID_PT_INTERLACED (1 << 7)
0454beab	55
f453ba04 DA	56	/* If detailed data is pixel timing */
	57	struct detailed_pixel_timing {
	58	u8 hactive_lo;
	59	u8 hblank_lo;
0454beab	60	u8 hactive_hblank_hi;
f453ba04 DA	61	u8 vactive_lo;
f453ba04 DA	62	u8 vblank_lo;
0454beab	63	u8 vactive_vblank_hi;
f453ba04 DA	64	u8 hsync_offset_lo;
f453ba04 DA	65	u8 hsync_pulse_width_lo;
0454beab MD	66	u8 vsync_offset_pulse_width_lo;
0454beab MD	67	u8 hsync_vsync_offset_pulse_width_hi;
f453ba04 DA	68	u8 width_mm_lo;
f453ba04 DA	69	u8 height_mm_lo;
0454beab	70	u8 width_height_mm_hi;
f453ba04 DA	71	u8 hborder;
f453ba04 DA	72	u8 vborder;
0454beab	73	u8 misc;
f453ba04 DA	74	} __attribute__((packed));
	75
	76	/* If it's not pixel timing, it'll be one of the below */
	77	struct detailed_data_string {
	78	u8 str[13];
	79	} __attribute__((packed));
	80
	81	struct detailed_data_monitor_range {
	82	u8 min_vfreq;
	83	u8 max_vfreq;
	84	u8 min_hfreq_khz;
	85	u8 max_hfreq_khz;
	86	u8 pixel_clock_mhz; /* need to multiply by 10 */
0454beab	87	__le16 sec_gtf_toggle; /* A000=use above, 20=use below */
f453ba04 DA	88	u8 hfreq_start_khz; /* need to multiply by 2 */
f453ba04 DA	89	u8 c; /* need to divide by 2 */
0454beab	90	__le16 m;
f453ba04 DA	91	u8 k;
	92	u8 j; /* need to divide by 2 */
	93	} __attribute__((packed));
	94
	95	struct detailed_data_wpindex {
e14cbee4	96	u8 white_yx_lo; /* Lower 2 bits each */
f453ba04 DA	97	u8 white_x_hi;
	98	u8 white_y_hi;
	99	u8 gamma; /* need to divide by 100 then add 1 */
	100	} __attribute__((packed));
	101
	102	struct detailed_data_color_point {
	103	u8 windex1;
	104	u8 wpindex1[3];
	105	u8 windex2;
	106	u8 wpindex2[3];
	107	} __attribute__((packed));
	108
9340d8cf AJ	109	struct cvt_timing {
	110	u8 code[3];
	111	} __attribute__((packed));
	112
f453ba04 DA	113	struct detailed_non_pixel {
	114	u8 pad1;
	115	u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
	116	fb=color point data, fa=standard timing data,
	117	f9=undefined, f8=mfg. reserved */
	118	u8 pad2;
	119	union {
	120	struct detailed_data_string str;
	121	struct detailed_data_monitor_range range;
	122	struct detailed_data_wpindex color;
	123	struct std_timing timings[5];
9340d8cf	124	struct cvt_timing cvt[4];
f453ba04 DA	125	} data;
	126	} __attribute__((packed));
	127
2dbdc52c AJ	128	#define EDID_DETAIL_EST_TIMINGS 0xf7
	129	#define EDID_DETAIL_CVT_3BYTE 0xf8
	130	#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
f453ba04 DA	131	#define EDID_DETAIL_STD_MODES 0xfa
	132	#define EDID_DETAIL_MONITOR_CPDATA 0xfb
	133	#define EDID_DETAIL_MONITOR_NAME 0xfc
	134	#define EDID_DETAIL_MONITOR_RANGE 0xfd
	135	#define EDID_DETAIL_MONITOR_STRING 0xfe
	136	#define EDID_DETAIL_MONITOR_SERIAL 0xff
	137
	138	struct detailed_timing {
0454beab	139	__le16 pixel_clock; /* need to multiply by 10 KHz */
f453ba04 DA	140	union {
	141	struct detailed_pixel_timing pixel_data;
	142	struct detailed_non_pixel other_data;
	143	} data;
	144	} __attribute__((packed));
	145
e14cbee4 MD	146	#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
	147	#define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1)
	148	#define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2)
0454beab	149	#define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3)
e14cbee4 MD	150	#define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4)
	151	#define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5)
	152	#define DRM_EDID_INPUT_DIGITAL (1 << 7) /* bits below must be zero if set */
0454beab	153
e14cbee4 MD	154	#define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0)
	155	#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
	156	#define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2)
0454beab	157	#define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
e14cbee4 MD	158	#define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5)
	159	#define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6)
	160	#define DRM_EDID_FEATURE_PM_STANDBY (1 << 7)
0454beab	161
f453ba04 DA	162	struct edid {
	163	u8 header[8];
	164	/* Vendor & product info */
	165	u8 mfg_id[2];
	166	u8 prod_code[2];
	167	u32 serial; /* FIXME: byte order */
	168	u8 mfg_week;
	169	u8 mfg_year;
	170	/* EDID version */
	171	u8 version;
	172	u8 revision;
	173	/* Display info: */
0454beab	174	u8 input;
f453ba04 DA	175	u8 width_cm;
	176	u8 height_cm;
	177	u8 gamma;
0454beab	178	u8 features;
f453ba04 DA	179	/* Color characteristics */
	180	u8 red_green_lo;
	181	u8 black_white_lo;
	182	u8 red_x;
	183	u8 red_y;
	184	u8 green_x;
	185	u8 green_y;
	186	u8 blue_x;
	187	u8 blue_y;
	188	u8 white_x;
	189	u8 white_y;
	190	/* Est. timings and mfg rsvd timings*/
	191	struct est_timings established_timings;
	192	/* Standard timings 1-8*/
	193	struct std_timing standard_timings[8];
	194	/* Detailing timings 1-4 */
	195	struct detailed_timing detailed_timings[4];
	196	/* Number of 128 byte ext. blocks */
	197	u8 extensions;
	198	/* Checksum */
	199	u8 checksum;
	200	} __attribute__((packed));
	201
f453ba04 DA	202	#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] \| ((e)->prod_code[1] << 8))
f453ba04 DA	203
3c537889 AD	204	/* define the number of Extension EDID block */
	205	#define DRM_MAX_EDID_EXT_NUM 4
	206
f453ba04	207	#endif /* __DRM_EDID_H__ */