xtensa: use the new byteorder headers
[linux-block.git] / include / asm-xtensa / ptrace.h
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1/*
2 * include/asm-xtensa/ptrace.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_PTRACE_H
12#define _XTENSA_PTRACE_H
13
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14/*
15 * Kernel stack
16 *
17 * +-----------------------+ -------- STACK_SIZE
18 * | register file | |
19 * +-----------------------+ |
20 * | struct pt_regs | |
21 * +-----------------------+ | ------ PT_REGS_OFFSET
22 * double : 16 bytes spill area : | ^
23 * excetion :- - - - - - - - - - - -: | |
24 * frame : struct pt_regs : | |
25 * :- - - - - - - - - - - -: | |
26 * | | | |
27 * | memory stack | | |
28 * | | | |
29 * ~ ~ ~ ~
30 * ~ ~ ~ ~
31 * | | | |
32 * | | | |
33 * +-----------------------+ | | --- STACK_BIAS
34 * | struct task_struct | | | ^
35 * current --> +-----------------------+ | | |
36 * | struct thread_info | | | |
37 * +-----------------------+ --------
38 */
39
40#define KERNEL_STACK_SIZE (2 * PAGE_SIZE)
41
42/* Offsets for exception_handlers[] (3 x 64-entries x 4-byte tables). */
43
44#define EXC_TABLE_KSTK 0x004 /* Kernel Stack */
45#define EXC_TABLE_DOUBLE_SAVE 0x008 /* Double exception save area for a0 */
46#define EXC_TABLE_FIXUP 0x00c /* Fixup handler */
47#define EXC_TABLE_PARAM 0x010 /* For passing a parameter to fixup */
48#define EXC_TABLE_SYSCALL_SAVE 0x014 /* For fast syscall handler */
49#define EXC_TABLE_FAST_USER 0x100 /* Fast user exception handler */
50#define EXC_TABLE_FAST_KERNEL 0x200 /* Fast kernel exception handler */
51#define EXC_TABLE_DEFAULT 0x300 /* Default C-Handler */
52#define EXC_TABLE_SIZE 0x400
53
54/* Registers used by strace */
55
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56#define REG_A_BASE 0x0000
57#define REG_AR_BASE 0x0100
58#define REG_PC 0x0020
59#define REG_PS 0x02e6
60#define REG_WB 0x0248
61#define REG_WS 0x0249
62#define REG_LBEG 0x0200
63#define REG_LEND 0x0201
64#define REG_LCOUNT 0x0202
65#define REG_SAR 0x0203
66
67#define SYSCALL_NR 0x00ff
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68
69/* Other PTRACE_ values defined in <linux/ptrace.h> using values 0-9,16,17,24 */
70
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71#define PTRACE_GETREGS 12
72#define PTRACE_SETREGS 13
73#define PTRACE_GETXTREGS 18
74#define PTRACE_SETXTREGS 19
9a8fd558 75
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76#ifdef __KERNEL__
77
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78#ifndef __ASSEMBLY__
79
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80/*
81 * This struct defines the way the registers are stored on the
82 * kernel stack during a system call or other kernel entry.
83 */
84struct pt_regs {
85 unsigned long pc; /* 4 */
86 unsigned long ps; /* 8 */
87 unsigned long depc; /* 12 */
88 unsigned long exccause; /* 16 */
89 unsigned long excvaddr; /* 20 */
90 unsigned long debugcause; /* 24 */
91 unsigned long wmask; /* 28 */
92 unsigned long lbeg; /* 32 */
93 unsigned long lend; /* 36 */
94 unsigned long lcount; /* 40 */
95 unsigned long sar; /* 44 */
96 unsigned long windowbase; /* 48 */
97 unsigned long windowstart; /* 52 */
98 unsigned long syscall; /* 56 */
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99 unsigned long icountlevel; /* 60 */
100 int reserved[1]; /* 64 */
9a8fd558 101
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102 /* Additional configurable registers that are used by the compiler. */
103 xtregs_opt_t xtregs_opt;
104
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105 /* Make sure the areg field is 16 bytes aligned. */
106 int align[0] __attribute__ ((aligned(16)));
107
108 /* current register frame.
109 * Note: The ESF for kernel exceptions ends after 16 registers!
110 */
111 unsigned long areg[16]; /* 128 (64) */
112};
113
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114#include <asm/variant/core.h>
115
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116# define task_pt_regs(tsk) ((struct pt_regs*) \
117 (task_stack_page(tsk) + KERNEL_STACK_SIZE - (XCHAL_NUM_AREGS-16)*4) - 1)
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118# define user_mode(regs) (((regs)->ps & 0x00000020)!=0)
119# define instruction_pointer(regs) ((regs)->pc)
120extern void show_regs(struct pt_regs *);
121
122# ifndef CONFIG_SMP
123# define profile_pc(regs) instruction_pointer(regs)
124# endif
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125
126#else /* __ASSEMBLY__ */
127
0013a854 128# include <asm/asm-offsets.h>
9a8fd558 129#define PT_REGS_OFFSET (KERNEL_STACK_SIZE - PT_USER_SIZE)
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130
131#endif /* !__ASSEMBLY__ */
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132
133#endif /* __KERNEL__ */
134
9a8fd558 135#endif /* _XTENSA_PTRACE_H */