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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes...
[linux-2.6-block.git] / include / asm-s390 / pgtable.h
CommitLineData
1da177e4
LT		 1/*
2 * include/asm-s390/pgtable.h
3 *
4 * S390 version
5 * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Hartmut Penner (hp@de.ibm.com)
7 * Ulrich Weigand (weigand@de.ibm.com)
8 * Martin Schwidefsky (schwidefsky@de.ibm.com)
9 *
10 * Derived from "include/asm-i386/pgtable.h"
11 */
12
13#ifndef _ASM_S390_PGTABLE_H
14#define _ASM_S390_PGTABLE_H
15
1da177e4
LT		 16/*
17 * The Linux memory management assumes a three-level page table setup. For
18 * s390 31 bit we "fold" the mid level into the top-level page table, so
19 * that we physically have the same two-level page table as the s390 mmu
20 * expects in 31 bit mode. For s390 64 bit we use three of the five levels
21 * the hardware provides (region first and region second tables are not
22 * used).
23 *
24 * The "pgd_xxx()" functions are trivial for a folded two-level
25 * setup: the pgd is never bad, and a pmd always exists (as it's folded
26 * into the pgd entry)
27 *
28 * This file contains the functions and defines necessary to modify and use
29 * the S390 page table tree.
30 */
31#ifndef __ASSEMBLY__
2dcea57a 32#include <linux/mm_types.h>
5b7baf05 33#include <asm/bitops.h>
1da177e4
LT		 34#include <asm/bug.h>
35#include <asm/processor.h>
1da177e4 36
1da177e4
LT		 37extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096)));
38extern void paging_init(void);
2b67fc46 39extern void vmem_map_init(void);
1da177e4
LT		 40
41/*
42 * The S390 doesn't have any external MMU info: the kernel page
43 * tables contain all the necessary information.
44 */
45#define update_mmu_cache(vma, address, pte) do { } while (0)
46
47/*
48 * ZERO_PAGE is a global shared page that is always zero: used
49 * for zero-mapped memory areas etc..
50 */
51extern char empty_zero_page[PAGE_SIZE];
52#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
53#endif /* !__ASSEMBLY__ */
54
55/*
56 * PMD_SHIFT determines the size of the area a second-level page
57 * table can map
58 * PGDIR_SHIFT determines what a third-level page table entry can map
59 */
60#ifndef __s390x__
146e4b3c
MS		 61# define PMD_SHIFT 20
62# define PUD_SHIFT 20
63# define PGDIR_SHIFT 20
1da177e4 64#else /* __s390x__ */
146e4b3c 65# define PMD_SHIFT 20
190a1d72 66# define PUD_SHIFT 31
5a216a20 67# define PGDIR_SHIFT 42
1da177e4
LT		 68#endif /* __s390x__ */
69
70#define PMD_SIZE (1UL << PMD_SHIFT)
71#define PMD_MASK (~(PMD_SIZE-1))
190a1d72
MS		 72#define PUD_SIZE (1UL << PUD_SHIFT)
73#define PUD_MASK (~(PUD_SIZE-1))
5a216a20
MS		 74#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
75#define PGDIR_MASK (~(PGDIR_SIZE-1))
1da177e4
LT		 76
77/*
78 * entries per page directory level: the S390 is two-level, so
79 * we don't really have any PMD directory physically.
80 * for S390 segment-table entries are combined to one PGD
81 * that leads to 1024 pte per pgd
82 */
146e4b3c 83#define PTRS_PER_PTE 256
1da177e4 84#ifndef __s390x__
146e4b3c 85#define PTRS_PER_PMD 1
5a216a20 86#define PTRS_PER_PUD 1
1da177e4 87#else /* __s390x__ */
146e4b3c 88#define PTRS_PER_PMD 2048
5a216a20 89#define PTRS_PER_PUD 2048
1da177e4 90#endif /* __s390x__ */
146e4b3c 91#define PTRS_PER_PGD 2048
1da177e4 92
d455a369
HD		 93#define FIRST_USER_ADDRESS 0
94
1da177e4
LT		 95#define pte_ERROR(e) \
96 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e))
97#define pmd_ERROR(e) \
98 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e))
190a1d72
MS		 99#define pud_ERROR(e) \
100 printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e))
1da177e4
LT		 101#define pgd_ERROR(e) \
102 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e))
103
104#ifndef __ASSEMBLY__
105/*
5fd9c6e2
CB		 106 * The vmalloc area will always be on the topmost area of the kernel
107 * mapping. We reserve 96MB (31bit) / 1GB (64bit) for vmalloc,
108 * which should be enough for any sane case.
109 * By putting vmalloc at the top, we maximise the gap between physical
110 * memory and vmalloc to catch misplaced memory accesses. As a side
111 * effect, this also makes sure that 64 bit module code cannot be used
112 * as system call address.
8b62bc96 113 */
1da177e4 114#ifndef __s390x__
5fd9c6e2
CB		 115#define VMALLOC_START 0x78000000UL
116#define VMALLOC_END 0x7e000000UL
0189103c 117#define VMEM_MAP_END 0x80000000UL
1da177e4 118#else /* __s390x__ */
5fd9c6e2
CB		 119#define VMALLOC_START 0x3e000000000UL
120#define VMALLOC_END 0x3e040000000UL
0189103c 121#define VMEM_MAP_END 0x40000000000UL
1da177e4
LT		 122#endif /* __s390x__ */
123
0189103c
HC		 124/*
125 * VMEM_MAX_PHYS is the highest physical address that can be added to the 1:1
126 * mapping. This needs to be calculated at compile time since the size of the
127 * VMEM_MAP is static but the size of struct page can change.
128 */
522d8dc0
MS		 129#define VMEM_MAX_PAGES ((VMEM_MAP_END - VMALLOC_END) / sizeof(struct page))
130#define VMEM_MAX_PFN min(VMALLOC_START >> PAGE_SHIFT, VMEM_MAX_PAGES)
131#define VMEM_MAX_PHYS ((VMEM_MAX_PFN << PAGE_SHIFT) & ~((16 << 20) - 1))
17f34580 132#define vmemmap ((struct page *) VMALLOC_END)
5fd9c6e2 133
1da177e4
LT		 134/*
135 * A 31 bit pagetable entry of S390 has following format:
136 * | PFRA | | OS |
137 * 0 0IP0
138 * 00000000001111111111222222222233
139 * 01234567890123456789012345678901
140 *
141 * I Page-Invalid Bit: Page is not available for address-translation
142 * P Page-Protection Bit: Store access not possible for page
143 *
144 * A 31 bit segmenttable entry of S390 has following format:
145 * | P-table origin | |PTL
146 * 0 IC
147 * 00000000001111111111222222222233
148 * 01234567890123456789012345678901
149 *
150 * I Segment-Invalid Bit: Segment is not available for address-translation
151 * C Common-Segment Bit: Segment is not private (PoP 3-30)
152 * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256)
153 *
154 * The 31 bit segmenttable origin of S390 has following format:
155 *
156 * |S-table origin | | STL |
157 * X **GPS
158 * 00000000001111111111222222222233
159 * 01234567890123456789012345678901
160 *
161 * X Space-Switch event:
162 * G Segment-Invalid Bit: *
163 * P Private-Space Bit: Segment is not private (PoP 3-30)
164 * S Storage-Alteration:
165 * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048)
166 *
167 * A 64 bit pagetable entry of S390 has following format:
168 * | PFRA |0IP0| OS |
169 * 0000000000111111111122222222223333333333444444444455555555556666
170 * 0123456789012345678901234567890123456789012345678901234567890123
171 *
172 * I Page-Invalid Bit: Page is not available for address-translation
173 * P Page-Protection Bit: Store access not possible for page
174 *
175 * A 64 bit segmenttable entry of S390 has following format:
176 * | P-table origin | TT
177 * 0000000000111111111122222222223333333333444444444455555555556666
178 * 0123456789012345678901234567890123456789012345678901234567890123
179 *
180 * I Segment-Invalid Bit: Segment is not available for address-translation
181 * C Common-Segment Bit: Segment is not private (PoP 3-30)
182 * P Page-Protection Bit: Store access not possible for page
183 * TT Type 00
184 *
185 * A 64 bit region table entry of S390 has following format:
186 * | S-table origin | TF TTTL
187 * 0000000000111111111122222222223333333333444444444455555555556666
188 * 0123456789012345678901234567890123456789012345678901234567890123
189 *
190 * I Segment-Invalid Bit: Segment is not available for address-translation
191 * TT Type 01
192 * TF
190a1d72 193 * TL Table length
1da177e4
LT		 194 *
195 * The 64 bit regiontable origin of S390 has following format:
196 * | region table origon | DTTL
197 * 0000000000111111111122222222223333333333444444444455555555556666
198 * 0123456789012345678901234567890123456789012345678901234567890123
199 *
200 * X Space-Switch event:
201 * G Segment-Invalid Bit:
202 * P Private-Space Bit:
203 * S Storage-Alteration:
204 * R Real space
205 * TL Table-Length:
206 *
207 * A storage key has the following format:
208 * | ACC |F|R|C|0|
209 * 0 3 4 5 6 7
210 * ACC: access key
211 * F : fetch protection bit
212 * R : referenced bit
213 * C : changed bit
214 */
215
216/* Hardware bits in the page table entry */
83377484
MS		 217#define _PAGE_RO 0x200 /* HW read-only bit */
218#define _PAGE_INVALID 0x400 /* HW invalid bit */
3610cce8
MS		 219
220/* Software bits in the page table entry */
83377484
MS		 221#define _PAGE_SWT 0x001 /* SW pte type bit t */
222#define _PAGE_SWX 0x002 /* SW pte type bit x */
a08cb629
NP		 223#define _PAGE_SPECIAL 0x004 /* SW associated with special page */
224#define __HAVE_ARCH_PTE_SPECIAL
1da177e4 225
83377484 226/* Six different types of pages. */
9282ed92
GS		 227#define _PAGE_TYPE_EMPTY 0x400
228#define _PAGE_TYPE_NONE 0x401
83377484
MS		 229#define _PAGE_TYPE_SWAP 0x403
230#define _PAGE_TYPE_FILE 0x601 /* bit 0x002 is used for offset !! */
9282ed92
GS		 231#define _PAGE_TYPE_RO 0x200
232#define _PAGE_TYPE_RW 0x000
c1821c2e
GS		 233#define _PAGE_TYPE_EX_RO 0x202
234#define _PAGE_TYPE_EX_RW 0x002
1da177e4 235
53492b1d
GS		 236/*
237 * Only four types for huge pages, using the invalid bit and protection bit
238 * of a segment table entry.
239 */
240#define _HPAGE_TYPE_EMPTY 0x020 /* _SEGMENT_ENTRY_INV */
241#define _HPAGE_TYPE_NONE 0x220
242#define _HPAGE_TYPE_RO 0x200 /* _SEGMENT_ENTRY_RO */
243#define _HPAGE_TYPE_RW 0x000
244
83377484
MS		 245/*
246 * PTE type bits are rather complicated. handle_pte_fault uses pte_present,
247 * pte_none and pte_file to find out the pte type WITHOUT holding the page
248 * table lock. ptep_clear_flush on the other hand uses ptep_clear_flush to
249 * invalidate a given pte. ipte sets the hw invalid bit and clears all tlbs
250 * for the page. The page table entry is set to _PAGE_TYPE_EMPTY afterwards.
251 * This change is done while holding the lock, but the intermediate step
252 * of a previously valid pte with the hw invalid bit set can be observed by
253 * handle_pte_fault. That makes it necessary that all valid pte types with
254 * the hw invalid bit set must be distinguishable from the four pte types
255 * empty, none, swap and file.
256 *
257 * irxt ipte irxt
258 * _PAGE_TYPE_EMPTY 1000 -> 1000
259 * _PAGE_TYPE_NONE 1001 -> 1001
260 * _PAGE_TYPE_SWAP 1011 -> 1011
261 * _PAGE_TYPE_FILE 11?1 -> 11?1
262 * _PAGE_TYPE_RO 0100 -> 1100
263 * _PAGE_TYPE_RW 0000 -> 1000
c1821c2e
GS		 264 * _PAGE_TYPE_EX_RO 0110 -> 1110
265 * _PAGE_TYPE_EX_RW 0010 -> 1010
83377484 266 *
c1821c2e 267 * pte_none is true for bits combinations 1000, 1010, 1100, 1110
83377484
MS		 268 * pte_present is true for bits combinations 0000, 0010, 0100, 0110, 1001
269 * pte_file is true for bits combinations 1101, 1111
c1821c2e 270 * swap pte is 1011 and 0001, 0011, 0101, 0111 are invalid.
83377484
MS		 271 */
272
5b7baf05
CB		 273/* Page status table bits for virtualization */
274#define RCP_PCL_BIT 55
275#define RCP_HR_BIT 54
276#define RCP_HC_BIT 53
277#define RCP_GR_BIT 50
278#define RCP_GC_BIT 49
279
1da177e4
LT		 280#ifndef __s390x__
281
3610cce8
MS		 282/* Bits in the segment table address-space-control-element */
283#define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */
284#define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */
285#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
286#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
287#define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */
1da177e4 288
3610cce8
MS		 289/* Bits in the segment table entry */
290#define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */
291#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
292#define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */
293#define _SEGMENT_ENTRY_PTL 0x0f /* page table length */
1da177e4 294
3610cce8
MS		 295#define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL)
296#define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV)
1da177e4
LT		 297
298#else /* __s390x__ */
299
3610cce8
MS		 300/* Bits in the segment/region table address-space-control-element */
301#define _ASCE_ORIGIN ~0xfffUL/* segment table origin */
302#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
303#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
304#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
305#define _ASCE_REAL_SPACE 0x20 /* real space control */
306#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
307#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
308#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
309#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
310#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
311#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
312
313/* Bits in the region table entry */
314#define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */
315#define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
316#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
317#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
318#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
319#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
320#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
321
322#define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH)
323#define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INV)
324#define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH)
325#define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INV)
326#define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH)
327#define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INV)
328
1da177e4 329/* Bits in the segment table entry */
3610cce8
MS		 330#define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */
331#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
332#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
1da177e4 333
3610cce8
MS		 334#define _SEGMENT_ENTRY (0)
335#define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV)
336
53492b1d
GS		 337#define _SEGMENT_ENTRY_LARGE 0x400 /* STE-format control, large page */
338#define _SEGMENT_ENTRY_CO 0x100 /* change-recording override */
339
3610cce8 340#endif /* __s390x__ */
1da177e4
LT		 341
342/*
3610cce8
MS		 343 * A user page table pointer has the space-switch-event bit, the
344 * private-space-control bit and the storage-alteration-event-control
345 * bit set. A kernel page table pointer doesn't need them.
1da177e4 346 */
3610cce8
MS		 347#define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \
348 _ASCE_ALT_EVENT)
1da177e4 349
3610cce8 350/* Bits int the storage key */
1da177e4
LT		 351#define _PAGE_CHANGED 0x02 /* HW changed bit */
352#define _PAGE_REFERENCED 0x04 /* HW referenced bit */
353
1da177e4 354/*
9282ed92 355 * Page protection definitions.
1da177e4 356 */
9282ed92
GS		 357#define PAGE_NONE __pgprot(_PAGE_TYPE_NONE)
358#define PAGE_RO __pgprot(_PAGE_TYPE_RO)
359#define PAGE_RW __pgprot(_PAGE_TYPE_RW)
c1821c2e
GS		 360#define PAGE_EX_RO __pgprot(_PAGE_TYPE_EX_RO)
361#define PAGE_EX_RW __pgprot(_PAGE_TYPE_EX_RW)
9282ed92
GS		 362
363#define PAGE_KERNEL PAGE_RW
364#define PAGE_COPY PAGE_RO
1da177e4
LT		 365
366/*
c1821c2e
GS		 367 * Dependent on the EXEC_PROTECT option s390 can do execute protection.
368 * Write permission always implies read permission. In theory with a
369 * primary/secondary page table execute only can be implemented but
370 * it would cost an additional bit in the pte to distinguish all the
371 * different pte types. To avoid that execute permission currently
372 * implies read permission as well.
1da177e4
LT		 373 */
374 /*xwr*/
9282ed92
GS		 375#define __P000 PAGE_NONE
376#define __P001 PAGE_RO
377#define __P010 PAGE_RO
378#define __P011 PAGE_RO
c1821c2e
GS		 379#define __P100 PAGE_EX_RO
380#define __P101 PAGE_EX_RO
381#define __P110 PAGE_EX_RO
382#define __P111 PAGE_EX_RO
9282ed92
GS		 383
384#define __S000 PAGE_NONE
385#define __S001 PAGE_RO
386#define __S010 PAGE_RW
387#define __S011 PAGE_RW
c1821c2e
GS		 388#define __S100 PAGE_EX_RO
389#define __S101 PAGE_EX_RO
390#define __S110 PAGE_EX_RW
391#define __S111 PAGE_EX_RW
392
393#ifndef __s390x__
3610cce8 394# define PxD_SHADOW_SHIFT 1
c1821c2e 395#else /* __s390x__ */
3610cce8 396# define PxD_SHADOW_SHIFT 2
c1821c2e
GS		 397#endif /* __s390x__ */
398
3610cce8 399static inline void *get_shadow_table(void *table)
c1821c2e 400{
3610cce8
MS		 401 unsigned long addr, offset;
402 struct page *page;
403
404 addr = (unsigned long) table;
405 offset = addr & ((PAGE_SIZE << PxD_SHADOW_SHIFT) - 1);
406 page = virt_to_page((void *)(addr ^ offset));
407 return (void *)(addr_t)(page->index ? (page->index | offset) : 0UL);
c1821c2e 408}
1da177e4
LT		 409
410/*
411 * Certain architectures need to do special things when PTEs
412 * within a page table are directly modified. Thus, the following
413 * hook is made available.
414 */
ba8a9229 415static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
146e4b3c 416 pte_t *ptep, pte_t entry)
1da177e4 417{
146e4b3c
MS		 418 *ptep = entry;
419 if (mm->context.noexec) {
420 if (!(pte_val(entry) & _PAGE_INVALID) &&
421 (pte_val(entry) & _PAGE_SWX))
422 pte_val(entry) |= _PAGE_RO;
c1821c2e 423 else
146e4b3c
MS		 424 pte_val(entry) = _PAGE_TYPE_EMPTY;
425 ptep[PTRS_PER_PTE] = entry;
c1821c2e 426 }
1da177e4 427}
1da177e4
LT		 428
429/*
430 * pgd/pmd/pte query functions
431 */
432#ifndef __s390x__
433
4448aaf0
AB		 434static inline int pgd_present(pgd_t pgd) { return 1; }
435static inline int pgd_none(pgd_t pgd) { return 0; }
436static inline int pgd_bad(pgd_t pgd) { return 0; }
1da177e4 437
190a1d72
MS		 438static inline int pud_present(pud_t pud) { return 1; }
439static inline int pud_none(pud_t pud) { return 0; }
440static inline int pud_bad(pud_t pud) { return 0; }
441
1da177e4
LT		 442#else /* __s390x__ */
443
5a216a20
MS		 444static inline int pgd_present(pgd_t pgd)
445{
6252d702
MS		 446 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
447 return 1;
5a216a20
MS		 448 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL;
449}
450
451static inline int pgd_none(pgd_t pgd)
452{
6252d702
MS		 453 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
454 return 0;
5a216a20
MS		 455 return (pgd_val(pgd) & _REGION_ENTRY_INV) != 0UL;
456}
457
458static inline int pgd_bad(pgd_t pgd)
459{
6252d702
MS		 460 /*
461 * With dynamic page table levels the pgd can be a region table
462 * entry or a segment table entry. Check for the bit that are
463 * invalid for either table entry.
464 */
5a216a20 465 unsigned long mask =
6252d702 466 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV &
5a216a20
MS		 467 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
468 return (pgd_val(pgd) & mask) != 0;
469}
190a1d72
MS		 470
471static inline int pud_present(pud_t pud)
1da177e4 472{
6252d702
MS		 473 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
474 return 1;
0d017923 475 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL;
1da177e4
LT		 476}
477
190a1d72 478static inline int pud_none(pud_t pud)
1da177e4 479{
6252d702
MS		 480 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
481 return 0;
0d017923 482 return (pud_val(pud) & _REGION_ENTRY_INV) != 0UL;
1da177e4
LT		 483}
484
190a1d72 485static inline int pud_bad(pud_t pud)
1da177e4 486{
6252d702
MS		 487 /*
488 * With dynamic page table levels the pud can be a region table
489 * entry or a segment table entry. Check for the bit that are
490 * invalid for either table entry.
491 */
5a216a20 492 unsigned long mask =
6252d702 493 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV &
5a216a20
MS		 494 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
495 return (pud_val(pud) & mask) != 0;
1da177e4
LT		 496}
497
3610cce8
MS		 498#endif /* __s390x__ */
499
4448aaf0 500static inline int pmd_present(pmd_t pmd)
1da177e4 501{
0d017923 502 return (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) != 0UL;
1da177e4
LT		 503}
504
4448aaf0 505static inline int pmd_none(pmd_t pmd)
1da177e4 506{
0d017923 507 return (pmd_val(pmd) & _SEGMENT_ENTRY_INV) != 0UL;
1da177e4
LT		 508}
509
4448aaf0 510static inline int pmd_bad(pmd_t pmd)
1da177e4 511{
3610cce8
MS		 512 unsigned long mask = ~_SEGMENT_ENTRY_ORIGIN & ~_SEGMENT_ENTRY_INV;
513 return (pmd_val(pmd) & mask) != _SEGMENT_ENTRY;
1da177e4
LT		 514}
515
4448aaf0 516static inline int pte_none(pte_t pte)
1da177e4 517{
83377484 518 return (pte_val(pte) & _PAGE_INVALID) && !(pte_val(pte) & _PAGE_SWT);
1da177e4
LT		 519}
520
4448aaf0 521static inline int pte_present(pte_t pte)
1da177e4 522{
83377484
MS		 523 unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT | _PAGE_SWX;
524 return (pte_val(pte) & mask) == _PAGE_TYPE_NONE ||
525 (!(pte_val(pte) & _PAGE_INVALID) &&
526 !(pte_val(pte) & _PAGE_SWT));
1da177e4
LT		 527}
528
4448aaf0 529static inline int pte_file(pte_t pte)
1da177e4 530{
83377484
MS		 531 unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT;
532 return (pte_val(pte) & mask) == _PAGE_TYPE_FILE;
1da177e4
LT		 533}
534
7e675137
NP		 535static inline int pte_special(pte_t pte)
536{
a08cb629 537 return (pte_val(pte) & _PAGE_SPECIAL);
7e675137
NP		 538}
539
ba8a9229
MS		 540#define __HAVE_ARCH_PTE_SAME
541#define pte_same(a,b) (pte_val(a) == pte_val(b))
1da177e4 542
5b7baf05
CB		 543static inline void rcp_lock(pte_t *ptep)
544{
545#ifdef CONFIG_PGSTE
546 unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
547 preempt_disable();
548 while (test_and_set_bit(RCP_PCL_BIT, pgste))
549 ;
550#endif
551}
552
553static inline void rcp_unlock(pte_t *ptep)
554{
555#ifdef CONFIG_PGSTE
556 unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
557 clear_bit(RCP_PCL_BIT, pgste);
558 preempt_enable();
559#endif
560}
561
562/* forward declaration for SetPageUptodate in page-flags.h*/
563static inline void page_clear_dirty(struct page *page);
564#include <linux/page-flags.h>
565
566static inline void ptep_rcp_copy(pte_t *ptep)
567{
568#ifdef CONFIG_PGSTE
569 struct page *page = virt_to_page(pte_val(*ptep));
570 unsigned int skey;
571 unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
572
573 skey = page_get_storage_key(page_to_phys(page));
574 if (skey & _PAGE_CHANGED)
c71799c1 575 set_bit_simple(RCP_GC_BIT, pgste);
5b7baf05 576 if (skey & _PAGE_REFERENCED)
c71799c1
HC		 577 set_bit_simple(RCP_GR_BIT, pgste);
578 if (test_and_clear_bit_simple(RCP_HC_BIT, pgste))
5b7baf05 579 SetPageDirty(page);
c71799c1 580 if (test_and_clear_bit_simple(RCP_HR_BIT, pgste))
5b7baf05
CB		 581 SetPageReferenced(page);
582#endif
583}
584
1da177e4
LT		 585/*
586 * query functions pte_write/pte_dirty/pte_young only work if
587 * pte_present() is true. Undefined behaviour if not..
588 */
4448aaf0 589static inline int pte_write(pte_t pte)
1da177e4
LT		 590{
591 return (pte_val(pte) & _PAGE_RO) == 0;
592}
593
4448aaf0 594static inline int pte_dirty(pte_t pte)
1da177e4
LT		 595{
596 /* A pte is neither clean nor dirty on s/390. The dirty bit
597 * is in the storage key. See page_test_and_clear_dirty for
598 * details.
599 */
600 return 0;
601}
602
4448aaf0 603static inline int pte_young(pte_t pte)
1da177e4
LT		 604{
605 /* A pte is neither young nor old on s/390. The young bit
606 * is in the storage key. See page_test_and_clear_young for
607 * details.
608 */
609 return 0;
610}
611
1da177e4
LT		 612/*
613 * pgd/pmd/pte modification functions
614 */
615
616#ifndef __s390x__
617
190a1d72
MS		 618#define pgd_clear(pgd) do { } while (0)
619#define pud_clear(pud) do { } while (0)
1da177e4 620
1da177e4
LT		 621#else /* __s390x__ */
622
5a216a20
MS		 623static inline void pgd_clear_kernel(pgd_t * pgd)
624{
6252d702
MS		 625 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
626 pgd_val(*pgd) = _REGION2_ENTRY_EMPTY;
5a216a20
MS		 627}
628
629static inline void pgd_clear(pgd_t * pgd)
630{
631 pgd_t *shadow = get_shadow_table(pgd);
632
633 pgd_clear_kernel(pgd);
634 if (shadow)
635 pgd_clear_kernel(shadow);
636}
190a1d72
MS		 637
638static inline void pud_clear_kernel(pud_t *pud)
1da177e4 639{
6252d702
MS		 640 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
641 pud_val(*pud) = _REGION3_ENTRY_EMPTY;
1da177e4
LT		 642}
643
6252d702 644static inline void pud_clear(pud_t *pud)
c1821c2e 645{
190a1d72 646 pud_t *shadow = get_shadow_table(pud);
c1821c2e 647
190a1d72
MS		 648 pud_clear_kernel(pud);
649 if (shadow)
650 pud_clear_kernel(shadow);
c1821c2e
GS		 651}
652
146e4b3c
MS		 653#endif /* __s390x__ */
654
c1821c2e 655static inline void pmd_clear_kernel(pmd_t * pmdp)
1da177e4 656{
3610cce8 657 pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY;
1da177e4
LT		 658}
659
146e4b3c 660static inline void pmd_clear(pmd_t *pmd)
c1821c2e 661{
146e4b3c 662 pmd_t *shadow = get_shadow_table(pmd);
c1821c2e 663
146e4b3c
MS		 664 pmd_clear_kernel(pmd);
665 if (shadow)
666 pmd_clear_kernel(shadow);
c1821c2e
GS		 667}
668
4448aaf0 669static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
1da177e4 670{
5b7baf05
CB		 671 if (mm->context.pgstes)
672 ptep_rcp_copy(ptep);
9282ed92 673 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
146e4b3c
MS		 674 if (mm->context.noexec)
675 pte_val(ptep[PTRS_PER_PTE]) = _PAGE_TYPE_EMPTY;
1da177e4
LT		 676}
677
678/*
679 * The following pte modification functions only work if
680 * pte_present() is true. Undefined behaviour if not..
681 */
4448aaf0 682static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
1da177e4
LT		 683{
684 pte_val(pte) &= PAGE_MASK;
685 pte_val(pte) |= pgprot_val(newprot);
686 return pte;
687}
688
4448aaf0 689static inline pte_t pte_wrprotect(pte_t pte)
1da177e4 690{
9282ed92 691 /* Do not clobber _PAGE_TYPE_NONE pages! */
1da177e4
LT		 692 if (!(pte_val(pte) & _PAGE_INVALID))
693 pte_val(pte) |= _PAGE_RO;
694 return pte;
695}
696
4448aaf0 697static inline pte_t pte_mkwrite(pte_t pte)
1da177e4
LT		 698{
699 pte_val(pte) &= ~_PAGE_RO;
700 return pte;
701}
702
4448aaf0 703static inline pte_t pte_mkclean(pte_t pte)
1da177e4
LT		 704{
705 /* The only user of pte_mkclean is the fork() code.
706 We must *not* clear the *physical* page dirty bit
707 just because fork() wants to clear the dirty bit in
708 *one* of the page's mappings. So we just do nothing. */
709 return pte;
710}
711
4448aaf0 712static inline pte_t pte_mkdirty(pte_t pte)
1da177e4
LT		 713{
714 /* We do not explicitly set the dirty bit because the
715 * sske instruction is slow. It is faster to let the
716 * next instruction set the dirty bit.
717 */
718 return pte;
719}
720
4448aaf0 721static inline pte_t pte_mkold(pte_t pte)
1da177e4
LT		 722{
723 /* S/390 doesn't keep its dirty/referenced bit in the pte.
724 * There is no point in clearing the real referenced bit.
725 */
726 return pte;
727}
728
4448aaf0 729static inline pte_t pte_mkyoung(pte_t pte)
1da177e4
LT		 730{
731 /* S/390 doesn't keep its dirty/referenced bit in the pte.
732 * There is no point in setting the real referenced bit.
733 */
734 return pte;
735}
736
7e675137
NP		 737static inline pte_t pte_mkspecial(pte_t pte)
738{
a08cb629 739 pte_val(pte) |= _PAGE_SPECIAL;
7e675137
NP		 740 return pte;
741}
742
ba8a9229
MS		 743#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
744static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
745 unsigned long addr, pte_t *ptep)
1da177e4 746{
5b7baf05
CB		 747#ifdef CONFIG_PGSTE
748 unsigned long physpage;
749 int young;
750 unsigned long *pgste;
751
752 if (!vma->vm_mm->context.pgstes)
753 return 0;
754 physpage = pte_val(*ptep) & PAGE_MASK;
755 pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
756
757 young = ((page_get_storage_key(physpage) & _PAGE_REFERENCED) != 0);
758 rcp_lock(ptep);
759 if (young)
c71799c1
HC		 760 set_bit_simple(RCP_GR_BIT, pgste);
761 young |= test_and_clear_bit_simple(RCP_HR_BIT, pgste);
5b7baf05
CB		 762 rcp_unlock(ptep);
763 return young;
764#endif
1da177e4
LT		 765 return 0;
766}
767
ba8a9229
MS		 768#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
769static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
770 unsigned long address, pte_t *ptep)
1da177e4 771{
5b7baf05
CB		 772 /* No need to flush TLB
773 * On s390 reference bits are in storage key and never in TLB
774 * With virtualization we handle the reference bit, without we
775 * we can simply return */
776#ifdef CONFIG_PGSTE
777 return ptep_test_and_clear_young(vma, address, ptep);
778#endif
ba8a9229 779 return 0;
1da177e4
LT		 780}
781
9282ed92 782static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
1da177e4 783{
9282ed92 784 if (!(pte_val(*ptep) & _PAGE_INVALID)) {
1da177e4 785#ifndef __s390x__
146e4b3c 786 /* pto must point to the start of the segment table */
1da177e4 787 pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00);
9282ed92
GS		 788#else
789 /* ipte in zarch mode can do the math */
790 pte_t *pto = ptep;
791#endif
94c12cc7
MS		 792 asm volatile(
793 " ipte %2,%3"
794 : "=m" (*ptep) : "m" (*ptep),
795 "a" (pto), "a" (address));
1da177e4 796 }
9282ed92
GS		 797}
798
146e4b3c
MS		 799static inline void ptep_invalidate(struct mm_struct *mm,
800 unsigned long address, pte_t *ptep)
9282ed92 801{
5b7baf05
CB		 802 if (mm->context.pgstes) {
803 rcp_lock(ptep);
804 __ptep_ipte(address, ptep);
805 ptep_rcp_copy(ptep);
806 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
807 rcp_unlock(ptep);
808 return;
809 }
9282ed92 810 __ptep_ipte(address, ptep);
5b7baf05
CB		 811 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
812 if (mm->context.noexec) {
146e4b3c 813 __ptep_ipte(address, ptep + PTRS_PER_PTE);
5b7baf05
CB		 814 pte_val(*(ptep + PTRS_PER_PTE)) = _PAGE_TYPE_EMPTY;
815 }
f0e47c22
MS		 816}
817
ba8a9229
MS		 818/*
819 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush
820 * both clear the TLB for the unmapped pte. The reason is that
821 * ptep_get_and_clear is used in common code (e.g. change_pte_range)
822 * to modify an active pte. The sequence is
823 * 1) ptep_get_and_clear
824 * 2) set_pte_at
825 * 3) flush_tlb_range
826 * On s390 the tlb needs to get flushed with the modification of the pte
827 * if the pte is active. The only way how this can be implemented is to
828 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range
829 * is a nop.
830 */
831#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
832#define ptep_get_and_clear(__mm, __address, __ptep) \
833({ \
834 pte_t __pte = *(__ptep); \
835 if (atomic_read(&(__mm)->mm_users) > 1 || \
836 (__mm) != current->active_mm) \
146e4b3c 837 ptep_invalidate(__mm, __address, __ptep); \
ba8a9229
MS		 838 else \
839 pte_clear((__mm), (__address), (__ptep)); \
840 __pte; \
841})
842
843#define __HAVE_ARCH_PTEP_CLEAR_FLUSH
f0e47c22
MS		 844static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
845 unsigned long address, pte_t *ptep)
846{
847 pte_t pte = *ptep;
146e4b3c 848 ptep_invalidate(vma->vm_mm, address, ptep);
1da177e4
LT		 849 return pte;
850}
851
ba8a9229
MS		 852/*
853 * The batched pte unmap code uses ptep_get_and_clear_full to clear the
854 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all
855 * tlbs of an mm if it can guarantee that the ptes of the mm_struct
856 * cannot be accessed while the batched unmap is running. In this case
857 * full==1 and a simple pte_clear is enough. See tlb.h.
858 */
859#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
860static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
861 unsigned long addr,
862 pte_t *ptep, int full)
1da177e4 863{
ba8a9229
MS		 864 pte_t pte = *ptep;
865
866 if (full)
867 pte_clear(mm, addr, ptep);
868 else
146e4b3c 869 ptep_invalidate(mm, addr, ptep);
ba8a9229 870 return pte;
1da177e4
LT		 871}
872
ba8a9229
MS		 873#define __HAVE_ARCH_PTEP_SET_WRPROTECT
874#define ptep_set_wrprotect(__mm, __addr, __ptep) \
875({ \
876 pte_t __pte = *(__ptep); \
877 if (pte_write(__pte)) { \
878 if (atomic_read(&(__mm)->mm_users) > 1 || \
879 (__mm) != current->active_mm) \
146e4b3c 880 ptep_invalidate(__mm, __addr, __ptep); \
ba8a9229
MS		 881 set_pte_at(__mm, __addr, __ptep, pte_wrprotect(__pte)); \
882 } \
883})
884
885#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
f0e47c22
MS		 886#define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __dirty) \
887({ \
888 int __changed = !pte_same(*(__ptep), __entry); \
889 if (__changed) { \
146e4b3c 890 ptep_invalidate((__vma)->vm_mm, __addr, __ptep); \
f0e47c22
MS		 891 set_pte_at((__vma)->vm_mm, __addr, __ptep, __entry); \
892 } \
893 __changed; \
8dab5241 894})
1da177e4
LT		 895
896/*
897 * Test and clear dirty bit in storage key.
898 * We can't clear the changed bit atomically. This is a potential
899 * race against modification of the referenced bit. This function
900 * should therefore only be called if it is not mapped in any
901 * address space.
902 */
ba8a9229 903#define __HAVE_ARCH_PAGE_TEST_DIRTY
6c210482 904static inline int page_test_dirty(struct page *page)
2dcea57a 905{
6c210482
MS		 906 return (page_get_storage_key(page_to_phys(page)) & _PAGE_CHANGED) != 0;
907}
2dcea57a 908
ba8a9229 909#define __HAVE_ARCH_PAGE_CLEAR_DIRTY
6c210482
MS		 910static inline void page_clear_dirty(struct page *page)
911{
912 page_set_storage_key(page_to_phys(page), PAGE_DEFAULT_KEY);
2dcea57a 913}
1da177e4
LT		 914
915/*
916 * Test and clear referenced bit in storage key.
917 */
ba8a9229 918#define __HAVE_ARCH_PAGE_TEST_AND_CLEAR_YOUNG
2dcea57a
HC		 919static inline int page_test_and_clear_young(struct page *page)
920{
0b2b6e1d 921 unsigned long physpage = page_to_phys(page);
2dcea57a
HC		 922 int ccode;
923
0b2b6e1d
HC		 924 asm volatile(
925 " rrbe 0,%1\n"
926 " ipm %0\n"
927 " srl %0,28\n"
2dcea57a
HC		 928 : "=d" (ccode) : "a" (physpage) : "cc" );
929 return ccode & 2;
930}
1da177e4
LT		 931
932/*
933 * Conversion functions: convert a page and protection to a page entry,
934 * and a page entry and page directory to the page they refer to.
935 */
936static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
937{
938 pte_t __pte;
939 pte_val(__pte) = physpage + pgprot_val(pgprot);
940 return __pte;
941}
942
2dcea57a
HC		 943static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
944{
0b2b6e1d 945 unsigned long physpage = page_to_phys(page);
1da177e4 946
2dcea57a
HC		 947 return mk_pte_phys(physpage, pgprot);
948}
949
190a1d72
MS		 950#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
951#define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
952#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
953#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
1da177e4 954
190a1d72
MS		 955#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
956#define pgd_offset_k(address) pgd_offset(&init_mm, address)
1da177e4 957
190a1d72 958#ifndef __s390x__
1da177e4 959
190a1d72
MS		 960#define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
961#define pud_deref(pmd) ({ BUG(); 0UL; })
962#define pgd_deref(pmd) ({ BUG(); 0UL; })
46a82b2d 963
190a1d72
MS		 964#define pud_offset(pgd, address) ((pud_t *) pgd)
965#define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address))
1da177e4 966
190a1d72 967#else /* __s390x__ */
1da177e4 968
190a1d72
MS		 969#define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
970#define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN)
5a216a20 971#define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN)
1da177e4 972
5a216a20
MS		 973static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address)
974{
6252d702
MS		 975 pud_t *pud = (pud_t *) pgd;
976 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
977 pud = (pud_t *) pgd_deref(*pgd);
5a216a20
MS		 978 return pud + pud_index(address);
979}
1da177e4 980
190a1d72 981static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
1da177e4 982{
6252d702
MS		 983 pmd_t *pmd = (pmd_t *) pud;
984 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
985 pmd = (pmd_t *) pud_deref(*pud);
190a1d72 986 return pmd + pmd_index(address);
1da177e4
LT		 987}
988
190a1d72 989#endif /* __s390x__ */
1da177e4 990
190a1d72
MS		 991#define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot))
992#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
993#define pte_page(x) pfn_to_page(pte_pfn(x))
1da177e4 994
190a1d72 995#define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
1da177e4 996
190a1d72
MS		 997/* Find an entry in the lowest level page table.. */
998#define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr))
999#define pte_offset_kernel(pmd, address) pte_offset(pmd,address)
1da177e4
LT		 1000#define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
1001#define pte_offset_map_nested(pmd, address) pte_offset_kernel(pmd, address)
1002#define pte_unmap(pte) do { } while (0)
1003#define pte_unmap_nested(pte) do { } while (0)
1004
1005/*
1006 * 31 bit swap entry format:
1007 * A page-table entry has some bits we have to treat in a special way.
1008 * Bits 0, 20 and bit 23 have to be zero, otherwise an specification
1009 * exception will occur instead of a page translation exception. The
1010 * specifiation exception has the bad habit not to store necessary
1011 * information in the lowcore.
1012 * Bit 21 and bit 22 are the page invalid bit and the page protection
1013 * bit. We set both to indicate a swapped page.
1014 * Bit 30 and 31 are used to distinguish the different page types. For
1015 * a swapped page these bits need to be zero.
1016 * This leaves the bits 1-19 and bits 24-29 to store type and offset.
1017 * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19
1018 * plus 24 for the offset.
1019 * 0| offset |0110|o|type |00|
1020 * 0 0000000001111111111 2222 2 22222 33
1021 * 0 1234567890123456789 0123 4 56789 01
1022 *
1023 * 64 bit swap entry format:
1024 * A page-table entry has some bits we have to treat in a special way.
1025 * Bits 52 and bit 55 have to be zero, otherwise an specification
1026 * exception will occur instead of a page translation exception. The
1027 * specifiation exception has the bad habit not to store necessary
1028 * information in the lowcore.
1029 * Bit 53 and bit 54 are the page invalid bit and the page protection
1030 * bit. We set both to indicate a swapped page.
1031 * Bit 62 and 63 are used to distinguish the different page types. For
1032 * a swapped page these bits need to be zero.
1033 * This leaves the bits 0-51 and bits 56-61 to store type and offset.
1034 * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51
1035 * plus 56 for the offset.
1036 * | offset |0110|o|type |00|
1037 * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66
1038 * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23
1039 */
1040#ifndef __s390x__
1041#define __SWP_OFFSET_MASK (~0UL >> 12)
1042#else
1043#define __SWP_OFFSET_MASK (~0UL >> 11)
1044#endif
4448aaf0 1045static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
1da177e4
LT		 1046{
1047 pte_t pte;
1048 offset &= __SWP_OFFSET_MASK;
9282ed92 1049 pte_val(pte) = _PAGE_TYPE_SWAP | ((type & 0x1f) << 2) |
1da177e4
LT		 1050 ((offset & 1UL) << 7) | ((offset & ~1UL) << 11);
1051 return pte;
1052}
1053
1054#define __swp_type(entry) (((entry).val >> 2) & 0x1f)
1055#define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1))
1056#define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
1057
1058#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1059#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
1060
1061#ifndef __s390x__
1062# define PTE_FILE_MAX_BITS 26
1063#else /* __s390x__ */
1064# define PTE_FILE_MAX_BITS 59
1065#endif /* __s390x__ */
1066
1067#define pte_to_pgoff(__pte) \
1068 ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f))
1069
1070#define pgoff_to_pte(__off) \
1071 ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \
9282ed92 1072 | _PAGE_TYPE_FILE })
1da177e4
LT		 1073
1074#endif /* !__ASSEMBLY__ */
1075
1076#define kern_addr_valid(addr) (1)
1077
17f34580
HC		 1078extern int vmem_add_mapping(unsigned long start, unsigned long size);
1079extern int vmem_remove_mapping(unsigned long start, unsigned long size);
402b0862 1080extern int s390_enable_sie(void);
f4eb07c1 1081
1da177e4
LT		 1082/*
1083 * No page table caches to initialise
1084 */
1085#define pgtable_cache_init() do { } while (0)
1086
1da177e4
LT		 1087#include <asm-generic/pgtable.h>
1088
1089#endif /* _S390_PAGE_H */
Linux 6.x block layer and io_uring tree(s)