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1da177e4 LT |
1 | /* |
2 | * include/asm-s390/pgtable.h | |
3 | * | |
4 | * S390 version | |
5 | * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation | |
6 | * Author(s): Hartmut Penner (hp@de.ibm.com) | |
7 | * Ulrich Weigand (weigand@de.ibm.com) | |
8 | * Martin Schwidefsky (schwidefsky@de.ibm.com) | |
9 | * | |
10 | * Derived from "include/asm-i386/pgtable.h" | |
11 | */ | |
12 | ||
13 | #ifndef _ASM_S390_PGTABLE_H | |
14 | #define _ASM_S390_PGTABLE_H | |
15 | ||
1da177e4 LT |
16 | /* |
17 | * The Linux memory management assumes a three-level page table setup. For | |
18 | * s390 31 bit we "fold" the mid level into the top-level page table, so | |
19 | * that we physically have the same two-level page table as the s390 mmu | |
20 | * expects in 31 bit mode. For s390 64 bit we use three of the five levels | |
21 | * the hardware provides (region first and region second tables are not | |
22 | * used). | |
23 | * | |
24 | * The "pgd_xxx()" functions are trivial for a folded two-level | |
25 | * setup: the pgd is never bad, and a pmd always exists (as it's folded | |
26 | * into the pgd entry) | |
27 | * | |
28 | * This file contains the functions and defines necessary to modify and use | |
29 | * the S390 page table tree. | |
30 | */ | |
31 | #ifndef __ASSEMBLY__ | |
2dcea57a | 32 | #include <linux/mm_types.h> |
1da177e4 LT |
33 | #include <asm/bug.h> |
34 | #include <asm/processor.h> | |
1da177e4 | 35 | |
1da177e4 LT |
36 | extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096))); |
37 | extern void paging_init(void); | |
2b67fc46 | 38 | extern void vmem_map_init(void); |
1da177e4 LT |
39 | |
40 | /* | |
41 | * The S390 doesn't have any external MMU info: the kernel page | |
42 | * tables contain all the necessary information. | |
43 | */ | |
44 | #define update_mmu_cache(vma, address, pte) do { } while (0) | |
45 | ||
46 | /* | |
47 | * ZERO_PAGE is a global shared page that is always zero: used | |
48 | * for zero-mapped memory areas etc.. | |
49 | */ | |
50 | extern char empty_zero_page[PAGE_SIZE]; | |
51 | #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) | |
52 | #endif /* !__ASSEMBLY__ */ | |
53 | ||
54 | /* | |
55 | * PMD_SHIFT determines the size of the area a second-level page | |
56 | * table can map | |
57 | * PGDIR_SHIFT determines what a third-level page table entry can map | |
58 | */ | |
59 | #ifndef __s390x__ | |
146e4b3c MS |
60 | # define PMD_SHIFT 20 |
61 | # define PUD_SHIFT 20 | |
62 | # define PGDIR_SHIFT 20 | |
1da177e4 | 63 | #else /* __s390x__ */ |
146e4b3c | 64 | # define PMD_SHIFT 20 |
190a1d72 | 65 | # define PUD_SHIFT 31 |
5a216a20 | 66 | # define PGDIR_SHIFT 42 |
1da177e4 LT |
67 | #endif /* __s390x__ */ |
68 | ||
69 | #define PMD_SIZE (1UL << PMD_SHIFT) | |
70 | #define PMD_MASK (~(PMD_SIZE-1)) | |
190a1d72 MS |
71 | #define PUD_SIZE (1UL << PUD_SHIFT) |
72 | #define PUD_MASK (~(PUD_SIZE-1)) | |
5a216a20 MS |
73 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) |
74 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
1da177e4 LT |
75 | |
76 | /* | |
77 | * entries per page directory level: the S390 is two-level, so | |
78 | * we don't really have any PMD directory physically. | |
79 | * for S390 segment-table entries are combined to one PGD | |
80 | * that leads to 1024 pte per pgd | |
81 | */ | |
146e4b3c | 82 | #define PTRS_PER_PTE 256 |
1da177e4 | 83 | #ifndef __s390x__ |
146e4b3c | 84 | #define PTRS_PER_PMD 1 |
5a216a20 | 85 | #define PTRS_PER_PUD 1 |
1da177e4 | 86 | #else /* __s390x__ */ |
146e4b3c | 87 | #define PTRS_PER_PMD 2048 |
5a216a20 | 88 | #define PTRS_PER_PUD 2048 |
1da177e4 | 89 | #endif /* __s390x__ */ |
146e4b3c | 90 | #define PTRS_PER_PGD 2048 |
1da177e4 | 91 | |
d455a369 HD |
92 | #define FIRST_USER_ADDRESS 0 |
93 | ||
1da177e4 LT |
94 | #define pte_ERROR(e) \ |
95 | printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e)) | |
96 | #define pmd_ERROR(e) \ | |
97 | printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e)) | |
190a1d72 MS |
98 | #define pud_ERROR(e) \ |
99 | printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e)) | |
1da177e4 LT |
100 | #define pgd_ERROR(e) \ |
101 | printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e)) | |
102 | ||
103 | #ifndef __ASSEMBLY__ | |
104 | /* | |
5fd9c6e2 CB |
105 | * The vmalloc area will always be on the topmost area of the kernel |
106 | * mapping. We reserve 96MB (31bit) / 1GB (64bit) for vmalloc, | |
107 | * which should be enough for any sane case. | |
108 | * By putting vmalloc at the top, we maximise the gap between physical | |
109 | * memory and vmalloc to catch misplaced memory accesses. As a side | |
110 | * effect, this also makes sure that 64 bit module code cannot be used | |
111 | * as system call address. | |
8b62bc96 | 112 | */ |
1da177e4 | 113 | #ifndef __s390x__ |
5fd9c6e2 CB |
114 | #define VMALLOC_START 0x78000000UL |
115 | #define VMALLOC_END 0x7e000000UL | |
0189103c | 116 | #define VMEM_MAP_END 0x80000000UL |
1da177e4 | 117 | #else /* __s390x__ */ |
5fd9c6e2 CB |
118 | #define VMALLOC_START 0x3e000000000UL |
119 | #define VMALLOC_END 0x3e040000000UL | |
0189103c | 120 | #define VMEM_MAP_END 0x40000000000UL |
1da177e4 LT |
121 | #endif /* __s390x__ */ |
122 | ||
0189103c HC |
123 | /* |
124 | * VMEM_MAX_PHYS is the highest physical address that can be added to the 1:1 | |
125 | * mapping. This needs to be calculated at compile time since the size of the | |
126 | * VMEM_MAP is static but the size of struct page can change. | |
127 | */ | |
522d8dc0 MS |
128 | #define VMEM_MAX_PAGES ((VMEM_MAP_END - VMALLOC_END) / sizeof(struct page)) |
129 | #define VMEM_MAX_PFN min(VMALLOC_START >> PAGE_SHIFT, VMEM_MAX_PAGES) | |
130 | #define VMEM_MAX_PHYS ((VMEM_MAX_PFN << PAGE_SHIFT) & ~((16 << 20) - 1)) | |
5fd9c6e2 | 131 | #define VMEM_MAP ((struct page *) VMALLOC_END) |
5fd9c6e2 | 132 | |
1da177e4 LT |
133 | /* |
134 | * A 31 bit pagetable entry of S390 has following format: | |
135 | * | PFRA | | OS | | |
136 | * 0 0IP0 | |
137 | * 00000000001111111111222222222233 | |
138 | * 01234567890123456789012345678901 | |
139 | * | |
140 | * I Page-Invalid Bit: Page is not available for address-translation | |
141 | * P Page-Protection Bit: Store access not possible for page | |
142 | * | |
143 | * A 31 bit segmenttable entry of S390 has following format: | |
144 | * | P-table origin | |PTL | |
145 | * 0 IC | |
146 | * 00000000001111111111222222222233 | |
147 | * 01234567890123456789012345678901 | |
148 | * | |
149 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
150 | * C Common-Segment Bit: Segment is not private (PoP 3-30) | |
151 | * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256) | |
152 | * | |
153 | * The 31 bit segmenttable origin of S390 has following format: | |
154 | * | |
155 | * |S-table origin | | STL | | |
156 | * X **GPS | |
157 | * 00000000001111111111222222222233 | |
158 | * 01234567890123456789012345678901 | |
159 | * | |
160 | * X Space-Switch event: | |
161 | * G Segment-Invalid Bit: * | |
162 | * P Private-Space Bit: Segment is not private (PoP 3-30) | |
163 | * S Storage-Alteration: | |
164 | * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048) | |
165 | * | |
166 | * A 64 bit pagetable entry of S390 has following format: | |
167 | * | PFRA |0IP0| OS | | |
168 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
169 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
170 | * | |
171 | * I Page-Invalid Bit: Page is not available for address-translation | |
172 | * P Page-Protection Bit: Store access not possible for page | |
173 | * | |
174 | * A 64 bit segmenttable entry of S390 has following format: | |
175 | * | P-table origin | TT | |
176 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
177 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
178 | * | |
179 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
180 | * C Common-Segment Bit: Segment is not private (PoP 3-30) | |
181 | * P Page-Protection Bit: Store access not possible for page | |
182 | * TT Type 00 | |
183 | * | |
184 | * A 64 bit region table entry of S390 has following format: | |
185 | * | S-table origin | TF TTTL | |
186 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
187 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
188 | * | |
189 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
190 | * TT Type 01 | |
191 | * TF | |
190a1d72 | 192 | * TL Table length |
1da177e4 LT |
193 | * |
194 | * The 64 bit regiontable origin of S390 has following format: | |
195 | * | region table origon | DTTL | |
196 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
197 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
198 | * | |
199 | * X Space-Switch event: | |
200 | * G Segment-Invalid Bit: | |
201 | * P Private-Space Bit: | |
202 | * S Storage-Alteration: | |
203 | * R Real space | |
204 | * TL Table-Length: | |
205 | * | |
206 | * A storage key has the following format: | |
207 | * | ACC |F|R|C|0| | |
208 | * 0 3 4 5 6 7 | |
209 | * ACC: access key | |
210 | * F : fetch protection bit | |
211 | * R : referenced bit | |
212 | * C : changed bit | |
213 | */ | |
214 | ||
215 | /* Hardware bits in the page table entry */ | |
83377484 MS |
216 | #define _PAGE_RO 0x200 /* HW read-only bit */ |
217 | #define _PAGE_INVALID 0x400 /* HW invalid bit */ | |
3610cce8 MS |
218 | |
219 | /* Software bits in the page table entry */ | |
83377484 MS |
220 | #define _PAGE_SWT 0x001 /* SW pte type bit t */ |
221 | #define _PAGE_SWX 0x002 /* SW pte type bit x */ | |
1da177e4 | 222 | |
83377484 | 223 | /* Six different types of pages. */ |
9282ed92 GS |
224 | #define _PAGE_TYPE_EMPTY 0x400 |
225 | #define _PAGE_TYPE_NONE 0x401 | |
83377484 MS |
226 | #define _PAGE_TYPE_SWAP 0x403 |
227 | #define _PAGE_TYPE_FILE 0x601 /* bit 0x002 is used for offset !! */ | |
9282ed92 GS |
228 | #define _PAGE_TYPE_RO 0x200 |
229 | #define _PAGE_TYPE_RW 0x000 | |
c1821c2e GS |
230 | #define _PAGE_TYPE_EX_RO 0x202 |
231 | #define _PAGE_TYPE_EX_RW 0x002 | |
1da177e4 | 232 | |
83377484 MS |
233 | /* |
234 | * PTE type bits are rather complicated. handle_pte_fault uses pte_present, | |
235 | * pte_none and pte_file to find out the pte type WITHOUT holding the page | |
236 | * table lock. ptep_clear_flush on the other hand uses ptep_clear_flush to | |
237 | * invalidate a given pte. ipte sets the hw invalid bit and clears all tlbs | |
238 | * for the page. The page table entry is set to _PAGE_TYPE_EMPTY afterwards. | |
239 | * This change is done while holding the lock, but the intermediate step | |
240 | * of a previously valid pte with the hw invalid bit set can be observed by | |
241 | * handle_pte_fault. That makes it necessary that all valid pte types with | |
242 | * the hw invalid bit set must be distinguishable from the four pte types | |
243 | * empty, none, swap and file. | |
244 | * | |
245 | * irxt ipte irxt | |
246 | * _PAGE_TYPE_EMPTY 1000 -> 1000 | |
247 | * _PAGE_TYPE_NONE 1001 -> 1001 | |
248 | * _PAGE_TYPE_SWAP 1011 -> 1011 | |
249 | * _PAGE_TYPE_FILE 11?1 -> 11?1 | |
250 | * _PAGE_TYPE_RO 0100 -> 1100 | |
251 | * _PAGE_TYPE_RW 0000 -> 1000 | |
c1821c2e GS |
252 | * _PAGE_TYPE_EX_RO 0110 -> 1110 |
253 | * _PAGE_TYPE_EX_RW 0010 -> 1010 | |
83377484 | 254 | * |
c1821c2e | 255 | * pte_none is true for bits combinations 1000, 1010, 1100, 1110 |
83377484 MS |
256 | * pte_present is true for bits combinations 0000, 0010, 0100, 0110, 1001 |
257 | * pte_file is true for bits combinations 1101, 1111 | |
c1821c2e | 258 | * swap pte is 1011 and 0001, 0011, 0101, 0111 are invalid. |
83377484 MS |
259 | */ |
260 | ||
1da177e4 LT |
261 | #ifndef __s390x__ |
262 | ||
3610cce8 MS |
263 | /* Bits in the segment table address-space-control-element */ |
264 | #define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */ | |
265 | #define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */ | |
266 | #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ | |
267 | #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ | |
268 | #define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */ | |
1da177e4 | 269 | |
3610cce8 MS |
270 | /* Bits in the segment table entry */ |
271 | #define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */ | |
272 | #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ | |
273 | #define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */ | |
274 | #define _SEGMENT_ENTRY_PTL 0x0f /* page table length */ | |
1da177e4 | 275 | |
3610cce8 MS |
276 | #define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL) |
277 | #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV) | |
1da177e4 LT |
278 | |
279 | #else /* __s390x__ */ | |
280 | ||
3610cce8 MS |
281 | /* Bits in the segment/region table address-space-control-element */ |
282 | #define _ASCE_ORIGIN ~0xfffUL/* segment table origin */ | |
283 | #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ | |
284 | #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ | |
285 | #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ | |
286 | #define _ASCE_REAL_SPACE 0x20 /* real space control */ | |
287 | #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ | |
288 | #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ | |
289 | #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ | |
290 | #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ | |
291 | #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ | |
292 | #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ | |
293 | ||
294 | /* Bits in the region table entry */ | |
295 | #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ | |
296 | #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */ | |
297 | #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ | |
298 | #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ | |
299 | #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ | |
300 | #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ | |
301 | #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ | |
302 | ||
303 | #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) | |
304 | #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INV) | |
305 | #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) | |
306 | #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INV) | |
307 | #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) | |
308 | #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INV) | |
309 | ||
1da177e4 | 310 | /* Bits in the segment table entry */ |
3610cce8 MS |
311 | #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */ |
312 | #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */ | |
313 | #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ | |
1da177e4 | 314 | |
3610cce8 MS |
315 | #define _SEGMENT_ENTRY (0) |
316 | #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV) | |
317 | ||
318 | #endif /* __s390x__ */ | |
1da177e4 LT |
319 | |
320 | /* | |
3610cce8 MS |
321 | * A user page table pointer has the space-switch-event bit, the |
322 | * private-space-control bit and the storage-alteration-event-control | |
323 | * bit set. A kernel page table pointer doesn't need them. | |
1da177e4 | 324 | */ |
3610cce8 MS |
325 | #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ |
326 | _ASCE_ALT_EVENT) | |
1da177e4 | 327 | |
3610cce8 | 328 | /* Bits int the storage key */ |
1da177e4 LT |
329 | #define _PAGE_CHANGED 0x02 /* HW changed bit */ |
330 | #define _PAGE_REFERENCED 0x04 /* HW referenced bit */ | |
331 | ||
1da177e4 | 332 | /* |
9282ed92 | 333 | * Page protection definitions. |
1da177e4 | 334 | */ |
9282ed92 GS |
335 | #define PAGE_NONE __pgprot(_PAGE_TYPE_NONE) |
336 | #define PAGE_RO __pgprot(_PAGE_TYPE_RO) | |
337 | #define PAGE_RW __pgprot(_PAGE_TYPE_RW) | |
c1821c2e GS |
338 | #define PAGE_EX_RO __pgprot(_PAGE_TYPE_EX_RO) |
339 | #define PAGE_EX_RW __pgprot(_PAGE_TYPE_EX_RW) | |
9282ed92 GS |
340 | |
341 | #define PAGE_KERNEL PAGE_RW | |
342 | #define PAGE_COPY PAGE_RO | |
1da177e4 LT |
343 | |
344 | /* | |
c1821c2e GS |
345 | * Dependent on the EXEC_PROTECT option s390 can do execute protection. |
346 | * Write permission always implies read permission. In theory with a | |
347 | * primary/secondary page table execute only can be implemented but | |
348 | * it would cost an additional bit in the pte to distinguish all the | |
349 | * different pte types. To avoid that execute permission currently | |
350 | * implies read permission as well. | |
1da177e4 LT |
351 | */ |
352 | /*xwr*/ | |
9282ed92 GS |
353 | #define __P000 PAGE_NONE |
354 | #define __P001 PAGE_RO | |
355 | #define __P010 PAGE_RO | |
356 | #define __P011 PAGE_RO | |
c1821c2e GS |
357 | #define __P100 PAGE_EX_RO |
358 | #define __P101 PAGE_EX_RO | |
359 | #define __P110 PAGE_EX_RO | |
360 | #define __P111 PAGE_EX_RO | |
9282ed92 GS |
361 | |
362 | #define __S000 PAGE_NONE | |
363 | #define __S001 PAGE_RO | |
364 | #define __S010 PAGE_RW | |
365 | #define __S011 PAGE_RW | |
c1821c2e GS |
366 | #define __S100 PAGE_EX_RO |
367 | #define __S101 PAGE_EX_RO | |
368 | #define __S110 PAGE_EX_RW | |
369 | #define __S111 PAGE_EX_RW | |
370 | ||
371 | #ifndef __s390x__ | |
3610cce8 | 372 | # define PxD_SHADOW_SHIFT 1 |
c1821c2e | 373 | #else /* __s390x__ */ |
3610cce8 | 374 | # define PxD_SHADOW_SHIFT 2 |
c1821c2e GS |
375 | #endif /* __s390x__ */ |
376 | ||
3610cce8 | 377 | static inline void *get_shadow_table(void *table) |
c1821c2e | 378 | { |
3610cce8 MS |
379 | unsigned long addr, offset; |
380 | struct page *page; | |
381 | ||
382 | addr = (unsigned long) table; | |
383 | offset = addr & ((PAGE_SIZE << PxD_SHADOW_SHIFT) - 1); | |
384 | page = virt_to_page((void *)(addr ^ offset)); | |
385 | return (void *)(addr_t)(page->index ? (page->index | offset) : 0UL); | |
c1821c2e | 386 | } |
1da177e4 LT |
387 | |
388 | /* | |
389 | * Certain architectures need to do special things when PTEs | |
390 | * within a page table are directly modified. Thus, the following | |
391 | * hook is made available. | |
392 | */ | |
ba8a9229 | 393 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, |
146e4b3c | 394 | pte_t *ptep, pte_t entry) |
1da177e4 | 395 | { |
146e4b3c MS |
396 | *ptep = entry; |
397 | if (mm->context.noexec) { | |
398 | if (!(pte_val(entry) & _PAGE_INVALID) && | |
399 | (pte_val(entry) & _PAGE_SWX)) | |
400 | pte_val(entry) |= _PAGE_RO; | |
c1821c2e | 401 | else |
146e4b3c MS |
402 | pte_val(entry) = _PAGE_TYPE_EMPTY; |
403 | ptep[PTRS_PER_PTE] = entry; | |
c1821c2e | 404 | } |
1da177e4 | 405 | } |
1da177e4 LT |
406 | |
407 | /* | |
408 | * pgd/pmd/pte query functions | |
409 | */ | |
410 | #ifndef __s390x__ | |
411 | ||
4448aaf0 AB |
412 | static inline int pgd_present(pgd_t pgd) { return 1; } |
413 | static inline int pgd_none(pgd_t pgd) { return 0; } | |
414 | static inline int pgd_bad(pgd_t pgd) { return 0; } | |
1da177e4 | 415 | |
190a1d72 MS |
416 | static inline int pud_present(pud_t pud) { return 1; } |
417 | static inline int pud_none(pud_t pud) { return 0; } | |
418 | static inline int pud_bad(pud_t pud) { return 0; } | |
419 | ||
1da177e4 LT |
420 | #else /* __s390x__ */ |
421 | ||
5a216a20 MS |
422 | static inline int pgd_present(pgd_t pgd) |
423 | { | |
424 | return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; | |
425 | } | |
426 | ||
427 | static inline int pgd_none(pgd_t pgd) | |
428 | { | |
429 | return (pgd_val(pgd) & _REGION_ENTRY_INV) != 0UL; | |
430 | } | |
431 | ||
432 | static inline int pgd_bad(pgd_t pgd) | |
433 | { | |
434 | unsigned long mask = | |
435 | ~_REGION_ENTRY_ORIGIN & ~_REGION_ENTRY_INV & | |
436 | ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; | |
437 | return (pgd_val(pgd) & mask) != 0; | |
438 | } | |
190a1d72 MS |
439 | |
440 | static inline int pud_present(pud_t pud) | |
1da177e4 | 441 | { |
0d017923 | 442 | return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; |
1da177e4 LT |
443 | } |
444 | ||
190a1d72 | 445 | static inline int pud_none(pud_t pud) |
1da177e4 | 446 | { |
0d017923 | 447 | return (pud_val(pud) & _REGION_ENTRY_INV) != 0UL; |
1da177e4 LT |
448 | } |
449 | ||
190a1d72 | 450 | static inline int pud_bad(pud_t pud) |
1da177e4 | 451 | { |
5a216a20 MS |
452 | unsigned long mask = |
453 | ~_REGION_ENTRY_ORIGIN & ~_REGION_ENTRY_INV & | |
454 | ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; | |
455 | return (pud_val(pud) & mask) != 0; | |
1da177e4 LT |
456 | } |
457 | ||
3610cce8 MS |
458 | #endif /* __s390x__ */ |
459 | ||
4448aaf0 | 460 | static inline int pmd_present(pmd_t pmd) |
1da177e4 | 461 | { |
0d017923 | 462 | return (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) != 0UL; |
1da177e4 LT |
463 | } |
464 | ||
4448aaf0 | 465 | static inline int pmd_none(pmd_t pmd) |
1da177e4 | 466 | { |
0d017923 | 467 | return (pmd_val(pmd) & _SEGMENT_ENTRY_INV) != 0UL; |
1da177e4 LT |
468 | } |
469 | ||
4448aaf0 | 470 | static inline int pmd_bad(pmd_t pmd) |
1da177e4 | 471 | { |
3610cce8 MS |
472 | unsigned long mask = ~_SEGMENT_ENTRY_ORIGIN & ~_SEGMENT_ENTRY_INV; |
473 | return (pmd_val(pmd) & mask) != _SEGMENT_ENTRY; | |
1da177e4 LT |
474 | } |
475 | ||
4448aaf0 | 476 | static inline int pte_none(pte_t pte) |
1da177e4 | 477 | { |
83377484 | 478 | return (pte_val(pte) & _PAGE_INVALID) && !(pte_val(pte) & _PAGE_SWT); |
1da177e4 LT |
479 | } |
480 | ||
4448aaf0 | 481 | static inline int pte_present(pte_t pte) |
1da177e4 | 482 | { |
83377484 MS |
483 | unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT | _PAGE_SWX; |
484 | return (pte_val(pte) & mask) == _PAGE_TYPE_NONE || | |
485 | (!(pte_val(pte) & _PAGE_INVALID) && | |
486 | !(pte_val(pte) & _PAGE_SWT)); | |
1da177e4 LT |
487 | } |
488 | ||
4448aaf0 | 489 | static inline int pte_file(pte_t pte) |
1da177e4 | 490 | { |
83377484 MS |
491 | unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT; |
492 | return (pte_val(pte) & mask) == _PAGE_TYPE_FILE; | |
1da177e4 LT |
493 | } |
494 | ||
ba8a9229 MS |
495 | #define __HAVE_ARCH_PTE_SAME |
496 | #define pte_same(a,b) (pte_val(a) == pte_val(b)) | |
1da177e4 LT |
497 | |
498 | /* | |
499 | * query functions pte_write/pte_dirty/pte_young only work if | |
500 | * pte_present() is true. Undefined behaviour if not.. | |
501 | */ | |
4448aaf0 | 502 | static inline int pte_write(pte_t pte) |
1da177e4 LT |
503 | { |
504 | return (pte_val(pte) & _PAGE_RO) == 0; | |
505 | } | |
506 | ||
4448aaf0 | 507 | static inline int pte_dirty(pte_t pte) |
1da177e4 LT |
508 | { |
509 | /* A pte is neither clean nor dirty on s/390. The dirty bit | |
510 | * is in the storage key. See page_test_and_clear_dirty for | |
511 | * details. | |
512 | */ | |
513 | return 0; | |
514 | } | |
515 | ||
4448aaf0 | 516 | static inline int pte_young(pte_t pte) |
1da177e4 LT |
517 | { |
518 | /* A pte is neither young nor old on s/390. The young bit | |
519 | * is in the storage key. See page_test_and_clear_young for | |
520 | * details. | |
521 | */ | |
522 | return 0; | |
523 | } | |
524 | ||
1da177e4 LT |
525 | /* |
526 | * pgd/pmd/pte modification functions | |
527 | */ | |
528 | ||
529 | #ifndef __s390x__ | |
530 | ||
190a1d72 MS |
531 | #define pgd_clear(pgd) do { } while (0) |
532 | #define pud_clear(pud) do { } while (0) | |
1da177e4 | 533 | |
1da177e4 LT |
534 | #else /* __s390x__ */ |
535 | ||
5a216a20 MS |
536 | static inline void pgd_clear_kernel(pgd_t * pgd) |
537 | { | |
538 | pgd_val(*pgd) = _REGION2_ENTRY_EMPTY; | |
539 | } | |
540 | ||
541 | static inline void pgd_clear(pgd_t * pgd) | |
542 | { | |
543 | pgd_t *shadow = get_shadow_table(pgd); | |
544 | ||
545 | pgd_clear_kernel(pgd); | |
546 | if (shadow) | |
547 | pgd_clear_kernel(shadow); | |
548 | } | |
190a1d72 MS |
549 | |
550 | static inline void pud_clear_kernel(pud_t *pud) | |
1da177e4 | 551 | { |
190a1d72 | 552 | pud_val(*pud) = _REGION3_ENTRY_EMPTY; |
1da177e4 LT |
553 | } |
554 | ||
190a1d72 | 555 | static inline void pud_clear(pud_t * pud) |
c1821c2e | 556 | { |
190a1d72 | 557 | pud_t *shadow = get_shadow_table(pud); |
c1821c2e | 558 | |
190a1d72 MS |
559 | pud_clear_kernel(pud); |
560 | if (shadow) | |
561 | pud_clear_kernel(shadow); | |
c1821c2e GS |
562 | } |
563 | ||
146e4b3c MS |
564 | #endif /* __s390x__ */ |
565 | ||
c1821c2e | 566 | static inline void pmd_clear_kernel(pmd_t * pmdp) |
1da177e4 | 567 | { |
3610cce8 | 568 | pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY; |
1da177e4 LT |
569 | } |
570 | ||
146e4b3c | 571 | static inline void pmd_clear(pmd_t *pmd) |
c1821c2e | 572 | { |
146e4b3c | 573 | pmd_t *shadow = get_shadow_table(pmd); |
c1821c2e | 574 | |
146e4b3c MS |
575 | pmd_clear_kernel(pmd); |
576 | if (shadow) | |
577 | pmd_clear_kernel(shadow); | |
c1821c2e GS |
578 | } |
579 | ||
4448aaf0 | 580 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) |
1da177e4 | 581 | { |
9282ed92 | 582 | pte_val(*ptep) = _PAGE_TYPE_EMPTY; |
146e4b3c MS |
583 | if (mm->context.noexec) |
584 | pte_val(ptep[PTRS_PER_PTE]) = _PAGE_TYPE_EMPTY; | |
1da177e4 LT |
585 | } |
586 | ||
587 | /* | |
588 | * The following pte modification functions only work if | |
589 | * pte_present() is true. Undefined behaviour if not.. | |
590 | */ | |
4448aaf0 | 591 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
1da177e4 LT |
592 | { |
593 | pte_val(pte) &= PAGE_MASK; | |
594 | pte_val(pte) |= pgprot_val(newprot); | |
595 | return pte; | |
596 | } | |
597 | ||
4448aaf0 | 598 | static inline pte_t pte_wrprotect(pte_t pte) |
1da177e4 | 599 | { |
9282ed92 | 600 | /* Do not clobber _PAGE_TYPE_NONE pages! */ |
1da177e4 LT |
601 | if (!(pte_val(pte) & _PAGE_INVALID)) |
602 | pte_val(pte) |= _PAGE_RO; | |
603 | return pte; | |
604 | } | |
605 | ||
4448aaf0 | 606 | static inline pte_t pte_mkwrite(pte_t pte) |
1da177e4 LT |
607 | { |
608 | pte_val(pte) &= ~_PAGE_RO; | |
609 | return pte; | |
610 | } | |
611 | ||
4448aaf0 | 612 | static inline pte_t pte_mkclean(pte_t pte) |
1da177e4 LT |
613 | { |
614 | /* The only user of pte_mkclean is the fork() code. | |
615 | We must *not* clear the *physical* page dirty bit | |
616 | just because fork() wants to clear the dirty bit in | |
617 | *one* of the page's mappings. So we just do nothing. */ | |
618 | return pte; | |
619 | } | |
620 | ||
4448aaf0 | 621 | static inline pte_t pte_mkdirty(pte_t pte) |
1da177e4 LT |
622 | { |
623 | /* We do not explicitly set the dirty bit because the | |
624 | * sske instruction is slow. It is faster to let the | |
625 | * next instruction set the dirty bit. | |
626 | */ | |
627 | return pte; | |
628 | } | |
629 | ||
4448aaf0 | 630 | static inline pte_t pte_mkold(pte_t pte) |
1da177e4 LT |
631 | { |
632 | /* S/390 doesn't keep its dirty/referenced bit in the pte. | |
633 | * There is no point in clearing the real referenced bit. | |
634 | */ | |
635 | return pte; | |
636 | } | |
637 | ||
4448aaf0 | 638 | static inline pte_t pte_mkyoung(pte_t pte) |
1da177e4 LT |
639 | { |
640 | /* S/390 doesn't keep its dirty/referenced bit in the pte. | |
641 | * There is no point in setting the real referenced bit. | |
642 | */ | |
643 | return pte; | |
644 | } | |
645 | ||
ba8a9229 MS |
646 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG |
647 | static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, | |
648 | unsigned long addr, pte_t *ptep) | |
1da177e4 LT |
649 | { |
650 | return 0; | |
651 | } | |
652 | ||
ba8a9229 MS |
653 | #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH |
654 | static inline int ptep_clear_flush_young(struct vm_area_struct *vma, | |
655 | unsigned long address, pte_t *ptep) | |
1da177e4 LT |
656 | { |
657 | /* No need to flush TLB; bits are in storage key */ | |
ba8a9229 | 658 | return 0; |
1da177e4 LT |
659 | } |
660 | ||
9282ed92 | 661 | static inline void __ptep_ipte(unsigned long address, pte_t *ptep) |
1da177e4 | 662 | { |
9282ed92 | 663 | if (!(pte_val(*ptep) & _PAGE_INVALID)) { |
1da177e4 | 664 | #ifndef __s390x__ |
146e4b3c | 665 | /* pto must point to the start of the segment table */ |
1da177e4 | 666 | pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00); |
9282ed92 GS |
667 | #else |
668 | /* ipte in zarch mode can do the math */ | |
669 | pte_t *pto = ptep; | |
670 | #endif | |
94c12cc7 MS |
671 | asm volatile( |
672 | " ipte %2,%3" | |
673 | : "=m" (*ptep) : "m" (*ptep), | |
674 | "a" (pto), "a" (address)); | |
1da177e4 | 675 | } |
9282ed92 GS |
676 | pte_val(*ptep) = _PAGE_TYPE_EMPTY; |
677 | } | |
678 | ||
146e4b3c MS |
679 | static inline void ptep_invalidate(struct mm_struct *mm, |
680 | unsigned long address, pte_t *ptep) | |
9282ed92 | 681 | { |
9282ed92 | 682 | __ptep_ipte(address, ptep); |
146e4b3c MS |
683 | if (mm->context.noexec) |
684 | __ptep_ipte(address, ptep + PTRS_PER_PTE); | |
f0e47c22 MS |
685 | } |
686 | ||
ba8a9229 MS |
687 | /* |
688 | * This is hard to understand. ptep_get_and_clear and ptep_clear_flush | |
689 | * both clear the TLB for the unmapped pte. The reason is that | |
690 | * ptep_get_and_clear is used in common code (e.g. change_pte_range) | |
691 | * to modify an active pte. The sequence is | |
692 | * 1) ptep_get_and_clear | |
693 | * 2) set_pte_at | |
694 | * 3) flush_tlb_range | |
695 | * On s390 the tlb needs to get flushed with the modification of the pte | |
696 | * if the pte is active. The only way how this can be implemented is to | |
697 | * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range | |
698 | * is a nop. | |
699 | */ | |
700 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | |
701 | #define ptep_get_and_clear(__mm, __address, __ptep) \ | |
702 | ({ \ | |
703 | pte_t __pte = *(__ptep); \ | |
704 | if (atomic_read(&(__mm)->mm_users) > 1 || \ | |
705 | (__mm) != current->active_mm) \ | |
146e4b3c | 706 | ptep_invalidate(__mm, __address, __ptep); \ |
ba8a9229 MS |
707 | else \ |
708 | pte_clear((__mm), (__address), (__ptep)); \ | |
709 | __pte; \ | |
710 | }) | |
711 | ||
712 | #define __HAVE_ARCH_PTEP_CLEAR_FLUSH | |
f0e47c22 MS |
713 | static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, |
714 | unsigned long address, pte_t *ptep) | |
715 | { | |
716 | pte_t pte = *ptep; | |
146e4b3c | 717 | ptep_invalidate(vma->vm_mm, address, ptep); |
1da177e4 LT |
718 | return pte; |
719 | } | |
720 | ||
ba8a9229 MS |
721 | /* |
722 | * The batched pte unmap code uses ptep_get_and_clear_full to clear the | |
723 | * ptes. Here an optimization is possible. tlb_gather_mmu flushes all | |
724 | * tlbs of an mm if it can guarantee that the ptes of the mm_struct | |
725 | * cannot be accessed while the batched unmap is running. In this case | |
726 | * full==1 and a simple pte_clear is enough. See tlb.h. | |
727 | */ | |
728 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL | |
729 | static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, | |
730 | unsigned long addr, | |
731 | pte_t *ptep, int full) | |
1da177e4 | 732 | { |
ba8a9229 MS |
733 | pte_t pte = *ptep; |
734 | ||
735 | if (full) | |
736 | pte_clear(mm, addr, ptep); | |
737 | else | |
146e4b3c | 738 | ptep_invalidate(mm, addr, ptep); |
ba8a9229 | 739 | return pte; |
1da177e4 LT |
740 | } |
741 | ||
ba8a9229 MS |
742 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT |
743 | #define ptep_set_wrprotect(__mm, __addr, __ptep) \ | |
744 | ({ \ | |
745 | pte_t __pte = *(__ptep); \ | |
746 | if (pte_write(__pte)) { \ | |
747 | if (atomic_read(&(__mm)->mm_users) > 1 || \ | |
748 | (__mm) != current->active_mm) \ | |
146e4b3c | 749 | ptep_invalidate(__mm, __addr, __ptep); \ |
ba8a9229 MS |
750 | set_pte_at(__mm, __addr, __ptep, pte_wrprotect(__pte)); \ |
751 | } \ | |
752 | }) | |
753 | ||
754 | #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS | |
f0e47c22 MS |
755 | #define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __dirty) \ |
756 | ({ \ | |
757 | int __changed = !pte_same(*(__ptep), __entry); \ | |
758 | if (__changed) { \ | |
146e4b3c | 759 | ptep_invalidate((__vma)->vm_mm, __addr, __ptep); \ |
f0e47c22 MS |
760 | set_pte_at((__vma)->vm_mm, __addr, __ptep, __entry); \ |
761 | } \ | |
762 | __changed; \ | |
8dab5241 | 763 | }) |
1da177e4 LT |
764 | |
765 | /* | |
766 | * Test and clear dirty bit in storage key. | |
767 | * We can't clear the changed bit atomically. This is a potential | |
768 | * race against modification of the referenced bit. This function | |
769 | * should therefore only be called if it is not mapped in any | |
770 | * address space. | |
771 | */ | |
ba8a9229 | 772 | #define __HAVE_ARCH_PAGE_TEST_DIRTY |
6c210482 | 773 | static inline int page_test_dirty(struct page *page) |
2dcea57a | 774 | { |
6c210482 MS |
775 | return (page_get_storage_key(page_to_phys(page)) & _PAGE_CHANGED) != 0; |
776 | } | |
2dcea57a | 777 | |
ba8a9229 | 778 | #define __HAVE_ARCH_PAGE_CLEAR_DIRTY |
6c210482 MS |
779 | static inline void page_clear_dirty(struct page *page) |
780 | { | |
781 | page_set_storage_key(page_to_phys(page), PAGE_DEFAULT_KEY); | |
2dcea57a | 782 | } |
1da177e4 LT |
783 | |
784 | /* | |
785 | * Test and clear referenced bit in storage key. | |
786 | */ | |
ba8a9229 | 787 | #define __HAVE_ARCH_PAGE_TEST_AND_CLEAR_YOUNG |
2dcea57a HC |
788 | static inline int page_test_and_clear_young(struct page *page) |
789 | { | |
0b2b6e1d | 790 | unsigned long physpage = page_to_phys(page); |
2dcea57a HC |
791 | int ccode; |
792 | ||
0b2b6e1d HC |
793 | asm volatile( |
794 | " rrbe 0,%1\n" | |
795 | " ipm %0\n" | |
796 | " srl %0,28\n" | |
2dcea57a HC |
797 | : "=d" (ccode) : "a" (physpage) : "cc" ); |
798 | return ccode & 2; | |
799 | } | |
1da177e4 LT |
800 | |
801 | /* | |
802 | * Conversion functions: convert a page and protection to a page entry, | |
803 | * and a page entry and page directory to the page they refer to. | |
804 | */ | |
805 | static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) | |
806 | { | |
807 | pte_t __pte; | |
808 | pte_val(__pte) = physpage + pgprot_val(pgprot); | |
809 | return __pte; | |
810 | } | |
811 | ||
2dcea57a HC |
812 | static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) |
813 | { | |
0b2b6e1d | 814 | unsigned long physpage = page_to_phys(page); |
1da177e4 | 815 | |
2dcea57a HC |
816 | return mk_pte_phys(physpage, pgprot); |
817 | } | |
818 | ||
190a1d72 MS |
819 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) |
820 | #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) | |
821 | #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) | |
822 | #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) | |
1da177e4 | 823 | |
190a1d72 MS |
824 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) |
825 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | |
1da177e4 | 826 | |
190a1d72 | 827 | #ifndef __s390x__ |
1da177e4 | 828 | |
190a1d72 MS |
829 | #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) |
830 | #define pud_deref(pmd) ({ BUG(); 0UL; }) | |
831 | #define pgd_deref(pmd) ({ BUG(); 0UL; }) | |
46a82b2d | 832 | |
190a1d72 MS |
833 | #define pud_offset(pgd, address) ((pud_t *) pgd) |
834 | #define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address)) | |
1da177e4 | 835 | |
190a1d72 | 836 | #else /* __s390x__ */ |
1da177e4 | 837 | |
190a1d72 MS |
838 | #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) |
839 | #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN) | |
5a216a20 | 840 | #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) |
1da177e4 | 841 | |
5a216a20 MS |
842 | static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address) |
843 | { | |
844 | pud_t *pud = (pud_t *) pgd_deref(*pgd); | |
845 | return pud + pud_index(address); | |
846 | } | |
1da177e4 | 847 | |
190a1d72 | 848 | static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) |
1da177e4 | 849 | { |
190a1d72 MS |
850 | pmd_t *pmd = (pmd_t *) pud_deref(*pud); |
851 | return pmd + pmd_index(address); | |
1da177e4 LT |
852 | } |
853 | ||
190a1d72 | 854 | #endif /* __s390x__ */ |
1da177e4 | 855 | |
190a1d72 MS |
856 | #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot)) |
857 | #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) | |
858 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | |
1da177e4 | 859 | |
190a1d72 | 860 | #define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT) |
1da177e4 | 861 | |
190a1d72 MS |
862 | /* Find an entry in the lowest level page table.. */ |
863 | #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr)) | |
864 | #define pte_offset_kernel(pmd, address) pte_offset(pmd,address) | |
1da177e4 LT |
865 | #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address) |
866 | #define pte_offset_map_nested(pmd, address) pte_offset_kernel(pmd, address) | |
867 | #define pte_unmap(pte) do { } while (0) | |
868 | #define pte_unmap_nested(pte) do { } while (0) | |
869 | ||
870 | /* | |
871 | * 31 bit swap entry format: | |
872 | * A page-table entry has some bits we have to treat in a special way. | |
873 | * Bits 0, 20 and bit 23 have to be zero, otherwise an specification | |
874 | * exception will occur instead of a page translation exception. The | |
875 | * specifiation exception has the bad habit not to store necessary | |
876 | * information in the lowcore. | |
877 | * Bit 21 and bit 22 are the page invalid bit and the page protection | |
878 | * bit. We set both to indicate a swapped page. | |
879 | * Bit 30 and 31 are used to distinguish the different page types. For | |
880 | * a swapped page these bits need to be zero. | |
881 | * This leaves the bits 1-19 and bits 24-29 to store type and offset. | |
882 | * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19 | |
883 | * plus 24 for the offset. | |
884 | * 0| offset |0110|o|type |00| | |
885 | * 0 0000000001111111111 2222 2 22222 33 | |
886 | * 0 1234567890123456789 0123 4 56789 01 | |
887 | * | |
888 | * 64 bit swap entry format: | |
889 | * A page-table entry has some bits we have to treat in a special way. | |
890 | * Bits 52 and bit 55 have to be zero, otherwise an specification | |
891 | * exception will occur instead of a page translation exception. The | |
892 | * specifiation exception has the bad habit not to store necessary | |
893 | * information in the lowcore. | |
894 | * Bit 53 and bit 54 are the page invalid bit and the page protection | |
895 | * bit. We set both to indicate a swapped page. | |
896 | * Bit 62 and 63 are used to distinguish the different page types. For | |
897 | * a swapped page these bits need to be zero. | |
898 | * This leaves the bits 0-51 and bits 56-61 to store type and offset. | |
899 | * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51 | |
900 | * plus 56 for the offset. | |
901 | * | offset |0110|o|type |00| | |
902 | * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66 | |
903 | * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23 | |
904 | */ | |
905 | #ifndef __s390x__ | |
906 | #define __SWP_OFFSET_MASK (~0UL >> 12) | |
907 | #else | |
908 | #define __SWP_OFFSET_MASK (~0UL >> 11) | |
909 | #endif | |
4448aaf0 | 910 | static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) |
1da177e4 LT |
911 | { |
912 | pte_t pte; | |
913 | offset &= __SWP_OFFSET_MASK; | |
9282ed92 | 914 | pte_val(pte) = _PAGE_TYPE_SWAP | ((type & 0x1f) << 2) | |
1da177e4 LT |
915 | ((offset & 1UL) << 7) | ((offset & ~1UL) << 11); |
916 | return pte; | |
917 | } | |
918 | ||
919 | #define __swp_type(entry) (((entry).val >> 2) & 0x1f) | |
920 | #define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1)) | |
921 | #define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) }) | |
922 | ||
923 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | |
924 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | |
925 | ||
926 | #ifndef __s390x__ | |
927 | # define PTE_FILE_MAX_BITS 26 | |
928 | #else /* __s390x__ */ | |
929 | # define PTE_FILE_MAX_BITS 59 | |
930 | #endif /* __s390x__ */ | |
931 | ||
932 | #define pte_to_pgoff(__pte) \ | |
933 | ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f)) | |
934 | ||
935 | #define pgoff_to_pte(__off) \ | |
936 | ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \ | |
9282ed92 | 937 | | _PAGE_TYPE_FILE }) |
1da177e4 LT |
938 | |
939 | #endif /* !__ASSEMBLY__ */ | |
940 | ||
941 | #define kern_addr_valid(addr) (1) | |
942 | ||
f4eb07c1 HC |
943 | extern int add_shared_memory(unsigned long start, unsigned long size); |
944 | extern int remove_shared_memory(unsigned long start, unsigned long size); | |
945 | ||
1da177e4 LT |
946 | /* |
947 | * No page table caches to initialise | |
948 | */ | |
949 | #define pgtable_cache_init() do { } while (0) | |
950 | ||
f4eb07c1 HC |
951 | #define __HAVE_ARCH_MEMMAP_INIT |
952 | extern void memmap_init(unsigned long, int, unsigned long, unsigned long); | |
953 | ||
1da177e4 LT |
954 | #include <asm-generic/pgtable.h> |
955 | ||
956 | #endif /* _S390_PAGE_H */ |