[S390] monwriter find header logic.
[linux-2.6-block.git] / include / asm-s390 / pgtable.h
CommitLineData
1da177e4
LT
1/*
2 * include/asm-s390/pgtable.h
3 *
4 * S390 version
5 * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Hartmut Penner (hp@de.ibm.com)
7 * Ulrich Weigand (weigand@de.ibm.com)
8 * Martin Schwidefsky (schwidefsky@de.ibm.com)
9 *
10 * Derived from "include/asm-i386/pgtable.h"
11 */
12
13#ifndef _ASM_S390_PGTABLE_H
14#define _ASM_S390_PGTABLE_H
15
16#include <asm-generic/4level-fixup.h>
17
18/*
19 * The Linux memory management assumes a three-level page table setup. For
20 * s390 31 bit we "fold" the mid level into the top-level page table, so
21 * that we physically have the same two-level page table as the s390 mmu
22 * expects in 31 bit mode. For s390 64 bit we use three of the five levels
23 * the hardware provides (region first and region second tables are not
24 * used).
25 *
26 * The "pgd_xxx()" functions are trivial for a folded two-level
27 * setup: the pgd is never bad, and a pmd always exists (as it's folded
28 * into the pgd entry)
29 *
30 * This file contains the functions and defines necessary to modify and use
31 * the S390 page table tree.
32 */
33#ifndef __ASSEMBLY__
2dcea57a 34#include <linux/mm_types.h>
1da177e4
LT
35#include <asm/bug.h>
36#include <asm/processor.h>
1da177e4
LT
37
38struct vm_area_struct; /* forward declaration (include/linux/mm.h) */
8c65b4a6 39struct mm_struct;
1da177e4
LT
40
41extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096)));
42extern void paging_init(void);
43
44/*
45 * The S390 doesn't have any external MMU info: the kernel page
46 * tables contain all the necessary information.
47 */
48#define update_mmu_cache(vma, address, pte) do { } while (0)
49
50/*
51 * ZERO_PAGE is a global shared page that is always zero: used
52 * for zero-mapped memory areas etc..
53 */
54extern char empty_zero_page[PAGE_SIZE];
55#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
56#endif /* !__ASSEMBLY__ */
57
58/*
59 * PMD_SHIFT determines the size of the area a second-level page
60 * table can map
61 * PGDIR_SHIFT determines what a third-level page table entry can map
62 */
63#ifndef __s390x__
64# define PMD_SHIFT 22
65# define PGDIR_SHIFT 22
66#else /* __s390x__ */
67# define PMD_SHIFT 21
68# define PGDIR_SHIFT 31
69#endif /* __s390x__ */
70
71#define PMD_SIZE (1UL << PMD_SHIFT)
72#define PMD_MASK (~(PMD_SIZE-1))
73#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
74#define PGDIR_MASK (~(PGDIR_SIZE-1))
75
76/*
77 * entries per page directory level: the S390 is two-level, so
78 * we don't really have any PMD directory physically.
79 * for S390 segment-table entries are combined to one PGD
80 * that leads to 1024 pte per pgd
81 */
82#ifndef __s390x__
83# define PTRS_PER_PTE 1024
84# define PTRS_PER_PMD 1
85# define PTRS_PER_PGD 512
86#else /* __s390x__ */
87# define PTRS_PER_PTE 512
88# define PTRS_PER_PMD 1024
89# define PTRS_PER_PGD 2048
90#endif /* __s390x__ */
91
d455a369
HD
92#define FIRST_USER_ADDRESS 0
93
1da177e4
LT
94#define pte_ERROR(e) \
95 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e))
96#define pmd_ERROR(e) \
97 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e))
98#define pgd_ERROR(e) \
99 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e))
100
101#ifndef __ASSEMBLY__
102/*
103 * Just any arbitrary offset to the start of the vmalloc VM area: the
104 * current 8MB value just means that there will be a 8MB "hole" after the
105 * physical memory until the kernel virtual memory starts. That means that
106 * any out-of-bounds memory accesses will hopefully be caught.
107 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
108 * area for the same reason. ;)
109 */
110#define VMALLOC_OFFSET (8*1024*1024)
111#define VMALLOC_START (((unsigned long) high_memory + VMALLOC_OFFSET) \
112 & ~(VMALLOC_OFFSET-1))
113#ifndef __s390x__
114# define VMALLOC_END (0x7fffffffL)
115#else /* __s390x__ */
116# define VMALLOC_END (0x40000000000L)
117#endif /* __s390x__ */
118
119
120/*
121 * A 31 bit pagetable entry of S390 has following format:
122 * | PFRA | | OS |
123 * 0 0IP0
124 * 00000000001111111111222222222233
125 * 01234567890123456789012345678901
126 *
127 * I Page-Invalid Bit: Page is not available for address-translation
128 * P Page-Protection Bit: Store access not possible for page
129 *
130 * A 31 bit segmenttable entry of S390 has following format:
131 * | P-table origin | |PTL
132 * 0 IC
133 * 00000000001111111111222222222233
134 * 01234567890123456789012345678901
135 *
136 * I Segment-Invalid Bit: Segment is not available for address-translation
137 * C Common-Segment Bit: Segment is not private (PoP 3-30)
138 * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256)
139 *
140 * The 31 bit segmenttable origin of S390 has following format:
141 *
142 * |S-table origin | | STL |
143 * X **GPS
144 * 00000000001111111111222222222233
145 * 01234567890123456789012345678901
146 *
147 * X Space-Switch event:
148 * G Segment-Invalid Bit: *
149 * P Private-Space Bit: Segment is not private (PoP 3-30)
150 * S Storage-Alteration:
151 * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048)
152 *
153 * A 64 bit pagetable entry of S390 has following format:
154 * | PFRA |0IP0| OS |
155 * 0000000000111111111122222222223333333333444444444455555555556666
156 * 0123456789012345678901234567890123456789012345678901234567890123
157 *
158 * I Page-Invalid Bit: Page is not available for address-translation
159 * P Page-Protection Bit: Store access not possible for page
160 *
161 * A 64 bit segmenttable entry of S390 has following format:
162 * | P-table origin | TT
163 * 0000000000111111111122222222223333333333444444444455555555556666
164 * 0123456789012345678901234567890123456789012345678901234567890123
165 *
166 * I Segment-Invalid Bit: Segment is not available for address-translation
167 * C Common-Segment Bit: Segment is not private (PoP 3-30)
168 * P Page-Protection Bit: Store access not possible for page
169 * TT Type 00
170 *
171 * A 64 bit region table entry of S390 has following format:
172 * | S-table origin | TF TTTL
173 * 0000000000111111111122222222223333333333444444444455555555556666
174 * 0123456789012345678901234567890123456789012345678901234567890123
175 *
176 * I Segment-Invalid Bit: Segment is not available for address-translation
177 * TT Type 01
178 * TF
179 * TL Table lenght
180 *
181 * The 64 bit regiontable origin of S390 has following format:
182 * | region table origon | DTTL
183 * 0000000000111111111122222222223333333333444444444455555555556666
184 * 0123456789012345678901234567890123456789012345678901234567890123
185 *
186 * X Space-Switch event:
187 * G Segment-Invalid Bit:
188 * P Private-Space Bit:
189 * S Storage-Alteration:
190 * R Real space
191 * TL Table-Length:
192 *
193 * A storage key has the following format:
194 * | ACC |F|R|C|0|
195 * 0 3 4 5 6 7
196 * ACC: access key
197 * F : fetch protection bit
198 * R : referenced bit
199 * C : changed bit
200 */
201
202/* Hardware bits in the page table entry */
203#define _PAGE_RO 0x200 /* HW read-only */
204#define _PAGE_INVALID 0x400 /* HW invalid */
205
9282ed92
GS
206/* Mask and six different types of pages. */
207#define _PAGE_TYPE_MASK 0x601
208#define _PAGE_TYPE_EMPTY 0x400
209#define _PAGE_TYPE_NONE 0x401
210#define _PAGE_TYPE_SWAP 0x600
211#define _PAGE_TYPE_FILE 0x601
212#define _PAGE_TYPE_RO 0x200
213#define _PAGE_TYPE_RW 0x000
1da177e4
LT
214
215#ifndef __s390x__
216
217/* Bits in the segment table entry */
218#define _PAGE_TABLE_LEN 0xf /* only full page-tables */
219#define _PAGE_TABLE_COM 0x10 /* common page-table */
220#define _PAGE_TABLE_INV 0x20 /* invalid page-table */
221#define _SEG_PRESENT 0x001 /* Software (overlap with PTL) */
222
223/* Bits int the storage key */
224#define _PAGE_CHANGED 0x02 /* HW changed bit */
225#define _PAGE_REFERENCED 0x04 /* HW referenced bit */
226
227#define _USER_SEG_TABLE_LEN 0x7f /* user-segment-table up to 2 GB */
228#define _KERNEL_SEG_TABLE_LEN 0x7f /* kernel-segment-table up to 2 GB */
229
230/*
231 * User and Kernel pagetables are identical
232 */
233#define _PAGE_TABLE _PAGE_TABLE_LEN
234#define _KERNPG_TABLE _PAGE_TABLE_LEN
235
236/*
237 * The Kernel segment-tables includes the User segment-table
238 */
239
240#define _SEGMENT_TABLE (_USER_SEG_TABLE_LEN|0x80000000|0x100)
241#define _KERNSEG_TABLE _KERNEL_SEG_TABLE_LEN
242
243#define USER_STD_MASK 0x00000080UL
244
245#else /* __s390x__ */
246
247/* Bits in the segment table entry */
248#define _PMD_ENTRY_INV 0x20 /* invalid segment table entry */
249#define _PMD_ENTRY 0x00
250
251/* Bits in the region third table entry */
252#define _PGD_ENTRY_INV 0x20 /* invalid region table entry */
253#define _PGD_ENTRY 0x07
254
255/*
256 * User and kernel page directory
257 */
258#define _REGION_THIRD 0x4
259#define _REGION_THIRD_LEN 0x3
260#define _REGION_TABLE (_REGION_THIRD|_REGION_THIRD_LEN|0x40|0x100)
261#define _KERN_REGION_TABLE (_REGION_THIRD|_REGION_THIRD_LEN)
262
263#define USER_STD_MASK 0x0000000000000080UL
264
265/* Bits in the storage key */
266#define _PAGE_CHANGED 0x02 /* HW changed bit */
267#define _PAGE_REFERENCED 0x04 /* HW referenced bit */
268
269#endif /* __s390x__ */
270
271/*
9282ed92 272 * Page protection definitions.
1da177e4 273 */
9282ed92
GS
274#define PAGE_NONE __pgprot(_PAGE_TYPE_NONE)
275#define PAGE_RO __pgprot(_PAGE_TYPE_RO)
276#define PAGE_RW __pgprot(_PAGE_TYPE_RW)
277
278#define PAGE_KERNEL PAGE_RW
279#define PAGE_COPY PAGE_RO
1da177e4
LT
280
281/*
282 * The S390 can't do page protection for execute, and considers that the
283 * same are read. Also, write permissions imply read permissions. This is
284 * the closest we can get..
285 */
286 /*xwr*/
9282ed92
GS
287#define __P000 PAGE_NONE
288#define __P001 PAGE_RO
289#define __P010 PAGE_RO
290#define __P011 PAGE_RO
291#define __P100 PAGE_RO
292#define __P101 PAGE_RO
293#define __P110 PAGE_RO
294#define __P111 PAGE_RO
295
296#define __S000 PAGE_NONE
297#define __S001 PAGE_RO
298#define __S010 PAGE_RW
299#define __S011 PAGE_RW
300#define __S100 PAGE_RO
301#define __S101 PAGE_RO
302#define __S110 PAGE_RW
303#define __S111 PAGE_RW
1da177e4
LT
304
305/*
306 * Certain architectures need to do special things when PTEs
307 * within a page table are directly modified. Thus, the following
308 * hook is made available.
309 */
4448aaf0 310static inline void set_pte(pte_t *pteptr, pte_t pteval)
1da177e4
LT
311{
312 *pteptr = pteval;
313}
314#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
315
316/*
317 * pgd/pmd/pte query functions
318 */
319#ifndef __s390x__
320
4448aaf0
AB
321static inline int pgd_present(pgd_t pgd) { return 1; }
322static inline int pgd_none(pgd_t pgd) { return 0; }
323static inline int pgd_bad(pgd_t pgd) { return 0; }
1da177e4 324
4448aaf0
AB
325static inline int pmd_present(pmd_t pmd) { return pmd_val(pmd) & _SEG_PRESENT; }
326static inline int pmd_none(pmd_t pmd) { return pmd_val(pmd) & _PAGE_TABLE_INV; }
327static inline int pmd_bad(pmd_t pmd)
1da177e4
LT
328{
329 return (pmd_val(pmd) & (~PAGE_MASK & ~_PAGE_TABLE_INV)) != _PAGE_TABLE;
330}
331
332#else /* __s390x__ */
333
4448aaf0 334static inline int pgd_present(pgd_t pgd)
1da177e4
LT
335{
336 return (pgd_val(pgd) & ~PAGE_MASK) == _PGD_ENTRY;
337}
338
4448aaf0 339static inline int pgd_none(pgd_t pgd)
1da177e4
LT
340{
341 return pgd_val(pgd) & _PGD_ENTRY_INV;
342}
343
4448aaf0 344static inline int pgd_bad(pgd_t pgd)
1da177e4
LT
345{
346 return (pgd_val(pgd) & (~PAGE_MASK & ~_PGD_ENTRY_INV)) != _PGD_ENTRY;
347}
348
4448aaf0 349static inline int pmd_present(pmd_t pmd)
1da177e4
LT
350{
351 return (pmd_val(pmd) & ~PAGE_MASK) == _PMD_ENTRY;
352}
353
4448aaf0 354static inline int pmd_none(pmd_t pmd)
1da177e4
LT
355{
356 return pmd_val(pmd) & _PMD_ENTRY_INV;
357}
358
4448aaf0 359static inline int pmd_bad(pmd_t pmd)
1da177e4
LT
360{
361 return (pmd_val(pmd) & (~PAGE_MASK & ~_PMD_ENTRY_INV)) != _PMD_ENTRY;
362}
363
364#endif /* __s390x__ */
365
4448aaf0 366static inline int pte_none(pte_t pte)
1da177e4 367{
9282ed92 368 return (pte_val(pte) & _PAGE_TYPE_MASK) == _PAGE_TYPE_EMPTY;
1da177e4
LT
369}
370
4448aaf0 371static inline int pte_present(pte_t pte)
1da177e4
LT
372{
373 return !(pte_val(pte) & _PAGE_INVALID) ||
9282ed92 374 (pte_val(pte) & _PAGE_TYPE_MASK) == _PAGE_TYPE_NONE;
1da177e4
LT
375}
376
4448aaf0 377static inline int pte_file(pte_t pte)
1da177e4 378{
9282ed92 379 return (pte_val(pte) & _PAGE_TYPE_MASK) == _PAGE_TYPE_FILE;
1da177e4
LT
380}
381
382#define pte_same(a,b) (pte_val(a) == pte_val(b))
383
384/*
385 * query functions pte_write/pte_dirty/pte_young only work if
386 * pte_present() is true. Undefined behaviour if not..
387 */
4448aaf0 388static inline int pte_write(pte_t pte)
1da177e4
LT
389{
390 return (pte_val(pte) & _PAGE_RO) == 0;
391}
392
4448aaf0 393static inline int pte_dirty(pte_t pte)
1da177e4
LT
394{
395 /* A pte is neither clean nor dirty on s/390. The dirty bit
396 * is in the storage key. See page_test_and_clear_dirty for
397 * details.
398 */
399 return 0;
400}
401
4448aaf0 402static inline int pte_young(pte_t pte)
1da177e4
LT
403{
404 /* A pte is neither young nor old on s/390. The young bit
405 * is in the storage key. See page_test_and_clear_young for
406 * details.
407 */
408 return 0;
409}
410
4448aaf0 411static inline int pte_read(pte_t pte)
1da177e4
LT
412{
413 /* All pages are readable since we don't use the fetch
414 * protection bit in the storage key.
415 */
416 return 1;
417}
418
419/*
420 * pgd/pmd/pte modification functions
421 */
422
423#ifndef __s390x__
424
4448aaf0 425static inline void pgd_clear(pgd_t * pgdp) { }
1da177e4 426
4448aaf0 427static inline void pmd_clear(pmd_t * pmdp)
1da177e4
LT
428{
429 pmd_val(pmdp[0]) = _PAGE_TABLE_INV;
430 pmd_val(pmdp[1]) = _PAGE_TABLE_INV;
431 pmd_val(pmdp[2]) = _PAGE_TABLE_INV;
432 pmd_val(pmdp[3]) = _PAGE_TABLE_INV;
433}
434
435#else /* __s390x__ */
436
4448aaf0 437static inline void pgd_clear(pgd_t * pgdp)
1da177e4
LT
438{
439 pgd_val(*pgdp) = _PGD_ENTRY_INV | _PGD_ENTRY;
440}
441
4448aaf0 442static inline void pmd_clear(pmd_t * pmdp)
1da177e4
LT
443{
444 pmd_val(*pmdp) = _PMD_ENTRY_INV | _PMD_ENTRY;
445 pmd_val1(*pmdp) = _PMD_ENTRY_INV | _PMD_ENTRY;
446}
447
448#endif /* __s390x__ */
449
4448aaf0 450static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
1da177e4 451{
9282ed92 452 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
1da177e4
LT
453}
454
455/*
456 * The following pte modification functions only work if
457 * pte_present() is true. Undefined behaviour if not..
458 */
4448aaf0 459static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
1da177e4
LT
460{
461 pte_val(pte) &= PAGE_MASK;
462 pte_val(pte) |= pgprot_val(newprot);
463 return pte;
464}
465
4448aaf0 466static inline pte_t pte_wrprotect(pte_t pte)
1da177e4 467{
9282ed92 468 /* Do not clobber _PAGE_TYPE_NONE pages! */
1da177e4
LT
469 if (!(pte_val(pte) & _PAGE_INVALID))
470 pte_val(pte) |= _PAGE_RO;
471 return pte;
472}
473
4448aaf0 474static inline pte_t pte_mkwrite(pte_t pte)
1da177e4
LT
475{
476 pte_val(pte) &= ~_PAGE_RO;
477 return pte;
478}
479
4448aaf0 480static inline pte_t pte_mkclean(pte_t pte)
1da177e4
LT
481{
482 /* The only user of pte_mkclean is the fork() code.
483 We must *not* clear the *physical* page dirty bit
484 just because fork() wants to clear the dirty bit in
485 *one* of the page's mappings. So we just do nothing. */
486 return pte;
487}
488
4448aaf0 489static inline pte_t pte_mkdirty(pte_t pte)
1da177e4
LT
490{
491 /* We do not explicitly set the dirty bit because the
492 * sske instruction is slow. It is faster to let the
493 * next instruction set the dirty bit.
494 */
495 return pte;
496}
497
4448aaf0 498static inline pte_t pte_mkold(pte_t pte)
1da177e4
LT
499{
500 /* S/390 doesn't keep its dirty/referenced bit in the pte.
501 * There is no point in clearing the real referenced bit.
502 */
503 return pte;
504}
505
4448aaf0 506static inline pte_t pte_mkyoung(pte_t pte)
1da177e4
LT
507{
508 /* S/390 doesn't keep its dirty/referenced bit in the pte.
509 * There is no point in setting the real referenced bit.
510 */
511 return pte;
512}
513
514static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
515{
516 return 0;
517}
518
519static inline int
520ptep_clear_flush_young(struct vm_area_struct *vma,
521 unsigned long address, pte_t *ptep)
522{
523 /* No need to flush TLB; bits are in storage key */
524 return ptep_test_and_clear_young(vma, address, ptep);
525}
526
527static inline int ptep_test_and_clear_dirty(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
528{
529 return 0;
530}
531
532static inline int
533ptep_clear_flush_dirty(struct vm_area_struct *vma,
534 unsigned long address, pte_t *ptep)
535{
536 /* No need to flush TLB; bits are in storage key */
537 return ptep_test_and_clear_dirty(vma, address, ptep);
538}
539
540static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
541{
542 pte_t pte = *ptep;
543 pte_clear(mm, addr, ptep);
544 return pte;
545}
546
9282ed92 547static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
1da177e4 548{
9282ed92 549 if (!(pte_val(*ptep) & _PAGE_INVALID)) {
1da177e4 550#ifndef __s390x__
1da177e4
LT
551 /* S390 has 1mb segments, we are emulating 4MB segments */
552 pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00);
9282ed92
GS
553#else
554 /* ipte in zarch mode can do the math */
555 pte_t *pto = ptep;
556#endif
94c12cc7
MS
557 asm volatile(
558 " ipte %2,%3"
559 : "=m" (*ptep) : "m" (*ptep),
560 "a" (pto), "a" (address));
1da177e4 561 }
9282ed92
GS
562 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
563}
564
565static inline pte_t
566ptep_clear_flush(struct vm_area_struct *vma,
567 unsigned long address, pte_t *ptep)
568{
569 pte_t pte = *ptep;
570
571 __ptep_ipte(address, ptep);
1da177e4
LT
572 return pte;
573}
574
575static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
576{
577 pte_t old_pte = *ptep;
578 set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
579}
580
581static inline void
582ptep_establish(struct vm_area_struct *vma,
583 unsigned long address, pte_t *ptep,
584 pte_t entry)
585{
586 ptep_clear_flush(vma, address, ptep);
587 set_pte(ptep, entry);
588}
589
590#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
591 ptep_establish(__vma, __address, __ptep, __entry)
592
593/*
594 * Test and clear dirty bit in storage key.
595 * We can't clear the changed bit atomically. This is a potential
596 * race against modification of the referenced bit. This function
597 * should therefore only be called if it is not mapped in any
598 * address space.
599 */
2dcea57a
HC
600static inline int page_test_and_clear_dirty(struct page *page)
601{
0b2b6e1d 602 unsigned long physpage = page_to_phys(page);
2dcea57a
HC
603 int skey = page_get_storage_key(physpage);
604
605 if (skey & _PAGE_CHANGED)
606 page_set_storage_key(physpage, skey & ~_PAGE_CHANGED);
607 return skey & _PAGE_CHANGED;
608}
1da177e4
LT
609
610/*
611 * Test and clear referenced bit in storage key.
612 */
2dcea57a
HC
613static inline int page_test_and_clear_young(struct page *page)
614{
0b2b6e1d 615 unsigned long physpage = page_to_phys(page);
2dcea57a
HC
616 int ccode;
617
0b2b6e1d
HC
618 asm volatile(
619 " rrbe 0,%1\n"
620 " ipm %0\n"
621 " srl %0,28\n"
2dcea57a
HC
622 : "=d" (ccode) : "a" (physpage) : "cc" );
623 return ccode & 2;
624}
1da177e4
LT
625
626/*
627 * Conversion functions: convert a page and protection to a page entry,
628 * and a page entry and page directory to the page they refer to.
629 */
630static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
631{
632 pte_t __pte;
633 pte_val(__pte) = physpage + pgprot_val(pgprot);
634 return __pte;
635}
636
2dcea57a
HC
637static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
638{
0b2b6e1d 639 unsigned long physpage = page_to_phys(page);
1da177e4 640
2dcea57a
HC
641 return mk_pte_phys(physpage, pgprot);
642}
643
644static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
645{
646 unsigned long physpage = __pa((pfn) << PAGE_SHIFT);
647
648 return mk_pte_phys(physpage, pgprot);
649}
1da177e4 650
1da177e4
LT
651#ifdef __s390x__
652
2dcea57a
HC
653static inline pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot)
654{
655 unsigned long physpage = __pa((pfn) << PAGE_SHIFT);
656
657 return __pmd(physpage + pgprot_val(pgprot));
658}
1da177e4
LT
659
660#endif /* __s390x__ */
661
662#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
663#define pte_page(x) pfn_to_page(pte_pfn(x))
664
46a82b2d 665#define pmd_page_vaddr(pmd) (pmd_val(pmd) & PAGE_MASK)
1da177e4 666
0b2b6e1d 667#define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
1da177e4 668
46a82b2d
DM
669#define pgd_page_vaddr(pgd) (pgd_val(pgd) & PAGE_MASK)
670
0b2b6e1d 671#define pgd_page(pgd) pfn_to_page(pgd_val(pgd) >> PAGE_SHIFT)
1da177e4
LT
672
673/* to find an entry in a page-table-directory */
674#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
675#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
676
677/* to find an entry in a kernel page-table-directory */
678#define pgd_offset_k(address) pgd_offset(&init_mm, address)
679
680#ifndef __s390x__
681
682/* Find an entry in the second-level page table.. */
4448aaf0 683static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
1da177e4
LT
684{
685 return (pmd_t *) dir;
686}
687
688#else /* __s390x__ */
689
690/* Find an entry in the second-level page table.. */
691#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
692#define pmd_offset(dir,addr) \
46a82b2d 693 ((pmd_t *) pgd_page_vaddr(*(dir)) + pmd_index(addr))
1da177e4
LT
694
695#endif /* __s390x__ */
696
697/* Find an entry in the third-level page table.. */
698#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
699#define pte_offset_kernel(pmd, address) \
46a82b2d 700 ((pte_t *) pmd_page_vaddr(*(pmd)) + pte_index(address))
1da177e4
LT
701#define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
702#define pte_offset_map_nested(pmd, address) pte_offset_kernel(pmd, address)
703#define pte_unmap(pte) do { } while (0)
704#define pte_unmap_nested(pte) do { } while (0)
705
706/*
707 * 31 bit swap entry format:
708 * A page-table entry has some bits we have to treat in a special way.
709 * Bits 0, 20 and bit 23 have to be zero, otherwise an specification
710 * exception will occur instead of a page translation exception. The
711 * specifiation exception has the bad habit not to store necessary
712 * information in the lowcore.
713 * Bit 21 and bit 22 are the page invalid bit and the page protection
714 * bit. We set both to indicate a swapped page.
715 * Bit 30 and 31 are used to distinguish the different page types. For
716 * a swapped page these bits need to be zero.
717 * This leaves the bits 1-19 and bits 24-29 to store type and offset.
718 * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19
719 * plus 24 for the offset.
720 * 0| offset |0110|o|type |00|
721 * 0 0000000001111111111 2222 2 22222 33
722 * 0 1234567890123456789 0123 4 56789 01
723 *
724 * 64 bit swap entry format:
725 * A page-table entry has some bits we have to treat in a special way.
726 * Bits 52 and bit 55 have to be zero, otherwise an specification
727 * exception will occur instead of a page translation exception. The
728 * specifiation exception has the bad habit not to store necessary
729 * information in the lowcore.
730 * Bit 53 and bit 54 are the page invalid bit and the page protection
731 * bit. We set both to indicate a swapped page.
732 * Bit 62 and 63 are used to distinguish the different page types. For
733 * a swapped page these bits need to be zero.
734 * This leaves the bits 0-51 and bits 56-61 to store type and offset.
735 * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51
736 * plus 56 for the offset.
737 * | offset |0110|o|type |00|
738 * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66
739 * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23
740 */
741#ifndef __s390x__
742#define __SWP_OFFSET_MASK (~0UL >> 12)
743#else
744#define __SWP_OFFSET_MASK (~0UL >> 11)
745#endif
4448aaf0 746static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
1da177e4
LT
747{
748 pte_t pte;
749 offset &= __SWP_OFFSET_MASK;
9282ed92 750 pte_val(pte) = _PAGE_TYPE_SWAP | ((type & 0x1f) << 2) |
1da177e4
LT
751 ((offset & 1UL) << 7) | ((offset & ~1UL) << 11);
752 return pte;
753}
754
755#define __swp_type(entry) (((entry).val >> 2) & 0x1f)
756#define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1))
757#define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
758
759#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
760#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
761
762#ifndef __s390x__
763# define PTE_FILE_MAX_BITS 26
764#else /* __s390x__ */
765# define PTE_FILE_MAX_BITS 59
766#endif /* __s390x__ */
767
768#define pte_to_pgoff(__pte) \
769 ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f))
770
771#define pgoff_to_pte(__off) \
772 ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \
9282ed92 773 | _PAGE_TYPE_FILE })
1da177e4
LT
774
775#endif /* !__ASSEMBLY__ */
776
777#define kern_addr_valid(addr) (1)
778
779/*
780 * No page table caches to initialise
781 */
782#define pgtable_cache_init() do { } while (0)
783
784#define __HAVE_ARCH_PTEP_ESTABLISH
785#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
786#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
787#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
788#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
789#define __HAVE_ARCH_PTEP_CLEAR_DIRTY_FLUSH
790#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
791#define __HAVE_ARCH_PTEP_CLEAR_FLUSH
792#define __HAVE_ARCH_PTEP_SET_WRPROTECT
793#define __HAVE_ARCH_PTE_SAME
794#define __HAVE_ARCH_PAGE_TEST_AND_CLEAR_DIRTY
795#define __HAVE_ARCH_PAGE_TEST_AND_CLEAR_YOUNG
796#include <asm-generic/pgtable.h>
797
798#endif /* _S390_PAGE_H */
799