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powerpc: Introduce VSX thread_struct and CONFIG_VSX
[linux-2.6-block.git] / include / asm-powerpc / cputable.h
CommitLineData
10b35d99
KG		 1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
10b35d99
KG		 4#define PPC_FEATURE_32 0x80000000
5#define PPC_FEATURE_64 0x40000000
6#define PPC_FEATURE_601_INSTR 0x20000000
7#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
8#define PPC_FEATURE_HAS_FPU 0x08000000
9#define PPC_FEATURE_HAS_MMU 0x04000000
10#define PPC_FEATURE_HAS_4xxMAC 0x02000000
11#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
12#define PPC_FEATURE_HAS_SPE 0x00800000
13#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
14#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
98599013 15#define PPC_FEATURE_NO_TB 0x00100000
a7ddc5e8
PM		 16#define PPC_FEATURE_POWER4 0x00080000
17#define PPC_FEATURE_POWER5 0x00040000
18#define PPC_FEATURE_POWER5_PLUS 0x00020000
19#define PPC_FEATURE_CELL 0x00010000
80f15dc7 20#define PPC_FEATURE_BOOKE 0x00008000
aa5cb021
BH		 21#define PPC_FEATURE_SMT 0x00004000
22#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
03054d51 23#define PPC_FEATURE_ARCH_2_05 0x00001000
b3ebd1d8 24#define PPC_FEATURE_PA6T 0x00000800
974a76f5
PM		 25#define PPC_FEATURE_HAS_DFP 0x00000400
26#define PPC_FEATURE_POWER6_EXT 0x00000200
e952e6c4 27#define PPC_FEATURE_ARCH_2_06 0x00000100
10b35d99 28
fab5db97
PM		 29#define PPC_FEATURE_TRUE_LE 0x00000002
30#define PPC_FEATURE_PPC_LE 0x00000001
31
10b35d99 32#ifdef __KERNEL__
d1cdcf22
AB		 33
34#include <asm/asm-compat.h>
c5157e58 35#include <asm/feature-fixups.h>
d1cdcf22 36
10b35d99
KG		 37#ifndef __ASSEMBLY__
38
39/* This structure can grow, it's real size is used by head.S code
40 * via the mkdefs mechanism.
41 */
42struct cpu_spec;
10b35d99 43
10b35d99 44typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
f39b7a55 45typedef void (*cpu_restore_t)(void);
10b35d99 46
32a33994 47enum powerpc_oprofile_type {
7a45fb19
AW		 48 PPC_OPROFILE_INVALID = 0,
49 PPC_OPROFILE_RS64 = 1,
50 PPC_OPROFILE_POWER4 = 2,
51 PPC_OPROFILE_G4 = 3,
39aef685 52 PPC_OPROFILE_FSL_EMB = 4,
18f2190d 53 PPC_OPROFILE_CELL = 5,
25fc530e 54 PPC_OPROFILE_PA6T = 6,
32a33994
AB		 55};
56
1bd2e5ae
OJ		 57enum powerpc_pmc_type {
58 PPC_PMC_DEFAULT = 0,
59 PPC_PMC_IBM = 1,
60 PPC_PMC_PA6T = 2,
61};
62
47c0bd1a
BH		 63struct pt_regs;
64
65extern int machine_check_generic(struct pt_regs *regs);
66extern int machine_check_4xx(struct pt_regs *regs);
67extern int machine_check_440A(struct pt_regs *regs);
68extern int machine_check_e500(struct pt_regs *regs);
69extern int machine_check_e200(struct pt_regs *regs);
70
87a72f9e 71/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
10b35d99
KG		 72struct cpu_spec {
73 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
74 unsigned int pvr_mask;
75 unsigned int pvr_value;
76
77 char *cpu_name;
78 unsigned long cpu_features; /* Kernel features */
79 unsigned int cpu_user_features; /* Userland features */
80
81 /* cache line sizes */
82 unsigned int icache_bsize;
83 unsigned int dcache_bsize;
84
85 /* number of performance monitor counters */
86 unsigned int num_pmcs;
1bd2e5ae 87 enum powerpc_pmc_type pmc_type;
10b35d99
KG		 88
89 /* this is called to initialize various CPU bits like L1 cache,
90 * BHT, SPD, etc... from head.S before branching to identify_machine
91 */
92 cpu_setup_t cpu_setup;
f39b7a55
OJ		 93 /* Used to restore cpu setup on secondary processors and at resume */
94 cpu_restore_t cpu_restore;
10b35d99
KG		 95
96 /* Used by oprofile userspace to select the right counters */
97 char *oprofile_cpu_type;
98
99 /* Processor specific oprofile operations */
32a33994 100 enum powerpc_oprofile_type oprofile_type;
80f15dc7 101
e78dbc80
MN		 102 /* Bit locations inside the mmcra change */
103 unsigned long oprofile_mmcra_sihv;
104 unsigned long oprofile_mmcra_sipr;
105
106 /* Bits to clear during an oprofile exception */
107 unsigned long oprofile_mmcra_clear;
108
80f15dc7
PM		 109 /* Name of processor class, for the ELF AT_PLATFORM entry */
110 char *platform;
47c0bd1a
BH		 111
112 /* Processor specific machine check handling. Return negative
113 * if the error is fatal, 1 if it was fully recovered and 0 to
114 * pass up (not CPU originated) */
115 int (*machine_check)(struct pt_regs *regs);
10b35d99
KG		 116};
117
10b35d99 118extern struct cpu_spec *cur_cpu_spec;
10b35d99 119
42c4aaad
BH		 120extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
121
974a76f5 122extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
0909c8c2
BH		 123extern void do_feature_fixups(unsigned long value, void *fixup_start,
124 void *fixup_end);
9b6b563c 125
10b35d99
KG		 126#endif /* __ASSEMBLY__ */
127
128/* CPU kernel features */
129
130/* Retain the 32b definitions all use bottom half of word */
4508dc21 131#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001)
10b35d99
KG		 132#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
133#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
134#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
135#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
136#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
137#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
aba11fc5 138#define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080)
10b35d99
KG		 139#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
140#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
141#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
142#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
143#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
144#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
145#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
146#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
147#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
148#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
149#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
150#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
3d15910b 151#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
fab5db97
PM		 152#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
153#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
aa42c69c 154#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
4508dc21 155#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
5e14d21e 156#define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
b64f87c1 157#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000)
10b35d99 158
3965f8c5
PM		 159/*
160 * Add the 64-bit processor unique features in the top half of the word;
161 * on 32-bit, make the names available but defined to be 0.
162 */
10b35d99 163#ifdef __powerpc64__
3965f8c5 164#define LONG_ASM_CONST(x) ASM_CONST(x)
10b35d99 165#else
3965f8c5 166#define LONG_ASM_CONST(x) 0
10b35d99
KG		 167#endif
168
3965f8c5
PM		 169#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
170#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
171#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
172#define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
173#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
174#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
175#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
176#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
3965f8c5
PM		 177#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
178#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
179#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
180#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
859deea9 181#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
974a76f5 182#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
4c198557 183#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
1189be65 184#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
f66bce5e 185#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000)
3965f8c5 186
10b35d99
KG		 187#ifndef __ASSEMBLY__
188
0470466d
SR		 189#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
190 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
191 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
10b35d99
KG		 192
193/* We only set the altivec features if the kernel was compiled with altivec
194 * support
195 */
196#ifdef CONFIG_ALTIVEC
197#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
198#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
199#else
200#define CPU_FTR_ALTIVEC_COMP 0
201#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
202#endif
203
5e14d21e
KG		 204/* We only set the spe features if the kernel was compiled with spe
205 * support
206 */
207#ifdef CONFIG_SPE
208#define CPU_FTR_SPE_COMP CPU_FTR_SPE
209#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
210#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
211#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
212#else
213#define CPU_FTR_SPE_COMP 0
214#define PPC_FEATURE_HAS_SPE_COMP 0
215#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
216#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
217#endif
218
11af1192
SW		 219/* We need to mark all pages as being coherent if we're SMP or we have a
220 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
221 * require it for PCI "streaming/prefetch" to work properly.
10b35d99 222 */
1775dbbc 223#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
11af1192 224 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260)
10b35d99
KG		 225#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
226#else
227#define CPU_FTR_COMMON 0
228#endif
229
230/* The powersave features NAP & DOZE seems to confuse BDI when
231 debugging. So if a BDI is used, disable theses
232 */
233#ifndef CONFIG_BDI_SWITCH
234#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
235#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
236#else
237#define CPU_FTR_MAYBE_CAN_DOZE 0
238#define CPU_FTR_MAYBE_CAN_NAP 0
239#endif
240
241#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
242 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
243 !defined(CONFIG_BOOKE))
244
4508dc21
DG		 245#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE | \
246 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
247#define CPU_FTRS_603 (CPU_FTR_COMMON | \
7c92943c 248 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
fab5db97 249 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 250#define CPU_FTRS_604 (CPU_FTR_COMMON | \
aba11fc5 251 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_PPC_LE)
4508dc21 252#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
7c92943c 253 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
fab5db97 254 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 255#define CPU_FTRS_740 (CPU_FTR_COMMON | \
7c92943c 256 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
fab5db97
PM		 257 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
258 CPU_FTR_PPC_LE)
4508dc21 259#define CPU_FTRS_750 (CPU_FTR_COMMON | \
7c92943c 260 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
fab5db97
PM		 261 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
262 CPU_FTR_PPC_LE)
b6f41cc8
JB		 263#define CPU_FTRS_750CL (CPU_FTRS_750 | CPU_FTR_HAS_HIGH_BATS)
264#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
265#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
266#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | \
267 CPU_FTR_HAS_HIGH_BATS)
268#define CPU_FTRS_750GX (CPU_FTRS_750FX)
4508dc21 269#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
7c92943c
SR		 270 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
271 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
fab5db97 272 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 273#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
7c92943c
SR		 274 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
275 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
fab5db97 276 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 277#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
7c92943c
SR		 278 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
279 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
b64f87c1 280 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 281#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
7c92943c
SR		 282 CPU_FTR_USE_TB | \
283 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
284 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
285 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
b64f87c1 286 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 287#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
b64f87c1 288 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c
SR		 289 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
290 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
fab5db97 291 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 292#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
b64f87c1 293 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c
SR		 294 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
295 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
fab5db97 296 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 297#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
b64f87c1 298 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c
SR		 299 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
300 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
301 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
fab5db97 302 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
4508dc21 303#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
7c92943c
SR		 304 CPU_FTR_USE_TB | \
305 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
306 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
307 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
b64f87c1 308 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 309#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
7c92943c
SR		 310 CPU_FTR_USE_TB | \
311 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
312 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
313 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
b64f87c1
BB		 314 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
315 CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 316#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
7c92943c
SR		 317 CPU_FTR_USE_TB | \
318 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
319 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
320 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
b64f87c1 321 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 322#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
7c92943c
SR		 323 CPU_FTR_USE_TB | \
324 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
325 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
326 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
b64f87c1 327 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 328#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
3d372548
JY		 329 CPU_FTR_USE_TB | \
330 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
331 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
332 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
b64f87c1 333 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 334#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
7c92943c 335 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
11af1192 336#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
7c92943c 337 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
4508dc21 338#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
7c92943c
SR		 339 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
340 CPU_FTR_COMMON)
4508dc21 341#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
aa42c69c
KP		 342 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
343 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
4508dc21 344#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | \
7c92943c 345 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
4508dc21
DG		 346#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
347#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
348#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
5e14d21e
KG		 349#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
350 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
351 CPU_FTR_UNIFIED_ID_CACHE)
fc4033b2
KG		 352#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
353 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN)
354#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
355 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | \
3dfa8773 356 CPU_FTR_NODSISRALIGN)
fc4033b2 357#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
aba11fc5
KG		 358 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN | \
359 CPU_FTR_L2CSR)
7c92943c 360#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
0b8e2e13
ME		 361
362/* 64-bit CPUs */
4508dc21 363#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
fab5db97 364 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
4508dc21 365#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \
7c92943c
SR		 366 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
367 CPU_FTR_MMCRA | CPU_FTR_CTRL)
4508dc21 368#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | \
00243000
OJ		 369 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
370 CPU_FTR_MMCRA)
4508dc21 371#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | \
00243000 372 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 373 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
4508dc21 374#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | \
00243000 375 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c
SR		 376 CPU_FTR_MMCRA | CPU_FTR_SMT | \
377 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
e78dbc80 378 CPU_FTR_PURR)
4508dc21 379#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | \
00243000 380 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
03054d51
AB		 381 CPU_FTR_MMCRA | CPU_FTR_SMT | \
382 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
4c198557
AB		 383 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
384 CPU_FTR_DSCR)
e952e6c4
MN		 385#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | \
386 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
387 CPU_FTR_MMCRA | CPU_FTR_SMT | \
388 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
389 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
390 CPU_FTR_DSCR)
4508dc21 391#define CPU_FTRS_CELL (CPU_FTR_USE_TB | \
00243000 392 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 393 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
859deea9 394 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
4508dc21 395#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | \
b3ebd1d8
OJ		 396 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
397 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
f66bce5e 398 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
4508dc21 399#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | \
7c92943c 400 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
10b35d99 401
2406f606 402#ifdef __powerpc64__
7c92943c
SR		 403#define CPU_FTRS_POSSIBLE \
404 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
03054d51 405 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
e952e6c4
MN		 406 CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
407 CPU_FTR_1T_SEGMENT)
2406f606 408#else
7c92943c
SR		 409enum {
410 CPU_FTRS_POSSIBLE =
10b35d99
KG		 411#if CLASSIC_PPC
412 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
413 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
414 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
415 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
416 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
417 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
418 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
aa42c69c
KP		 419 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
420 CPU_FTRS_CLASSIC32 |
10b35d99
KG		 421#else
422 CPU_FTRS_GENERIC_32 |
423#endif
10b35d99
KG		 424#ifdef CONFIG_8xx
425 CPU_FTRS_8XX |
426#endif
427#ifdef CONFIG_40x
428 CPU_FTRS_40X |
429#endif
430#ifdef CONFIG_44x
431 CPU_FTRS_44X |
432#endif
433#ifdef CONFIG_E200
434 CPU_FTRS_E200 |
435#endif
436#ifdef CONFIG_E500
3dfa8773 437 CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
10b35d99 438#endif
10b35d99 439 0,
7c92943c
SR		 440};
441#endif /* __powerpc64__ */
10b35d99 442
2406f606 443#ifdef __powerpc64__
7c92943c
SR		 444#define CPU_FTRS_ALWAYS \
445 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
03054d51 446 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
e952e6c4 447 CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
2406f606 448#else
7c92943c
SR		 449enum {
450 CPU_FTRS_ALWAYS =
10b35d99
KG		 451#if CLASSIC_PPC
452 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
453 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
454 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
455 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
456 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
457 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
458 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
aa42c69c
KP		 459 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
460 CPU_FTRS_CLASSIC32 &
10b35d99
KG		 461#else
462 CPU_FTRS_GENERIC_32 &
463#endif
10b35d99
KG		 464#ifdef CONFIG_8xx
465 CPU_FTRS_8XX &
466#endif
467#ifdef CONFIG_40x
468 CPU_FTRS_40X &
469#endif
470#ifdef CONFIG_44x
471 CPU_FTRS_44X &
472#endif
473#ifdef CONFIG_E200
474 CPU_FTRS_E200 &
475#endif
476#ifdef CONFIG_E500
3dfa8773 477 CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
10b35d99 478#endif
10b35d99
KG		 479 CPU_FTRS_POSSIBLE,
480};
7c92943c 481#endif /* __powerpc64__ */
10b35d99
KG		 482
483static inline int cpu_has_feature(unsigned long feature)
484{
485 return (CPU_FTRS_ALWAYS & feature) ||
486 (CPU_FTRS_POSSIBLE
10b35d99 487 & cur_cpu_spec->cpu_features
10b35d99
KG		 488 & feature);
489}
490
491#endif /* !__ASSEMBLY__ */
492
10b35d99
KG		 493#endif /* __KERNEL__ */
494#endif /* __ASM_POWERPC_CPUTABLE_H */
Linux 6.x block layer and io_uring tree(s)