[linux-2.6-block.git] / include / asm-mips / hazards.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2003, 2004 Ralf Baechle
 */
#ifndef _ASM_HAZARDS_H
#define _ASM_HAZARDS_H

#include <linux/config.h>

#ifdef __ASSEMBLY__

	.macro	_ssnop
	sll	$0, $0, 1
	.endm

	.macro	_ehb
	sll	$0, $0, 3
	.endm

/*
 * RM9000 hazards.  When the JTLB is updated by tlbwi or tlbwr, a subsequent
 * use of the JTLB for instructions should not occur for 4 cpu cycles and use
 * for data translations should not occur for 3 cpu cycles.
 */
#ifdef CONFIG_CPU_RM9000

	.macro	mtc0_tlbw_hazard
	.set	push
	.set	mips32
	_ssnop; _ssnop; _ssnop; _ssnop
	.set	pop
	.endm

	.macro	tlbw_eret_hazard
	.set	push
	.set	mips32
	_ssnop; _ssnop; _ssnop; _ssnop
	.set	pop
	.endm

#else

/*
 * The taken branch will result in a two cycle penalty for the two killed
 * instructions on R4000 / R4400.  Other processors only have a single cycle
 * hazard so this is nice trick to have an optimal code for a range of
 * processors.
 */
	.macro	mtc0_tlbw_hazard
	b	. + 8
	.endm

	.macro	tlbw_eret_hazard
	.endm
#endif

/*
 * mtc0->mfc0 hazard
 * The 24K has a 2 cycle mtc0/mfc0 execution hazard.
 * It is a MIPS32R2 processor so ehb will clear the hazard.
 */

#ifdef CONFIG_CPU_MIPSR2
/*
 * Use a macro for ehb unless explicit support for MIPSR2 is enabled
 */

#define irq_enable_hazard
	_ehb

#define irq_disable_hazard
	_ehb

#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)

/*
 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
 */

#define irq_enable_hazard

#define irq_disable_hazard

#else

/*
 * Classic MIPS needs 1 - 3 nops or ssnops
 */
#define irq_enable_hazard
#define irq_disable_hazard						\
	_ssnop; _ssnop; _ssnop

#endif

#else /* __ASSEMBLY__ */

__asm__(
	"	.macro	_ssnop					\n\t"
	"	sll	$0, $2, 1				\n\t"
	"	.endm						\n\t"
	"							\n\t"
	"	.macro	_ehb					\n\t"
	"	sll	$0, $0, 3				\n\t"
	"	.endm						\n\t");

#ifdef CONFIG_CPU_RM9000
/*
 * RM9000 hazards.  When the JTLB is updated by tlbwi or tlbwr, a subsequent
 * use of the JTLB for instructions should not occur for 4 cpu cycles and use
 * for data translations should not occur for 3 cpu cycles.
 */

#define mtc0_tlbw_hazard()						\
	__asm__ __volatile__(						\
		".set\tmips32\n\t"					\
		"_ssnop; _ssnop; _ssnop; _ssnop\n\t"			\
		".set\tmips0")

#define tlbw_use_hazard()						\
	__asm__ __volatile__(						\
		".set\tmips32\n\t"					\
		"_ssnop; _ssnop; _ssnop; _ssnop\n\t"			\
		".set\tmips0")
#else

/*
 * Overkill warning ...
 */
#define mtc0_tlbw_hazard()						\
	__asm__ __volatile__(						\
		".set noreorder\n\t"					\
		"nop; nop; nop; nop; nop; nop;\n\t"			\
		".set reorder\n\t")

#define tlbw_use_hazard()						\
	__asm__ __volatile__(						\
		".set noreorder\n\t"					\
		"nop; nop; nop; nop; nop; nop;\n\t"			\
		".set reorder\n\t")

#endif

/*
 * mtc0->mfc0 hazard
 * The 24K has a 2 cycle mtc0/mfc0 execution hazard.
 * It is a MIPS32R2 processor so ehb will clear the hazard.
 */

#ifdef CONFIG_CPU_MIPSR2
/*
 * Use a macro for ehb unless explicit support for MIPSR2 is enabled
 */
__asm__(
	"	.macro\tirq_enable_hazard			\n\t"
	"	_ehb						\n\t"
	"	.endm						\n\t"
	"							\n\t"
	"	.macro\tirq_disable_hazard			\n\t"
	"	_ehb						\n\t"
	"	.endm");

#define irq_enable_hazard()						\
	__asm__ __volatile__(						\
	"_ehb\t\t\t\t# irq_enable_hazard")

#define irq_disable_hazard()						\
	__asm__ __volatile__(						\
	"_ehb\t\t\t\t# irq_disable_hazard")

#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)

/*
 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
 */

__asm__(
	"	.macro\tirq_enable_hazard			\n\t"
	"	.endm						\n\t"
	"							\n\t"
	"	.macro\tirq_disable_hazard			\n\t"
	"	.endm");

#define irq_enable_hazard()	do { } while (0)
#define irq_disable_hazard()	do { } while (0)

#else

/*
 * Default for classic MIPS processors.  Assume worst case hazards but don't
 * care about the irq_enable_hazard - sooner or later the hardware will
 * enable it and we don't care when exactly.
 */

__asm__(
	"	#						\n\t"
	"	# There is a hazard but we do not care		\n\t"
	"	#						\n\t"
	"	.macro\tirq_enable_hazard			\n\t"
	"	.endm						\n\t"
	"							\n\t"
	"	.macro\tirq_disable_hazard			\n\t"
	"	_ssnop; _ssnop; _ssnop				\n\t"
	"	.endm");

#define irq_enable_hazard()	do { } while (0)
#define irq_disable_hazard()						\
	__asm__ __volatile__(						\
	"_ssnop; _ssnop; _ssnop;\t\t# irq_disable_hazard")

#endif

#endif /* __ASSEMBLY__ */

#endif /* _ASM_HAZARDS_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2003, 2004 Ralf Baechle
	7	*/
	8	#ifndef _ASM_HAZARDS_H
	9	#define _ASM_HAZARDS_H
	10
	11	#include <linux/config.h>
	12
	13	#ifdef __ASSEMBLY__
	14
	15	.macro _ssnop
	16	sll $0, $0, 1
	17	.endm
	18
	19	.macro _ehb
	20	sll $0, $0, 3
	21	.endm
	22
	23	/*
	24	* RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
	25	* use of the JTLB for instructions should not occur for 4 cpu cycles and use
	26	* for data translations should not occur for 3 cpu cycles.
	27	*/
	28	#ifdef CONFIG_CPU_RM9000
	29
	30	.macro mtc0_tlbw_hazard
	31	.set push
	32	.set mips32
	33	_ssnop; _ssnop; _ssnop; _ssnop
	34	.set pop
	35	.endm
	36
	37	.macro tlbw_eret_hazard
	38	.set push
	39	.set mips32
	40	_ssnop; _ssnop; _ssnop; _ssnop
	41	.set pop
	42	.endm
	43
	44	#else
	45
	46	/*
	47	* The taken branch will result in a two cycle penalty for the two killed
	48	* instructions on R4000 / R4400. Other processors only have a single cycle
	49	* hazard so this is nice trick to have an optimal code for a range of
	50	* processors.
	51	*/
	52	.macro mtc0_tlbw_hazard
	53	b . + 8
	54	.endm
	55
	56	.macro tlbw_eret_hazard
	57	.endm
	58	#endif
	59
	60	/*
	61	* mtc0->mfc0 hazard
	62	* The 24K has a 2 cycle mtc0/mfc0 execution hazard.
	63	* It is a MIPS32R2 processor so ehb will clear the hazard.
	64	*/
65
66	#ifdef CONFIG_CPU_MIPSR2
67	/*
68	* Use a macro for ehb unless explicit support for MIPSR2 is enabled
69	*/
70
71	#define irq_enable_hazard
72	_ehb
73
74	#define irq_disable_hazard
75	_ehb
76
77	#elif defined(CONFIG_CPU_R10000) \|\| defined(CONFIG_CPU_RM9000)
78
79	/*
80	* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
81	*/
82
83	#define irq_enable_hazard
84
85	#define irq_disable_hazard
86
87	#else
88
89	/*
90	* Classic MIPS needs 1 - 3 nops or ssnops
91	*/
92	#define irq_enable_hazard
93	#define irq_disable_hazard \
94	_ssnop; _ssnop; _ssnop
95
96	#endif
97
98	#else /* __ASSEMBLY__ */
99
100	__asm__(
101	" .macro _ssnop \n\t"
102	" sll $0, $2, 1 \n\t"
103	" .endm \n\t"
104	" \n\t"
105	" .macro _ehb \n\t"
106	" sll $0, $0, 3 \n\t"
107	" .endm \n\t");
108
109	#ifdef CONFIG_CPU_RM9000
110	/*
111	* RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
112	* use of the JTLB for instructions should not occur for 4 cpu cycles and use
113	* for data translations should not occur for 3 cpu cycles.
114	*/
115
116	#define mtc0_tlbw_hazard() \
117	__asm__ __volatile__( \
118	".set\tmips32\n\t" \
119	"_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
120	".set\tmips0")
121
122	#define tlbw_use_hazard() \
123	__asm__ __volatile__( \
124	".set\tmips32\n\t" \
125	"_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
126	".set\tmips0")
127	#else
128
129	/*
130	* Overkill warning ...
131	*/
132	#define mtc0_tlbw_hazard() \
133	__asm__ __volatile__( \
134	".set noreorder\n\t" \
135	"nop; nop; nop; nop; nop; nop;\n\t" \
136	".set reorder\n\t")
137
138	#define tlbw_use_hazard() \
139	__asm__ __volatile__( \
140	".set noreorder\n\t" \
141	"nop; nop; nop; nop; nop; nop;\n\t" \
142	".set reorder\n\t")
143
144	#endif
145
146	/*
147	* mtc0->mfc0 hazard
148	* The 24K has a 2 cycle mtc0/mfc0 execution hazard.
149	* It is a MIPS32R2 processor so ehb will clear the hazard.
150	*/
151
152	#ifdef CONFIG_CPU_MIPSR2
153	/*
154	* Use a macro for ehb unless explicit support for MIPSR2 is enabled
155	*/
156	__asm__(
157	" .macro\tirq_enable_hazard \n\t"
158	" _ehb \n\t"
159	" .endm \n\t"
160	" \n\t"
161	" .macro\tirq_disable_hazard \n\t"
162	" _ehb \n\t"
163	" .endm");
164
165	#define irq_enable_hazard() \
166	__asm__ __volatile__( \
167	"_ehb\t\t\t\t# irq_enable_hazard")
168
169	#define irq_disable_hazard() \
170	__asm__ __volatile__( \
171	"_ehb\t\t\t\t# irq_disable_hazard")
172
173	#elif defined(CONFIG_CPU_R10000) \|\| defined(CONFIG_CPU_RM9000)
174
175	/*
176	* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
177	*/
178
179	__asm__(
180	" .macro\tirq_enable_hazard \n\t"
181	" .endm \n\t"
182	" \n\t"
183	" .macro\tirq_disable_hazard \n\t"
184	" .endm");
185
186	#define irq_enable_hazard() do { } while (0)
187	#define irq_disable_hazard() do { } while (0)
188
189	#else
190
191	/*
192	* Default for classic MIPS processors. Assume worst case hazards but don't
193	* care about the irq_enable_hazard - sooner or later the hardware will
194	* enable it and we don't care when exactly.
195	*/
196
197	__asm__(
198	" # \n\t"
199	" # There is a hazard but we do not care \n\t"
200	" # \n\t"
201	" .macro\tirq_enable_hazard \n\t"
202	" .endm \n\t"
203	" \n\t"
204	" .macro\tirq_disable_hazard \n\t"
205	" _ssnop; _ssnop; _ssnop \n\t"
206	" .endm");
207
208	#define irq_enable_hazard() do { } while (0)
209	#define irq_disable_hazard() \
210	__asm__ __volatile__( \
211	"_ssnop; _ssnop; _ssnop;\t\t# irq_disable_hazard")
212
213	#endif
214
215	#endif /* __ASSEMBLY__ */
216
217	#endif /* _ASM_HAZARDS_H */