Commit | Line | Data |
---|---|---|
58d08319 JN |
1 | #ifndef __pio_defs_h |
2 | #define __pio_defs_h | |
3 | ||
4 | /* | |
5 | * This file is autogenerated from | |
6 | * file: pio.r | |
7 | * | |
8 | * by ../../../tools/rdesc/bin/rdes2c -outfile pio_defs.h pio.r | |
9 | * Any changes here will be lost. | |
10 | * | |
11 | * -*- buffer-read-only: t -*- | |
12 | */ | |
13 | /* Main access macros */ | |
14 | #ifndef REG_RD | |
15 | #define REG_RD( scope, inst, reg ) \ | |
16 | REG_READ( reg_##scope##_##reg, \ | |
17 | (inst) + REG_RD_ADDR_##scope##_##reg ) | |
18 | #endif | |
19 | ||
20 | #ifndef REG_WR | |
21 | #define REG_WR( scope, inst, reg, val ) \ | |
22 | REG_WRITE( reg_##scope##_##reg, \ | |
23 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
24 | #endif | |
25 | ||
26 | #ifndef REG_RD_VECT | |
27 | #define REG_RD_VECT( scope, inst, reg, index ) \ | |
28 | REG_READ( reg_##scope##_##reg, \ | |
29 | (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
30 | (index) * STRIDE_##scope##_##reg ) | |
31 | #endif | |
32 | ||
33 | #ifndef REG_WR_VECT | |
34 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ | |
35 | REG_WRITE( reg_##scope##_##reg, \ | |
36 | (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
37 | (index) * STRIDE_##scope##_##reg, (val) ) | |
38 | #endif | |
39 | ||
40 | #ifndef REG_RD_INT | |
41 | #define REG_RD_INT( scope, inst, reg ) \ | |
42 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) | |
43 | #endif | |
44 | ||
45 | #ifndef REG_WR_INT | |
46 | #define REG_WR_INT( scope, inst, reg, val ) \ | |
47 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) | |
48 | #endif | |
49 | ||
50 | #ifndef REG_RD_INT_VECT | |
51 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ | |
52 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
53 | (index) * STRIDE_##scope##_##reg ) | |
54 | #endif | |
55 | ||
56 | #ifndef REG_WR_INT_VECT | |
57 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ | |
58 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ | |
59 | (index) * STRIDE_##scope##_##reg, (val) ) | |
60 | #endif | |
61 | ||
62 | #ifndef REG_TYPE_CONV | |
63 | #define REG_TYPE_CONV( type, orgtype, val ) \ | |
64 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) | |
65 | #endif | |
66 | ||
67 | #ifndef reg_page_size | |
68 | #define reg_page_size 8192 | |
69 | #endif | |
70 | ||
71 | #ifndef REG_ADDR | |
72 | #define REG_ADDR( scope, inst, reg ) \ | |
73 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) | |
74 | #endif | |
75 | ||
76 | #ifndef REG_ADDR_VECT | |
77 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
78 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ | |
79 | (index) * STRIDE_##scope##_##reg ) | |
80 | #endif | |
81 | ||
82 | /* C-code for register scope pio */ | |
83 | ||
84 | /* Register rw_data, scope pio, type rw */ | |
85 | typedef unsigned int reg_pio_rw_data; | |
86 | #define REG_RD_ADDR_pio_rw_data 64 | |
87 | #define REG_WR_ADDR_pio_rw_data 64 | |
88 | ||
89 | /* Register rw_io_access0, scope pio, type rw */ | |
90 | typedef struct { | |
91 | unsigned int data : 8; | |
92 | unsigned int dummy1 : 24; | |
93 | } reg_pio_rw_io_access0; | |
94 | #define REG_RD_ADDR_pio_rw_io_access0 0 | |
95 | #define REG_WR_ADDR_pio_rw_io_access0 0 | |
96 | ||
97 | /* Register rw_io_access1, scope pio, type rw */ | |
98 | typedef struct { | |
99 | unsigned int data : 8; | |
100 | unsigned int dummy1 : 24; | |
101 | } reg_pio_rw_io_access1; | |
102 | #define REG_RD_ADDR_pio_rw_io_access1 4 | |
103 | #define REG_WR_ADDR_pio_rw_io_access1 4 | |
104 | ||
105 | /* Register rw_io_access2, scope pio, type rw */ | |
106 | typedef struct { | |
107 | unsigned int data : 8; | |
108 | unsigned int dummy1 : 24; | |
109 | } reg_pio_rw_io_access2; | |
110 | #define REG_RD_ADDR_pio_rw_io_access2 8 | |
111 | #define REG_WR_ADDR_pio_rw_io_access2 8 | |
112 | ||
113 | /* Register rw_io_access3, scope pio, type rw */ | |
114 | typedef struct { | |
115 | unsigned int data : 8; | |
116 | unsigned int dummy1 : 24; | |
117 | } reg_pio_rw_io_access3; | |
118 | #define REG_RD_ADDR_pio_rw_io_access3 12 | |
119 | #define REG_WR_ADDR_pio_rw_io_access3 12 | |
120 | ||
121 | /* Register rw_io_access4, scope pio, type rw */ | |
122 | typedef struct { | |
123 | unsigned int data : 8; | |
124 | unsigned int dummy1 : 24; | |
125 | } reg_pio_rw_io_access4; | |
126 | #define REG_RD_ADDR_pio_rw_io_access4 16 | |
127 | #define REG_WR_ADDR_pio_rw_io_access4 16 | |
128 | ||
129 | /* Register rw_io_access5, scope pio, type rw */ | |
130 | typedef struct { | |
131 | unsigned int data : 8; | |
132 | unsigned int dummy1 : 24; | |
133 | } reg_pio_rw_io_access5; | |
134 | #define REG_RD_ADDR_pio_rw_io_access5 20 | |
135 | #define REG_WR_ADDR_pio_rw_io_access5 20 | |
136 | ||
137 | /* Register rw_io_access6, scope pio, type rw */ | |
138 | typedef struct { | |
139 | unsigned int data : 8; | |
140 | unsigned int dummy1 : 24; | |
141 | } reg_pio_rw_io_access6; | |
142 | #define REG_RD_ADDR_pio_rw_io_access6 24 | |
143 | #define REG_WR_ADDR_pio_rw_io_access6 24 | |
144 | ||
145 | /* Register rw_io_access7, scope pio, type rw */ | |
146 | typedef struct { | |
147 | unsigned int data : 8; | |
148 | unsigned int dummy1 : 24; | |
149 | } reg_pio_rw_io_access7; | |
150 | #define REG_RD_ADDR_pio_rw_io_access7 28 | |
151 | #define REG_WR_ADDR_pio_rw_io_access7 28 | |
152 | ||
153 | /* Register rw_io_access8, scope pio, type rw */ | |
154 | typedef struct { | |
155 | unsigned int data : 8; | |
156 | unsigned int dummy1 : 24; | |
157 | } reg_pio_rw_io_access8; | |
158 | #define REG_RD_ADDR_pio_rw_io_access8 32 | |
159 | #define REG_WR_ADDR_pio_rw_io_access8 32 | |
160 | ||
161 | /* Register rw_io_access9, scope pio, type rw */ | |
162 | typedef struct { | |
163 | unsigned int data : 8; | |
164 | unsigned int dummy1 : 24; | |
165 | } reg_pio_rw_io_access9; | |
166 | #define REG_RD_ADDR_pio_rw_io_access9 36 | |
167 | #define REG_WR_ADDR_pio_rw_io_access9 36 | |
168 | ||
169 | /* Register rw_io_access10, scope pio, type rw */ | |
170 | typedef struct { | |
171 | unsigned int data : 8; | |
172 | unsigned int dummy1 : 24; | |
173 | } reg_pio_rw_io_access10; | |
174 | #define REG_RD_ADDR_pio_rw_io_access10 40 | |
175 | #define REG_WR_ADDR_pio_rw_io_access10 40 | |
176 | ||
177 | /* Register rw_io_access11, scope pio, type rw */ | |
178 | typedef struct { | |
179 | unsigned int data : 8; | |
180 | unsigned int dummy1 : 24; | |
181 | } reg_pio_rw_io_access11; | |
182 | #define REG_RD_ADDR_pio_rw_io_access11 44 | |
183 | #define REG_WR_ADDR_pio_rw_io_access11 44 | |
184 | ||
185 | /* Register rw_io_access12, scope pio, type rw */ | |
186 | typedef struct { | |
187 | unsigned int data : 8; | |
188 | unsigned int dummy1 : 24; | |
189 | } reg_pio_rw_io_access12; | |
190 | #define REG_RD_ADDR_pio_rw_io_access12 48 | |
191 | #define REG_WR_ADDR_pio_rw_io_access12 48 | |
192 | ||
193 | /* Register rw_io_access13, scope pio, type rw */ | |
194 | typedef struct { | |
195 | unsigned int data : 8; | |
196 | unsigned int dummy1 : 24; | |
197 | } reg_pio_rw_io_access13; | |
198 | #define REG_RD_ADDR_pio_rw_io_access13 52 | |
199 | #define REG_WR_ADDR_pio_rw_io_access13 52 | |
200 | ||
201 | /* Register rw_io_access14, scope pio, type rw */ | |
202 | typedef struct { | |
203 | unsigned int data : 8; | |
204 | unsigned int dummy1 : 24; | |
205 | } reg_pio_rw_io_access14; | |
206 | #define REG_RD_ADDR_pio_rw_io_access14 56 | |
207 | #define REG_WR_ADDR_pio_rw_io_access14 56 | |
208 | ||
209 | /* Register rw_io_access15, scope pio, type rw */ | |
210 | typedef struct { | |
211 | unsigned int data : 8; | |
212 | unsigned int dummy1 : 24; | |
213 | } reg_pio_rw_io_access15; | |
214 | #define REG_RD_ADDR_pio_rw_io_access15 60 | |
215 | #define REG_WR_ADDR_pio_rw_io_access15 60 | |
216 | ||
217 | /* Register rw_ce0_cfg, scope pio, type rw */ | |
218 | typedef struct { | |
219 | unsigned int lw : 6; | |
220 | unsigned int ew : 3; | |
221 | unsigned int zw : 3; | |
222 | unsigned int aw : 2; | |
223 | unsigned int mode : 2; | |
224 | unsigned int dummy1 : 16; | |
225 | } reg_pio_rw_ce0_cfg; | |
226 | #define REG_RD_ADDR_pio_rw_ce0_cfg 68 | |
227 | #define REG_WR_ADDR_pio_rw_ce0_cfg 68 | |
228 | ||
229 | /* Register rw_ce1_cfg, scope pio, type rw */ | |
230 | typedef struct { | |
231 | unsigned int lw : 6; | |
232 | unsigned int ew : 3; | |
233 | unsigned int zw : 3; | |
234 | unsigned int aw : 2; | |
235 | unsigned int mode : 2; | |
236 | unsigned int dummy1 : 16; | |
237 | } reg_pio_rw_ce1_cfg; | |
238 | #define REG_RD_ADDR_pio_rw_ce1_cfg 72 | |
239 | #define REG_WR_ADDR_pio_rw_ce1_cfg 72 | |
240 | ||
241 | /* Register rw_ce2_cfg, scope pio, type rw */ | |
242 | typedef struct { | |
243 | unsigned int lw : 6; | |
244 | unsigned int ew : 3; | |
245 | unsigned int zw : 3; | |
246 | unsigned int aw : 2; | |
247 | unsigned int mode : 2; | |
248 | unsigned int dummy1 : 16; | |
249 | } reg_pio_rw_ce2_cfg; | |
250 | #define REG_RD_ADDR_pio_rw_ce2_cfg 76 | |
251 | #define REG_WR_ADDR_pio_rw_ce2_cfg 76 | |
252 | ||
253 | /* Register rw_dout, scope pio, type rw */ | |
254 | typedef struct { | |
255 | unsigned int data : 8; | |
256 | unsigned int rd_n : 1; | |
257 | unsigned int wr_n : 1; | |
258 | unsigned int a0 : 1; | |
259 | unsigned int a1 : 1; | |
260 | unsigned int ce0_n : 1; | |
261 | unsigned int ce1_n : 1; | |
262 | unsigned int ce2_n : 1; | |
263 | unsigned int rdy : 1; | |
264 | unsigned int dummy1 : 16; | |
265 | } reg_pio_rw_dout; | |
266 | #define REG_RD_ADDR_pio_rw_dout 80 | |
267 | #define REG_WR_ADDR_pio_rw_dout 80 | |
268 | ||
269 | /* Register rw_oe, scope pio, type rw */ | |
270 | typedef struct { | |
271 | unsigned int data : 8; | |
272 | unsigned int rd_n : 1; | |
273 | unsigned int wr_n : 1; | |
274 | unsigned int a0 : 1; | |
275 | unsigned int a1 : 1; | |
276 | unsigned int ce0_n : 1; | |
277 | unsigned int ce1_n : 1; | |
278 | unsigned int ce2_n : 1; | |
279 | unsigned int rdy : 1; | |
280 | unsigned int dummy1 : 16; | |
281 | } reg_pio_rw_oe; | |
282 | #define REG_RD_ADDR_pio_rw_oe 84 | |
283 | #define REG_WR_ADDR_pio_rw_oe 84 | |
284 | ||
285 | /* Register rw_man_ctrl, scope pio, type rw */ | |
286 | typedef struct { | |
287 | unsigned int data : 8; | |
288 | unsigned int rd_n : 1; | |
289 | unsigned int wr_n : 1; | |
290 | unsigned int a0 : 1; | |
291 | unsigned int a1 : 1; | |
292 | unsigned int ce0_n : 1; | |
293 | unsigned int ce1_n : 1; | |
294 | unsigned int ce2_n : 1; | |
295 | unsigned int rdy : 1; | |
296 | unsigned int dummy1 : 16; | |
297 | } reg_pio_rw_man_ctrl; | |
298 | #define REG_RD_ADDR_pio_rw_man_ctrl 88 | |
299 | #define REG_WR_ADDR_pio_rw_man_ctrl 88 | |
300 | ||
301 | /* Register r_din, scope pio, type r */ | |
302 | typedef struct { | |
303 | unsigned int data : 8; | |
304 | unsigned int rd_n : 1; | |
305 | unsigned int wr_n : 1; | |
306 | unsigned int a0 : 1; | |
307 | unsigned int a1 : 1; | |
308 | unsigned int ce0_n : 1; | |
309 | unsigned int ce1_n : 1; | |
310 | unsigned int ce2_n : 1; | |
311 | unsigned int rdy : 1; | |
312 | unsigned int dummy1 : 16; | |
313 | } reg_pio_r_din; | |
314 | #define REG_RD_ADDR_pio_r_din 92 | |
315 | ||
316 | /* Register r_stat, scope pio, type r */ | |
317 | typedef struct { | |
318 | unsigned int busy : 1; | |
319 | unsigned int dummy1 : 31; | |
320 | } reg_pio_r_stat; | |
321 | #define REG_RD_ADDR_pio_r_stat 96 | |
322 | ||
323 | /* Register rw_intr_mask, scope pio, type rw */ | |
324 | typedef struct { | |
325 | unsigned int rdy : 1; | |
326 | unsigned int dummy1 : 31; | |
327 | } reg_pio_rw_intr_mask; | |
328 | #define REG_RD_ADDR_pio_rw_intr_mask 100 | |
329 | #define REG_WR_ADDR_pio_rw_intr_mask 100 | |
330 | ||
331 | /* Register rw_ack_intr, scope pio, type rw */ | |
332 | typedef struct { | |
333 | unsigned int rdy : 1; | |
334 | unsigned int dummy1 : 31; | |
335 | } reg_pio_rw_ack_intr; | |
336 | #define REG_RD_ADDR_pio_rw_ack_intr 104 | |
337 | #define REG_WR_ADDR_pio_rw_ack_intr 104 | |
338 | ||
339 | /* Register r_intr, scope pio, type r */ | |
340 | typedef struct { | |
341 | unsigned int rdy : 1; | |
342 | unsigned int dummy1 : 31; | |
343 | } reg_pio_r_intr; | |
344 | #define REG_RD_ADDR_pio_r_intr 108 | |
345 | ||
346 | /* Register r_masked_intr, scope pio, type r */ | |
347 | typedef struct { | |
348 | unsigned int rdy : 1; | |
349 | unsigned int dummy1 : 31; | |
350 | } reg_pio_r_masked_intr; | |
351 | #define REG_RD_ADDR_pio_r_masked_intr 112 | |
352 | ||
353 | ||
354 | /* Constants */ | |
355 | enum { | |
356 | regk_pio_a2 = 0x00000003, | |
357 | regk_pio_no = 0x00000000, | |
358 | regk_pio_normal = 0x00000000, | |
359 | regk_pio_rd = 0x00000001, | |
360 | regk_pio_rw_ce0_cfg_default = 0x00000000, | |
361 | regk_pio_rw_ce1_cfg_default = 0x00000000, | |
362 | regk_pio_rw_ce2_cfg_default = 0x00000000, | |
363 | regk_pio_rw_intr_mask_default = 0x00000000, | |
364 | regk_pio_rw_man_ctrl_default = 0x00000000, | |
365 | regk_pio_rw_oe_default = 0x00000000, | |
366 | regk_pio_wr = 0x00000002, | |
367 | regk_pio_wr_ce2 = 0x00000003, | |
368 | regk_pio_yes = 0x00000001, | |
369 | regk_pio_yes_all = 0x000000ff | |
370 | }; | |
371 | #endif /* __pio_defs_h */ |