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58d08319 JN |
1 | #ifndef __gio_defs_asm_h |
2 | #define __gio_defs_asm_h | |
3 | ||
4 | /* | |
5 | * This file is autogenerated from | |
6 | * file: gio.r | |
7 | * | |
8 | * by ../../../tools/rdesc/bin/rdes2c -asm -outfile gio_defs_asm.h gio.r | |
9 | * Any changes here will be lost. | |
10 | * | |
11 | * -*- buffer-read-only: t -*- | |
12 | */ | |
13 | ||
14 | #ifndef REG_FIELD | |
15 | #define REG_FIELD( scope, reg, field, value ) \ | |
16 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | |
17 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | |
18 | #endif | |
19 | ||
20 | #ifndef REG_STATE | |
21 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | |
22 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | |
23 | #define REG_STATE_X_( k, shift ) (k << shift) | |
24 | #endif | |
25 | ||
26 | #ifndef REG_MASK | |
27 | #define REG_MASK( scope, reg, field ) \ | |
28 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | |
29 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | |
30 | #endif | |
31 | ||
32 | #ifndef REG_LSB | |
33 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | |
34 | #endif | |
35 | ||
36 | #ifndef REG_BIT | |
37 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | |
38 | #endif | |
39 | ||
40 | #ifndef REG_ADDR | |
41 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | |
42 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | |
43 | #endif | |
44 | ||
45 | #ifndef REG_ADDR_VECT | |
46 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
47 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | |
48 | STRIDE_##scope##_##reg ) | |
49 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | |
50 | ((inst) + offs + (index) * stride) | |
51 | #endif | |
52 | ||
53 | /* Register r_pa_din, scope gio, type r */ | |
54 | #define reg_gio_r_pa_din___data___lsb 0 | |
55 | #define reg_gio_r_pa_din___data___width 32 | |
56 | #define reg_gio_r_pa_din_offset 0 | |
57 | ||
58 | /* Register rw_pa_dout, scope gio, type rw */ | |
59 | #define reg_gio_rw_pa_dout___data___lsb 0 | |
60 | #define reg_gio_rw_pa_dout___data___width 32 | |
61 | #define reg_gio_rw_pa_dout_offset 4 | |
62 | ||
63 | /* Register rw_pa_oe, scope gio, type rw */ | |
64 | #define reg_gio_rw_pa_oe___oe___lsb 0 | |
65 | #define reg_gio_rw_pa_oe___oe___width 32 | |
66 | #define reg_gio_rw_pa_oe_offset 8 | |
67 | ||
68 | /* Register rw_pa_byte0_dout, scope gio, type rw */ | |
69 | #define reg_gio_rw_pa_byte0_dout___data___lsb 0 | |
70 | #define reg_gio_rw_pa_byte0_dout___data___width 8 | |
71 | #define reg_gio_rw_pa_byte0_dout_offset 12 | |
72 | ||
73 | /* Register rw_pa_byte0_oe, scope gio, type rw */ | |
74 | #define reg_gio_rw_pa_byte0_oe___oe___lsb 0 | |
75 | #define reg_gio_rw_pa_byte0_oe___oe___width 8 | |
76 | #define reg_gio_rw_pa_byte0_oe_offset 16 | |
77 | ||
78 | /* Register rw_pa_byte1_dout, scope gio, type rw */ | |
79 | #define reg_gio_rw_pa_byte1_dout___data___lsb 0 | |
80 | #define reg_gio_rw_pa_byte1_dout___data___width 8 | |
81 | #define reg_gio_rw_pa_byte1_dout_offset 20 | |
82 | ||
83 | /* Register rw_pa_byte1_oe, scope gio, type rw */ | |
84 | #define reg_gio_rw_pa_byte1_oe___oe___lsb 0 | |
85 | #define reg_gio_rw_pa_byte1_oe___oe___width 8 | |
86 | #define reg_gio_rw_pa_byte1_oe_offset 24 | |
87 | ||
88 | /* Register rw_pa_byte2_dout, scope gio, type rw */ | |
89 | #define reg_gio_rw_pa_byte2_dout___data___lsb 0 | |
90 | #define reg_gio_rw_pa_byte2_dout___data___width 8 | |
91 | #define reg_gio_rw_pa_byte2_dout_offset 28 | |
92 | ||
93 | /* Register rw_pa_byte2_oe, scope gio, type rw */ | |
94 | #define reg_gio_rw_pa_byte2_oe___oe___lsb 0 | |
95 | #define reg_gio_rw_pa_byte2_oe___oe___width 8 | |
96 | #define reg_gio_rw_pa_byte2_oe_offset 32 | |
97 | ||
98 | /* Register rw_pa_byte3_dout, scope gio, type rw */ | |
99 | #define reg_gio_rw_pa_byte3_dout___data___lsb 0 | |
100 | #define reg_gio_rw_pa_byte3_dout___data___width 8 | |
101 | #define reg_gio_rw_pa_byte3_dout_offset 36 | |
102 | ||
103 | /* Register rw_pa_byte3_oe, scope gio, type rw */ | |
104 | #define reg_gio_rw_pa_byte3_oe___oe___lsb 0 | |
105 | #define reg_gio_rw_pa_byte3_oe___oe___width 8 | |
106 | #define reg_gio_rw_pa_byte3_oe_offset 40 | |
107 | ||
108 | /* Register r_pb_din, scope gio, type r */ | |
109 | #define reg_gio_r_pb_din___data___lsb 0 | |
110 | #define reg_gio_r_pb_din___data___width 32 | |
111 | #define reg_gio_r_pb_din_offset 44 | |
112 | ||
113 | /* Register rw_pb_dout, scope gio, type rw */ | |
114 | #define reg_gio_rw_pb_dout___data___lsb 0 | |
115 | #define reg_gio_rw_pb_dout___data___width 32 | |
116 | #define reg_gio_rw_pb_dout_offset 48 | |
117 | ||
118 | /* Register rw_pb_oe, scope gio, type rw */ | |
119 | #define reg_gio_rw_pb_oe___oe___lsb 0 | |
120 | #define reg_gio_rw_pb_oe___oe___width 32 | |
121 | #define reg_gio_rw_pb_oe_offset 52 | |
122 | ||
123 | /* Register rw_pb_byte0_dout, scope gio, type rw */ | |
124 | #define reg_gio_rw_pb_byte0_dout___data___lsb 0 | |
125 | #define reg_gio_rw_pb_byte0_dout___data___width 8 | |
126 | #define reg_gio_rw_pb_byte0_dout_offset 56 | |
127 | ||
128 | /* Register rw_pb_byte0_oe, scope gio, type rw */ | |
129 | #define reg_gio_rw_pb_byte0_oe___oe___lsb 0 | |
130 | #define reg_gio_rw_pb_byte0_oe___oe___width 8 | |
131 | #define reg_gio_rw_pb_byte0_oe_offset 60 | |
132 | ||
133 | /* Register rw_pb_byte1_dout, scope gio, type rw */ | |
134 | #define reg_gio_rw_pb_byte1_dout___data___lsb 0 | |
135 | #define reg_gio_rw_pb_byte1_dout___data___width 8 | |
136 | #define reg_gio_rw_pb_byte1_dout_offset 64 | |
137 | ||
138 | /* Register rw_pb_byte1_oe, scope gio, type rw */ | |
139 | #define reg_gio_rw_pb_byte1_oe___oe___lsb 0 | |
140 | #define reg_gio_rw_pb_byte1_oe___oe___width 8 | |
141 | #define reg_gio_rw_pb_byte1_oe_offset 68 | |
142 | ||
143 | /* Register rw_pb_byte2_dout, scope gio, type rw */ | |
144 | #define reg_gio_rw_pb_byte2_dout___data___lsb 0 | |
145 | #define reg_gio_rw_pb_byte2_dout___data___width 8 | |
146 | #define reg_gio_rw_pb_byte2_dout_offset 72 | |
147 | ||
148 | /* Register rw_pb_byte2_oe, scope gio, type rw */ | |
149 | #define reg_gio_rw_pb_byte2_oe___oe___lsb 0 | |
150 | #define reg_gio_rw_pb_byte2_oe___oe___width 8 | |
151 | #define reg_gio_rw_pb_byte2_oe_offset 76 | |
152 | ||
153 | /* Register rw_pb_byte3_dout, scope gio, type rw */ | |
154 | #define reg_gio_rw_pb_byte3_dout___data___lsb 0 | |
155 | #define reg_gio_rw_pb_byte3_dout___data___width 8 | |
156 | #define reg_gio_rw_pb_byte3_dout_offset 80 | |
157 | ||
158 | /* Register rw_pb_byte3_oe, scope gio, type rw */ | |
159 | #define reg_gio_rw_pb_byte3_oe___oe___lsb 0 | |
160 | #define reg_gio_rw_pb_byte3_oe___oe___width 8 | |
161 | #define reg_gio_rw_pb_byte3_oe_offset 84 | |
162 | ||
163 | /* Register r_pc_din, scope gio, type r */ | |
164 | #define reg_gio_r_pc_din___data___lsb 0 | |
165 | #define reg_gio_r_pc_din___data___width 16 | |
166 | #define reg_gio_r_pc_din_offset 88 | |
167 | ||
168 | /* Register rw_pc_dout, scope gio, type rw */ | |
169 | #define reg_gio_rw_pc_dout___data___lsb 0 | |
170 | #define reg_gio_rw_pc_dout___data___width 16 | |
171 | #define reg_gio_rw_pc_dout_offset 92 | |
172 | ||
173 | /* Register rw_pc_oe, scope gio, type rw */ | |
174 | #define reg_gio_rw_pc_oe___oe___lsb 0 | |
175 | #define reg_gio_rw_pc_oe___oe___width 16 | |
176 | #define reg_gio_rw_pc_oe_offset 96 | |
177 | ||
178 | /* Register rw_pc_byte0_dout, scope gio, type rw */ | |
179 | #define reg_gio_rw_pc_byte0_dout___data___lsb 0 | |
180 | #define reg_gio_rw_pc_byte0_dout___data___width 8 | |
181 | #define reg_gio_rw_pc_byte0_dout_offset 100 | |
182 | ||
183 | /* Register rw_pc_byte0_oe, scope gio, type rw */ | |
184 | #define reg_gio_rw_pc_byte0_oe___oe___lsb 0 | |
185 | #define reg_gio_rw_pc_byte0_oe___oe___width 8 | |
186 | #define reg_gio_rw_pc_byte0_oe_offset 104 | |
187 | ||
188 | /* Register rw_pc_byte1_dout, scope gio, type rw */ | |
189 | #define reg_gio_rw_pc_byte1_dout___data___lsb 0 | |
190 | #define reg_gio_rw_pc_byte1_dout___data___width 8 | |
191 | #define reg_gio_rw_pc_byte1_dout_offset 108 | |
192 | ||
193 | /* Register rw_pc_byte1_oe, scope gio, type rw */ | |
194 | #define reg_gio_rw_pc_byte1_oe___oe___lsb 0 | |
195 | #define reg_gio_rw_pc_byte1_oe___oe___width 8 | |
196 | #define reg_gio_rw_pc_byte1_oe_offset 112 | |
197 | ||
198 | /* Register r_pd_din, scope gio, type r */ | |
199 | #define reg_gio_r_pd_din___data___lsb 0 | |
200 | #define reg_gio_r_pd_din___data___width 32 | |
201 | #define reg_gio_r_pd_din_offset 116 | |
202 | ||
203 | /* Register rw_intr_cfg, scope gio, type rw */ | |
204 | #define reg_gio_rw_intr_cfg___intr0___lsb 0 | |
205 | #define reg_gio_rw_intr_cfg___intr0___width 3 | |
206 | #define reg_gio_rw_intr_cfg___intr1___lsb 3 | |
207 | #define reg_gio_rw_intr_cfg___intr1___width 3 | |
208 | #define reg_gio_rw_intr_cfg___intr2___lsb 6 | |
209 | #define reg_gio_rw_intr_cfg___intr2___width 3 | |
210 | #define reg_gio_rw_intr_cfg___intr3___lsb 9 | |
211 | #define reg_gio_rw_intr_cfg___intr3___width 3 | |
212 | #define reg_gio_rw_intr_cfg___intr4___lsb 12 | |
213 | #define reg_gio_rw_intr_cfg___intr4___width 3 | |
214 | #define reg_gio_rw_intr_cfg___intr5___lsb 15 | |
215 | #define reg_gio_rw_intr_cfg___intr5___width 3 | |
216 | #define reg_gio_rw_intr_cfg___intr6___lsb 18 | |
217 | #define reg_gio_rw_intr_cfg___intr6___width 3 | |
218 | #define reg_gio_rw_intr_cfg___intr7___lsb 21 | |
219 | #define reg_gio_rw_intr_cfg___intr7___width 3 | |
220 | #define reg_gio_rw_intr_cfg_offset 120 | |
221 | ||
222 | /* Register rw_intr_pins, scope gio, type rw */ | |
223 | #define reg_gio_rw_intr_pins___intr0___lsb 0 | |
224 | #define reg_gio_rw_intr_pins___intr0___width 4 | |
225 | #define reg_gio_rw_intr_pins___intr1___lsb 4 | |
226 | #define reg_gio_rw_intr_pins___intr1___width 4 | |
227 | #define reg_gio_rw_intr_pins___intr2___lsb 8 | |
228 | #define reg_gio_rw_intr_pins___intr2___width 4 | |
229 | #define reg_gio_rw_intr_pins___intr3___lsb 12 | |
230 | #define reg_gio_rw_intr_pins___intr3___width 4 | |
231 | #define reg_gio_rw_intr_pins___intr4___lsb 16 | |
232 | #define reg_gio_rw_intr_pins___intr4___width 4 | |
233 | #define reg_gio_rw_intr_pins___intr5___lsb 20 | |
234 | #define reg_gio_rw_intr_pins___intr5___width 4 | |
235 | #define reg_gio_rw_intr_pins___intr6___lsb 24 | |
236 | #define reg_gio_rw_intr_pins___intr6___width 4 | |
237 | #define reg_gio_rw_intr_pins___intr7___lsb 28 | |
238 | #define reg_gio_rw_intr_pins___intr7___width 4 | |
239 | #define reg_gio_rw_intr_pins_offset 124 | |
240 | ||
241 | /* Register rw_intr_mask, scope gio, type rw */ | |
242 | #define reg_gio_rw_intr_mask___intr0___lsb 0 | |
243 | #define reg_gio_rw_intr_mask___intr0___width 1 | |
244 | #define reg_gio_rw_intr_mask___intr0___bit 0 | |
245 | #define reg_gio_rw_intr_mask___intr1___lsb 1 | |
246 | #define reg_gio_rw_intr_mask___intr1___width 1 | |
247 | #define reg_gio_rw_intr_mask___intr1___bit 1 | |
248 | #define reg_gio_rw_intr_mask___intr2___lsb 2 | |
249 | #define reg_gio_rw_intr_mask___intr2___width 1 | |
250 | #define reg_gio_rw_intr_mask___intr2___bit 2 | |
251 | #define reg_gio_rw_intr_mask___intr3___lsb 3 | |
252 | #define reg_gio_rw_intr_mask___intr3___width 1 | |
253 | #define reg_gio_rw_intr_mask___intr3___bit 3 | |
254 | #define reg_gio_rw_intr_mask___intr4___lsb 4 | |
255 | #define reg_gio_rw_intr_mask___intr4___width 1 | |
256 | #define reg_gio_rw_intr_mask___intr4___bit 4 | |
257 | #define reg_gio_rw_intr_mask___intr5___lsb 5 | |
258 | #define reg_gio_rw_intr_mask___intr5___width 1 | |
259 | #define reg_gio_rw_intr_mask___intr5___bit 5 | |
260 | #define reg_gio_rw_intr_mask___intr6___lsb 6 | |
261 | #define reg_gio_rw_intr_mask___intr6___width 1 | |
262 | #define reg_gio_rw_intr_mask___intr6___bit 6 | |
263 | #define reg_gio_rw_intr_mask___intr7___lsb 7 | |
264 | #define reg_gio_rw_intr_mask___intr7___width 1 | |
265 | #define reg_gio_rw_intr_mask___intr7___bit 7 | |
266 | #define reg_gio_rw_intr_mask___i2c0_done___lsb 8 | |
267 | #define reg_gio_rw_intr_mask___i2c0_done___width 1 | |
268 | #define reg_gio_rw_intr_mask___i2c0_done___bit 8 | |
269 | #define reg_gio_rw_intr_mask___i2c1_done___lsb 9 | |
270 | #define reg_gio_rw_intr_mask___i2c1_done___width 1 | |
271 | #define reg_gio_rw_intr_mask___i2c1_done___bit 9 | |
272 | #define reg_gio_rw_intr_mask_offset 128 | |
273 | ||
274 | /* Register rw_ack_intr, scope gio, type rw */ | |
275 | #define reg_gio_rw_ack_intr___intr0___lsb 0 | |
276 | #define reg_gio_rw_ack_intr___intr0___width 1 | |
277 | #define reg_gio_rw_ack_intr___intr0___bit 0 | |
278 | #define reg_gio_rw_ack_intr___intr1___lsb 1 | |
279 | #define reg_gio_rw_ack_intr___intr1___width 1 | |
280 | #define reg_gio_rw_ack_intr___intr1___bit 1 | |
281 | #define reg_gio_rw_ack_intr___intr2___lsb 2 | |
282 | #define reg_gio_rw_ack_intr___intr2___width 1 | |
283 | #define reg_gio_rw_ack_intr___intr2___bit 2 | |
284 | #define reg_gio_rw_ack_intr___intr3___lsb 3 | |
285 | #define reg_gio_rw_ack_intr___intr3___width 1 | |
286 | #define reg_gio_rw_ack_intr___intr3___bit 3 | |
287 | #define reg_gio_rw_ack_intr___intr4___lsb 4 | |
288 | #define reg_gio_rw_ack_intr___intr4___width 1 | |
289 | #define reg_gio_rw_ack_intr___intr4___bit 4 | |
290 | #define reg_gio_rw_ack_intr___intr5___lsb 5 | |
291 | #define reg_gio_rw_ack_intr___intr5___width 1 | |
292 | #define reg_gio_rw_ack_intr___intr5___bit 5 | |
293 | #define reg_gio_rw_ack_intr___intr6___lsb 6 | |
294 | #define reg_gio_rw_ack_intr___intr6___width 1 | |
295 | #define reg_gio_rw_ack_intr___intr6___bit 6 | |
296 | #define reg_gio_rw_ack_intr___intr7___lsb 7 | |
297 | #define reg_gio_rw_ack_intr___intr7___width 1 | |
298 | #define reg_gio_rw_ack_intr___intr7___bit 7 | |
299 | #define reg_gio_rw_ack_intr___i2c0_done___lsb 8 | |
300 | #define reg_gio_rw_ack_intr___i2c0_done___width 1 | |
301 | #define reg_gio_rw_ack_intr___i2c0_done___bit 8 | |
302 | #define reg_gio_rw_ack_intr___i2c1_done___lsb 9 | |
303 | #define reg_gio_rw_ack_intr___i2c1_done___width 1 | |
304 | #define reg_gio_rw_ack_intr___i2c1_done___bit 9 | |
305 | #define reg_gio_rw_ack_intr_offset 132 | |
306 | ||
307 | /* Register r_intr, scope gio, type r */ | |
308 | #define reg_gio_r_intr___intr0___lsb 0 | |
309 | #define reg_gio_r_intr___intr0___width 1 | |
310 | #define reg_gio_r_intr___intr0___bit 0 | |
311 | #define reg_gio_r_intr___intr1___lsb 1 | |
312 | #define reg_gio_r_intr___intr1___width 1 | |
313 | #define reg_gio_r_intr___intr1___bit 1 | |
314 | #define reg_gio_r_intr___intr2___lsb 2 | |
315 | #define reg_gio_r_intr___intr2___width 1 | |
316 | #define reg_gio_r_intr___intr2___bit 2 | |
317 | #define reg_gio_r_intr___intr3___lsb 3 | |
318 | #define reg_gio_r_intr___intr3___width 1 | |
319 | #define reg_gio_r_intr___intr3___bit 3 | |
320 | #define reg_gio_r_intr___intr4___lsb 4 | |
321 | #define reg_gio_r_intr___intr4___width 1 | |
322 | #define reg_gio_r_intr___intr4___bit 4 | |
323 | #define reg_gio_r_intr___intr5___lsb 5 | |
324 | #define reg_gio_r_intr___intr5___width 1 | |
325 | #define reg_gio_r_intr___intr5___bit 5 | |
326 | #define reg_gio_r_intr___intr6___lsb 6 | |
327 | #define reg_gio_r_intr___intr6___width 1 | |
328 | #define reg_gio_r_intr___intr6___bit 6 | |
329 | #define reg_gio_r_intr___intr7___lsb 7 | |
330 | #define reg_gio_r_intr___intr7___width 1 | |
331 | #define reg_gio_r_intr___intr7___bit 7 | |
332 | #define reg_gio_r_intr___i2c0_done___lsb 8 | |
333 | #define reg_gio_r_intr___i2c0_done___width 1 | |
334 | #define reg_gio_r_intr___i2c0_done___bit 8 | |
335 | #define reg_gio_r_intr___i2c1_done___lsb 9 | |
336 | #define reg_gio_r_intr___i2c1_done___width 1 | |
337 | #define reg_gio_r_intr___i2c1_done___bit 9 | |
338 | #define reg_gio_r_intr_offset 136 | |
339 | ||
340 | /* Register r_masked_intr, scope gio, type r */ | |
341 | #define reg_gio_r_masked_intr___intr0___lsb 0 | |
342 | #define reg_gio_r_masked_intr___intr0___width 1 | |
343 | #define reg_gio_r_masked_intr___intr0___bit 0 | |
344 | #define reg_gio_r_masked_intr___intr1___lsb 1 | |
345 | #define reg_gio_r_masked_intr___intr1___width 1 | |
346 | #define reg_gio_r_masked_intr___intr1___bit 1 | |
347 | #define reg_gio_r_masked_intr___intr2___lsb 2 | |
348 | #define reg_gio_r_masked_intr___intr2___width 1 | |
349 | #define reg_gio_r_masked_intr___intr2___bit 2 | |
350 | #define reg_gio_r_masked_intr___intr3___lsb 3 | |
351 | #define reg_gio_r_masked_intr___intr3___width 1 | |
352 | #define reg_gio_r_masked_intr___intr3___bit 3 | |
353 | #define reg_gio_r_masked_intr___intr4___lsb 4 | |
354 | #define reg_gio_r_masked_intr___intr4___width 1 | |
355 | #define reg_gio_r_masked_intr___intr4___bit 4 | |
356 | #define reg_gio_r_masked_intr___intr5___lsb 5 | |
357 | #define reg_gio_r_masked_intr___intr5___width 1 | |
358 | #define reg_gio_r_masked_intr___intr5___bit 5 | |
359 | #define reg_gio_r_masked_intr___intr6___lsb 6 | |
360 | #define reg_gio_r_masked_intr___intr6___width 1 | |
361 | #define reg_gio_r_masked_intr___intr6___bit 6 | |
362 | #define reg_gio_r_masked_intr___intr7___lsb 7 | |
363 | #define reg_gio_r_masked_intr___intr7___width 1 | |
364 | #define reg_gio_r_masked_intr___intr7___bit 7 | |
365 | #define reg_gio_r_masked_intr___i2c0_done___lsb 8 | |
366 | #define reg_gio_r_masked_intr___i2c0_done___width 1 | |
367 | #define reg_gio_r_masked_intr___i2c0_done___bit 8 | |
368 | #define reg_gio_r_masked_intr___i2c1_done___lsb 9 | |
369 | #define reg_gio_r_masked_intr___i2c1_done___width 1 | |
370 | #define reg_gio_r_masked_intr___i2c1_done___bit 9 | |
371 | #define reg_gio_r_masked_intr_offset 140 | |
372 | ||
373 | /* Register rw_i2c0_start, scope gio, type rw */ | |
374 | #define reg_gio_rw_i2c0_start___run___lsb 0 | |
375 | #define reg_gio_rw_i2c0_start___run___width 1 | |
376 | #define reg_gio_rw_i2c0_start___run___bit 0 | |
377 | #define reg_gio_rw_i2c0_start_offset 144 | |
378 | ||
379 | /* Register rw_i2c0_cfg, scope gio, type rw */ | |
380 | #define reg_gio_rw_i2c0_cfg___en___lsb 0 | |
381 | #define reg_gio_rw_i2c0_cfg___en___width 1 | |
382 | #define reg_gio_rw_i2c0_cfg___en___bit 0 | |
383 | #define reg_gio_rw_i2c0_cfg___bit_order___lsb 1 | |
384 | #define reg_gio_rw_i2c0_cfg___bit_order___width 1 | |
385 | #define reg_gio_rw_i2c0_cfg___bit_order___bit 1 | |
386 | #define reg_gio_rw_i2c0_cfg___scl_io___lsb 2 | |
387 | #define reg_gio_rw_i2c0_cfg___scl_io___width 1 | |
388 | #define reg_gio_rw_i2c0_cfg___scl_io___bit 2 | |
389 | #define reg_gio_rw_i2c0_cfg___scl_inv___lsb 3 | |
390 | #define reg_gio_rw_i2c0_cfg___scl_inv___width 1 | |
391 | #define reg_gio_rw_i2c0_cfg___scl_inv___bit 3 | |
392 | #define reg_gio_rw_i2c0_cfg___sda_io___lsb 4 | |
393 | #define reg_gio_rw_i2c0_cfg___sda_io___width 1 | |
394 | #define reg_gio_rw_i2c0_cfg___sda_io___bit 4 | |
395 | #define reg_gio_rw_i2c0_cfg___sda_idle___lsb 5 | |
396 | #define reg_gio_rw_i2c0_cfg___sda_idle___width 1 | |
397 | #define reg_gio_rw_i2c0_cfg___sda_idle___bit 5 | |
398 | #define reg_gio_rw_i2c0_cfg_offset 148 | |
399 | ||
400 | /* Register rw_i2c0_ctrl, scope gio, type rw */ | |
401 | #define reg_gio_rw_i2c0_ctrl___trf_bits___lsb 0 | |
402 | #define reg_gio_rw_i2c0_ctrl___trf_bits___width 6 | |
403 | #define reg_gio_rw_i2c0_ctrl___switch_dir___lsb 6 | |
404 | #define reg_gio_rw_i2c0_ctrl___switch_dir___width 6 | |
405 | #define reg_gio_rw_i2c0_ctrl___extra_start___lsb 12 | |
406 | #define reg_gio_rw_i2c0_ctrl___extra_start___width 3 | |
407 | #define reg_gio_rw_i2c0_ctrl___early_end___lsb 15 | |
408 | #define reg_gio_rw_i2c0_ctrl___early_end___width 1 | |
409 | #define reg_gio_rw_i2c0_ctrl___early_end___bit 15 | |
410 | #define reg_gio_rw_i2c0_ctrl___start_stop___lsb 16 | |
411 | #define reg_gio_rw_i2c0_ctrl___start_stop___width 1 | |
412 | #define reg_gio_rw_i2c0_ctrl___start_stop___bit 16 | |
413 | #define reg_gio_rw_i2c0_ctrl___ack_dir0___lsb 17 | |
414 | #define reg_gio_rw_i2c0_ctrl___ack_dir0___width 1 | |
415 | #define reg_gio_rw_i2c0_ctrl___ack_dir0___bit 17 | |
416 | #define reg_gio_rw_i2c0_ctrl___ack_dir1___lsb 18 | |
417 | #define reg_gio_rw_i2c0_ctrl___ack_dir1___width 1 | |
418 | #define reg_gio_rw_i2c0_ctrl___ack_dir1___bit 18 | |
419 | #define reg_gio_rw_i2c0_ctrl___ack_dir2___lsb 19 | |
420 | #define reg_gio_rw_i2c0_ctrl___ack_dir2___width 1 | |
421 | #define reg_gio_rw_i2c0_ctrl___ack_dir2___bit 19 | |
422 | #define reg_gio_rw_i2c0_ctrl___ack_dir3___lsb 20 | |
423 | #define reg_gio_rw_i2c0_ctrl___ack_dir3___width 1 | |
424 | #define reg_gio_rw_i2c0_ctrl___ack_dir3___bit 20 | |
425 | #define reg_gio_rw_i2c0_ctrl___ack_dir4___lsb 21 | |
426 | #define reg_gio_rw_i2c0_ctrl___ack_dir4___width 1 | |
427 | #define reg_gio_rw_i2c0_ctrl___ack_dir4___bit 21 | |
428 | #define reg_gio_rw_i2c0_ctrl___ack_dir5___lsb 22 | |
429 | #define reg_gio_rw_i2c0_ctrl___ack_dir5___width 1 | |
430 | #define reg_gio_rw_i2c0_ctrl___ack_dir5___bit 22 | |
431 | #define reg_gio_rw_i2c0_ctrl___ack_bit___lsb 23 | |
432 | #define reg_gio_rw_i2c0_ctrl___ack_bit___width 1 | |
433 | #define reg_gio_rw_i2c0_ctrl___ack_bit___bit 23 | |
434 | #define reg_gio_rw_i2c0_ctrl___start_bit___lsb 24 | |
435 | #define reg_gio_rw_i2c0_ctrl___start_bit___width 1 | |
436 | #define reg_gio_rw_i2c0_ctrl___start_bit___bit 24 | |
437 | #define reg_gio_rw_i2c0_ctrl___freq___lsb 25 | |
438 | #define reg_gio_rw_i2c0_ctrl___freq___width 2 | |
439 | #define reg_gio_rw_i2c0_ctrl_offset 152 | |
440 | ||
441 | /* Register rw_i2c0_data, scope gio, type rw */ | |
442 | #define reg_gio_rw_i2c0_data___data0___lsb 0 | |
443 | #define reg_gio_rw_i2c0_data___data0___width 8 | |
444 | #define reg_gio_rw_i2c0_data___data1___lsb 8 | |
445 | #define reg_gio_rw_i2c0_data___data1___width 8 | |
446 | #define reg_gio_rw_i2c0_data___data2___lsb 16 | |
447 | #define reg_gio_rw_i2c0_data___data2___width 8 | |
448 | #define reg_gio_rw_i2c0_data___data3___lsb 24 | |
449 | #define reg_gio_rw_i2c0_data___data3___width 8 | |
450 | #define reg_gio_rw_i2c0_data_offset 156 | |
451 | ||
452 | /* Register rw_i2c0_data2, scope gio, type rw */ | |
453 | #define reg_gio_rw_i2c0_data2___data4___lsb 0 | |
454 | #define reg_gio_rw_i2c0_data2___data4___width 8 | |
455 | #define reg_gio_rw_i2c0_data2___data5___lsb 8 | |
456 | #define reg_gio_rw_i2c0_data2___data5___width 8 | |
457 | #define reg_gio_rw_i2c0_data2___start_val___lsb 16 | |
458 | #define reg_gio_rw_i2c0_data2___start_val___width 6 | |
459 | #define reg_gio_rw_i2c0_data2___ack_val___lsb 22 | |
460 | #define reg_gio_rw_i2c0_data2___ack_val___width 6 | |
461 | #define reg_gio_rw_i2c0_data2_offset 160 | |
462 | ||
463 | /* Register rw_i2c1_start, scope gio, type rw */ | |
464 | #define reg_gio_rw_i2c1_start___run___lsb 0 | |
465 | #define reg_gio_rw_i2c1_start___run___width 1 | |
466 | #define reg_gio_rw_i2c1_start___run___bit 0 | |
467 | #define reg_gio_rw_i2c1_start_offset 164 | |
468 | ||
469 | /* Register rw_i2c1_cfg, scope gio, type rw */ | |
470 | #define reg_gio_rw_i2c1_cfg___en___lsb 0 | |
471 | #define reg_gio_rw_i2c1_cfg___en___width 1 | |
472 | #define reg_gio_rw_i2c1_cfg___en___bit 0 | |
473 | #define reg_gio_rw_i2c1_cfg___bit_order___lsb 1 | |
474 | #define reg_gio_rw_i2c1_cfg___bit_order___width 1 | |
475 | #define reg_gio_rw_i2c1_cfg___bit_order___bit 1 | |
476 | #define reg_gio_rw_i2c1_cfg___scl_io___lsb 2 | |
477 | #define reg_gio_rw_i2c1_cfg___scl_io___width 1 | |
478 | #define reg_gio_rw_i2c1_cfg___scl_io___bit 2 | |
479 | #define reg_gio_rw_i2c1_cfg___scl_inv___lsb 3 | |
480 | #define reg_gio_rw_i2c1_cfg___scl_inv___width 1 | |
481 | #define reg_gio_rw_i2c1_cfg___scl_inv___bit 3 | |
482 | #define reg_gio_rw_i2c1_cfg___sda0_io___lsb 4 | |
483 | #define reg_gio_rw_i2c1_cfg___sda0_io___width 1 | |
484 | #define reg_gio_rw_i2c1_cfg___sda0_io___bit 4 | |
485 | #define reg_gio_rw_i2c1_cfg___sda0_idle___lsb 5 | |
486 | #define reg_gio_rw_i2c1_cfg___sda0_idle___width 1 | |
487 | #define reg_gio_rw_i2c1_cfg___sda0_idle___bit 5 | |
488 | #define reg_gio_rw_i2c1_cfg___sda1_io___lsb 6 | |
489 | #define reg_gio_rw_i2c1_cfg___sda1_io___width 1 | |
490 | #define reg_gio_rw_i2c1_cfg___sda1_io___bit 6 | |
491 | #define reg_gio_rw_i2c1_cfg___sda1_idle___lsb 7 | |
492 | #define reg_gio_rw_i2c1_cfg___sda1_idle___width 1 | |
493 | #define reg_gio_rw_i2c1_cfg___sda1_idle___bit 7 | |
494 | #define reg_gio_rw_i2c1_cfg___sda2_io___lsb 8 | |
495 | #define reg_gio_rw_i2c1_cfg___sda2_io___width 1 | |
496 | #define reg_gio_rw_i2c1_cfg___sda2_io___bit 8 | |
497 | #define reg_gio_rw_i2c1_cfg___sda2_idle___lsb 9 | |
498 | #define reg_gio_rw_i2c1_cfg___sda2_idle___width 1 | |
499 | #define reg_gio_rw_i2c1_cfg___sda2_idle___bit 9 | |
500 | #define reg_gio_rw_i2c1_cfg___sda3_io___lsb 10 | |
501 | #define reg_gio_rw_i2c1_cfg___sda3_io___width 1 | |
502 | #define reg_gio_rw_i2c1_cfg___sda3_io___bit 10 | |
503 | #define reg_gio_rw_i2c1_cfg___sda3_idle___lsb 11 | |
504 | #define reg_gio_rw_i2c1_cfg___sda3_idle___width 1 | |
505 | #define reg_gio_rw_i2c1_cfg___sda3_idle___bit 11 | |
506 | #define reg_gio_rw_i2c1_cfg___sda_sel___lsb 12 | |
507 | #define reg_gio_rw_i2c1_cfg___sda_sel___width 2 | |
508 | #define reg_gio_rw_i2c1_cfg___sen_idle___lsb 14 | |
509 | #define reg_gio_rw_i2c1_cfg___sen_idle___width 1 | |
510 | #define reg_gio_rw_i2c1_cfg___sen_idle___bit 14 | |
511 | #define reg_gio_rw_i2c1_cfg___sen_inv___lsb 15 | |
512 | #define reg_gio_rw_i2c1_cfg___sen_inv___width 1 | |
513 | #define reg_gio_rw_i2c1_cfg___sen_inv___bit 15 | |
514 | #define reg_gio_rw_i2c1_cfg___sen_sel___lsb 16 | |
515 | #define reg_gio_rw_i2c1_cfg___sen_sel___width 2 | |
516 | #define reg_gio_rw_i2c1_cfg_offset 168 | |
517 | ||
518 | /* Register rw_i2c1_ctrl, scope gio, type rw */ | |
519 | #define reg_gio_rw_i2c1_ctrl___trf_bits___lsb 0 | |
520 | #define reg_gio_rw_i2c1_ctrl___trf_bits___width 6 | |
521 | #define reg_gio_rw_i2c1_ctrl___switch_dir___lsb 6 | |
522 | #define reg_gio_rw_i2c1_ctrl___switch_dir___width 6 | |
523 | #define reg_gio_rw_i2c1_ctrl___extra_start___lsb 12 | |
524 | #define reg_gio_rw_i2c1_ctrl___extra_start___width 3 | |
525 | #define reg_gio_rw_i2c1_ctrl___early_end___lsb 15 | |
526 | #define reg_gio_rw_i2c1_ctrl___early_end___width 1 | |
527 | #define reg_gio_rw_i2c1_ctrl___early_end___bit 15 | |
528 | #define reg_gio_rw_i2c1_ctrl___start_stop___lsb 16 | |
529 | #define reg_gio_rw_i2c1_ctrl___start_stop___width 1 | |
530 | #define reg_gio_rw_i2c1_ctrl___start_stop___bit 16 | |
531 | #define reg_gio_rw_i2c1_ctrl___ack_dir0___lsb 17 | |
532 | #define reg_gio_rw_i2c1_ctrl___ack_dir0___width 1 | |
533 | #define reg_gio_rw_i2c1_ctrl___ack_dir0___bit 17 | |
534 | #define reg_gio_rw_i2c1_ctrl___ack_dir1___lsb 18 | |
535 | #define reg_gio_rw_i2c1_ctrl___ack_dir1___width 1 | |
536 | #define reg_gio_rw_i2c1_ctrl___ack_dir1___bit 18 | |
537 | #define reg_gio_rw_i2c1_ctrl___ack_dir2___lsb 19 | |
538 | #define reg_gio_rw_i2c1_ctrl___ack_dir2___width 1 | |
539 | #define reg_gio_rw_i2c1_ctrl___ack_dir2___bit 19 | |
540 | #define reg_gio_rw_i2c1_ctrl___ack_dir3___lsb 20 | |
541 | #define reg_gio_rw_i2c1_ctrl___ack_dir3___width 1 | |
542 | #define reg_gio_rw_i2c1_ctrl___ack_dir3___bit 20 | |
543 | #define reg_gio_rw_i2c1_ctrl___ack_dir4___lsb 21 | |
544 | #define reg_gio_rw_i2c1_ctrl___ack_dir4___width 1 | |
545 | #define reg_gio_rw_i2c1_ctrl___ack_dir4___bit 21 | |
546 | #define reg_gio_rw_i2c1_ctrl___ack_dir5___lsb 22 | |
547 | #define reg_gio_rw_i2c1_ctrl___ack_dir5___width 1 | |
548 | #define reg_gio_rw_i2c1_ctrl___ack_dir5___bit 22 | |
549 | #define reg_gio_rw_i2c1_ctrl___ack_bit___lsb 23 | |
550 | #define reg_gio_rw_i2c1_ctrl___ack_bit___width 1 | |
551 | #define reg_gio_rw_i2c1_ctrl___ack_bit___bit 23 | |
552 | #define reg_gio_rw_i2c1_ctrl___start_bit___lsb 24 | |
553 | #define reg_gio_rw_i2c1_ctrl___start_bit___width 1 | |
554 | #define reg_gio_rw_i2c1_ctrl___start_bit___bit 24 | |
555 | #define reg_gio_rw_i2c1_ctrl___freq___lsb 25 | |
556 | #define reg_gio_rw_i2c1_ctrl___freq___width 2 | |
557 | #define reg_gio_rw_i2c1_ctrl_offset 172 | |
558 | ||
559 | /* Register rw_i2c1_data, scope gio, type rw */ | |
560 | #define reg_gio_rw_i2c1_data___data0___lsb 0 | |
561 | #define reg_gio_rw_i2c1_data___data0___width 8 | |
562 | #define reg_gio_rw_i2c1_data___data1___lsb 8 | |
563 | #define reg_gio_rw_i2c1_data___data1___width 8 | |
564 | #define reg_gio_rw_i2c1_data___data2___lsb 16 | |
565 | #define reg_gio_rw_i2c1_data___data2___width 8 | |
566 | #define reg_gio_rw_i2c1_data___data3___lsb 24 | |
567 | #define reg_gio_rw_i2c1_data___data3___width 8 | |
568 | #define reg_gio_rw_i2c1_data_offset 176 | |
569 | ||
570 | /* Register rw_i2c1_data2, scope gio, type rw */ | |
571 | #define reg_gio_rw_i2c1_data2___data4___lsb 0 | |
572 | #define reg_gio_rw_i2c1_data2___data4___width 8 | |
573 | #define reg_gio_rw_i2c1_data2___data5___lsb 8 | |
574 | #define reg_gio_rw_i2c1_data2___data5___width 8 | |
575 | #define reg_gio_rw_i2c1_data2___start_val___lsb 16 | |
576 | #define reg_gio_rw_i2c1_data2___start_val___width 6 | |
577 | #define reg_gio_rw_i2c1_data2___ack_val___lsb 22 | |
578 | #define reg_gio_rw_i2c1_data2___ack_val___width 6 | |
579 | #define reg_gio_rw_i2c1_data2_offset 180 | |
580 | ||
581 | /* Register r_ppwm_stat, scope gio, type r */ | |
582 | #define reg_gio_r_ppwm_stat___freq___lsb 0 | |
583 | #define reg_gio_r_ppwm_stat___freq___width 2 | |
584 | #define reg_gio_r_ppwm_stat_offset 184 | |
585 | ||
586 | /* Register rw_ppwm_data, scope gio, type rw */ | |
587 | #define reg_gio_rw_ppwm_data___data___lsb 0 | |
588 | #define reg_gio_rw_ppwm_data___data___width 8 | |
589 | #define reg_gio_rw_ppwm_data_offset 188 | |
590 | ||
591 | /* Register rw_pwm0_ctrl, scope gio, type rw */ | |
592 | #define reg_gio_rw_pwm0_ctrl___mode___lsb 0 | |
593 | #define reg_gio_rw_pwm0_ctrl___mode___width 2 | |
594 | #define reg_gio_rw_pwm0_ctrl___ccd_override___lsb 2 | |
595 | #define reg_gio_rw_pwm0_ctrl___ccd_override___width 1 | |
596 | #define reg_gio_rw_pwm0_ctrl___ccd_override___bit 2 | |
597 | #define reg_gio_rw_pwm0_ctrl___ccd_val___lsb 3 | |
598 | #define reg_gio_rw_pwm0_ctrl___ccd_val___width 1 | |
599 | #define reg_gio_rw_pwm0_ctrl___ccd_val___bit 3 | |
600 | #define reg_gio_rw_pwm0_ctrl_offset 192 | |
601 | ||
602 | /* Register rw_pwm0_var, scope gio, type rw */ | |
603 | #define reg_gio_rw_pwm0_var___lo___lsb 0 | |
604 | #define reg_gio_rw_pwm0_var___lo___width 13 | |
605 | #define reg_gio_rw_pwm0_var___hi___lsb 13 | |
606 | #define reg_gio_rw_pwm0_var___hi___width 13 | |
607 | #define reg_gio_rw_pwm0_var_offset 196 | |
608 | ||
609 | /* Register rw_pwm0_data, scope gio, type rw */ | |
610 | #define reg_gio_rw_pwm0_data___data___lsb 0 | |
611 | #define reg_gio_rw_pwm0_data___data___width 8 | |
612 | #define reg_gio_rw_pwm0_data_offset 200 | |
613 | ||
614 | /* Register rw_pwm1_ctrl, scope gio, type rw */ | |
615 | #define reg_gio_rw_pwm1_ctrl___mode___lsb 0 | |
616 | #define reg_gio_rw_pwm1_ctrl___mode___width 2 | |
617 | #define reg_gio_rw_pwm1_ctrl___ccd_override___lsb 2 | |
618 | #define reg_gio_rw_pwm1_ctrl___ccd_override___width 1 | |
619 | #define reg_gio_rw_pwm1_ctrl___ccd_override___bit 2 | |
620 | #define reg_gio_rw_pwm1_ctrl___ccd_val___lsb 3 | |
621 | #define reg_gio_rw_pwm1_ctrl___ccd_val___width 1 | |
622 | #define reg_gio_rw_pwm1_ctrl___ccd_val___bit 3 | |
623 | #define reg_gio_rw_pwm1_ctrl_offset 204 | |
624 | ||
625 | /* Register rw_pwm1_var, scope gio, type rw */ | |
626 | #define reg_gio_rw_pwm1_var___lo___lsb 0 | |
627 | #define reg_gio_rw_pwm1_var___lo___width 13 | |
628 | #define reg_gio_rw_pwm1_var___hi___lsb 13 | |
629 | #define reg_gio_rw_pwm1_var___hi___width 13 | |
630 | #define reg_gio_rw_pwm1_var_offset 208 | |
631 | ||
632 | /* Register rw_pwm1_data, scope gio, type rw */ | |
633 | #define reg_gio_rw_pwm1_data___data___lsb 0 | |
634 | #define reg_gio_rw_pwm1_data___data___width 8 | |
635 | #define reg_gio_rw_pwm1_data_offset 212 | |
636 | ||
637 | /* Register rw_pwm2_ctrl, scope gio, type rw */ | |
638 | #define reg_gio_rw_pwm2_ctrl___mode___lsb 0 | |
639 | #define reg_gio_rw_pwm2_ctrl___mode___width 2 | |
640 | #define reg_gio_rw_pwm2_ctrl___ccd_override___lsb 2 | |
641 | #define reg_gio_rw_pwm2_ctrl___ccd_override___width 1 | |
642 | #define reg_gio_rw_pwm2_ctrl___ccd_override___bit 2 | |
643 | #define reg_gio_rw_pwm2_ctrl___ccd_val___lsb 3 | |
644 | #define reg_gio_rw_pwm2_ctrl___ccd_val___width 1 | |
645 | #define reg_gio_rw_pwm2_ctrl___ccd_val___bit 3 | |
646 | #define reg_gio_rw_pwm2_ctrl_offset 216 | |
647 | ||
648 | /* Register rw_pwm2_var, scope gio, type rw */ | |
649 | #define reg_gio_rw_pwm2_var___lo___lsb 0 | |
650 | #define reg_gio_rw_pwm2_var___lo___width 13 | |
651 | #define reg_gio_rw_pwm2_var___hi___lsb 13 | |
652 | #define reg_gio_rw_pwm2_var___hi___width 13 | |
653 | #define reg_gio_rw_pwm2_var_offset 220 | |
654 | ||
655 | /* Register rw_pwm2_data, scope gio, type rw */ | |
656 | #define reg_gio_rw_pwm2_data___data___lsb 0 | |
657 | #define reg_gio_rw_pwm2_data___data___width 8 | |
658 | #define reg_gio_rw_pwm2_data_offset 224 | |
659 | ||
660 | /* Register rw_pwm_in_cfg, scope gio, type rw */ | |
661 | #define reg_gio_rw_pwm_in_cfg___pin___lsb 0 | |
662 | #define reg_gio_rw_pwm_in_cfg___pin___width 3 | |
663 | #define reg_gio_rw_pwm_in_cfg_offset 228 | |
664 | ||
665 | /* Register r_pwm_in_lo, scope gio, type r */ | |
666 | #define reg_gio_r_pwm_in_lo___data___lsb 0 | |
667 | #define reg_gio_r_pwm_in_lo___data___width 32 | |
668 | #define reg_gio_r_pwm_in_lo_offset 232 | |
669 | ||
670 | /* Register r_pwm_in_hi, scope gio, type r */ | |
671 | #define reg_gio_r_pwm_in_hi___data___lsb 0 | |
672 | #define reg_gio_r_pwm_in_hi___data___width 32 | |
673 | #define reg_gio_r_pwm_in_hi_offset 236 | |
674 | ||
675 | /* Register r_pwm_in_cnt, scope gio, type r */ | |
676 | #define reg_gio_r_pwm_in_cnt___data___lsb 0 | |
677 | #define reg_gio_r_pwm_in_cnt___data___width 32 | |
678 | #define reg_gio_r_pwm_in_cnt_offset 240 | |
679 | ||
680 | ||
681 | /* Constants */ | |
682 | #define regk_gio_anyedge 0x00000007 | |
683 | #define regk_gio_f100k 0x00000000 | |
684 | #define regk_gio_f1562 0x00000000 | |
685 | #define regk_gio_f195 0x00000003 | |
686 | #define regk_gio_f1m 0x00000002 | |
687 | #define regk_gio_f390 0x00000002 | |
688 | #define regk_gio_f400k 0x00000001 | |
689 | #define regk_gio_f5m 0x00000003 | |
690 | #define regk_gio_f781 0x00000001 | |
691 | #define regk_gio_hi 0x00000001 | |
692 | #define regk_gio_in 0x00000000 | |
693 | #define regk_gio_intr_pa0 0x00000000 | |
694 | #define regk_gio_intr_pa1 0x00000000 | |
695 | #define regk_gio_intr_pa10 0x00000001 | |
696 | #define regk_gio_intr_pa11 0x00000001 | |
697 | #define regk_gio_intr_pa12 0x00000001 | |
698 | #define regk_gio_intr_pa13 0x00000001 | |
699 | #define regk_gio_intr_pa14 0x00000001 | |
700 | #define regk_gio_intr_pa15 0x00000001 | |
701 | #define regk_gio_intr_pa16 0x00000002 | |
702 | #define regk_gio_intr_pa17 0x00000002 | |
703 | #define regk_gio_intr_pa18 0x00000002 | |
704 | #define regk_gio_intr_pa19 0x00000002 | |
705 | #define regk_gio_intr_pa2 0x00000000 | |
706 | #define regk_gio_intr_pa20 0x00000002 | |
707 | #define regk_gio_intr_pa21 0x00000002 | |
708 | #define regk_gio_intr_pa22 0x00000002 | |
709 | #define regk_gio_intr_pa23 0x00000002 | |
710 | #define regk_gio_intr_pa24 0x00000003 | |
711 | #define regk_gio_intr_pa25 0x00000003 | |
712 | #define regk_gio_intr_pa26 0x00000003 | |
713 | #define regk_gio_intr_pa27 0x00000003 | |
714 | #define regk_gio_intr_pa28 0x00000003 | |
715 | #define regk_gio_intr_pa29 0x00000003 | |
716 | #define regk_gio_intr_pa3 0x00000000 | |
717 | #define regk_gio_intr_pa30 0x00000003 | |
718 | #define regk_gio_intr_pa31 0x00000003 | |
719 | #define regk_gio_intr_pa4 0x00000000 | |
720 | #define regk_gio_intr_pa5 0x00000000 | |
721 | #define regk_gio_intr_pa6 0x00000000 | |
722 | #define regk_gio_intr_pa7 0x00000000 | |
723 | #define regk_gio_intr_pa8 0x00000001 | |
724 | #define regk_gio_intr_pa9 0x00000001 | |
725 | #define regk_gio_intr_pb0 0x00000004 | |
726 | #define regk_gio_intr_pb1 0x00000004 | |
727 | #define regk_gio_intr_pb10 0x00000005 | |
728 | #define regk_gio_intr_pb11 0x00000005 | |
729 | #define regk_gio_intr_pb12 0x00000005 | |
730 | #define regk_gio_intr_pb13 0x00000005 | |
731 | #define regk_gio_intr_pb14 0x00000005 | |
732 | #define regk_gio_intr_pb15 0x00000005 | |
733 | #define regk_gio_intr_pb16 0x00000006 | |
734 | #define regk_gio_intr_pb17 0x00000006 | |
735 | #define regk_gio_intr_pb18 0x00000006 | |
736 | #define regk_gio_intr_pb19 0x00000006 | |
737 | #define regk_gio_intr_pb2 0x00000004 | |
738 | #define regk_gio_intr_pb20 0x00000006 | |
739 | #define regk_gio_intr_pb21 0x00000006 | |
740 | #define regk_gio_intr_pb22 0x00000006 | |
741 | #define regk_gio_intr_pb23 0x00000006 | |
742 | #define regk_gio_intr_pb24 0x00000007 | |
743 | #define regk_gio_intr_pb25 0x00000007 | |
744 | #define regk_gio_intr_pb26 0x00000007 | |
745 | #define regk_gio_intr_pb27 0x00000007 | |
746 | #define regk_gio_intr_pb28 0x00000007 | |
747 | #define regk_gio_intr_pb29 0x00000007 | |
748 | #define regk_gio_intr_pb3 0x00000004 | |
749 | #define regk_gio_intr_pb30 0x00000007 | |
750 | #define regk_gio_intr_pb31 0x00000007 | |
751 | #define regk_gio_intr_pb4 0x00000004 | |
752 | #define regk_gio_intr_pb5 0x00000004 | |
753 | #define regk_gio_intr_pb6 0x00000004 | |
754 | #define regk_gio_intr_pb7 0x00000004 | |
755 | #define regk_gio_intr_pb8 0x00000005 | |
756 | #define regk_gio_intr_pb9 0x00000005 | |
757 | #define regk_gio_intr_pc0 0x00000008 | |
758 | #define regk_gio_intr_pc1 0x00000008 | |
759 | #define regk_gio_intr_pc10 0x00000009 | |
760 | #define regk_gio_intr_pc11 0x00000009 | |
761 | #define regk_gio_intr_pc12 0x00000009 | |
762 | #define regk_gio_intr_pc13 0x00000009 | |
763 | #define regk_gio_intr_pc14 0x00000009 | |
764 | #define regk_gio_intr_pc15 0x00000009 | |
765 | #define regk_gio_intr_pc2 0x00000008 | |
766 | #define regk_gio_intr_pc3 0x00000008 | |
767 | #define regk_gio_intr_pc4 0x00000008 | |
768 | #define regk_gio_intr_pc5 0x00000008 | |
769 | #define regk_gio_intr_pc6 0x00000008 | |
770 | #define regk_gio_intr_pc7 0x00000008 | |
771 | #define regk_gio_intr_pc8 0x00000009 | |
772 | #define regk_gio_intr_pc9 0x00000009 | |
773 | #define regk_gio_intr_pd0 0x0000000c | |
774 | #define regk_gio_intr_pd1 0x0000000c | |
775 | #define regk_gio_intr_pd10 0x0000000d | |
776 | #define regk_gio_intr_pd11 0x0000000d | |
777 | #define regk_gio_intr_pd12 0x0000000d | |
778 | #define regk_gio_intr_pd13 0x0000000d | |
779 | #define regk_gio_intr_pd14 0x0000000d | |
780 | #define regk_gio_intr_pd15 0x0000000d | |
781 | #define regk_gio_intr_pd16 0x0000000e | |
782 | #define regk_gio_intr_pd17 0x0000000e | |
783 | #define regk_gio_intr_pd18 0x0000000e | |
784 | #define regk_gio_intr_pd19 0x0000000e | |
785 | #define regk_gio_intr_pd2 0x0000000c | |
786 | #define regk_gio_intr_pd20 0x0000000e | |
787 | #define regk_gio_intr_pd21 0x0000000e | |
788 | #define regk_gio_intr_pd22 0x0000000e | |
789 | #define regk_gio_intr_pd23 0x0000000e | |
790 | #define regk_gio_intr_pd24 0x0000000f | |
791 | #define regk_gio_intr_pd25 0x0000000f | |
792 | #define regk_gio_intr_pd26 0x0000000f | |
793 | #define regk_gio_intr_pd27 0x0000000f | |
794 | #define regk_gio_intr_pd28 0x0000000f | |
795 | #define regk_gio_intr_pd29 0x0000000f | |
796 | #define regk_gio_intr_pd3 0x0000000c | |
797 | #define regk_gio_intr_pd30 0x0000000f | |
798 | #define regk_gio_intr_pd31 0x0000000f | |
799 | #define regk_gio_intr_pd4 0x0000000c | |
800 | #define regk_gio_intr_pd5 0x0000000c | |
801 | #define regk_gio_intr_pd6 0x0000000c | |
802 | #define regk_gio_intr_pd7 0x0000000c | |
803 | #define regk_gio_intr_pd8 0x0000000d | |
804 | #define regk_gio_intr_pd9 0x0000000d | |
805 | #define regk_gio_lo 0x00000002 | |
806 | #define regk_gio_lsb 0x00000000 | |
807 | #define regk_gio_msb 0x00000001 | |
808 | #define regk_gio_negedge 0x00000006 | |
809 | #define regk_gio_no 0x00000000 | |
810 | #define regk_gio_no_switch 0x0000003f | |
811 | #define regk_gio_none 0x00000007 | |
812 | #define regk_gio_off 0x00000000 | |
813 | #define regk_gio_opendrain 0x00000000 | |
814 | #define regk_gio_out 0x00000001 | |
815 | #define regk_gio_posedge 0x00000005 | |
816 | #define regk_gio_pwm_hfp 0x00000002 | |
817 | #define regk_gio_pwm_pa0 0x00000001 | |
818 | #define regk_gio_pwm_pa19 0x00000004 | |
819 | #define regk_gio_pwm_pa6 0x00000002 | |
820 | #define regk_gio_pwm_pa7 0x00000003 | |
821 | #define regk_gio_pwm_pb26 0x00000005 | |
822 | #define regk_gio_pwm_pd23 0x00000006 | |
823 | #define regk_gio_pwm_pd31 0x00000007 | |
824 | #define regk_gio_pwm_std 0x00000001 | |
825 | #define regk_gio_pwm_var 0x00000003 | |
826 | #define regk_gio_rw_i2c0_cfg_default 0x00000020 | |
827 | #define regk_gio_rw_i2c0_ctrl_default 0x00010000 | |
828 | #define regk_gio_rw_i2c0_start_default 0x00000000 | |
829 | #define regk_gio_rw_i2c1_cfg_default 0x00000aa0 | |
830 | #define regk_gio_rw_i2c1_ctrl_default 0x00010000 | |
831 | #define regk_gio_rw_i2c1_start_default 0x00000000 | |
832 | #define regk_gio_rw_intr_cfg_default 0x00000000 | |
833 | #define regk_gio_rw_intr_mask_default 0x00000000 | |
834 | #define regk_gio_rw_pa_oe_default 0x00000000 | |
835 | #define regk_gio_rw_pb_oe_default 0x00000000 | |
836 | #define regk_gio_rw_pc_oe_default 0x00000000 | |
837 | #define regk_gio_rw_ppwm_data_default 0x00000000 | |
838 | #define regk_gio_rw_pwm0_ctrl_default 0x00000000 | |
839 | #define regk_gio_rw_pwm1_ctrl_default 0x00000000 | |
840 | #define regk_gio_rw_pwm2_ctrl_default 0x00000000 | |
841 | #define regk_gio_rw_pwm_in_cfg_default 0x00000000 | |
842 | #define regk_gio_sda0 0x00000000 | |
843 | #define regk_gio_sda1 0x00000001 | |
844 | #define regk_gio_sda2 0x00000002 | |
845 | #define regk_gio_sda3 0x00000003 | |
846 | #define regk_gio_sen 0x00000000 | |
847 | #define regk_gio_set 0x00000003 | |
848 | #define regk_gio_yes 0x00000001 | |
849 | #endif /* __gio_defs_asm_h */ |