[linux-2.6-block.git] / include / asm-arm / system.h

#ifndef __ASM_ARM_SYSTEM_H
#define __ASM_ARM_SYSTEM_H

#ifdef __KERNEL__


#define CPU_ARCH_UNKNOWN	0
#define CPU_ARCH_ARMv3		1
#define CPU_ARCH_ARMv4		2
#define CPU_ARCH_ARMv4T		3
#define CPU_ARCH_ARMv5		4
#define CPU_ARCH_ARMv5T		5
#define CPU_ARCH_ARMv5TE	6
#define CPU_ARCH_ARMv5TEJ	7
#define CPU_ARCH_ARMv6		8

/*
 * CR1 bits (CP#15 CR1)
 */
#define CR_M	(1 << 0)	/* MMU enable				*/
#define CR_A	(1 << 1)	/* Alignment abort enable		*/
#define CR_C	(1 << 2)	/* Dcache enable			*/
#define CR_W	(1 << 3)	/* Write buffer enable			*/
#define CR_P	(1 << 4)	/* 32-bit exception handler		*/
#define CR_D	(1 << 5)	/* 32-bit data address range		*/
#define CR_L	(1 << 6)	/* Implementation defined		*/
#define CR_B	(1 << 7)	/* Big endian				*/
#define CR_S	(1 << 8)	/* System MMU protection		*/
#define CR_R	(1 << 9)	/* ROM MMU protection			*/
#define CR_F	(1 << 10)	/* Implementation defined		*/
#define CR_Z	(1 << 11)	/* Implementation defined		*/
#define CR_I	(1 << 12)	/* Icache enable			*/
#define CR_V	(1 << 13)	/* Vectors relocated to 0xffff0000	*/
#define CR_RR	(1 << 14)	/* Round Robin cache replacement	*/
#define CR_L4	(1 << 15)	/* LDR pc can set T bit			*/
#define CR_DT	(1 << 16)
#define CR_IT	(1 << 18)
#define CR_ST	(1 << 19)
#define CR_FI	(1 << 21)	/* Fast interrupt (lower latency mode)	*/
#define CR_U	(1 << 22)	/* Unaligned access operation		*/
#define CR_XP	(1 << 23)	/* Extended page tables			*/
#define CR_VE	(1 << 24)	/* Vectored interrupts			*/

#define CPUID_ID	0
#define CPUID_CACHETYPE	1
#define CPUID_TCM	2
#define CPUID_TLBTYPE	3

#ifdef CONFIG_CPU_CP15
#define read_cpuid(reg)							\
	({								\
		unsigned int __val;					\
		asm("mrc	p15, 0, %0, c0, c0, " __stringify(reg)	\
		    : "=r" (__val)					\
		    :							\
		    : "cc");						\
		__val;							\
	})
#else
#define read_cpuid(reg) (processor_id)
#endif

/*
 * This is used to ensure the compiler did actually allocate the register we
 * asked it for some inline assembly sequences.  Apparently we can't trust
 * the compiler from one version to another so a bit of paranoia won't hurt.
 * This string is meant to be concatenated with the inline asm string and
 * will cause compilation to stop on mismatch.
 * (for details, see gcc PR 15089)
 */
#define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"

#ifndef __ASSEMBLY__

#include <linux/linkage.h>

struct thread_info;
struct task_struct;

/* information about the system we're running on */
extern unsigned int system_rev;
extern unsigned int system_serial_low;
extern unsigned int system_serial_high;
extern unsigned int mem_fclk_21285;

struct pt_regs;

void die(const char *msg, struct pt_regs *regs, int err)
		__attribute__((noreturn));

struct siginfo;
void notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
		unsigned long err, unsigned long trap);

void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
				       struct pt_regs *),
		     int sig, const char *name);

#define xchg(ptr,x) \
	((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))

#define tas(ptr) (xchg((ptr),1))

extern asmlinkage void __backtrace(void);
extern asmlinkage void c_backtrace(unsigned long fp, int pmode);

struct mm_struct;
extern void show_pte(struct mm_struct *mm, unsigned long addr);
extern void __show_regs(struct pt_regs *);

extern int cpu_architecture(void);
extern void cpu_init(void);

void arm_machine_restart(char mode);
extern void (*arm_pm_restart)(char str);

/*
 * Intel's XScale3 core supports some v6 features (supersections, L2)
 * but advertises itself as v5 as it does not support the v6 ISA.  For
 * this reason, we need a way to explicitly test for this type of CPU.
 */
#ifndef CONFIG_CPU_XSC3
#define cpu_is_xsc3()	0
#else
static inline int cpu_is_xsc3(void)
{
	extern unsigned int processor_id;

	if ((processor_id & 0xffffe000) == 0x69056000)
		return 1;

	return 0;
}
#endif

#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
#define	cpu_is_xscale()	0
#else
#define	cpu_is_xscale()	1
#endif

static inline unsigned int get_cr(void)
{
	unsigned int val;
	asm("mrc p15, 0, %0, c1, c0, 0	@ get CR" : "=r" (val) : : "cc");
	return val;
}

static inline void set_cr(unsigned int val)
{
	asm volatile("mcr p15, 0, %0, c1, c0, 0	@ set CR"
	  : : "r" (val) : "cc");
}

#define CPACC_FULL(n)		(3 << (n * 2))
#define CPACC_SVC(n)		(1 << (n * 2))
#define CPACC_DISABLE(n)	(0 << (n * 2))

static inline unsigned int get_copro_access(void)
{
	unsigned int val;
	asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
	  : "=r" (val) : : "cc");
	return val;
}

static inline void set_copro_access(unsigned int val)
{
	asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
	  : : "r" (val) : "cc");
}

extern unsigned long cr_no_alignment;	/* defined in entry-armv.S */
extern unsigned long cr_alignment;	/* defined in entry-armv.S */

#ifndef CONFIG_SMP
static inline void adjust_cr(unsigned long mask, unsigned long set)
{
	unsigned long flags, cr;

	mask &= ~CR_A;

	set &= mask;

	local_irq_save(flags);

	cr_no_alignment = (cr_no_alignment & ~mask) | set;
	cr_alignment = (cr_alignment & ~mask) | set;

	set_cr((get_cr() & ~mask) | set);

	local_irq_restore(flags);
}
#endif

#define UDBG_UNDEFINED	(1 << 0)
#define UDBG_SYSCALL	(1 << 1)
#define UDBG_BADABORT	(1 << 2)
#define UDBG_SEGV	(1 << 3)
#define UDBG_BUS	(1 << 4)

extern unsigned int user_debug;

#if __LINUX_ARM_ARCH__ >= 4
#define vectors_high()	(cr_alignment & CR_V)
#else
#define vectors_high()	(0)
#endif

#if __LINUX_ARM_ARCH__ >= 6
#define mb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
                                   : : "r" (0) : "memory")
#else
#define mb() __asm__ __volatile__ ("" : : : "memory")
#endif
#define rmb() mb()
#define wmb() mb()
#define read_barrier_depends() do { } while(0)
#define set_mb(var, value)  do { var = value; mb(); } while (0)
#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");

/*
 * switch_mm() may do a full cache flush over the context switch,
 * so enable interrupts over the context switch to avoid high
 * latency.
 */
#define __ARCH_WANT_INTERRUPTS_ON_CTXSW

/*
 * switch_to(prev, next) should switch from task `prev' to `next'
 * `prev' will never be the same as `next'.  schedule() itself
 * contains the memory barrier to tell GCC not to cache `current'.
 */
extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);

#define switch_to(prev,next,last)					\
do {									\
	last = __switch_to(prev,task_thread_info(prev), task_thread_info(next));	\
} while (0)

/*
 * On SMP systems, when the scheduler does migration-cost autodetection,
 * it needs a way to flush as much of the CPU's caches as possible.
 *
 * TODO: fill this in!
 */
static inline void sched_cacheflush(void)
{
}

#include <linux/irqflags.h>

#ifdef CONFIG_SMP

#define smp_mb()		mb()
#define smp_rmb()		rmb()
#define smp_wmb()		wmb()
#define smp_read_barrier_depends()		read_barrier_depends()

#else

#define smp_mb()		barrier()
#define smp_rmb()		barrier()
#define smp_wmb()		barrier()
#define smp_read_barrier_depends()		do { } while(0)

#endif /* CONFIG_SMP */

#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
/*
 * On the StrongARM, "swp" is terminally broken since it bypasses the
 * cache totally.  This means that the cache becomes inconsistent, and,
 * since we use normal loads/stores as well, this is really bad.
 * Typically, this causes oopsen in filp_close, but could have other,
 * more disasterous effects.  There are two work-arounds:
 *  1. Disable interrupts and emulate the atomic swap
 *  2. Clean the cache, perform atomic swap, flush the cache
 *
 * We choose (1) since its the "easiest" to achieve here and is not
 * dependent on the processor type.
 *
 * NOTE that this solution won't work on an SMP system, so explcitly
 * forbid it here.
 */
#define swp_is_buggy
#endif

static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
{
	extern void __bad_xchg(volatile void *, int);
	unsigned long ret;
#ifdef swp_is_buggy
	unsigned long flags;
#endif
#if __LINUX_ARM_ARCH__ >= 6
	unsigned int tmp;
#endif

	switch (size) {
#if __LINUX_ARM_ARCH__ >= 6
	case 1:
		asm volatile("@	__xchg1\n"
		"1:	ldrexb	%0, [%3]\n"
		"	strexb	%1, %2, [%3]\n"
		"	teq	%1, #0\n"
		"	bne	1b"
			: "=&r" (ret), "=&r" (tmp)
			: "r" (x), "r" (ptr)
			: "memory", "cc");
		break;
	case 4:
		asm volatile("@	__xchg4\n"
		"1:	ldrex	%0, [%3]\n"
		"	strex	%1, %2, [%3]\n"
		"	teq	%1, #0\n"
		"	bne	1b"
			: "=&r" (ret), "=&r" (tmp)
			: "r" (x), "r" (ptr)
			: "memory", "cc");
		break;
#elif defined(swp_is_buggy)
#ifdef CONFIG_SMP
#error SMP is not supported on this platform
#endif
	case 1:
		raw_local_irq_save(flags);
		ret = *(volatile unsigned char *)ptr;
		*(volatile unsigned char *)ptr = x;
		raw_local_irq_restore(flags);
		break;

	case 4:
		raw_local_irq_save(flags);
		ret = *(volatile unsigned long *)ptr;
		*(volatile unsigned long *)ptr = x;
		raw_local_irq_restore(flags);
		break;
#else
	case 1:
		asm volatile("@	__xchg1\n"
		"	swpb	%0, %1, [%2]"
			: "=&r" (ret)
			: "r" (x), "r" (ptr)
			: "memory", "cc");
		break;
	case 4:
		asm volatile("@	__xchg4\n"
		"	swp	%0, %1, [%2]"
			: "=&r" (ret)
			: "r" (x), "r" (ptr)
			: "memory", "cc");
		break;
#endif
	default:
		__bad_xchg(ptr, size), ret = 0;
		break;
	}

	return ret;
}

extern void disable_hlt(void);
extern void enable_hlt(void);

#endif /* __ASSEMBLY__ */

#define arch_align_stack(x) (x)

#endif /* __KERNEL__ */

#endif
Commit	Line	Data
1da177e4 LT	1	#ifndef __ASM_ARM_SYSTEM_H
	2	#define __ASM_ARM_SYSTEM_H
	3
	4	#ifdef __KERNEL__
	5
1da177e4 LT	6
	7	#define CPU_ARCH_UNKNOWN 0
	8	#define CPU_ARCH_ARMv3 1
	9	#define CPU_ARCH_ARMv4 2
	10	#define CPU_ARCH_ARMv4T 3
	11	#define CPU_ARCH_ARMv5 4
	12	#define CPU_ARCH_ARMv5T 5
	13	#define CPU_ARCH_ARMv5TE 6
	14	#define CPU_ARCH_ARMv5TEJ 7
	15	#define CPU_ARCH_ARMv6 8
	16
	17	/*
	18	* CR1 bits (CP#15 CR1)
	19	*/
	20	#define CR_M (1 << 0) /* MMU enable */
	21	#define CR_A (1 << 1) /* Alignment abort enable */
	22	#define CR_C (1 << 2) /* Dcache enable */
	23	#define CR_W (1 << 3) /* Write buffer enable */
	24	#define CR_P (1 << 4) /* 32-bit exception handler */
	25	#define CR_D (1 << 5) /* 32-bit data address range */
	26	#define CR_L (1 << 6) /* Implementation defined */
	27	#define CR_B (1 << 7) /* Big endian */
	28	#define CR_S (1 << 8) /* System MMU protection */
	29	#define CR_R (1 << 9) /* ROM MMU protection */
	30	#define CR_F (1 << 10) /* Implementation defined */
	31	#define CR_Z (1 << 11) /* Implementation defined */
	32	#define CR_I (1 << 12) /* Icache enable */
	33	#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
	34	#define CR_RR (1 << 14) /* Round Robin cache replacement */
	35	#define CR_L4 (1 << 15) /* LDR pc can set T bit */
	36	#define CR_DT (1 << 16)
	37	#define CR_IT (1 << 18)
	38	#define CR_ST (1 << 19)
	39	#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
	40	#define CR_U (1 << 22) /* Unaligned access operation */
	41	#define CR_XP (1 << 23) /* Extended page tables */
	42	#define CR_VE (1 << 24) /* Vectored interrupts */
	43
	44	#define CPUID_ID 0
	45	#define CPUID_CACHETYPE 1
	46	#define CPUID_TCM 2
	47	#define CPUID_TLBTYPE 3
	48
f12d0d7c	49	#ifdef CONFIG_CPU_CP15
1da177e4 LT	50	#define read_cpuid(reg) \
	51	({ \
	52	unsigned int __val; \
	53	asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
	54	: "=r" (__val) \
	55	: \
	56	: "cc"); \
	57	__val; \
	58	})
f12d0d7c HC	59	#else
	60	#define read_cpuid(reg) (processor_id)
	61	#endif
1da177e4 LT	62
	63	/*
	64	* This is used to ensure the compiler did actually allocate the register we
	65	* asked it for some inline assembly sequences. Apparently we can't trust
	66	* the compiler from one version to another so a bit of paranoia won't hurt.
	67	* This string is meant to be concatenated with the inline asm string and
	68	* will cause compilation to stop on mismatch.
	69	* (for details, see gcc PR 15089)
	70	*/
	71	#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
	72
	73	#ifndef __ASSEMBLY__
	74
	75	#include <linux/linkage.h>
	76
	77	struct thread_info;
	78	struct task_struct;
	79
	80	/* information about the system we're running on */
	81	extern unsigned int system_rev;
	82	extern unsigned int system_serial_low;
	83	extern unsigned int system_serial_high;
	84	extern unsigned int mem_fclk_21285;
	85
	86	struct pt_regs;
	87
	88	void die(const char msg, struct pt_regs regs, int err)
	89	__attribute__((noreturn));
	90
cfb0810e RK	91	struct siginfo;
	92	void notify_die(const char str, struct pt_regs regs, struct siginfo *info,
	93	unsigned long err, unsigned long trap);
1da177e4 LT	94
	95	void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
	96	struct pt_regs *),
	97	int sig, const char *name);
	98
1da177e4 LT	99	#define xchg(ptr,x) \
	100	((__typeof__((ptr)))__xchg((unsigned long)(x),(ptr),sizeof((ptr))))
	101
	102	#define tas(ptr) (xchg((ptr),1))
	103
	104	extern asmlinkage void __backtrace(void);
652a12ef	105	extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
5470dc65 RK	106
5470dc65 RK	107	struct mm_struct;
652a12ef RK	108	extern void show_pte(struct mm_struct *mm, unsigned long addr);
652a12ef RK	109	extern void __show_regs(struct pt_regs *);
1da177e4 LT	110
1da177e4 LT	111	extern int cpu_architecture(void);
36c5ed23	112	extern void cpu_init(void);
1da177e4	113
74617fb6 RP	114	void arm_machine_restart(char mode);
	115	extern void (*arm_pm_restart)(char str);
	116
23bdf86a LB	117	/*
	118	* Intel's XScale3 core supports some v6 features (supersections, L2)
	119	* but advertises itself as v5 as it does not support the v6 ISA. For
	120	* this reason, we need a way to explicitly test for this type of CPU.
	121	*/
	122	#ifndef CONFIG_CPU_XSC3
	123	#define cpu_is_xsc3() 0
	124	#else
	125	static inline int cpu_is_xsc3(void)
	126	{
	127	extern unsigned int processor_id;
	128
	129	if ((processor_id & 0xffffe000) == 0x69056000)
	130	return 1;
	131
	132	return 0;
	133	}
	134	#endif
	135
5cedae9c DS	136	#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
	137	#define cpu_is_xscale() 0
	138	#else
	139	#define cpu_is_xscale() 1
	140	#endif
	141
efe90d27 RK	142	static inline unsigned int get_cr(void)
	143	{
	144	unsigned int val;
	145	asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
	146	return val;
	147	}
	148
	149	static inline void set_cr(unsigned int val)
	150	{
	151	asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
	152	: : "r" (val) : "cc");
	153	}
	154
	155	#define CPACC_FULL(n) (3 << (n * 2))
	156	#define CPACC_SVC(n) (1 << (n * 2))
	157	#define CPACC_DISABLE(n) (0 << (n * 2))
	158
	159	static inline unsigned int get_copro_access(void)
	160	{
	161	unsigned int val;
	162	asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
	163	: "=r" (val) : : "cc");
	164	return val;
	165	}
	166
	167	static inline void set_copro_access(unsigned int val)
	168	{
	169	asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
	170	: : "r" (val) : "cc");
	171	}
1da177e4 LT	172
	173	extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
	174	extern unsigned long cr_alignment; /* defined in entry-armv.S */
	175
47fd7052 RK	176	#ifndef CONFIG_SMP
	177	static inline void adjust_cr(unsigned long mask, unsigned long set)
	178	{
	179	unsigned long flags, cr;
	180
	181	mask &= ~CR_A;
	182
	183	set &= mask;
	184
	185	local_irq_save(flags);
	186
	187	cr_no_alignment = (cr_no_alignment & ~mask) \| set;
	188	cr_alignment = (cr_alignment & ~mask) \| set;
	189
	190	set_cr((get_cr() & ~mask) \| set);
	191
	192	local_irq_restore(flags);
	193	}
	194	#endif
	195
1da177e4 LT	196	#define UDBG_UNDEFINED (1 << 0)
	197	#define UDBG_SYSCALL (1 << 1)
	198	#define UDBG_BADABORT (1 << 2)
	199	#define UDBG_SEGV (1 << 3)
	200	#define UDBG_BUS (1 << 4)
	201
	202	extern unsigned int user_debug;
	203
	204	#if __LINUX_ARM_ARCH__ >= 4
	205	#define vectors_high() (cr_alignment & CR_V)
	206	#else
	207	#define vectors_high() (0)
	208	#endif
	209
6d9b37a3 RK	210	#if __LINUX_ARM_ARCH__ >= 6
	211	#define mb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
	212	: : "r" (0) : "memory")
	213	#else
1da177e4	214	#define mb() __asm__ __volatile__ ("" : : : "memory")
6d9b37a3	215	#endif
1da177e4 LT	216	#define rmb() mb()
	217	#define wmb() mb()
	218	#define read_barrier_depends() do { } while(0)
	219	#define set_mb(var, value) do { var = value; mb(); } while (0)
1da177e4 LT	220	#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
1da177e4 LT	221
1da177e4	222	/*
4866cde0 NP	223	* switch_mm() may do a full cache flush over the context switch,
	224	* so enable interrupts over the context switch to avoid high
	225	* latency.
1da177e4	226	*/
4866cde0	227	#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
1da177e4 LT	228
	229	/*
	230	* switch_to(prev, next) should switch from task `prev' to `next'
	231	* `prev' will never be the same as `next'. schedule() itself
	232	* contains the memory barrier to tell GCC not to cache `current'.
	233	*/
	234	extern struct task_struct __switch_to(struct task_struct , struct thread_info , struct thread_info );
	235
	236	#define switch_to(prev,next,last) \
	237	do { \
e7c1b32f	238	last = __switch_to(prev,task_thread_info(prev), task_thread_info(next)); \
1da177e4 LT	239	} while (0)
1da177e4 LT	240
4dc7a0bb IM	241	/*
	242	* On SMP systems, when the scheduler does migration-cost autodetection,
	243	* it needs a way to flush as much of the CPU's caches as possible.
	244	*
	245	* TODO: fill this in!
	246	*/
	247	static inline void sched_cacheflush(void)
	248	{
	249	}
	250
7ad1bcb2	251	#include <linux/irqflags.h>
1da177e4 LT	252
1da177e4 LT	253	#ifdef CONFIG_SMP
1da177e4 LT	254
	255	#define smp_mb() mb()
	256	#define smp_rmb() rmb()
	257	#define smp_wmb() wmb()
	258	#define smp_read_barrier_depends() read_barrier_depends()
	259
	260	#else
	261
	262	#define smp_mb() barrier()
	263	#define smp_rmb() barrier()
	264	#define smp_wmb() barrier()
	265	#define smp_read_barrier_depends() do { } while(0)
	266
053a7b5b RK	267	#endif /* CONFIG_SMP */
053a7b5b RK	268
1da177e4 LT	269	#if defined(CONFIG_CPU_SA1100) \|\| defined(CONFIG_CPU_SA110)
	270	/*
	271	* On the StrongARM, "swp" is terminally broken since it bypasses the
	272	* cache totally. This means that the cache becomes inconsistent, and,
	273	* since we use normal loads/stores as well, this is really bad.
	274	* Typically, this causes oopsen in filp_close, but could have other,
	275	* more disasterous effects. There are two work-arounds:
	276	* 1. Disable interrupts and emulate the atomic swap
	277	* 2. Clean the cache, perform atomic swap, flush the cache
	278	*
	279	* We choose (1) since its the "easiest" to achieve here and is not
	280	* dependent on the processor type.
053a7b5b RK	281	*
	282	* NOTE that this solution won't work on an SMP system, so explcitly
	283	* forbid it here.
1da177e4 LT	284	*/
	285	#define swp_is_buggy
	286	#endif
	287
	288	static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
	289	{
	290	extern void __bad_xchg(volatile void *, int);
	291	unsigned long ret;
	292	#ifdef swp_is_buggy
	293	unsigned long flags;
	294	#endif
9560782f RK	295	#if __LINUX_ARM_ARCH__ >= 6
	296	unsigned int tmp;
	297	#endif
1da177e4 LT	298
1da177e4 LT	299	switch (size) {
9560782f RK	300	#if __LINUX_ARM_ARCH__ >= 6
	301	case 1:
	302	asm volatile("@ __xchg1\n"
	303	"1: ldrexb %0, [%3]\n"
	304	" strexb %1, %2, [%3]\n"
	305	" teq %1, #0\n"
	306	" bne 1b"
	307	: "=&r" (ret), "=&r" (tmp)
	308	: "r" (x), "r" (ptr)
	309	: "memory", "cc");
	310	break;
	311	case 4:
	312	asm volatile("@ __xchg4\n"
	313	"1: ldrex %0, [%3]\n"
	314	" strex %1, %2, [%3]\n"
	315	" teq %1, #0\n"
	316	" bne 1b"
	317	: "=&r" (ret), "=&r" (tmp)
	318	: "r" (x), "r" (ptr)
	319	: "memory", "cc");
	320	break;
	321	#elif defined(swp_is_buggy)
	322	#ifdef CONFIG_SMP
	323	#error SMP is not supported on this platform
	324	#endif
	325	case 1:
e7cc2c59	326	raw_local_irq_save(flags);
9560782f RK	327	ret = (volatile unsigned char )ptr;
9560782f RK	328	(volatile unsigned char )ptr = x;
e7cc2c59	329	raw_local_irq_restore(flags);
9560782f RK	330	break;
	331
	332	case 4:
e7cc2c59	333	raw_local_irq_save(flags);
9560782f RK	334	ret = (volatile unsigned long )ptr;
9560782f RK	335	(volatile unsigned long )ptr = x;
e7cc2c59	336	raw_local_irq_restore(flags);
9560782f	337	break;
1da177e4	338	#else
9560782f RK	339	case 1:
	340	asm volatile("@ __xchg1\n"
	341	" swpb %0, %1, [%2]"
	342	: "=&r" (ret)
	343	: "r" (x), "r" (ptr)
	344	: "memory", "cc");
	345	break;
	346	case 4:
	347	asm volatile("@ __xchg4\n"
	348	" swp %0, %1, [%2]"
	349	: "=&r" (ret)
	350	: "r" (x), "r" (ptr)
	351	: "memory", "cc");
	352	break;
1da177e4	353	#endif
9560782f RK	354	default:
	355	__bad_xchg(ptr, size), ret = 0;
	356	break;
1da177e4 LT	357	}
	358
	359	return ret;
	360	}
	361
dabaeff0 BD	362	extern void disable_hlt(void);
	363	extern void enable_hlt(void);
	364
1da177e4 LT	365	#endif /* __ASSEMBLY__ */
	366
	367	#define arch_align_stack(x) (x)
	368
	369	#endif /* __KERNEL__ */
	370
	371	#endif